1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // IT block predicate field
15 def it_pred : Operand<i32> {
16 let PrintMethod = "printPredicateOperand";
19 // IT block condition mask
20 def it_mask : Operand<i32> {
21 let PrintMethod = "printThumbITMask";
24 // Table branch address
25 def tb_addrmode : Operand<i32> {
26 let PrintMethod = "printTBAddrMode";
29 // Shifted operands. No register controlled shifts for Thumb2.
30 // Note: We do not support rrx shifted operands yet.
31 def t2_so_reg : Operand<i32>, // reg imm
32 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg",
34 let PrintMethod = "printT2SOOperand";
35 let MIOperandInfo = (ops GPR, i32imm);
38 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
39 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
40 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
43 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
44 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
45 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32);
48 // t2_so_imm - Match a 32-bit immediate operand, which is an
49 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
50 // immediate splatted into multiple bytes of the word. t2_so_imm values are
51 // represented in the imm field in the same 12-bit form that they are encoded
52 // into t2_so_imm instructions: the 8-bit immediate is the least significant bits
53 // [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
54 def t2_so_imm : Operand<i32>,
56 return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
59 // t2_so_imm_not - Match an immediate that is a complement
61 def t2_so_imm_not : Operand<i32>,
63 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
64 }], t2_so_imm_not_XFORM>;
66 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
67 def t2_so_imm_neg : Operand<i32>,
69 return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
70 }], t2_so_imm_neg_XFORM>;
72 /// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
73 def imm1_31 : PatLeaf<(i32 imm), [{
74 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
77 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
78 def imm0_4095 : Operand<i32>,
80 return (uint32_t)N->getZExtValue() < 4096;
83 def imm0_4095_neg : PatLeaf<(i32 imm), [{
84 return (uint32_t)(-N->getZExtValue()) < 4096;
87 def imm0_255_neg : PatLeaf<(i32 imm), [{
88 return (uint32_t)(-N->getZExtValue()) < 255;
91 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
93 def imm0_65535 : PatLeaf<(i32 imm), [{
94 return (uint32_t)N->getZExtValue() < 65536;
97 /// Split a 32-bit immediate into two 16 bit parts.
98 def t2_lo16 : SDNodeXForm<imm, [{
99 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
103 def t2_hi16 : SDNodeXForm<imm, [{
104 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
107 def t2_lo16AllZero : PatLeaf<(i32 imm), [{
108 // Returns true if all low 16-bits are 0.
109 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
113 // Define Thumb2 specific addressing modes.
115 // t2addrmode_imm12 := reg + imm12
116 def t2addrmode_imm12 : Operand<i32>,
117 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> {
118 let PrintMethod = "printT2AddrModeImm12Operand";
119 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
122 // t2addrmode_imm8 := reg - imm8
123 def t2addrmode_imm8 : Operand<i32>,
124 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> {
125 let PrintMethod = "printT2AddrModeImm8Operand";
126 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
129 def t2am_imm8_offset : Operand<i32>,
130 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", []>{
131 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
134 // t2addrmode_imm8s4 := reg +/- (imm8 << 2)
135 def t2addrmode_imm8s4 : Operand<i32>,
136 ComplexPattern<i32, 2, "SelectT2AddrModeImm8s4", []> {
137 let PrintMethod = "printT2AddrModeImm8s4Operand";
138 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
141 // t2addrmode_so_reg := reg + (reg << imm2)
142 def t2addrmode_so_reg : Operand<i32>,
143 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> {
144 let PrintMethod = "printT2AddrModeSoRegOperand";
145 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
149 //===----------------------------------------------------------------------===//
150 // Multiclass helpers...
153 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
154 /// unary operation that produces a value. These are predicable and can be
155 /// changed to modify CPSR.
156 multiclass T2I_un_irs<string opc, PatFrag opnode, bit Cheap = 0, bit ReMat = 0>{
158 def i : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iALU,
160 [(set GPR:$dst, (opnode t2_so_imm:$src))]> {
161 let isAsCheapAsAMove = Cheap;
162 let isReMaterializable = ReMat;
165 def r : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
166 opc, ".w $dst, $src",
167 [(set GPR:$dst, (opnode GPR:$src))]>;
169 def s : T2I<(outs GPR:$dst), (ins t2_so_reg:$src), IIC_iALU,
170 opc, ".w $dst, $src",
171 [(set GPR:$dst, (opnode t2_so_reg:$src))]>;
174 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
175 // binary operation that produces a value. These are predicable and can be
176 /// changed to modify CPSR.
177 multiclass T2I_bin_irs<string opc, PatFrag opnode,
178 bit Commutable = 0, string wide =""> {
180 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU,
181 opc, " $dst, $lhs, $rhs",
182 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
184 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
185 opc, !strconcat(wide, " $dst, $lhs, $rhs"),
186 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
187 let isCommutable = Commutable;
190 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU,
191 opc, !strconcat(wide, " $dst, $lhs, $rhs"),
192 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
195 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need
196 // the ".w" prefix to indicate that they are wide.
197 multiclass T2I_bin_w_irs<string opc, PatFrag opnode, bit Commutable = 0> :
198 T2I_bin_irs<opc, opnode, Commutable, ".w">;
200 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are
201 /// reversed. It doesn't define the 'rr' form since it's handled by its
202 /// T2I_bin_irs counterpart.
203 multiclass T2I_rbin_is<string opc, PatFrag opnode> {
205 def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs), IIC_iALU,
206 opc, ".w $dst, $rhs, $lhs",
207 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
209 def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs), IIC_iALU,
210 opc, " $dst, $rhs, $lhs",
211 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
214 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
215 /// instruction modifies the CPSR register.
216 let Defs = [CPSR] in {
217 multiclass T2I_bin_s_irs<string opc, PatFrag opnode, bit Commutable = 0> {
219 def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU,
220 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
221 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
223 def rr : T2I<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
224 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
225 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
226 let isCommutable = Commutable;
229 def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU,
230 !strconcat(opc, "s"), ".w $dst, $lhs, $rhs",
231 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
235 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg})
236 /// patterns for a binary operation that produces a value.
237 multiclass T2I_bin_ii12rs<string opc, PatFrag opnode, bit Commutable = 0> {
239 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU,
240 opc, ".w $dst, $lhs, $rhs",
241 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
243 def ri12 : T2sI<(outs GPR:$dst), (ins GPR:$lhs, imm0_4095:$rhs), IIC_iALU,
244 !strconcat(opc, "w"), " $dst, $lhs, $rhs",
245 [(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
247 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
248 opc, ".w $dst, $lhs, $rhs",
249 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]> {
250 let isCommutable = Commutable;
253 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU,
254 opc, ".w $dst, $lhs, $rhs",
255 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
258 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a
259 /// binary operation that produces a value and use and define the carry bit.
260 /// It's not predicable.
261 let Uses = [CPSR] in {
262 multiclass T2I_adde_sube_irs<string opc, PatFrag opnode, bit Commutable = 0> {
264 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU,
265 opc, " $dst, $lhs, $rhs",
266 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
267 Requires<[IsThumb2, CarryDefIsUnused]>;
269 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
270 opc, ".w $dst, $lhs, $rhs",
271 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
272 Requires<[IsThumb2, CarryDefIsUnused]> {
273 let isCommutable = Commutable;
276 def rs : T2sI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU,
277 opc, ".w $dst, $lhs, $rhs",
278 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
279 Requires<[IsThumb2, CarryDefIsUnused]>;
280 // Carry setting variants
282 def Sri : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU,
283 !strconcat(opc, "s $dst, $lhs, $rhs"),
284 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
285 Requires<[IsThumb2, CarryDefIsUsed]> {
289 def Srr : T2XI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
290 !strconcat(opc, "s.w $dst, $lhs, $rhs"),
291 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
292 Requires<[IsThumb2, CarryDefIsUsed]> {
294 let isCommutable = Commutable;
297 def Srs : T2XI<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU,
298 !strconcat(opc, "s.w $dst, $lhs, $rhs"),
299 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
300 Requires<[IsThumb2, CarryDefIsUsed]> {
306 /// T2I_rbin_s_is - Same as T2I_rbin_is except sets 's' bit.
307 let Defs = [CPSR] in {
308 multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
310 def ri : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
312 !strconcat(opc, "${s}.w $dst, $rhs, $lhs"),
313 [(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
315 def rs : T2XI<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
317 !strconcat(opc, "${s} $dst, $rhs, $lhs"),
318 [(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
322 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
323 // rotate operation that produces a value.
324 multiclass T2I_sh_ir<string opc, PatFrag opnode> {
326 def ri : T2sI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALU,
327 opc, ".w $dst, $lhs, $rhs",
328 [(set GPR:$dst, (opnode GPR:$lhs, imm1_31:$rhs))]>;
330 def rr : T2sI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
331 opc, ".w $dst, $lhs, $rhs",
332 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>;
335 /// T21_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
336 /// patterns. Similar to T2I_bin_irs except the instruction does not produce
337 /// a explicit result, only implicitly set CPSR.
338 let Defs = [CPSR] in {
339 multiclass T2I_cmp_is<string opc, PatFrag opnode> {
341 def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs), IIC_iALU,
342 opc, ".w $lhs, $rhs",
343 [(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
345 def rr : T2I<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
346 opc, ".w $lhs, $rhs",
347 [(opnode GPR:$lhs, GPR:$rhs)]>;
349 def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs), IIC_iALU,
350 opc, ".w $lhs, $rhs",
351 [(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
355 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
356 multiclass T2I_ld<string opc, PatFrag opnode> {
357 def i12 : T2Ii12<(outs GPR:$dst), (ins t2addrmode_imm12:$addr), IIC_iLoad,
358 opc, ".w $dst, $addr",
359 [(set GPR:$dst, (opnode t2addrmode_imm12:$addr))]>;
360 def i8 : T2Ii8 <(outs GPR:$dst), (ins t2addrmode_imm8:$addr), IIC_iLoad,
362 [(set GPR:$dst, (opnode t2addrmode_imm8:$addr))]>;
363 def s : T2Iso <(outs GPR:$dst), (ins t2addrmode_so_reg:$addr), IIC_iLoad,
364 opc, ".w $dst, $addr",
365 [(set GPR:$dst, (opnode t2addrmode_so_reg:$addr))]>;
366 def pci : T2Ipc <(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoad,
367 opc, ".w $dst, $addr",
368 [(set GPR:$dst, (opnode (ARMWrapper tconstpool:$addr)))]>;
371 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
372 multiclass T2I_st<string opc, PatFrag opnode> {
373 def i12 : T2Ii12<(outs), (ins GPR:$src, t2addrmode_imm12:$addr), IIC_iStore,
374 opc, ".w $src, $addr",
375 [(opnode GPR:$src, t2addrmode_imm12:$addr)]>;
376 def i8 : T2Ii8 <(outs), (ins GPR:$src, t2addrmode_imm8:$addr), IIC_iStore,
378 [(opnode GPR:$src, t2addrmode_imm8:$addr)]>;
379 def s : T2Iso <(outs), (ins GPR:$src, t2addrmode_so_reg:$addr), IIC_iStore,
380 opc, ".w $src, $addr",
381 [(opnode GPR:$src, t2addrmode_so_reg:$addr)]>;
384 /// T2I_picld - Defines the PIC load pattern.
385 class T2I_picld<string opc, PatFrag opnode> :
386 T2I<(outs GPR:$dst), (ins addrmodepc:$addr), IIC_iLoad,
387 !strconcat("${addr:label}:\n\t", opc), " $dst, $addr",
388 [(set GPR:$dst, (opnode addrmodepc:$addr))]>;
390 /// T2I_picst - Defines the PIC store pattern.
391 class T2I_picst<string opc, PatFrag opnode> :
392 T2I<(outs), (ins GPR:$src, addrmodepc:$addr), IIC_iStore,
393 !strconcat("${addr:label}:\n\t", opc), " $src, $addr",
394 [(opnode GPR:$src, addrmodepc:$addr)]>;
397 /// T2I_unary_rrot - A unary operation with two forms: one whose operand is a
398 /// register and one whose operand is a register rotated by 8/16/24.
399 multiclass T2I_unary_rrot<string opc, PatFrag opnode> {
400 def r : T2I<(outs GPR:$dst), (ins GPR:$Src), IIC_iALU,
401 opc, ".w $dst, $Src",
402 [(set GPR:$dst, (opnode GPR:$Src))]>;
403 def r_rot : T2I<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), IIC_iALU,
404 opc, ".w $dst, $Src, ror $rot",
405 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>;
408 /// T2I_bin_rrot - A binary operation with two forms: one whose operand is a
409 /// register and one whose operand is a register rotated by 8/16/24.
410 multiclass T2I_bin_rrot<string opc, PatFrag opnode> {
411 def rr : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), IIC_iALU,
412 opc, " $dst, $LHS, $RHS",
413 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>;
414 def rr_rot : T2I<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
415 IIC_iALU, opc, " $dst, $LHS, $RHS, ror $rot",
416 [(set GPR:$dst, (opnode GPR:$LHS,
417 (rotr GPR:$RHS, rot_imm:$rot)))]>;
420 //===----------------------------------------------------------------------===//
422 //===----------------------------------------------------------------------===//
424 //===----------------------------------------------------------------------===//
425 // Miscellaneous Instructions.
428 // LEApcrel - Load a pc-relative address into a register without offending the
430 def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALU,
431 "adr$p.w $dst, #$label", []>;
433 def t2LEApcrelJT : T2XI<(outs GPR:$dst),
434 (ins i32imm:$label, lane_cst:$id, pred:$p), IIC_iALU,
435 "adr$p.w $dst, #${label}_${id}", []>;
437 // ADD r, sp, {so_imm|i12}
438 def t2ADDrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), IIC_iALU,
439 "add", ".w $dst, $sp, $imm", []>;
440 def t2ADDrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), IIC_iALU,
441 "addw", " $dst, $sp, $imm", []>;
444 def t2ADDrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), IIC_iALU,
445 "add", ".w $dst, $sp, $rhs", []>;
447 // SUB r, sp, {so_imm|i12}
448 def t2SUBrSPi : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm), IIC_iALU,
449 "sub", ".w $dst, $sp, $imm", []>;
450 def t2SUBrSPi12 : T2I<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm), IIC_iALU,
451 "subw", " $dst, $sp, $imm", []>;
454 def t2SUBrSPs : T2sI<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs), IIC_iALU,
455 "sub", " $dst, $sp, $rhs", []>;
458 // Pseudo instruction that will expand into a t2SUBrSPi + a copy.
459 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
460 def t2SUBrSPi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_imm:$imm),
461 NoItinerary, "@ sub.w $dst, $sp, $imm", []>;
462 def t2SUBrSPi12_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, imm0_4095:$imm),
463 NoItinerary, "@ subw $dst, $sp, $imm", []>;
464 def t2SUBrSPs_ : PseudoInst<(outs GPR:$dst), (ins GPR:$sp, t2_so_reg:$rhs),
465 NoItinerary, "@ sub $dst, $sp, $rhs", []>;
466 } // usesCustomDAGSchedInserter
469 //===----------------------------------------------------------------------===//
470 // Load / store Instructions.
474 let canFoldAsLoad = 1 in
475 defm t2LDR : T2I_ld<"ldr", UnOpFrag<(load node:$Src)>>;
477 // Loads with zero extension
478 defm t2LDRH : T2I_ld<"ldrh", UnOpFrag<(zextloadi16 node:$Src)>>;
479 defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
481 // Loads with sign extension
482 defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
483 defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
487 def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst), (ins t2addrmode_imm8s4:$addr),
488 IIC_iLoad, "ldrd", " $dst, $addr", []>;
489 def t2LDRDpci : T2Ii8s4<(outs GPR:$dst), (ins i32imm:$addr), IIC_iLoad,
490 "ldrd", " $dst, $addr", []>;
493 // zextload i1 -> zextload i8
494 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr),
495 (t2LDRBi12 t2addrmode_imm12:$addr)>;
496 def : T2Pat<(zextloadi1 t2addrmode_imm8:$addr),
497 (t2LDRBi8 t2addrmode_imm8:$addr)>;
498 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr),
499 (t2LDRBs t2addrmode_so_reg:$addr)>;
500 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)),
501 (t2LDRBpci tconstpool:$addr)>;
503 // extload -> zextload
504 // FIXME: Reduce the number of patterns by legalizing extload to zextload
506 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr),
507 (t2LDRBi12 t2addrmode_imm12:$addr)>;
508 def : T2Pat<(extloadi1 t2addrmode_imm8:$addr),
509 (t2LDRBi8 t2addrmode_imm8:$addr)>;
510 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr),
511 (t2LDRBs t2addrmode_so_reg:$addr)>;
512 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)),
513 (t2LDRBpci tconstpool:$addr)>;
515 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr),
516 (t2LDRBi12 t2addrmode_imm12:$addr)>;
517 def : T2Pat<(extloadi8 t2addrmode_imm8:$addr),
518 (t2LDRBi8 t2addrmode_imm8:$addr)>;
519 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr),
520 (t2LDRBs t2addrmode_so_reg:$addr)>;
521 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)),
522 (t2LDRBpci tconstpool:$addr)>;
524 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr),
525 (t2LDRHi12 t2addrmode_imm12:$addr)>;
526 def : T2Pat<(extloadi16 t2addrmode_imm8:$addr),
527 (t2LDRHi8 t2addrmode_imm8:$addr)>;
528 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr),
529 (t2LDRHs t2addrmode_so_reg:$addr)>;
530 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)),
531 (t2LDRHpci tconstpool:$addr)>;
535 def t2LDR_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
536 (ins t2addrmode_imm8:$addr),
537 AddrModeT2_i8, IndexModePre, IIC_iLoad,
538 "ldr", " $dst, $addr!", "$addr.base = $base_wb",
541 def t2LDR_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
542 (ins GPR:$base, t2am_imm8_offset:$offset),
543 AddrModeT2_i8, IndexModePost, IIC_iLoad,
544 "ldr", " $dst, [$base], $offset", "$base = $base_wb",
547 def t2LDRB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
548 (ins t2addrmode_imm8:$addr),
549 AddrModeT2_i8, IndexModePre, IIC_iLoad,
550 "ldrb", " $dst, $addr!", "$addr.base = $base_wb",
552 def t2LDRB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
553 (ins GPR:$base, t2am_imm8_offset:$offset),
554 AddrModeT2_i8, IndexModePost, IIC_iLoad,
555 "ldrb", " $dst, [$base], $offset", "$base = $base_wb",
558 def t2LDRH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
559 (ins t2addrmode_imm8:$addr),
560 AddrModeT2_i8, IndexModePre, IIC_iLoad,
561 "ldrh", " $dst, $addr!", "$addr.base = $base_wb",
563 def t2LDRH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
564 (ins GPR:$base, t2am_imm8_offset:$offset),
565 AddrModeT2_i8, IndexModePost, IIC_iLoad,
566 "ldrh", " $dst, [$base], $offset", "$base = $base_wb",
569 def t2LDRSB_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
570 (ins t2addrmode_imm8:$addr),
571 AddrModeT2_i8, IndexModePre, IIC_iLoad,
572 "ldrsb", " $dst, $addr!", "$addr.base = $base_wb",
574 def t2LDRSB_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
575 (ins GPR:$base, t2am_imm8_offset:$offset),
576 AddrModeT2_i8, IndexModePost, IIC_iLoad,
577 "ldrsb", " $dst, [$base], $offset", "$base = $base_wb",
580 def t2LDRSH_PRE : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
581 (ins t2addrmode_imm8:$addr),
582 AddrModeT2_i8, IndexModePre, IIC_iLoad,
583 "ldrsh", " $dst, $addr!", "$addr.base = $base_wb",
585 def t2LDRSH_POST : T2Iidxldst<(outs GPR:$dst, GPR:$base_wb),
586 (ins GPR:$base, t2am_imm8_offset:$offset),
587 AddrModeT2_i8, IndexModePost, IIC_iLoad,
588 "ldrsh", " $dst, [$base], $offset", "$base = $base_wb",
593 defm t2STR : T2I_st<"str", BinOpFrag<(store node:$LHS, node:$RHS)>>;
594 defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
595 defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
599 def t2STRDi8 : T2Ii8s4<(outs), (ins GPR:$src, t2addrmode_imm8s4:$addr),
600 IIC_iStore, "strd", " $src, $addr", []>;
603 def t2STR_PRE : T2Iidxldst<(outs GPR:$base_wb),
604 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
605 AddrModeT2_i8, IndexModePre, IIC_iStore,
606 "str", " $src, [$base, $offset]!", "$base = $base_wb",
608 (pre_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
610 def t2STR_POST : T2Iidxldst<(outs GPR:$base_wb),
611 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
612 AddrModeT2_i8, IndexModePost, IIC_iStore,
613 "str", " $src, [$base], $offset", "$base = $base_wb",
615 (post_store GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
617 def t2STRH_PRE : T2Iidxldst<(outs GPR:$base_wb),
618 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
619 AddrModeT2_i8, IndexModePre, IIC_iStore,
620 "strh", " $src, [$base, $offset]!", "$base = $base_wb",
622 (pre_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
624 def t2STRH_POST : T2Iidxldst<(outs GPR:$base_wb),
625 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
626 AddrModeT2_i8, IndexModePost, IIC_iStore,
627 "strh", " $src, [$base], $offset", "$base = $base_wb",
629 (post_truncsti16 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
631 def t2STRB_PRE : T2Iidxldst<(outs GPR:$base_wb),
632 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
633 AddrModeT2_i8, IndexModePre, IIC_iStore,
634 "strb", " $src, [$base, $offset]!", "$base = $base_wb",
636 (pre_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
638 def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
639 (ins GPR:$src, GPR:$base, t2am_imm8_offset:$offset),
640 AddrModeT2_i8, IndexModePost, IIC_iStore,
641 "strb", " $src, [$base], $offset", "$base = $base_wb",
643 (post_truncsti8 GPR:$src, GPR:$base, t2am_imm8_offset:$offset))]>;
646 // FIXME: ldrd / strd pre / post variants
648 //===----------------------------------------------------------------------===//
649 // Load / store multiple Instructions.
653 def t2LDM : T2XI<(outs),
654 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
655 IIC_iLoad, "ldm${addr:submode}${p}${addr:wide} $addr, $dst1", []>;
658 def t2STM : T2XI<(outs),
659 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
660 IIC_iStore, "stm${addr:submode}${p}${addr:wide} $addr, $src1", []>;
662 //===----------------------------------------------------------------------===//
663 // Move Instructions.
666 let neverHasSideEffects = 1 in
667 def t2MOVr : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
668 "mov", ".w $dst, $src", []>;
670 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
671 def t2MOVi : T2sI<(outs GPR:$dst), (ins t2_so_imm:$src), IIC_iALU,
672 "mov", ".w $dst, $src",
673 [(set GPR:$dst, t2_so_imm:$src)]>;
675 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
676 def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src), IIC_iALU,
677 "movw", " $dst, $src",
678 [(set GPR:$dst, imm0_65535:$src)]>;
680 // FIXME: Also available in ARM mode.
681 let Constraints = "$src = $dst" in
682 def t2MOVTi16 : T2sI<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm), IIC_iALU,
683 "movt", " $dst, $imm",
685 (or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
687 //===----------------------------------------------------------------------===//
688 // Extend Instructions.
693 defm t2SXTB : T2I_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
694 defm t2SXTH : T2I_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
696 defm t2SXTAB : T2I_bin_rrot<"sxtab",
697 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
698 defm t2SXTAH : T2I_bin_rrot<"sxtah",
699 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
701 // TODO: SXT(A){B|H}16
705 let AddedComplexity = 16 in {
706 defm t2UXTB : T2I_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
707 defm t2UXTH : T2I_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
708 defm t2UXTB16 : T2I_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
710 def : T2Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
711 (t2UXTB16r_rot GPR:$Src, 24)>;
712 def : T2Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
713 (t2UXTB16r_rot GPR:$Src, 8)>;
715 defm t2UXTAB : T2I_bin_rrot<"uxtab",
716 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
717 defm t2UXTAH : T2I_bin_rrot<"uxtah",
718 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
721 //===----------------------------------------------------------------------===//
722 // Arithmetic Instructions.
725 defm t2ADD : T2I_bin_ii12rs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
726 defm t2SUB : T2I_bin_ii12rs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
728 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
729 defm t2ADDS : T2I_bin_s_irs <"add", BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
730 defm t2SUBS : T2I_bin_s_irs <"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
732 defm t2ADC : T2I_adde_sube_irs<"adc",BinOpFrag<(adde node:$LHS, node:$RHS)>,1>;
733 defm t2SBC : T2I_adde_sube_irs<"sbc",BinOpFrag<(sube node:$LHS, node:$RHS)>>;
736 defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
737 defm t2RSBS : T2I_rbin_s_is <"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
739 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
740 let AddedComplexity = 1 in
741 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm),
742 (t2SUBri GPR:$src, imm0_255_neg:$imm)>;
743 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
744 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
745 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm),
746 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
749 //===----------------------------------------------------------------------===//
750 // Shift and rotate Instructions.
753 defm t2LSL : T2I_sh_ir<"lsl", BinOpFrag<(shl node:$LHS, node:$RHS)>>;
754 defm t2LSR : T2I_sh_ir<"lsr", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
755 defm t2ASR : T2I_sh_ir<"asr", BinOpFrag<(sra node:$LHS, node:$RHS)>>;
756 defm t2ROR : T2I_sh_ir<"ror", BinOpFrag<(rotr node:$LHS, node:$RHS)>>;
758 def t2MOVrx : T2sI<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
759 "rrx", ".w $dst, $src",
760 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
762 let Defs = [CPSR] in {
763 def t2MOVsrl_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
764 "lsrs.w $dst, $src, #1",
765 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
766 def t2MOVsra_flag : T2XI<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
767 "asrs.w $dst, $src, #1",
768 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
771 //===----------------------------------------------------------------------===//
772 // Bitwise Instructions.
775 defm t2AND : T2I_bin_w_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
776 defm t2ORR : T2I_bin_w_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
777 defm t2EOR : T2I_bin_w_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
779 defm t2BIC : T2I_bin_w_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
781 let Constraints = "$src = $dst" in
782 def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm), IIC_iALU,
783 "bfc", " $dst, $imm",
784 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
786 // FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
788 defm t2ORN : T2I_bin_irs<"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
790 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version
791 let AddedComplexity = 1 in
792 defm t2MVN : T2I_un_irs <"mvn", UnOpFrag<(not node:$Src)>, 1, 1>;
795 def : T2Pat<(and GPR:$src, t2_so_imm_not:$imm),
796 (t2BICri GPR:$src, t2_so_imm_not:$imm)>;
798 // FIXME: Disable this pattern on Darwin to workaround an assembler bug.
799 def : T2Pat<(or GPR:$src, t2_so_imm_not:$imm),
800 (t2ORNri GPR:$src, t2_so_imm_not:$imm)>,
801 Requires<[IsThumb2]>;
803 def : T2Pat<(t2_so_imm_not:$src),
804 (t2MVNi t2_so_imm_not:$src)>;
806 //===----------------------------------------------------------------------===//
807 // Multiply Instructions.
809 let isCommutable = 1 in
810 def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYw,
811 "mul", " $dst, $a, $b",
812 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
814 def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMPYw,
815 "mla", " $dst, $a, $b, $c",
816 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
818 def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMPYw,
819 "mls", " $dst, $a, $b, $c",
820 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
822 // Extra precision multiplies with low / high results
823 let neverHasSideEffects = 1 in {
824 let isCommutable = 1 in {
825 def t2SMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMPYl,
826 "smull", " $ldst, $hdst, $a, $b", []>;
828 def t2UMULL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMPYl,
829 "umull", " $ldst, $hdst, $a, $b", []>;
832 // Multiply + accumulate
833 def t2SMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMPYl,
834 "smlal", " $ldst, $hdst, $a, $b", []>;
836 def t2UMLAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMPYl,
837 "umlal", " $ldst, $hdst, $a, $b", []>;
839 def t2UMAAL : T2I<(outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), IIC_iMPYl,
840 "umaal", " $ldst, $hdst, $a, $b", []>;
841 } // neverHasSideEffects
843 // Most significant word multiply
844 def t2SMMUL : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYw,
845 "smmul", " $dst, $a, $b",
846 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>;
848 def t2SMMLA : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMPYw,
849 "smmla", " $dst, $a, $b, $c",
850 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>;
853 def t2SMMLS : T2I <(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), IIC_iMPYw,
854 "smmls", " $dst, $a, $b, $c",
855 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>;
857 multiclass T2I_smul<string opc, PatFrag opnode> {
858 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYw,
859 !strconcat(opc, "bb"), " $dst, $a, $b",
860 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
861 (sext_inreg GPR:$b, i16)))]>;
863 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYw,
864 !strconcat(opc, "bt"), " $dst, $a, $b",
865 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
866 (sra GPR:$b, (i32 16))))]>;
868 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYw,
869 !strconcat(opc, "tb"), " $dst, $a, $b",
870 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
871 (sext_inreg GPR:$b, i16)))]>;
873 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYw,
874 !strconcat(opc, "tt"), " $dst, $a, $b",
875 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
876 (sra GPR:$b, (i32 16))))]>;
878 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYh,
879 !strconcat(opc, "wb"), " $dst, $a, $b",
880 [(set GPR:$dst, (sra (opnode GPR:$a,
881 (sext_inreg GPR:$b, i16)), (i32 16)))]>;
883 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b), IIC_iMPYh,
884 !strconcat(opc, "wt"), " $dst, $a, $b",
885 [(set GPR:$dst, (sra (opnode GPR:$a,
886 (sra GPR:$b, (i32 16))), (i32 16)))]>;
890 multiclass T2I_smla<string opc, PatFrag opnode> {
891 def BB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMPYw,
892 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
893 [(set GPR:$dst, (add GPR:$acc,
894 (opnode (sext_inreg GPR:$a, i16),
895 (sext_inreg GPR:$b, i16))))]>;
897 def BT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMPYw,
898 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
899 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
900 (sra GPR:$b, (i32 16)))))]>;
902 def TB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMPYw,
903 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
904 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
905 (sext_inreg GPR:$b, i16))))]>;
907 def TT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMPYw,
908 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
909 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
910 (sra GPR:$b, (i32 16)))))]>;
912 def WB : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMPYw,
913 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
914 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
915 (sext_inreg GPR:$b, i16)), (i32 16))))]>;
917 def WT : T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), IIC_iMPYw,
918 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
919 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
920 (sra GPR:$b, (i32 16))), (i32 16))))]>;
923 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
924 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
926 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
927 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
930 //===----------------------------------------------------------------------===//
931 // Misc. Arithmetic Instructions.
934 def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
935 "clz", " $dst, $src",
936 [(set GPR:$dst, (ctlz GPR:$src))]>;
938 def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
939 "rev", ".w $dst, $src",
940 [(set GPR:$dst, (bswap GPR:$src))]>;
942 def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
943 "rev16", ".w $dst, $src",
945 (or (and (srl GPR:$src, (i32 8)), 0xFF),
946 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
947 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
948 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
950 def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
951 "revsh", ".w $dst, $src",
954 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
955 (shl GPR:$src, (i32 8))), i16))]>;
957 def t2PKHBT : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
958 IIC_iALU, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
959 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
960 (and (shl GPR:$src2, (i32 imm:$shamt)),
963 // Alternate cases for PKHBT where identities eliminate some nodes.
964 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
965 (t2PKHBT GPR:$src1, GPR:$src2, 0)>;
966 def : T2Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
967 (t2PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
969 def t2PKHTB : T2I<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
970 IIC_iALU, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
971 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
972 (and (sra GPR:$src2, imm16_31:$shamt),
975 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
976 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
977 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
978 (t2PKHTB GPR:$src1, GPR:$src2, 16)>;
979 def : T2Pat<(or (and GPR:$src1, 0xFFFF0000),
980 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
981 (t2PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
983 //===----------------------------------------------------------------------===//
984 // Comparison Instructions...
987 defm t2CMP : T2I_cmp_is<"cmp",
988 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
989 defm t2CMPz : T2I_cmp_is<"cmp",
990 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
992 defm t2CMN : T2I_cmp_is<"cmn",
993 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
994 defm t2CMNz : T2I_cmp_is<"cmn",
995 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
997 def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
998 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1000 def : T2Pat<(ARMcmpZ GPR:$src, t2_so_imm_neg:$imm),
1001 (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
1003 defm t2TST : T2I_cmp_is<"tst",
1004 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>>;
1005 defm t2TEQ : T2I_cmp_is<"teq",
1006 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>>;
1008 // A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
1009 // Short range conditional branch. Looks awesome for loops. Need to figure
1010 // out how to use this one.
1013 // Conditional moves
1014 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1015 // a two-value operand where a dag node expects two operands. :(
1016 def t2MOVCCr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true), IIC_iALU,
1017 "mov", ".w $dst, $true",
1018 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1019 RegConstraint<"$false = $dst">;
1021 def t2MOVCCi : T2I<(outs GPR:$dst), (ins GPR:$false, t2_so_imm:$true), IIC_iALU,
1022 "mov", ".w $dst, $true",
1023 [/*(set GPR:$dst, (ARMcmov GPR:$false, t2_so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1024 RegConstraint<"$false = $dst">;
1026 def t2MOVCClsl : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1027 IIC_iALU, "lsl", ".w $dst, $true, $rhs", []>,
1028 RegConstraint<"$false = $dst">;
1029 def t2MOVCClsr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1030 IIC_iALU, "lsr", ".w $dst, $true, $rhs", []>,
1031 RegConstraint<"$false = $dst">;
1032 def t2MOVCCasr : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1033 IIC_iALU, "asr", ".w $dst, $true, $rhs", []>,
1034 RegConstraint<"$false = $dst">;
1035 def t2MOVCCror : T2I<(outs GPR:$dst), (ins GPR:$false, GPR:$true, i32imm:$rhs),
1036 IIC_iALU, "ror", ".w $dst, $true, $rhs", []>,
1037 RegConstraint<"$false = $dst">;
1039 //===----------------------------------------------------------------------===//
1043 // __aeabi_read_tp preserves the registers r1-r3.
1045 Defs = [R0, R12, LR, CPSR] in {
1046 def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
1047 "bl __aeabi_read_tp",
1048 [(set R0, ARMthread_pointer)]>;
1051 //===----------------------------------------------------------------------===//
1052 // SJLJ Exception handling intrinsics
1053 // eh_sjlj_setjmp() is an instruction sequence to store the return
1054 // address and save #0 in R0 for the non-longjmp case.
1055 // Since by its nature we may be coming from some other function to get
1056 // here, and we're using the stack frame for the containing function to
1057 // save/restore registers, we can't keep anything live in regs across
1058 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1059 // when we get here from a longjmp(). We force everthing out of registers
1060 // except for our own input by listing the relevant registers in Defs. By
1061 // doing so, we also cause the prologue/epilogue code to actively preserve
1062 // all of the callee-saved resgisters, which is exactly what we want.
1064 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
1065 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
1066 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
1068 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins GPR:$src),
1069 AddrModeNone, SizeSpecial, NoItinerary,
1070 "str.w sp, [$src, #+8] @ eh_setjmp begin\n"
1073 "\tstr.w r12, [$src, #+4]\n"
1076 "0:\tmovs r0, #1 @ eh_setjmp end\n"
1078 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1083 //===----------------------------------------------------------------------===//
1084 // Control-Flow Instructions
1087 // FIXME: remove when we have a way to marking a MI with these properties.
1088 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
1090 // FIXME: Should pc be an implicit operand like PICADD, etc?
1091 let isReturn = 1, isTerminator = 1, mayLoad = 1 in
1092 def t2LDM_RET : T2XI<(outs),
1093 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
1094 IIC_Br, "ldm${addr:submode}${p}${addr:wide} $addr, $dst1",
1097 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1098 let isPredicable = 1 in
1099 def t2B : T2XI<(outs), (ins brtarget:$target), IIC_Br,
1103 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1106 (ins GPR:$target, GPR:$index, jt2block_operand:$jt, i32imm:$id),
1107 IIC_Br, "mov pc, $target\n$jt",
1108 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>;
1110 // FIXME: Add a non-pc based case that can be predicated.
1113 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
1114 IIC_Br, "tbb $index\n$jt", []>;
1118 (ins tb_addrmode:$index, jt2block_operand:$jt, i32imm:$id),
1119 IIC_Br, "tbh $index\n$jt", []>;
1120 } // isNotDuplicable, isIndirectBranch
1122 } // isBranch, isTerminator, isBarrier
1124 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1125 // a two-value operand where a dag node expects two operands. :(
1126 let isBranch = 1, isTerminator = 1 in
1127 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br,
1129 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
1133 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
1134 AddrModeNone, Size2Bytes, IIC_iALU,
1135 "it$mask $cc", "", []>;
1137 //===----------------------------------------------------------------------===//
1138 // Non-Instruction Patterns
1141 // ConstantPool, GlobalAddress, and JumpTable
1142 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
1143 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
1144 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1145 (t2LEApcrelJT tjumptable:$dst, imm:$id)>;
1147 // Large immediate handling.
1149 def : T2Pat<(i32 imm:$src),
1150 (t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)), (t2_hi16 imm:$src))>;