1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Define Thumb specific addressing modes.
71 // t_addrmode_rr := reg + reg
73 def t_addrmode_rr : Operand<i32>,
74 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
75 let PrintMethod = "printThumbAddrModeRROperand";
76 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
79 // t_addrmode_s4 := reg + reg
82 def t_addrmode_s4 : Operand<i32>,
83 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
84 let PrintMethod = "printThumbAddrModeS4Operand";
85 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
88 // t_addrmode_s2 := reg + reg
91 def t_addrmode_s2 : Operand<i32>,
92 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
93 let PrintMethod = "printThumbAddrModeS2Operand";
94 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
97 // t_addrmode_s1 := reg + reg
100 def t_addrmode_s1 : Operand<i32>,
101 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
102 let PrintMethod = "printThumbAddrModeS1Operand";
103 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
106 // t_addrmode_sp := sp + imm8 * 4
108 def t_addrmode_sp : Operand<i32>,
109 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
110 let PrintMethod = "printThumbAddrModeSPOperand";
111 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
114 //===----------------------------------------------------------------------===//
115 // Miscellaneous Instructions.
118 let Defs = [SP], Uses = [SP] in {
119 def tADJCALLSTACKUP :
120 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
121 "@ tADJCALLSTACKUP $amt1",
122 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb]>;
124 def tADJCALLSTACKDOWN :
125 PseudoInst<(outs), (ins i32imm:$amt),
126 "@ tADJCALLSTACKDOWN $amt",
127 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb]>;
130 let isNotDuplicable = 1 in
131 def tPICADD : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
132 "$cp:\n\tadd $dst, pc",
133 [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
135 //===----------------------------------------------------------------------===//
136 // Control Flow Instructions.
139 let isReturn = 1, isTerminator = 1 in {
140 def tBX_RET : TI<(outs), (ins), "bx lr", [(ARMretflag)]>;
141 // Alternative return instruction used by vararg functions.
142 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), "bx $target", []>;
145 // FIXME: remove when we have a way to marking a MI with these properties.
146 let isReturn = 1, isTerminator = 1 in
147 def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins),
151 Defs = [R0, R1, R2, R3, LR,
152 D0, D1, D2, D3, D4, D5, D6, D7] in {
153 def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops),
155 [(ARMtcall tglobaladdr:$func)]>;
157 def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops),
159 [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
160 def tBLXr : TI<(outs), (ins tGPR:$func, variable_ops),
162 [(ARMtcall tGPR:$func)]>, Requires<[HasV5T]>;
164 def tBX : TIx2<(outs), (ins tGPR:$func, variable_ops),
165 "cpy lr, pc\n\tbx $func",
166 [(ARMcall_nolink tGPR:$func)]>;
169 let isBranch = 1, isTerminator = 1 in {
170 let isBarrier = 1 in {
171 let isPredicable = 1 in
172 def tB : TI<(outs), (ins brtarget:$target), "b $target",
176 def tBfar : TIx2<(outs), (ins brtarget:$target), "bl $target\t@ far jump",[]>;
178 def tBR_JTr : TJTI<(outs),
179 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
180 "cpy pc, $target \n\t.align\t2\n$jt",
181 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
185 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
186 // a two-value operand where a dag node expects two operands. :(
187 let isBranch = 1, isTerminator = 1 in
188 def tBcc : TI<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target",
189 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
191 //===----------------------------------------------------------------------===//
192 // Load Store Instructions.
195 let canFoldAsLoad = 1 in
196 def tLDR : TI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr),
198 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
200 def tLDRB : TI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr),
202 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
204 def tLDRH : TI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr),
206 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
208 def tLDRSB : TI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
210 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
212 def tLDRSH : TI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
214 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
216 let canFoldAsLoad = 1 in
217 def tLDRspi : TIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
219 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
221 // Special instruction for restore. It cannot clobber condition register
222 // when it's expanded by eliminateCallFramePseudoInstr().
223 let canFoldAsLoad = 1, mayLoad = 1 in
224 def tRestore : TIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
225 "ldr $dst, $addr", []>;
228 let canFoldAsLoad = 1 in
229 def tLDRpci : TIs<(outs tGPR:$dst), (ins i32imm:$addr),
231 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
233 // Special LDR for loads from non-pc-relative constpools.
234 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
235 def tLDRcp : TIs<(outs tGPR:$dst), (ins i32imm:$addr),
236 "ldr $dst, $addr", []>;
238 def tSTR : TI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr),
240 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
242 def tSTRB : TI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr),
244 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
246 def tSTRH : TI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr),
248 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
250 def tSTRspi : TIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
252 [(store tGPR:$src, t_addrmode_sp:$addr)]>;
254 let mayStore = 1 in {
255 // Special instruction for spill. It cannot clobber condition register
256 // when it's expanded by eliminateCallFramePseudoInstr().
257 def tSpill : TIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
258 "str $src, $addr", []>;
261 //===----------------------------------------------------------------------===//
262 // Load / store multiple Instructions.
265 // TODO: A7-44: LDMIA - load multiple
268 def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
272 def tPUSH : TI<(outs), (ins reglist:$src1, variable_ops),
275 //===----------------------------------------------------------------------===//
276 // Arithmetic Instructions.
280 let isCommutable = 1 in
281 def tADC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
283 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
285 def tADDS : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
286 "add $dst, $lhs, $rhs",
287 [(set tGPR:$dst, (addc tGPR:$lhs, tGPR:$rhs))]>;
290 def tADDi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
291 "add $dst, $lhs, $rhs",
292 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
294 def tADDi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
296 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
298 def tADDrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
299 "add $dst, $lhs, $rhs",
300 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
302 let neverHasSideEffects = 1 in
303 def tADDhirr : T1It<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs),
304 "add $dst, $rhs @ addhirr", []>;
306 def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs),
307 "add $dst, pc, $rhs * 4", []>;
309 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs),
310 "add $dst, $sp, $rhs * 4 @ addrspi", []>;
312 def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
313 "add $dst, $rhs * 4", []>;
315 let isCommutable = 1 in
316 def tAND : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
318 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
320 def tASRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
321 "asr $dst, $lhs, $rhs",
322 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
324 def tASRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
326 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
328 def tBIC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
330 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
333 def tCMN : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
335 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
337 def tCMPi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs),
339 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
341 def tCMPr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
343 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
345 def tTST : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
347 [(ARMcmpNZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
349 def tCMNNZ : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
351 [(ARMcmpNZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
353 def tCMPNZi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs),
355 [(ARMcmpNZ tGPR:$lhs, imm0_255:$rhs)]>;
357 def tCMPNZr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
359 [(ARMcmpNZ tGPR:$lhs, tGPR:$rhs)]>;
361 // TODO: A7-37: CMP(3) - cmp hi regs
363 let isCommutable = 1 in
364 def tEOR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
366 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
368 def tLSLri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
369 "lsl $dst, $lhs, $rhs",
370 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
372 def tLSLrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
374 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
376 def tLSRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
377 "lsr $dst, $lhs, $rhs",
378 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
380 def tLSRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
382 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
384 // FIXME: This is not rematerializable because mov changes the condition code.
385 def tMOVi8 : T1I<(outs tGPR:$dst), (ins i32imm:$src),
387 [(set tGPR:$dst, imm0_255:$src)]>;
389 // TODO: A7-73: MOV(2) - mov setting flag.
392 // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
393 // which is MOV(3). This also supports high registers.
394 let neverHasSideEffects = 1 in {
395 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src),
396 "cpy $dst, $src", []>;
397 def tMOVhir2lor : T1I<(outs tGPR:$dst), (ins GPR:$src),
398 "cpy $dst, $src\t@ hir2lor", []>;
399 def tMOVlor2hir : T1I<(outs GPR:$dst), (ins tGPR:$src),
400 "cpy $dst, $src\t@ lor2hir", []>;
401 def tMOVhir2hir : T1I<(outs GPR:$dst), (ins GPR:$src),
402 "cpy $dst, $src\t@ hir2hir", []>;
403 } // neverHasSideEffects
405 let isCommutable = 1 in
406 def tMUL : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
408 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
410 def tMVN : T1I<(outs tGPR:$dst), (ins tGPR:$src),
412 [(set tGPR:$dst, (not tGPR:$src))]>;
414 def tNEG : T1I<(outs tGPR:$dst), (ins tGPR:$src),
416 [(set tGPR:$dst, (ineg tGPR:$src))]>;
418 let isCommutable = 1 in
419 def tORR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
421 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
424 def tREV : T1I<(outs tGPR:$dst), (ins tGPR:$src),
426 [(set tGPR:$dst, (bswap tGPR:$src))]>,
427 Requires<[IsThumb, HasV6]>;
429 def tREV16 : T1I<(outs tGPR:$dst), (ins tGPR:$src),
432 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
433 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
434 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
435 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
436 Requires<[IsThumb, HasV6]>;
438 def tREVSH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
442 (or (srl (and tGPR:$src, 0xFFFF), (i32 8)),
443 (shl tGPR:$src, (i32 8))), i16))]>,
444 Requires<[IsThumb, HasV6]>;
446 def tROR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
448 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
451 // Subtract with carry
452 def tSBC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
454 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
456 def tSUBS : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
457 "sub $dst, $lhs, $rhs",
458 [(set tGPR:$dst, (subc tGPR:$lhs, tGPR:$rhs))]>;
461 // TODO: A7-96: STMIA - store multiple.
463 def tSUBi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
464 "sub $dst, $lhs, $rhs",
465 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
467 def tSUBi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
469 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
471 def tSUBrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
472 "sub $dst, $lhs, $rhs",
473 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
475 def tSUBspi : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
476 "sub $dst, $rhs * 4", []>;
478 def tSXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src),
480 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
481 Requires<[IsThumb, HasV6]>;
482 def tSXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
484 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
485 Requires<[IsThumb, HasV6]>;
488 def tUXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src),
490 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
491 Requires<[IsThumb, HasV6]>;
492 def tUXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
494 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
495 Requires<[IsThumb, HasV6]>;
498 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
499 // Expanded by the scheduler into a branch sequence.
500 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
502 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
504 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
506 // tLEApcrel - Load a pc-relative address into a register without offending the
508 def tLEApcrel : TIx2<(outs tGPR:$dst), (ins i32imm:$label),
509 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
510 "${:private}PCRELL${:uid}+4))\n"),
511 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
512 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
515 def tLEApcrelJT : TIx2<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id),
516 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
517 "${:private}PCRELL${:uid}+4))\n"),
518 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
519 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
522 //===----------------------------------------------------------------------===//
526 // __aeabi_read_tp preserves the registers r1-r3.
529 def tTPsoft : TIx2<(outs), (ins),
530 "bl __aeabi_read_tp",
531 [(set R0, ARMthread_pointer)]>;
534 //===----------------------------------------------------------------------===//
535 // Non-Instruction Patterns
538 // ConstantPool, GlobalAddress
539 def : ThumbPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
540 def : ThumbPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
543 def : ThumbPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
544 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
547 def : ThumbPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
548 def : ThumbV5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
550 // Indirect calls to ARM routines
551 def : ThumbV5Pat<(ARMcall tGPR:$dst), (tBLXr tGPR:$dst)>;
553 // zextload i1 -> zextload i8
554 def : ThumbPat<(zextloadi1 t_addrmode_s1:$addr),
555 (tLDRB t_addrmode_s1:$addr)>;
557 // extload -> zextload
558 def : ThumbPat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
559 def : ThumbPat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
560 def : ThumbPat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
562 // Large immediate handling.
565 def : Thumb1Pat<(i32 thumb_immshifted:$src),
566 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
567 (thumb_immshifted_shamt imm:$src))>;
569 def : Thumb1Pat<(i32 imm0_255_comp:$src),
570 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;