1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
30 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
31 def imm0_7 : PatLeaf<(i32 imm), [{
32 return (uint32_t)N->getZExtValue() < 8;
34 def imm0_7_neg : PatLeaf<(i32 imm), [{
35 return (uint32_t)-N->getZExtValue() < 8;
38 def imm0_255 : PatLeaf<(i32 imm), [{
39 return (uint32_t)N->getZExtValue() < 256;
41 def imm0_255_comp : PatLeaf<(i32 imm), [{
42 return ~((uint32_t)N->getZExtValue()) < 256;
45 def imm8_255 : PatLeaf<(i32 imm), [{
46 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
48 def imm8_255_neg : PatLeaf<(i32 imm), [{
49 unsigned Val = -N->getZExtValue();
50 return Val >= 8 && Val < 256;
53 // Break imm's up into two pieces: an immediate + a left shift. This uses
54 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
55 // to get the val/shift pieces.
56 def thumb_immshifted : PatLeaf<(imm), [{
57 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
60 def thumb_immshifted_val : SDNodeXForm<imm, [{
61 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
62 return CurDAG->getTargetConstant(V, MVT::i32);
65 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 // Scaled 4 immediate.
71 def t_imm_s4 : Operand<i32> {
72 let PrintMethod = "printThumbS4ImmOperand";
75 // Define Thumb specific addressing modes.
77 def MemModeThumbAsmOperand : AsmOperandClass {
78 let Name = "MemModeThumb";
79 let SuperClasses = [];
82 // t_addrmode_rr := reg + reg
84 def t_addrmode_rr : Operand<i32>,
85 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
86 let PrintMethod = "printThumbAddrModeRROperand";
87 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
90 // t_addrmode_s4 := reg + reg
93 def t_addrmode_s4 : Operand<i32>,
94 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
95 let EncoderMethod = "getAddrModeS4OpValue";
96 let PrintMethod = "printThumbAddrModeS4Operand";
97 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
98 let ParserMatchClass = MemModeThumbAsmOperand;
101 // t_addrmode_s2 := reg + reg
104 def t_addrmode_s2 : Operand<i32>,
105 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
106 let EncoderMethod = "getAddrModeS2OpValue";
107 let PrintMethod = "printThumbAddrModeS2Operand";
108 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
109 let ParserMatchClass = MemModeThumbAsmOperand;
112 // t_addrmode_s1 := reg + reg
115 def t_addrmode_s1 : Operand<i32>,
116 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
117 let EncoderMethod = "getAddrModeS1OpValue";
118 let PrintMethod = "printThumbAddrModeS1Operand";
119 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
120 let ParserMatchClass = MemModeThumbAsmOperand;
123 // t_addrmode_sp := sp + imm8 * 4
125 def t_addrmode_sp : Operand<i32>,
126 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
127 let PrintMethod = "printThumbAddrModeSPOperand";
128 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
129 let ParserMatchClass = MemModeThumbAsmOperand;
132 //===----------------------------------------------------------------------===//
133 // Miscellaneous Instructions.
136 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
137 // from removing one half of the matched pairs. That breaks PEI, which assumes
138 // these will always be in pairs, and asserts if it finds otherwise. Better way?
139 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
140 def tADJCALLSTACKUP :
141 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
142 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
143 Requires<[IsThumb, IsThumb1Only]>;
145 def tADJCALLSTACKDOWN :
146 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
147 [(ARMcallseq_start imm:$amt)]>,
148 Requires<[IsThumb, IsThumb1Only]>;
151 // T1Disassembly - A simple class to make encoding some disassembly patterns
152 // easier and less verbose.
153 class T1Disassembly<bits<2> op1, bits<8> op2>
154 : T1Encoding<0b101111> {
159 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
160 [/* For disassembly only; pattern left blank */]>,
161 T1Disassembly<0b11, 0x00>; // A8.6.110
163 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
164 [/* For disassembly only; pattern left blank */]>,
165 T1Disassembly<0b11, 0x10>; // A8.6.410
167 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
168 [/* For disassembly only; pattern left blank */]>,
169 T1Disassembly<0b11, 0x20>; // A8.6.408
171 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
172 [/* For disassembly only; pattern left blank */]>,
173 T1Disassembly<0b11, 0x30>; // A8.6.409
175 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
176 [/* For disassembly only; pattern left blank */]>,
177 T1Disassembly<0b11, 0x40>; // A8.6.157
179 // The i32imm operand $val can be used by a debugger to store more information
180 // about the breakpoint.
181 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
182 [/* For disassembly only; pattern left blank */]>,
183 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
189 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
190 [/* For disassembly only; pattern left blank */]>,
191 T1Encoding<0b101101> {
193 let Inst{9-5} = 0b10010;
195 let Inst{3} = 1; // Big-Endian
196 let Inst{2-0} = 0b000;
199 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
200 [/* For disassembly only; pattern left blank */]>,
201 T1Encoding<0b101101> {
203 let Inst{9-5} = 0b10010;
205 let Inst{3} = 0; // Little-Endian
206 let Inst{2-0} = 0b000;
209 // Change Processor State is a system instruction -- for disassembly only.
210 // The singleton $opt operand contains the following information:
212 // opt{4-0} = mode ==> don't care
213 // opt{5} = changemode ==> 0 (false for 16-bit Thumb instr)
214 // opt{8-6} = AIF from Inst{2-0}
215 // opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
217 // The opt{4-0} and opt{5} sub-fields are to accommodate 32-bit Thumb and ARM
218 // CPS which has more options.
219 def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt",
220 [/* For disassembly only; pattern left blank */]>,
224 // FIXME: Finish encoding.
227 // For both thumb1 and thumb2.
228 let isNotDuplicable = 1, isCodeGenOnly = 1 in
229 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
230 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
231 T1Special<{0,0,?,?}> {
234 let Inst{6-3} = 0b1111; // Rm = pc
238 // PC relative add (ADR).
239 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
240 "add\t$dst, pc, $rhs", []>,
241 T1Encoding<{1,0,1,0,0,?}> {
245 let Inst{10-8} = dst;
249 // ADD <Rd>, sp, #<imm8>
250 // This is rematerializable, which is particularly useful for taking the
251 // address of locals.
252 let isReMaterializable = 1 in
253 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
254 "add\t$dst, $sp, $rhs", []>,
255 T1Encoding<{1,0,1,0,1,?}> {
259 let Inst{10-8} = dst;
263 // ADD sp, sp, #<imm7>
264 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
265 "add\t$dst, $rhs", []>,
266 T1Misc<{0,0,0,0,0,?,?}> {
272 // SUB sp, sp, #<imm7>
273 // FIXME: The encoding and the ASM string don't match up.
274 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
275 "sub\t$dst, $rhs", []>,
276 T1Misc<{0,0,0,0,1,?,?}> {
283 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
284 "add\t$dst, $rhs", []>,
285 T1Special<{0,0,?,?}> {
286 // A8.6.9 Encoding T1
288 let Inst{7} = dst{3};
289 let Inst{6-3} = 0b1101;
290 let Inst{2-0} = dst{2-0};
294 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
295 "add\t$dst, $rhs", []>,
296 T1Special<{0,0,?,?}> {
297 // A8.6.9 Encoding T2
301 let Inst{2-0} = 0b101;
304 //===----------------------------------------------------------------------===//
305 // Control Flow Instructions.
308 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
309 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
311 T1Special<{1,1,0,?}> {
313 let Inst{6-3} = 0b1110; // Rm = lr
314 let Inst{2-0} = 0b000;
317 // Alternative return instruction used by vararg functions.
318 def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
321 T1Special<{1,1,0,?}> {
325 let Inst{2-0} = 0b000;
330 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
331 def tBRIND : TI<(outs), (ins GPR:$Rm),
335 T1Special<{1,0,?,?}> {
338 let Inst{7} = 1; // <Rd> = Inst{7:2-0} = pc
340 let Inst{2-0} = 0b111;
344 // FIXME: remove when we have a way to marking a MI with these properties.
345 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
346 hasExtraDefRegAllocReq = 1 in
347 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
349 "pop${p}\t$regs", []>,
350 T1Misc<{1,1,0,?,?,?,?}> {
353 let Inst{8} = regs{15}; // registers = P:'0000000':register_list
354 let Inst{7-0} = regs{7-0};
357 // All calls clobber the non-callee saved registers. SP is marked as a use to
358 // prevent stack-pointer assignments that appear immediately before calls from
359 // potentially appearing dead.
361 // On non-Darwin platforms R9 is callee-saved.
362 Defs = [R0, R1, R2, R3, R12, LR,
363 D0, D1, D2, D3, D4, D5, D6, D7,
364 D16, D17, D18, D19, D20, D21, D22, D23,
365 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
367 // Also used for Thumb2
368 def tBL : TIx2<0b11110, 0b11, 1,
369 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
371 [(ARMtcall tglobaladdr:$func)]>,
372 Requires<[IsThumb, IsNotDarwin]> {
377 // ARMv5T and above, also used for Thumb2
378 def tBLXi : TIx2<0b11110, 0b11, 0,
379 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
381 [(ARMcall tglobaladdr:$func)]>,
382 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
387 // Also used for Thumb2
388 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
390 [(ARMtcall GPR:$func)]>,
391 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
392 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
395 // FIXME: Should be a pseudo.
396 let isCodeGenOnly = 1 in
397 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
398 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
399 "mov\tlr, pc\n\tbx\t$func",
400 [(ARMcall_nolink tGPR:$func)]>,
401 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
405 // On Darwin R9 is call-clobbered.
406 // R7 is marked as a use to prevent frame-pointer assignments from being
407 // moved above / below calls.
408 Defs = [R0, R1, R2, R3, R9, R12, LR,
409 D0, D1, D2, D3, D4, D5, D6, D7,
410 D16, D17, D18, D19, D20, D21, D22, D23,
411 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
413 // Also used for Thumb2
414 def tBLr9 : TIx2<0b11110, 0b11, 1,
415 (outs), (ins pred:$p, i32imm:$func, variable_ops), IIC_Br,
417 [(ARMtcall tglobaladdr:$func)]>,
418 Requires<[IsThumb, IsDarwin]> {
423 // ARMv5T and above, also used for Thumb2
424 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
425 (outs), (ins pred:$p, i32imm:$func, variable_ops), IIC_Br,
427 [(ARMcall tglobaladdr:$func)]>,
428 Requires<[IsThumb, HasV5T, IsDarwin]> {
433 // Also used for Thumb2
434 def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
436 [(ARMtcall GPR:$func)]>,
437 Requires<[IsThumb, HasV5T, IsDarwin]>,
438 T1Special<{1,1,1,?}> {
441 let Inst{6-3} = func;
442 let Inst{2-0} = 0b000;
446 let isCodeGenOnly = 1 in
447 // FIXME: Should be a pseudo.
448 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
449 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
450 "mov\tlr, pc\n\tbx\t$func",
451 [(ARMcall_nolink tGPR:$func)]>,
452 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
455 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
456 let isPredicable = 1 in
457 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
458 "b\t$target", [(br bb:$target)]>,
459 T1Encoding<{1,1,1,0,0,?}>;
463 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
466 def tBR_JTr : tPseudoInst<(outs),
467 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
469 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
470 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
474 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
475 // a two-value operand where a dag node expects two operands. :(
476 let isBranch = 1, isTerminator = 1 in
477 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
479 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
480 T1Encoding<{1,1,0,1,?,?}>;
482 // Compare and branch on zero / non-zero
483 let isBranch = 1, isTerminator = 1 in {
484 def tCBZ : T1I<(outs), (ins tGPR:$Rn, brtarget:$target), IIC_Br,
485 "cbz\t$Rn, $target", []>,
486 T1Misc<{0,0,?,1,?,?,?}> {
490 let Inst{9} = target{5};
491 let Inst{7-3} = target{4-0};
495 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
496 "cbnz\t$cmp, $target", []>,
497 T1Misc<{1,0,?,1,?,?,?}> {
501 let Inst{9} = target{5};
502 let Inst{7-3} = target{4-0};
507 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
508 // A8.6.16 B: Encoding T1
509 // If Inst{11-8} == 0b1111 then SEE SVC
510 let isCall = 1, Uses = [SP] in
511 def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
512 "svc", "\t$imm", []>, Encoding16 {
514 let Inst{15-12} = 0b1101;
515 let Inst{11-8} = 0b1111;
519 // The assembler uses 0xDEFE for a trap instruction.
520 let isBarrier = 1, isTerminator = 1 in
521 def tTRAP : TI<(outs), (ins), IIC_Br,
522 "trap", [(trap)]>, Encoding16 {
526 //===----------------------------------------------------------------------===//
527 // Load Store Instructions.
530 let canFoldAsLoad = 1, isReMaterializable = 1 in
531 def tLDR : // A8.6.60
532 T1pILdStEncode<0b100, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
533 AddrModeT1_4, IIC_iLoad_r,
534 "ldr", "\t$Rt, $addr",
535 [(set tGPR:$Rt, (load t_addrmode_s4:$addr))]>;
537 def tLDRi: // A8.6.57
538 T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
539 AddrModeT1_4, IIC_iLoad_r,
540 "ldr", "\t$Rt, $addr",
543 def tLDRB : // A8.6.64
544 T1pILdStEncode<0b110, (outs tGPR:$Rt), (ins t_addrmode_s1:$addr),
545 AddrModeT1_1, IIC_iLoad_bh_r,
546 "ldrb", "\t$Rt, $addr",
547 [(set tGPR:$Rt, (zextloadi8 t_addrmode_s1:$addr))]>;
549 def tLDRBi : // A8.6.61
550 T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$dst), (ins t_addrmode_s1:$addr),
551 AddrModeT1_1, IIC_iLoad_bh_r,
552 "ldrb", "\t$dst, $addr",
555 def tLDRH : // A8.6.76
556 T1pILdStEncode<0b101, (outs tGPR:$dst), (ins t_addrmode_s2:$addr),
557 AddrModeT1_2, IIC_iLoad_bh_r,
558 "ldrh", "\t$dst, $addr",
559 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
561 def tLDRHi: // A8.6.73
562 T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$dst), (ins t_addrmode_s2:$addr),
563 AddrModeT1_2, IIC_iLoad_bh_r,
564 "ldrh", "\t$dst, $addr",
567 let AddedComplexity = 10 in
568 def tLDRSB : // A8.6.80
569 T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
570 AddrModeT1_1, IIC_iLoad_bh_r,
571 "ldrsb", "\t$dst, $addr",
572 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
574 let AddedComplexity = 10 in
575 def tLDRSH : // A8.6.84
576 T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
577 AddrModeT1_2, IIC_iLoad_bh_r,
578 "ldrsh", "\t$dst, $addr",
579 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
581 let canFoldAsLoad = 1 in
582 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
583 "ldr", "\t$dst, $addr",
584 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
587 // Special instruction for restore. It cannot clobber condition register
588 // when it's expanded by eliminateCallFramePseudoInstr().
589 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
590 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
591 "ldr", "\t$dst, $addr", []>,
595 // FIXME: Use ldr.n to work around a Darwin assembler bug.
596 let canFoldAsLoad = 1, isReMaterializable = 1 in
597 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins i32imm:$addr), IIC_iLoad_i,
598 "ldr", ".n\t$Rt, $addr",
599 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
600 T1Encoding<{0,1,0,0,1,?}> {
604 // FIXME: Finish for the addr.
607 // Special LDR for loads from non-pc-relative constpools.
608 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
609 isReMaterializable = 1 in
610 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
611 "ldr", "\t$dst, $addr", []>,
614 def tSTR : // A8.6.194
615 T1pILdStEncode<0b000, (outs), (ins tGPR:$src, t_addrmode_s4:$addr),
616 AddrModeT1_4, IIC_iStore_r,
617 "str", "\t$src, $addr",
618 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
620 def tSTRi : // A8.6.192
621 T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$src, t_addrmode_s4:$addr),
622 AddrModeT1_4, IIC_iStore_r,
623 "str", "\t$src, $addr",
626 def tSTRB : // A8.6.197
627 T1pILdStEncode<0b010, (outs), (ins tGPR:$src, t_addrmode_s1:$addr),
628 AddrModeT1_1, IIC_iStore_bh_r,
629 "strb", "\t$src, $addr",
630 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
632 def tSTRBi : // A8.6.195
633 T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$src, t_addrmode_s1:$addr),
634 AddrModeT1_1, IIC_iStore_bh_r,
635 "strb", "\t$src, $addr",
638 def tSTRH : // A8.6.207
639 T1pILdStEncode<0b001, (outs), (ins tGPR:$src, t_addrmode_s2:$addr),
640 AddrModeT1_2, IIC_iStore_bh_r,
641 "strh", "\t$src, $addr",
642 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
644 def tSTRHi : // A8.6.205
645 T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$src, t_addrmode_s2:$addr),
646 AddrModeT1_2, IIC_iStore_bh_r,
647 "strh", "\t$src, $addr",
650 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
651 "str", "\t$src, $addr",
652 [(store tGPR:$src, t_addrmode_sp:$addr)]>,
655 let mayStore = 1, neverHasSideEffects = 1 in
656 // Special instruction for spill. It cannot clobber condition register when it's
657 // expanded by eliminateCallFramePseudoInstr().
658 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
659 "str", "\t$src, $addr", []>,
662 //===----------------------------------------------------------------------===//
663 // Load / store multiple Instructions.
666 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
667 InstrItinClass itin_upd, bits<6> T1Enc,
670 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
671 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
676 let Inst{7-0} = regs;
679 T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
680 itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
685 let Inst{7-0} = regs;
689 // These require base address to be written back or one of the loaded regs.
690 let neverHasSideEffects = 1 in {
692 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
693 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
696 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
697 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
700 } // neverHasSideEffects
702 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
703 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
705 "pop${p}\t$regs", []>,
706 T1Misc<{1,1,0,?,?,?,?}> {
708 let Inst{8} = regs{15};
709 let Inst{7-0} = regs{7-0};
712 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
713 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
715 "push${p}\t$regs", []>,
716 T1Misc<{0,1,0,?,?,?,?}> {
718 let Inst{8} = regs{14};
719 let Inst{7-0} = regs{7-0};
722 //===----------------------------------------------------------------------===//
723 // Arithmetic Instructions.
726 // Helper classes for encoding T1pI patterns:
727 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
728 string opc, string asm, list<dag> pattern>
729 : T1pI<oops, iops, itin, opc, asm, pattern>,
730 T1DataProcessing<opA> {
736 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
737 string opc, string asm, list<dag> pattern>
738 : T1pI<oops, iops, itin, opc, asm, pattern>,
746 // Helper classes for encoding T1sI patterns:
747 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
748 string opc, string asm, list<dag> pattern>
749 : T1sI<oops, iops, itin, opc, asm, pattern>,
750 T1DataProcessing<opA> {
756 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
757 string opc, string asm, list<dag> pattern>
758 : T1sI<oops, iops, itin, opc, asm, pattern>,
767 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
768 string opc, string asm, list<dag> pattern>
769 : T1sI<oops, iops, itin, opc, asm, pattern>,
777 // Helper classes for encoding T1sIt patterns:
778 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
779 string opc, string asm, list<dag> pattern>
780 : T1sIt<oops, iops, itin, opc, asm, pattern>,
781 T1DataProcessing<opA> {
787 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
788 string opc, string asm, list<dag> pattern>
789 : T1sIt<oops, iops, itin, opc, asm, pattern>,
793 let Inst{10-8} = Rdn;
794 let Inst{7-0} = imm8;
797 // Add with carry register
798 let isCommutable = 1, Uses = [CPSR] in
800 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
801 "adc", "\t$Rdn, $Rm",
802 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
805 def tADDi3 : // A8.6.4 T1
806 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), IIC_iALUi,
807 "add", "\t$Rd, $Rm, $imm3",
808 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
810 let Inst{8-6} = imm3;
813 def tADDi8 : // A8.6.4 T2
814 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
816 "add", "\t$Rdn, $imm8",
817 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
820 let isCommutable = 1 in
821 def tADDrr : // A8.6.6 T1
822 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
824 "add", "\t$Rd, $Rn, $Rm",
825 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
827 let neverHasSideEffects = 1 in
828 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
829 "add", "\t$Rdn, $Rm", []>,
830 T1Special<{0,0,?,?}> {
834 let Inst{7} = Rdn{3};
836 let Inst{2-0} = Rdn{2-0};
840 let isCommutable = 1 in
841 def tAND : // A8.6.12
842 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
844 "and", "\t$Rdn, $Rm",
845 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
848 def tASRri : // A8.6.14
849 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
851 "asr", "\t$Rd, $Rm, $imm5",
852 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> {
854 let Inst{10-6} = imm5;
858 def tASRrr : // A8.6.15
859 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
861 "asr", "\t$Rdn, $Rm",
862 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
865 def tBIC : // A8.6.20
866 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
868 "bic", "\t$Rdn, $Rm",
869 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
872 let isCompare = 1, Defs = [CPSR] in {
873 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
874 // Compare-to-zero still works out, just not the relationals
875 //def tCMN : // A8.6.33
876 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
878 // "cmn", "\t$lhs, $rhs",
879 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
881 def tCMNz : // A8.6.33
882 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
885 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
887 } // isCompare = 1, Defs = [CPSR]
890 let isCompare = 1, Defs = [CPSR] in {
891 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
892 "cmp", "\t$Rn, $imm8",
893 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
894 T1General<{1,0,1,?,?}> {
899 let Inst{7-0} = imm8;
902 def tCMPzi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
903 "cmp", "\t$Rn, $imm8",
904 [(ARMcmpZ tGPR:$Rn, imm0_255:$imm8)]>,
905 T1General<{1,0,1,?,?}> {
909 let Inst{7-0} = 0x00;
913 def tCMPr : // A8.6.36 T1
914 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
917 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
919 def tCMPzr : // A8.6.36 T1
920 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iCMPr,
922 [(ARMcmpZ tGPR:$Rn, tGPR:$Rm)]>;
924 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
925 "cmp", "\t$Rn, $Rm", []>,
926 T1Special<{0,1,?,?}> {
932 let Inst{2-0} = Rn{2-0};
934 def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
935 "cmp", "\t$lhs, $rhs", []>,
936 T1Special<{0,1,?,?}> {
942 let Inst{2-0} = Rn{2-0};
945 } // isCompare = 1, Defs = [CPSR]
949 let isCommutable = 1 in
950 def tEOR : // A8.6.45
951 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
953 "eor", "\t$Rdn, $Rm",
954 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
957 def tLSLri : // A8.6.88
958 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
960 "lsl", "\t$Rd, $Rm, $imm5",
961 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
963 let Inst{10-6} = imm5;
967 def tLSLrr : // A8.6.89
968 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
970 "lsl", "\t$Rdn, $Rm",
971 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
974 def tLSRri : // A8.6.90
975 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
977 "lsr", "\t$Rd, $Rm, $imm5",
978 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> {
980 let Inst{10-6} = imm5;
984 def tLSRrr : // A8.6.91
985 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
987 "lsr", "\t$Rdn, $Rm",
988 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
992 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins i32imm:$imm8), IIC_iMOVi,
993 "mov", "\t$Rd, $imm8",
994 [(set tGPR:$Rd, imm0_255:$imm8)]>,
995 T1General<{1,0,0,?,?}> {
1000 let Inst{7-0} = imm8;
1003 // TODO: A7-73: MOV(2) - mov setting flag.
1005 let neverHasSideEffects = 1 in {
1006 // FIXME: Make this predicable.
1007 def tMOVr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1008 "mov\t$Rd, $Rm", []>,
1013 // Bits {7-6} are encoded by the T1Special value.
1014 let Inst{5-3} = Rm{2-0};
1015 let Inst{2-0} = Rd{2-0};
1017 let Defs = [CPSR] in
1018 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1019 "movs\t$Rd, $Rm", []>, Encoding16 {
1023 let Inst{15-6} = 0b0000000000;
1028 // FIXME: Make these predicable.
1029 def tMOVgpr2tgpr : T1I<(outs tGPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1030 "mov\t$Rd, $Rm", []>,
1031 T1Special<{1,0,0,?}> {
1035 // Bit {7} is encoded by the T1Special value.
1037 let Inst{2-0} = Rd{2-0};
1039 def tMOVtgpr2gpr : T1I<(outs GPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1040 "mov\t$Rd, $Rm", []>,
1041 T1Special<{1,0,?,0}> {
1045 // Bit {6} is encoded by the T1Special value.
1046 let Inst{7} = Rd{3};
1047 let Inst{5-3} = Rm{2-0};
1048 let Inst{2-0} = Rd{2-0};
1050 def tMOVgpr2gpr : T1I<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1051 "mov\t$Rd, $Rm", []>,
1052 T1Special<{1,0,?,?}> {
1056 let Inst{7} = Rd{3};
1058 let Inst{2-0} = Rd{2-0};
1060 } // neverHasSideEffects
1062 // Multiply register
1063 let isCommutable = 1 in
1064 def tMUL : // A8.6.105 T1
1065 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1067 "mul", "\t$Rdn, $Rm, $Rdn",
1068 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1070 // Move inverse register
1071 def tMVN : // A8.6.107
1072 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1073 "mvn", "\t$Rd, $Rn",
1074 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1076 // Bitwise or register
1077 let isCommutable = 1 in
1078 def tORR : // A8.6.114
1079 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1081 "orr", "\t$Rdn, $Rm",
1082 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1085 def tREV : // A8.6.134
1086 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1088 "rev", "\t$Rd, $Rm",
1089 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1090 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1092 def tREV16 : // A8.6.135
1093 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1095 "rev16", "\t$Rd, $Rm",
1097 (or (and (srl tGPR:$Rm, (i32 8)), 0xFF),
1098 (or (and (shl tGPR:$Rm, (i32 8)), 0xFF00),
1099 (or (and (srl tGPR:$Rm, (i32 8)), 0xFF0000),
1100 (and (shl tGPR:$Rm, (i32 8)), 0xFF000000)))))]>,
1101 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1103 def tREVSH : // A8.6.136
1104 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1106 "revsh", "\t$Rd, $Rm",
1109 (or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
1110 (shl tGPR:$Rm, (i32 8))), i16))]>,
1111 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1113 // Rotate right register
1114 def tROR : // A8.6.139
1115 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1117 "ror", "\t$Rdn, $Rm",
1118 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1121 def tRSB : // A8.6.141
1122 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1124 "rsb", "\t$Rd, $Rn, #0",
1125 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1127 // Subtract with carry register
1128 let Uses = [CPSR] in
1129 def tSBC : // A8.6.151
1130 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1132 "sbc", "\t$Rdn, $Rm",
1133 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1135 // Subtract immediate
1136 def tSUBi3 : // A8.6.210 T1
1137 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1139 "sub", "\t$Rd, $Rm, $imm3",
1140 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1142 let Inst{8-6} = imm3;
1145 def tSUBi8 : // A8.6.210 T2
1146 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1148 "sub", "\t$Rdn, $imm8",
1149 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1151 // Subtract register
1152 def tSUBrr : // A8.6.212
1153 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1155 "sub", "\t$Rd, $Rn, $Rm",
1156 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1158 // TODO: A7-96: STMIA - store multiple.
1161 def tSXTB : // A8.6.222
1162 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1164 "sxtb", "\t$Rd, $Rm",
1165 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1166 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1168 // Sign-extend short
1169 def tSXTH : // A8.6.224
1170 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1172 "sxth", "\t$Rd, $Rm",
1173 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1174 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1177 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1178 def tTST : // A8.6.230
1179 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1180 "tst", "\t$Rn, $Rm",
1181 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1184 def tUXTB : // A8.6.262
1185 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1187 "uxtb", "\t$Rd, $Rm",
1188 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1189 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1191 // Zero-extend short
1192 def tUXTH : // A8.6.264
1193 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1195 "uxth", "\t$Rd, $Rm",
1196 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1197 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1199 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1200 // Expanded after instruction selection into a branch sequence.
1201 let usesCustomInserter = 1 in // Expanded after instruction selection.
1202 def tMOVCCr_pseudo :
1203 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1205 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1208 // 16-bit movcc in IT blocks for Thumb2.
1209 let neverHasSideEffects = 1 in {
1210 def tMOVCCr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iCMOVr,
1211 "mov", "\t$Rdn, $Rm", []>,
1212 T1Special<{1,0,?,?}> {
1215 let Inst{7} = Rdn{3};
1217 let Inst{2-0} = Rdn{2-0};
1220 let isMoveImm = 1 in
1221 def tMOVCCi : T1pIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$Rm), IIC_iCMOVi,
1222 "mov", "\t$Rdn, $Rm", []>,
1223 T1General<{1,0,0,?,?}> {
1226 let Inst{10-8} = Rdn;
1230 } // neverHasSideEffects
1232 // tLEApcrel - Load a pc-relative address into a register without offending the
1234 let neverHasSideEffects = 1, isReMaterializable = 1 in
1235 def tLEApcrel : T1I<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), IIC_iALUi,
1236 "adr${p}\t$Rd, #$label", []>,
1237 T1Encoding<{1,0,1,0,0,?}> {
1240 let Inst{10-8} = Rd;
1241 // FIXME: Add label encoding/fixup
1244 def tLEApcrelJT : T1I<(outs tGPR:$Rd),
1245 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1246 IIC_iALUi, "adr${p}\t$Rd, #${label}_${id}", []>,
1247 T1Encoding<{1,0,1,0,0,?}> {
1250 let Inst{10-8} = Rd;
1251 // FIXME: Add label encoding/fixup
1254 //===----------------------------------------------------------------------===//
1258 // __aeabi_read_tp preserves the registers r1-r3.
1259 let isCall = 1, Defs = [R0, LR], Uses = [SP] in
1260 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
1261 "bl\t__aeabi_read_tp",
1262 [(set R0, ARMthread_pointer)]> {
1263 // Encoding is 0xf7fffffe.
1264 let Inst = 0xf7fffffe;
1267 //===----------------------------------------------------------------------===//
1268 // SJLJ Exception handling intrinsics
1271 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1272 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1273 // from some other function to get here, and we're using the stack frame for the
1274 // containing function to save/restore registers, we can't keep anything live in
1275 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1276 // tromped upon when we get here from a longjmp(). We force everthing out of
1277 // registers except for our own input by listing the relevant registers in
1278 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1279 // preserve all of the callee-saved resgisters, which is exactly what we want.
1280 // $val is a scratch register for our use.
1281 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ],
1282 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1283 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1284 AddrModeNone, SizeSpecial, NoItinerary, "","",
1285 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1287 // FIXME: Non-Darwin version(s)
1288 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1289 Defs = [ R7, LR, SP ] in
1290 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1291 AddrModeNone, SizeSpecial, IndexModeNone,
1292 Pseudo, NoItinerary, "", "",
1293 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1294 Requires<[IsThumb, IsDarwin]>;
1296 //===----------------------------------------------------------------------===//
1297 // Non-Instruction Patterns
1301 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1302 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1303 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1304 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1305 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1306 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1308 // Subtract with carry
1309 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1310 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1311 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1312 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1313 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1314 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1316 // ConstantPool, GlobalAddress
1317 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1318 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1321 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1322 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1325 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1326 Requires<[IsThumb, IsNotDarwin]>;
1327 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1328 Requires<[IsThumb, IsDarwin]>;
1330 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1331 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1332 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1333 Requires<[IsThumb, HasV5T, IsDarwin]>;
1335 // Indirect calls to ARM routines
1336 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1337 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1338 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1339 Requires<[IsThumb, HasV5T, IsDarwin]>;
1341 // zextload i1 -> zextload i8
1342 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
1343 (tLDRB t_addrmode_s1:$addr)>;
1345 // extload -> zextload
1346 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
1347 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
1348 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
1350 // If it's impossible to use [r,r] address mode for sextload, select to
1351 // ldr{b|h} + sxt{b|h} instead.
1352 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1353 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
1354 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1355 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
1356 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
1357 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1359 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1360 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
1361 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
1362 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
1364 // Large immediate handling.
1367 def : T1Pat<(i32 thumb_immshifted:$src),
1368 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1369 (thumb_immshifted_shamt imm:$src))>;
1371 def : T1Pat<(i32 imm0_255_comp:$src),
1372 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1374 // Pseudo instruction that combines ldr from constpool and add pc. This should
1375 // be expanded into two instructions late to allow if-conversion and
1377 let isReMaterializable = 1 in
1378 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1380 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1382 Requires<[IsThumb, IsThumb1Only]>;