1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Define Thumb specific addressing modes.
71 // t_addrmode_rr := reg + reg
73 def t_addrmode_rr : Operand<i32>,
74 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
75 let PrintMethod = "printThumbAddrModeRROperand";
76 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
79 // t_addrmode_s4 := reg + reg
82 def t_addrmode_s4 : Operand<i32>,
83 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
84 let PrintMethod = "printThumbAddrModeS4Operand";
85 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
88 // t_addrmode_s2 := reg + reg
91 def t_addrmode_s2 : Operand<i32>,
92 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
93 let PrintMethod = "printThumbAddrModeS2Operand";
94 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
97 // t_addrmode_s1 := reg + reg
100 def t_addrmode_s1 : Operand<i32>,
101 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
102 let PrintMethod = "printThumbAddrModeS1Operand";
103 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
106 // t_addrmode_sp := sp + imm8 * 4
108 def t_addrmode_sp : Operand<i32>,
109 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
110 let PrintMethod = "printThumbAddrModeSPOperand";
111 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
114 //===----------------------------------------------------------------------===//
115 // Miscellaneous Instructions.
118 let Defs = [SP], Uses = [SP] in {
119 def tADJCALLSTACKUP :
120 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
121 "@ tADJCALLSTACKUP $amt1",
122 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb]>;
124 def tADJCALLSTACKDOWN :
125 PseudoInst<(outs), (ins i32imm:$amt),
126 "@ tADJCALLSTACKDOWN $amt",
127 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb]>;
130 let isNotDuplicable = 1 in
131 def tPICADD : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
132 "$cp:\n\tadd $dst, pc",
133 [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
136 def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs),
137 "add $dst, pc, $rhs * 4", []>;
140 // FIXME: hard code sp?
141 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs),
142 "add $dst, $sp, $rhs * 4 @ addrspi", []>;
145 // FIXME: hard code sp?
146 def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
147 "add $dst, $rhs * 4", []>;
149 // FIXME: Make use of the following?
153 //===----------------------------------------------------------------------===//
154 // Control Flow Instructions.
157 let isReturn = 1, isTerminator = 1 in {
158 def tBX_RET : TI<(outs), (ins), "bx lr", [(ARMretflag)]>;
159 // Alternative return instruction used by vararg functions.
160 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), "bx $target", []>;
163 // FIXME: remove when we have a way to marking a MI with these properties.
164 let isReturn = 1, isTerminator = 1 in
165 def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins),
169 Defs = [R0, R1, R2, R3, LR,
170 D0, D1, D2, D3, D4, D5, D6, D7] in {
171 def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops),
173 [(ARMtcall tglobaladdr:$func)]>;
175 def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops),
177 [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
178 def tBLXr : TI<(outs), (ins tGPR:$func, variable_ops),
180 [(ARMtcall tGPR:$func)]>, Requires<[HasV5T]>;
182 def tBX : TIx2<(outs), (ins tGPR:$func, variable_ops),
183 "cpy lr, pc\n\tbx $func",
184 [(ARMcall_nolink tGPR:$func)]>;
187 let isBranch = 1, isTerminator = 1 in {
188 let isBarrier = 1 in {
189 let isPredicable = 1 in
190 def tB : TI<(outs), (ins brtarget:$target), "b $target",
194 def tBfar : TIx2<(outs), (ins brtarget:$target), "bl $target\t@ far jump",[]>;
196 def tBR_JTr : TJTI<(outs),
197 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
198 "cpy pc, $target \n\t.align\t2\n$jt",
199 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
203 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
204 // a two-value operand where a dag node expects two operands. :(
205 let isBranch = 1, isTerminator = 1 in
206 def tBcc : TI<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target",
207 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
209 //===----------------------------------------------------------------------===//
210 // Load Store Instructions.
213 let canFoldAsLoad = 1 in
214 def tLDR : TI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr),
216 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
218 def tLDRB : TI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr),
220 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
222 def tLDRH : TI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr),
224 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
226 def tLDRSB : TI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
228 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
230 def tLDRSH : TI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
232 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
234 let canFoldAsLoad = 1 in
235 def tLDRspi : TIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
237 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
239 // Special instruction for restore. It cannot clobber condition register
240 // when it's expanded by eliminateCallFramePseudoInstr().
241 let canFoldAsLoad = 1, mayLoad = 1 in
242 def tRestore : TIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
243 "ldr $dst, $addr", []>;
246 let canFoldAsLoad = 1 in
247 def tLDRpci : TIs<(outs tGPR:$dst), (ins i32imm:$addr),
249 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
251 // Special LDR for loads from non-pc-relative constpools.
252 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
253 def tLDRcp : TIs<(outs tGPR:$dst), (ins i32imm:$addr),
254 "ldr $dst, $addr", []>;
256 def tSTR : TI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr),
258 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
260 def tSTRB : TI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr),
262 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
264 def tSTRH : TI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr),
266 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
268 def tSTRspi : TIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
270 [(store tGPR:$src, t_addrmode_sp:$addr)]>;
272 let mayStore = 1 in {
273 // Special instruction for spill. It cannot clobber condition register
274 // when it's expanded by eliminateCallFramePseudoInstr().
275 def tSpill : TIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
276 "str $src, $addr", []>;
279 //===----------------------------------------------------------------------===//
280 // Load / store multiple Instructions.
283 // TODO: A7-44: LDMIA - load multiple
286 def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
290 def tPUSH : TI<(outs), (ins reglist:$src1, variable_ops),
293 //===----------------------------------------------------------------------===//
294 // Arithmetic Instructions.
297 // Add with carry register
298 let isCommutable = 1, Defs = [CPSR], Uses = [CPSR] in
299 def tADCS : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
301 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
304 let Defs = [CPSR] in {
305 def tADDi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
306 "add $dst, $lhs, $rhs",
307 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
308 def tADDSi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
309 "add $dst, $lhs, $rhs",
310 [(set tGPR:$dst, (addc tGPR:$lhs, imm0_7:$rhs))]>;
313 let Defs = [CPSR] in {
314 def tADDi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
316 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
317 def tADDSi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
319 [(set tGPR:$dst, (addc tGPR:$lhs, imm8_255:$rhs))]>;
323 let isCommutable = 1, Defs = [CPSR] in {
324 def tADDrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
325 "add $dst, $lhs, $rhs",
326 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
327 def tADDSrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
328 "add $dst, $lhs, $rhs",
329 [(set tGPR:$dst, (addc tGPR:$lhs, tGPR:$rhs))]>;
332 let neverHasSideEffects = 1 in
333 def tADDhirr : T1It<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs),
334 "add $dst, $rhs @ addhirr", []>;
337 let isCommutable = 1, Defs = [CPSR] in
338 def tAND : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
340 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
344 def tASRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
345 "asr $dst, $lhs, $rhs",
346 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
350 def tASRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
352 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
356 def tBIC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
358 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
361 let Defs = [CPSR] in {
362 def tCMN : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
364 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
365 def tCMNNZ : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
367 [(ARMcmpNZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
371 let Defs = [CPSR] in {
372 def tCMPi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs),
374 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
375 def tCMPNZi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs),
377 [(ARMcmpNZ tGPR:$lhs, imm0_255:$rhs)]>;
382 let Defs = [CPSR] in {
383 def tCMPr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
385 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
386 def tCMPNZr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
388 [(ARMcmpNZ tGPR:$lhs, tGPR:$rhs)]>;
391 // TODO: A7-37: CMP(3) - cmp hi regs
394 let isCommutable = 1, Defs = [CPSR] in
395 def tEOR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
397 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
401 def tLSLri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
402 "lsl $dst, $lhs, $rhs",
403 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
407 def tLSLrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
409 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
413 def tLSRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
414 "lsr $dst, $lhs, $rhs",
415 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
419 def tLSRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
421 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
425 def tMOVi8 : T1I<(outs tGPR:$dst), (ins i32imm:$src),
427 [(set tGPR:$dst, imm0_255:$src)]>;
429 // TODO: A7-73: MOV(2) - mov setting flag.
432 // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
433 // which is MOV(3). This also supports high registers.
434 let neverHasSideEffects = 1 in {
435 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src),
436 "cpy $dst, $src", []>;
437 def tMOVhir2lor : T1I<(outs tGPR:$dst), (ins GPR:$src),
438 "cpy $dst, $src\t@ hir2lor", []>;
439 def tMOVlor2hir : T1I<(outs GPR:$dst), (ins tGPR:$src),
440 "cpy $dst, $src\t@ lor2hir", []>;
441 def tMOVhir2hir : T1I<(outs GPR:$dst), (ins GPR:$src),
442 "cpy $dst, $src\t@ hir2hir", []>;
443 } // neverHasSideEffects
446 let isCommutable = 1, Defs = [CPSR] in
447 def tMUL : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
449 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
451 // move inverse register
453 def tMVN : T1I<(outs tGPR:$dst), (ins tGPR:$src),
455 [(set tGPR:$dst, (not tGPR:$src))]>;
459 def tNEG : T1I<(outs tGPR:$dst), (ins tGPR:$src),
461 [(set tGPR:$dst, (ineg tGPR:$src))]>;
463 // bitwise or register
464 let isCommutable = 1, Defs = [CPSR] in
465 def tORR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
467 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
470 def tREV : T1I<(outs tGPR:$dst), (ins tGPR:$src),
472 [(set tGPR:$dst, (bswap tGPR:$src))]>,
473 Requires<[IsThumb, HasV6]>;
475 def tREV16 : T1I<(outs tGPR:$dst), (ins tGPR:$src),
478 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
479 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
480 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
481 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
482 Requires<[IsThumb, HasV6]>;
484 def tREVSH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
488 (or (srl (and tGPR:$src, 0xFFFF), (i32 8)),
489 (shl tGPR:$src, (i32 8))), i16))]>,
490 Requires<[IsThumb, HasV6]>;
492 // rotate right register
494 def tROR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
496 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
498 // Subtract with carry register
499 let Defs = [CPSR], Uses = [CPSR] in
500 def tSBCS : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
502 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
504 // Subtract immediate
505 let Defs = [CPSR] in {
506 def tSUBi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
507 "sub $dst, $lhs, $rhs",
508 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
509 def tSUBSi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
510 "sub $dst, $lhs, $rhs",
511 [(set tGPR:$dst, (addc tGPR:$lhs, imm0_7_neg:$rhs))]>;
514 let Defs = [CPSR] in {
515 def tSUBi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
517 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
518 def tSUBSi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
520 [(set tGPR:$dst, (addc tGPR:$lhs, imm8_255_neg:$rhs))]>;
524 let Defs = [CPSR] in {
525 def tSUBrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
526 "sub $dst, $lhs, $rhs",
527 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
528 def tSUBSrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
529 "sub $dst, $lhs, $rhs",
530 [(set tGPR:$dst, (subc tGPR:$lhs, tGPR:$rhs))]>;
533 // TODO: A7-96: STMIA - store multiple.
535 def tSUBspi : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
536 "sub $dst, $rhs * 4", []>;
539 def tSXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src),
541 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
542 Requires<[IsThumb, HasV6]>;
545 def tSXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
547 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
548 Requires<[IsThumb, HasV6]>;
552 def tTST : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
554 [(ARMcmpNZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
557 def tUXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src),
559 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
560 Requires<[IsThumb, HasV6]>;
563 def tUXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
565 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
566 Requires<[IsThumb, HasV6]>;
569 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
570 // Expanded by the scheduler into a branch sequence.
571 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
573 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
575 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
577 // tLEApcrel - Load a pc-relative address into a register without offending the
579 def tLEApcrel : TIx2<(outs tGPR:$dst), (ins i32imm:$label),
580 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
581 "${:private}PCRELL${:uid}+4))\n"),
582 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
583 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
586 def tLEApcrelJT : TIx2<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id),
587 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
588 "${:private}PCRELL${:uid}+4))\n"),
589 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
590 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
593 //===----------------------------------------------------------------------===//
597 // __aeabi_read_tp preserves the registers r1-r3.
600 def tTPsoft : TIx2<(outs), (ins),
601 "bl __aeabi_read_tp",
602 [(set R0, ARMthread_pointer)]>;
605 //===----------------------------------------------------------------------===//
606 // Non-Instruction Patterns
609 // ConstantPool, GlobalAddress
610 def : ThumbPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
611 def : ThumbPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
614 def : ThumbPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
615 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
618 def : ThumbPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
619 def : ThumbV5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
621 // Indirect calls to ARM routines
622 def : ThumbV5Pat<(ARMcall tGPR:$dst), (tBLXr tGPR:$dst)>;
624 // zextload i1 -> zextload i8
625 def : ThumbPat<(zextloadi1 t_addrmode_s1:$addr),
626 (tLDRB t_addrmode_s1:$addr)>;
628 // extload -> zextload
629 def : ThumbPat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
630 def : ThumbPat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
631 def : ThumbPat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
633 // Large immediate handling.
636 def : Thumb1Pat<(i32 thumb_immshifted:$src),
637 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
638 (thumb_immshifted_shamt imm:$src))>;
640 def : Thumb1Pat<(i32 imm0_255_comp:$src),
641 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;