1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
30 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
31 def imm0_7 : PatLeaf<(i32 imm), [{
32 return (uint32_t)N->getZExtValue() < 8;
34 def imm0_7_neg : PatLeaf<(i32 imm), [{
35 return (uint32_t)-N->getZExtValue() < 8;
38 def imm0_255 : PatLeaf<(i32 imm), [{
39 return (uint32_t)N->getZExtValue() < 256;
41 def imm0_255_comp : PatLeaf<(i32 imm), [{
42 return ~((uint32_t)N->getZExtValue()) < 256;
45 def imm8_255 : PatLeaf<(i32 imm), [{
46 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
48 def imm8_255_neg : PatLeaf<(i32 imm), [{
49 unsigned Val = -N->getZExtValue();
50 return Val >= 8 && Val < 256;
53 // Break imm's up into two pieces: an immediate + a left shift. This uses
54 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
55 // to get the val/shift pieces.
56 def thumb_immshifted : PatLeaf<(imm), [{
57 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
60 def thumb_immshifted_val : SDNodeXForm<imm, [{
61 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
62 return CurDAG->getTargetConstant(V, MVT::i32);
65 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 // Scaled 4 immediate.
71 def t_imm_s4 : Operand<i32> {
72 let PrintMethod = "printThumbS4ImmOperand";
75 // Define Thumb specific addressing modes.
77 def t_cbtarget : Operand<i32> {
78 let EncoderMethod = "getThumbCBTargetOpValue";
81 def t_bltarget : Operand<i32> {
82 let EncoderMethod = "getThumbBLTargetOpValue";
85 def t_blxtarget : Operand<i32> {
86 let EncoderMethod = "getThumbBLXTargetOpValue";
89 def MemModeThumbAsmOperand : AsmOperandClass {
90 let Name = "MemModeThumb";
91 let SuperClasses = [];
94 // t_addrmode_rr := reg + reg
96 def t_addrmode_rr : Operand<i32>,
97 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
98 let PrintMethod = "printThumbAddrModeRROperand";
99 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
102 // t_addrmode_s4 := reg + reg
105 def t_addrmode_s4 : Operand<i32>,
106 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
107 let EncoderMethod = "getAddrModeSOpValue";
108 let PrintMethod = "printThumbAddrModeS4Operand";
109 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
110 let ParserMatchClass = MemModeThumbAsmOperand;
113 // t_addrmode_s2 := reg + reg
116 def t_addrmode_s2 : Operand<i32>,
117 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
118 let EncoderMethod = "getAddrModeSOpValue";
119 let PrintMethod = "printThumbAddrModeS2Operand";
120 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
121 let ParserMatchClass = MemModeThumbAsmOperand;
124 // t_addrmode_s1 := reg + reg
127 def t_addrmode_s1 : Operand<i32>,
128 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
129 let EncoderMethod = "getAddrModeSOpValue";
130 let PrintMethod = "printThumbAddrModeS1Operand";
131 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
132 let ParserMatchClass = MemModeThumbAsmOperand;
135 // t_addrmode_sp := sp + imm8 * 4
137 def t_addrmode_sp : Operand<i32>,
138 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
139 let EncoderMethod = "getAddrModeThumbSPOpValue";
140 let PrintMethod = "printThumbAddrModeSPOperand";
141 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
142 let ParserMatchClass = MemModeThumbAsmOperand;
145 // t_addrmode_pc := <label> => pc + imm8 * 4
147 def t_addrmode_pc : Operand<i32> {
148 let EncoderMethod = "getAddrModePCOpValue";
149 let ParserMatchClass = MemModeThumbAsmOperand;
152 //===----------------------------------------------------------------------===//
153 // Miscellaneous Instructions.
156 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
157 // from removing one half of the matched pairs. That breaks PEI, which assumes
158 // these will always be in pairs, and asserts if it finds otherwise. Better way?
159 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
160 def tADJCALLSTACKUP :
161 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
162 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
163 Requires<[IsThumb, IsThumb1Only]>;
165 def tADJCALLSTACKDOWN :
166 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
167 [(ARMcallseq_start imm:$amt)]>,
168 Requires<[IsThumb, IsThumb1Only]>;
171 // T1Disassembly - A simple class to make encoding some disassembly patterns
172 // easier and less verbose.
173 class T1Disassembly<bits<2> op1, bits<8> op2>
174 : T1Encoding<0b101111> {
179 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
180 [/* For disassembly only; pattern left blank */]>,
181 T1Disassembly<0b11, 0x00>; // A8.6.110
183 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
184 [/* For disassembly only; pattern left blank */]>,
185 T1Disassembly<0b11, 0x10>; // A8.6.410
187 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
188 [/* For disassembly only; pattern left blank */]>,
189 T1Disassembly<0b11, 0x20>; // A8.6.408
191 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
192 [/* For disassembly only; pattern left blank */]>,
193 T1Disassembly<0b11, 0x30>; // A8.6.409
195 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
196 [/* For disassembly only; pattern left blank */]>,
197 T1Disassembly<0b11, 0x40>; // A8.6.157
199 // The i32imm operand $val can be used by a debugger to store more information
200 // about the breakpoint.
201 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
202 [/* For disassembly only; pattern left blank */]>,
203 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
209 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
210 [/* For disassembly only; pattern left blank */]>,
211 T1Encoding<0b101101> {
213 let Inst{9-5} = 0b10010;
215 let Inst{3} = 1; // Big-Endian
216 let Inst{2-0} = 0b000;
219 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
220 [/* For disassembly only; pattern left blank */]>,
221 T1Encoding<0b101101> {
223 let Inst{9-5} = 0b10010;
225 let Inst{3} = 0; // Little-Endian
226 let Inst{2-0} = 0b000;
229 // Change Processor State is a system instruction -- for disassembly only.
230 // The singleton $opt operand contains the following information:
232 // opt{4-0} = mode ==> don't care
233 // opt{5} = changemode ==> 0 (false for 16-bit Thumb instr)
234 // opt{8-6} = AIF from Inst{2-0}
235 // opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
237 // The opt{4-0} and opt{5} sub-fields are to accommodate 32-bit Thumb and ARM
238 // CPS which has more options.
239 def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt",
240 [/* For disassembly only; pattern left blank */]>,
244 // FIXME: Finish encoding.
247 // For both thumb1 and thumb2.
248 let isNotDuplicable = 1, isCodeGenOnly = 1 in
249 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
250 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
251 T1Special<{0,0,?,?}> {
254 let Inst{6-3} = 0b1111; // Rm = pc
258 // PC relative add (ADR).
259 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
260 "add\t$dst, pc, $rhs", []>,
261 T1Encoding<{1,0,1,0,0,?}> {
265 let Inst{10-8} = dst;
269 // ADD <Rd>, sp, #<imm8>
270 // This is rematerializable, which is particularly useful for taking the
271 // address of locals.
272 let isReMaterializable = 1 in
273 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
274 "add\t$dst, $sp, $rhs", []>,
275 T1Encoding<{1,0,1,0,1,?}> {
279 let Inst{10-8} = dst;
283 // ADD sp, sp, #<imm7>
284 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
285 "add\t$dst, $rhs", []>,
286 T1Misc<{0,0,0,0,0,?,?}> {
292 // SUB sp, sp, #<imm7>
293 // FIXME: The encoding and the ASM string don't match up.
294 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
295 "sub\t$dst, $rhs", []>,
296 T1Misc<{0,0,0,0,1,?,?}> {
303 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
304 "add\t$dst, $rhs", []>,
305 T1Special<{0,0,?,?}> {
306 // A8.6.9 Encoding T1
308 let Inst{7} = dst{3};
309 let Inst{6-3} = 0b1101;
310 let Inst{2-0} = dst{2-0};
314 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
315 "add\t$dst, $rhs", []>,
316 T1Special<{0,0,?,?}> {
317 // A8.6.9 Encoding T2
321 let Inst{2-0} = 0b101;
324 //===----------------------------------------------------------------------===//
325 // Control Flow Instructions.
328 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
329 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
331 T1Special<{1,1,0,?}> {
333 let Inst{6-3} = 0b1110; // Rm = lr
334 let Inst{2-0} = 0b000;
337 // Alternative return instruction used by vararg functions.
338 def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
341 T1Special<{1,1,0,?}> {
345 let Inst{2-0} = 0b000;
350 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
351 def tBRIND : TI<(outs), (ins GPR:$Rm),
355 T1Special<{1,0,?,?}> {
358 let Inst{7} = 1; // <Rd> = Inst{7:2-0} = pc
360 let Inst{2-0} = 0b111;
364 // FIXME: remove when we have a way to marking a MI with these properties.
365 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
366 hasExtraDefRegAllocReq = 1 in
367 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
369 "pop${p}\t$regs", []>,
370 T1Misc<{1,1,0,?,?,?,?}> {
373 let Inst{8} = regs{15}; // registers = P:'0000000':register_list
374 let Inst{7-0} = regs{7-0};
377 // All calls clobber the non-callee saved registers. SP is marked as a use to
378 // prevent stack-pointer assignments that appear immediately before calls from
379 // potentially appearing dead.
381 // On non-Darwin platforms R9 is callee-saved.
382 Defs = [R0, R1, R2, R3, R12, LR,
383 D0, D1, D2, D3, D4, D5, D6, D7,
384 D16, D17, D18, D19, D20, D21, D22, D23,
385 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
387 // Also used for Thumb2
388 def tBL : TIx2<0b11110, 0b11, 1,
389 (outs), (ins t_bltarget:$func, variable_ops), IIC_Br,
391 [(ARMtcall tglobaladdr:$func)]>,
392 Requires<[IsThumb, IsNotDarwin]> {
394 let Inst{25-16} = func{20-11};
397 let Inst{10-0} = func{10-0};
400 // ARMv5T and above, also used for Thumb2
401 def tBLXi : TIx2<0b11110, 0b11, 0,
402 (outs), (ins t_blxtarget:$func, variable_ops), IIC_Br,
404 [(ARMcall tglobaladdr:$func)]>,
405 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
407 let Inst{25-16} = func{20-11};
410 let Inst{10-1} = func{10-1};
411 let Inst{0} = 0; // func{0} is assumed zero
414 // Also used for Thumb2
415 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
417 [(ARMtcall GPR:$func)]>,
418 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
419 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
422 // FIXME: Should be a pseudo.
423 let isCodeGenOnly = 1 in
424 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
425 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
426 "mov\tlr, pc\n\tbx\t$func",
427 [(ARMcall_nolink tGPR:$func)]>,
428 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
432 // On Darwin R9 is call-clobbered.
433 // R7 is marked as a use to prevent frame-pointer assignments from being
434 // moved above / below calls.
435 Defs = [R0, R1, R2, R3, R9, R12, LR,
436 D0, D1, D2, D3, D4, D5, D6, D7,
437 D16, D17, D18, D19, D20, D21, D22, D23,
438 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
440 // Also used for Thumb2
441 def tBLr9 : TIx2<0b11110, 0b11, 1,
442 (outs), (ins pred:$p, t_bltarget:$func, variable_ops),
443 IIC_Br, "bl${p}\t$func",
444 [(ARMtcall tglobaladdr:$func)]>,
445 Requires<[IsThumb, IsDarwin]> {
447 let Inst{25-16} = func{20-11};
450 let Inst{10-0} = func{10-0};
453 // ARMv5T and above, also used for Thumb2
454 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
455 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
456 IIC_Br, "blx${p}\t$func",
457 [(ARMcall tglobaladdr:$func)]>,
458 Requires<[IsThumb, HasV5T, IsDarwin]> {
460 let Inst{25-16} = func{20-11};
463 let Inst{10-1} = func{10-1};
464 let Inst{0} = 0; // func{0} is assumed zero
467 // Also used for Thumb2
468 def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
470 [(ARMtcall GPR:$func)]>,
471 Requires<[IsThumb, HasV5T, IsDarwin]>,
472 T1Special<{1,1,1,?}> {
475 let Inst{6-3} = func;
476 let Inst{2-0} = 0b000;
480 let isCodeGenOnly = 1 in
481 // FIXME: Should be a pseudo.
482 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
483 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
484 "mov\tlr, pc\n\tbx\t$func",
485 [(ARMcall_nolink tGPR:$func)]>,
486 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
489 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
490 let isPredicable = 1 in
491 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
492 "b\t$target", [(br bb:$target)]>,
493 T1Encoding<{1,1,1,0,0,?}>;
497 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
500 def tBR_JTr : tPseudoInst<(outs),
501 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
503 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
504 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
508 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
509 // a two-value operand where a dag node expects two operands. :(
510 let isBranch = 1, isTerminator = 1 in
511 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$p), IIC_Br,
513 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
514 T1Encoding<{1,1,0,1,?,?}> {
519 // Compare and branch on zero / non-zero
520 let isBranch = 1, isTerminator = 1 in {
521 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
522 "cbz\t$Rn, $target", []>,
523 T1Misc<{0,0,?,1,?,?,?}> {
527 let Inst{9} = target{5};
528 let Inst{7-3} = target{4-0};
532 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, t_cbtarget:$target), IIC_Br,
533 "cbnz\t$cmp, $target", []>,
534 T1Misc<{1,0,?,1,?,?,?}> {
538 let Inst{9} = target{5};
539 let Inst{7-3} = target{4-0};
544 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
545 // A8.6.16 B: Encoding T1
546 // If Inst{11-8} == 0b1111 then SEE SVC
547 let isCall = 1, Uses = [SP] in
548 def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
549 "svc", "\t$imm", []>, Encoding16 {
551 let Inst{15-12} = 0b1101;
552 let Inst{11-8} = 0b1111;
556 // The assembler uses 0xDEFE for a trap instruction.
557 let isBarrier = 1, isTerminator = 1 in
558 def tTRAP : TI<(outs), (ins), IIC_Br,
559 "trap", [(trap)]>, Encoding16 {
563 //===----------------------------------------------------------------------===//
564 // Load Store Instructions.
567 let canFoldAsLoad = 1, isReMaterializable = 1 in
568 def tLDR : // A8.6.60
569 T1pILdStEncode<0b100, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
570 AddrModeT1_4, IIC_iLoad_r,
571 "ldr", "\t$Rt, $addr",
572 [(set tGPR:$Rt, (load t_addrmode_s4:$addr))]>;
574 def tLDRi : // A8.6.57
575 T1pILdStEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
576 AddrModeT1_4, IIC_iLoad_r,
577 "ldr", "\t$Rt, $addr",
580 def tLDRB : // A8.6.64
581 T1pILdStEncode<0b110, (outs tGPR:$Rt), (ins t_addrmode_s1:$addr),
582 AddrModeT1_1, IIC_iLoad_bh_r,
583 "ldrb", "\t$Rt, $addr",
584 [(set tGPR:$Rt, (zextloadi8 t_addrmode_s1:$addr))]>;
586 def tLDRBi : // A8.6.61
587 T1pILdStEncodeImm<0b0111, 1, (outs tGPR:$Rt), (ins t_addrmode_s1:$addr),
588 AddrModeT1_1, IIC_iLoad_bh_r,
589 "ldrb", "\t$Rt, $addr",
592 def tLDRH : // A8.6.76
593 T1pILdStEncode<0b101, (outs tGPR:$dst), (ins t_addrmode_s2:$addr),
594 AddrModeT1_2, IIC_iLoad_bh_r,
595 "ldrh", "\t$dst, $addr",
596 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
598 def tLDRHi : // A8.6.73
599 T1pILdStEncodeImm<0b1000, 1, (outs tGPR:$Rt), (ins t_addrmode_s2:$addr),
600 AddrModeT1_2, IIC_iLoad_bh_r,
601 "ldrh", "\t$Rt, $addr",
604 let AddedComplexity = 10 in
605 def tLDRSB : // A8.6.80
606 T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
607 AddrModeT1_1, IIC_iLoad_bh_r,
608 "ldrsb", "\t$dst, $addr",
609 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
611 let AddedComplexity = 10 in
612 def tLDRSH : // A8.6.84
613 T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
614 AddrModeT1_2, IIC_iLoad_bh_r,
615 "ldrsh", "\t$dst, $addr",
616 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
618 let canFoldAsLoad = 1 in
619 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
620 "ldr", "\t$Rt, $addr",
621 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
626 let Inst{7-0} = addr;
629 // Special instruction for restore. It cannot clobber condition register
630 // when it's expanded by eliminateCallFramePseudoInstr().
631 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
632 // FIXME: Pseudo for tLDRspi
633 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
634 "ldr", "\t$dst, $addr", []>,
638 // FIXME: Use ldr.n to work around a Darwin assembler bug.
639 let canFoldAsLoad = 1, isReMaterializable = 1 in
640 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
641 "ldr", ".n\t$Rt, $addr",
642 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
643 T1Encoding<{0,1,0,0,1,?}> {
648 let Inst{7-0} = addr;
651 // Special LDR for loads from non-pc-relative constpools.
652 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
653 isReMaterializable = 1 in
654 def tLDRcp : T1pIs<(outs tGPR:$Rt), (ins i32imm:$addr), IIC_iLoad_i,
655 "ldr", "\t$Rt, $addr", []>,
661 let Inst{7-0} = addr;
664 def tSTR : // A8.6.194
665 T1pILdStEncode<0b000, (outs), (ins tGPR:$src, t_addrmode_s4:$addr),
666 AddrModeT1_4, IIC_iStore_r,
667 "str", "\t$src, $addr",
668 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
670 def tSTRi : // A8.6.192
671 T1pILdStEncodeImm<0b0110, 0, (outs), (ins tGPR:$Rt, t_addrmode_s4:$addr),
672 AddrModeT1_4, IIC_iStore_r,
673 "str", "\t$Rt, $addr",
676 def tSTRB : // A8.6.197
677 T1pILdStEncode<0b010, (outs), (ins tGPR:$src, t_addrmode_s1:$addr),
678 AddrModeT1_1, IIC_iStore_bh_r,
679 "strb", "\t$src, $addr",
680 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
682 def tSTRBi : // A8.6.195
683 T1pILdStEncodeImm<0b0111, 0, (outs), (ins tGPR:$Rt, t_addrmode_s1:$addr),
684 AddrModeT1_1, IIC_iStore_bh_r,
685 "strb", "\t$Rt, $addr",
688 def tSTRH : // A8.6.207
689 T1pILdStEncode<0b001, (outs), (ins tGPR:$src, t_addrmode_s2:$addr),
690 AddrModeT1_2, IIC_iStore_bh_r,
691 "strh", "\t$src, $addr",
692 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
694 def tSTRHi : // A8.6.205
695 T1pILdStEncodeImm<0b1000, 0, (outs), (ins tGPR:$Rt, t_addrmode_s2:$addr),
696 AddrModeT1_2, IIC_iStore_bh_r,
697 "strh", "\t$Rt, $addr",
700 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
701 "str", "\t$Rt, $addr",
702 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
707 let Inst{7-0} = addr;
710 let mayStore = 1, neverHasSideEffects = 1 in
711 // Special instruction for spill. It cannot clobber condition register when it's
712 // expanded by eliminateCallFramePseudoInstr().
713 // FIXME: Pseudo for tSTRspi
714 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
715 "str", "\t$src, $addr", []>,
718 //===----------------------------------------------------------------------===//
719 // Load / store multiple Instructions.
722 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
723 InstrItinClass itin_upd, bits<6> T1Enc,
726 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
727 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
732 let Inst{7-0} = regs;
735 T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
736 itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
741 let Inst{7-0} = regs;
745 // These require base address to be written back or one of the loaded regs.
746 let neverHasSideEffects = 1 in {
748 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
749 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
752 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
753 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
756 } // neverHasSideEffects
758 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
759 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
761 "pop${p}\t$regs", []>,
762 T1Misc<{1,1,0,?,?,?,?}> {
764 let Inst{8} = regs{15};
765 let Inst{7-0} = regs{7-0};
768 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
769 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
771 "push${p}\t$regs", []>,
772 T1Misc<{0,1,0,?,?,?,?}> {
774 let Inst{8} = regs{14};
775 let Inst{7-0} = regs{7-0};
778 //===----------------------------------------------------------------------===//
779 // Arithmetic Instructions.
782 // Helper classes for encoding T1pI patterns:
783 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
784 string opc, string asm, list<dag> pattern>
785 : T1pI<oops, iops, itin, opc, asm, pattern>,
786 T1DataProcessing<opA> {
792 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
793 string opc, string asm, list<dag> pattern>
794 : T1pI<oops, iops, itin, opc, asm, pattern>,
802 // Helper classes for encoding T1sI patterns:
803 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
804 string opc, string asm, list<dag> pattern>
805 : T1sI<oops, iops, itin, opc, asm, pattern>,
806 T1DataProcessing<opA> {
812 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
813 string opc, string asm, list<dag> pattern>
814 : T1sI<oops, iops, itin, opc, asm, pattern>,
823 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
824 string opc, string asm, list<dag> pattern>
825 : T1sI<oops, iops, itin, opc, asm, pattern>,
833 // Helper classes for encoding T1sIt patterns:
834 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
835 string opc, string asm, list<dag> pattern>
836 : T1sIt<oops, iops, itin, opc, asm, pattern>,
837 T1DataProcessing<opA> {
843 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
844 string opc, string asm, list<dag> pattern>
845 : T1sIt<oops, iops, itin, opc, asm, pattern>,
849 let Inst{10-8} = Rdn;
850 let Inst{7-0} = imm8;
853 // Add with carry register
854 let isCommutable = 1, Uses = [CPSR] in
856 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
857 "adc", "\t$Rdn, $Rm",
858 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
861 def tADDi3 : // A8.6.4 T1
862 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), IIC_iALUi,
863 "add", "\t$Rd, $Rm, $imm3",
864 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
866 let Inst{8-6} = imm3;
869 def tADDi8 : // A8.6.4 T2
870 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
872 "add", "\t$Rdn, $imm8",
873 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
876 let isCommutable = 1 in
877 def tADDrr : // A8.6.6 T1
878 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
880 "add", "\t$Rd, $Rn, $Rm",
881 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
883 let neverHasSideEffects = 1 in
884 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
885 "add", "\t$Rdn, $Rm", []>,
886 T1Special<{0,0,?,?}> {
890 let Inst{7} = Rdn{3};
892 let Inst{2-0} = Rdn{2-0};
896 let isCommutable = 1 in
897 def tAND : // A8.6.12
898 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
900 "and", "\t$Rdn, $Rm",
901 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
904 def tASRri : // A8.6.14
905 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
907 "asr", "\t$Rd, $Rm, $imm5",
908 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> {
910 let Inst{10-6} = imm5;
914 def tASRrr : // A8.6.15
915 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
917 "asr", "\t$Rdn, $Rm",
918 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
921 def tBIC : // A8.6.20
922 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
924 "bic", "\t$Rdn, $Rm",
925 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
928 let isCompare = 1, Defs = [CPSR] in {
929 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
930 // Compare-to-zero still works out, just not the relationals
931 //def tCMN : // A8.6.33
932 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
934 // "cmn", "\t$lhs, $rhs",
935 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
937 def tCMNz : // A8.6.33
938 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
941 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
943 } // isCompare = 1, Defs = [CPSR]
946 let isCompare = 1, Defs = [CPSR] in {
947 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
948 "cmp", "\t$Rn, $imm8",
949 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
950 T1General<{1,0,1,?,?}> {
955 let Inst{7-0} = imm8;
959 def tCMPr : // A8.6.36 T1
960 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
963 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
965 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
966 "cmp", "\t$Rn, $Rm", []>,
967 T1Special<{0,1,?,?}> {
973 let Inst{2-0} = Rn{2-0};
975 } // isCompare = 1, Defs = [CPSR]
979 let isCommutable = 1 in
980 def tEOR : // A8.6.45
981 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
983 "eor", "\t$Rdn, $Rm",
984 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
987 def tLSLri : // A8.6.88
988 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
990 "lsl", "\t$Rd, $Rm, $imm5",
991 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
993 let Inst{10-6} = imm5;
997 def tLSLrr : // A8.6.89
998 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1000 "lsl", "\t$Rdn, $Rm",
1001 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
1004 def tLSRri : // A8.6.90
1005 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1007 "lsr", "\t$Rd, $Rm, $imm5",
1008 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> {
1010 let Inst{10-6} = imm5;
1014 def tLSRrr : // A8.6.91
1015 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1017 "lsr", "\t$Rdn, $Rm",
1018 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1021 let isMoveImm = 1 in
1022 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins i32imm:$imm8), IIC_iMOVi,
1023 "mov", "\t$Rd, $imm8",
1024 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1025 T1General<{1,0,0,?,?}> {
1029 let Inst{10-8} = Rd;
1030 let Inst{7-0} = imm8;
1033 // TODO: A7-73: MOV(2) - mov setting flag.
1035 let neverHasSideEffects = 1 in {
1036 // FIXME: Make this predicable.
1037 def tMOVr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1038 "mov\t$Rd, $Rm", []>,
1043 // Bits {7-6} are encoded by the T1Special value.
1044 let Inst{5-3} = Rm{2-0};
1045 let Inst{2-0} = Rd{2-0};
1047 let Defs = [CPSR] in
1048 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1049 "movs\t$Rd, $Rm", []>, Encoding16 {
1053 let Inst{15-6} = 0b0000000000;
1058 // FIXME: Make these predicable.
1059 def tMOVgpr2tgpr : T1I<(outs tGPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1060 "mov\t$Rd, $Rm", []>,
1061 T1Special<{1,0,0,?}> {
1065 // Bit {7} is encoded by the T1Special value.
1067 let Inst{2-0} = Rd{2-0};
1069 def tMOVtgpr2gpr : T1I<(outs GPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1070 "mov\t$Rd, $Rm", []>,
1071 T1Special<{1,0,?,0}> {
1075 // Bit {6} is encoded by the T1Special value.
1076 let Inst{7} = Rd{3};
1077 let Inst{5-3} = Rm{2-0};
1078 let Inst{2-0} = Rd{2-0};
1080 def tMOVgpr2gpr : T1I<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1081 "mov\t$Rd, $Rm", []>,
1082 T1Special<{1,0,?,?}> {
1086 let Inst{7} = Rd{3};
1088 let Inst{2-0} = Rd{2-0};
1090 } // neverHasSideEffects
1092 // Multiply register
1093 let isCommutable = 1 in
1094 def tMUL : // A8.6.105 T1
1095 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1097 "mul", "\t$Rdn, $Rm, $Rdn",
1098 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1100 // Move inverse register
1101 def tMVN : // A8.6.107
1102 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1103 "mvn", "\t$Rd, $Rn",
1104 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1106 // Bitwise or register
1107 let isCommutable = 1 in
1108 def tORR : // A8.6.114
1109 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1111 "orr", "\t$Rdn, $Rm",
1112 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1115 def tREV : // A8.6.134
1116 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1118 "rev", "\t$Rd, $Rm",
1119 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1120 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1122 def tREV16 : // A8.6.135
1123 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1125 "rev16", "\t$Rd, $Rm",
1127 (or (and (srl tGPR:$Rm, (i32 8)), 0xFF),
1128 (or (and (shl tGPR:$Rm, (i32 8)), 0xFF00),
1129 (or (and (srl tGPR:$Rm, (i32 8)), 0xFF0000),
1130 (and (shl tGPR:$Rm, (i32 8)), 0xFF000000)))))]>,
1131 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1133 def tREVSH : // A8.6.136
1134 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1136 "revsh", "\t$Rd, $Rm",
1139 (or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
1140 (shl tGPR:$Rm, (i32 8))), i16))]>,
1141 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1143 // Rotate right register
1144 def tROR : // A8.6.139
1145 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1147 "ror", "\t$Rdn, $Rm",
1148 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1151 def tRSB : // A8.6.141
1152 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1154 "rsb", "\t$Rd, $Rn, #0",
1155 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1157 // Subtract with carry register
1158 let Uses = [CPSR] in
1159 def tSBC : // A8.6.151
1160 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1162 "sbc", "\t$Rdn, $Rm",
1163 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1165 // Subtract immediate
1166 def tSUBi3 : // A8.6.210 T1
1167 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1169 "sub", "\t$Rd, $Rm, $imm3",
1170 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1172 let Inst{8-6} = imm3;
1175 def tSUBi8 : // A8.6.210 T2
1176 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1178 "sub", "\t$Rdn, $imm8",
1179 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1181 // Subtract register
1182 def tSUBrr : // A8.6.212
1183 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1185 "sub", "\t$Rd, $Rn, $Rm",
1186 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1188 // TODO: A7-96: STMIA - store multiple.
1191 def tSXTB : // A8.6.222
1192 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1194 "sxtb", "\t$Rd, $Rm",
1195 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1196 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1198 // Sign-extend short
1199 def tSXTH : // A8.6.224
1200 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1202 "sxth", "\t$Rd, $Rm",
1203 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1204 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1207 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1208 def tTST : // A8.6.230
1209 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1210 "tst", "\t$Rn, $Rm",
1211 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1214 def tUXTB : // A8.6.262
1215 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1217 "uxtb", "\t$Rd, $Rm",
1218 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1219 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1221 // Zero-extend short
1222 def tUXTH : // A8.6.264
1223 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1225 "uxth", "\t$Rd, $Rm",
1226 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1227 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1229 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1230 // Expanded after instruction selection into a branch sequence.
1231 let usesCustomInserter = 1 in // Expanded after instruction selection.
1232 def tMOVCCr_pseudo :
1233 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1235 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1238 // 16-bit movcc in IT blocks for Thumb2.
1239 let neverHasSideEffects = 1 in {
1240 def tMOVCCr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iCMOVr,
1241 "mov", "\t$Rdn, $Rm", []>,
1242 T1Special<{1,0,?,?}> {
1245 let Inst{7} = Rdn{3};
1247 let Inst{2-0} = Rdn{2-0};
1250 let isMoveImm = 1 in
1251 def tMOVCCi : T1pIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$Rm), IIC_iCMOVi,
1252 "mov", "\t$Rdn, $Rm", []>,
1253 T1General<{1,0,0,?,?}> {
1256 let Inst{10-8} = Rdn;
1260 } // neverHasSideEffects
1262 // tLEApcrel - Load a pc-relative address into a register without offending the
1264 let neverHasSideEffects = 1, isReMaterializable = 1 in
1265 def tLEApcrel : T1I<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), IIC_iALUi,
1266 "adr${p}\t$Rd, #$label", []>,
1267 T1Encoding<{1,0,1,0,0,?}> {
1270 let Inst{10-8} = Rd;
1271 // FIXME: Add label encoding/fixup
1274 def tLEApcrelJT : T1I<(outs tGPR:$Rd),
1275 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1276 IIC_iALUi, "adr${p}\t$Rd, #${label}_${id}", []>,
1277 T1Encoding<{1,0,1,0,0,?}> {
1280 let Inst{10-8} = Rd;
1281 // FIXME: Add label encoding/fixup
1284 //===----------------------------------------------------------------------===//
1288 // __aeabi_read_tp preserves the registers r1-r3.
1289 let isCall = 1, Defs = [R0, LR], Uses = [SP] in
1290 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
1291 "bl\t__aeabi_read_tp",
1292 [(set R0, ARMthread_pointer)]> {
1293 // Encoding is 0xf7fffffe.
1294 let Inst = 0xf7fffffe;
1297 //===----------------------------------------------------------------------===//
1298 // SJLJ Exception handling intrinsics
1301 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1302 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1303 // from some other function to get here, and we're using the stack frame for the
1304 // containing function to save/restore registers, we can't keep anything live in
1305 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1306 // tromped upon when we get here from a longjmp(). We force everthing out of
1307 // registers except for our own input by listing the relevant registers in
1308 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1309 // preserve all of the callee-saved resgisters, which is exactly what we want.
1310 // $val is a scratch register for our use.
1311 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ],
1312 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1313 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1314 AddrModeNone, SizeSpecial, NoItinerary, "","",
1315 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1317 // FIXME: Non-Darwin version(s)
1318 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1319 Defs = [ R7, LR, SP ] in
1320 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1321 AddrModeNone, SizeSpecial, IndexModeNone,
1322 Pseudo, NoItinerary, "", "",
1323 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1324 Requires<[IsThumb, IsDarwin]>;
1326 //===----------------------------------------------------------------------===//
1327 // Non-Instruction Patterns
1331 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1332 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1333 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1334 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1337 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1338 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1339 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1340 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1341 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1342 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1344 // Subtract with carry
1345 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1346 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1347 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1348 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1349 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1350 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1352 // ConstantPool, GlobalAddress
1353 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1354 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1357 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1358 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1361 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1362 Requires<[IsThumb, IsNotDarwin]>;
1363 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1364 Requires<[IsThumb, IsDarwin]>;
1366 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1367 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1368 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1369 Requires<[IsThumb, HasV5T, IsDarwin]>;
1371 // Indirect calls to ARM routines
1372 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1373 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1374 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1375 Requires<[IsThumb, HasV5T, IsDarwin]>;
1377 // zextload i1 -> zextload i8
1378 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
1379 (tLDRB t_addrmode_s1:$addr)>;
1381 // extload -> zextload
1382 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
1383 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
1384 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
1386 // If it's impossible to use [r,r] address mode for sextload, select to
1387 // ldr{b|h} + sxt{b|h} instead.
1388 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1389 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
1390 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1391 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
1392 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
1393 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1395 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1396 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
1397 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
1398 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
1400 // Large immediate handling.
1403 def : T1Pat<(i32 thumb_immshifted:$src),
1404 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1405 (thumb_immshifted_shamt imm:$src))>;
1407 def : T1Pat<(i32 imm0_255_comp:$src),
1408 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1410 // Pseudo instruction that combines ldr from constpool and add pc. This should
1411 // be expanded into two instructions late to allow if-conversion and
1413 let isReMaterializable = 1 in
1414 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1416 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1418 Requires<[IsThumb, IsThumb1Only]>;