1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
30 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
31 def imm0_7 : PatLeaf<(i32 imm), [{
32 return (uint32_t)N->getZExtValue() < 8;
34 def imm0_7_neg : PatLeaf<(i32 imm), [{
35 return (uint32_t)-N->getZExtValue() < 8;
38 def imm0_255 : PatLeaf<(i32 imm), [{
39 return (uint32_t)N->getZExtValue() < 256;
41 def imm0_255_comp : PatLeaf<(i32 imm), [{
42 return ~((uint32_t)N->getZExtValue()) < 256;
45 def imm8_255 : PatLeaf<(i32 imm), [{
46 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
48 def imm8_255_neg : PatLeaf<(i32 imm), [{
49 unsigned Val = -N->getZExtValue();
50 return Val >= 8 && Val < 256;
53 // Break imm's up into two pieces: an immediate + a left shift.
54 // This uses thumb_immshifted to match and thumb_immshifted_val and
55 // thumb_immshifted_shamt to get the val/shift pieces.
56 def thumb_immshifted : PatLeaf<(imm), [{
57 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
60 def thumb_immshifted_val : SDNodeXForm<imm, [{
61 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
62 return CurDAG->getTargetConstant(V, MVT::i32);
65 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 // Scaled 4 immediate.
71 def t_imm_s4 : Operand<i32> {
72 let PrintMethod = "printThumbS4ImmOperand";
75 // Define Thumb specific addressing modes.
77 // t_addrmode_rr := reg + reg
79 def t_addrmode_rr : Operand<i32>,
80 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
81 let PrintMethod = "printThumbAddrModeRROperand";
82 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
85 // t_addrmode_s4 := reg + reg
88 def t_addrmode_s4 : Operand<i32>,
89 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
90 let PrintMethod = "printThumbAddrModeS4Operand";
91 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
94 // t_addrmode_s2 := reg + reg
97 def t_addrmode_s2 : Operand<i32>,
98 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
99 let PrintMethod = "printThumbAddrModeS2Operand";
100 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
103 // t_addrmode_s1 := reg + reg
106 def t_addrmode_s1 : Operand<i32>,
107 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
108 let PrintMethod = "printThumbAddrModeS1Operand";
109 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
112 // t_addrmode_sp := sp + imm8 * 4
114 def t_addrmode_sp : Operand<i32>,
115 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
116 let PrintMethod = "printThumbAddrModeSPOperand";
117 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
120 //===----------------------------------------------------------------------===//
121 // Miscellaneous Instructions.
124 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
125 // from removing one half of the matched pairs. That breaks PEI, which assumes
126 // these will always be in pairs, and asserts if it finds otherwise. Better way?
127 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
128 def tADJCALLSTACKUP :
129 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
130 "${:comment} tADJCALLSTACKUP $amt1",
131 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
133 def tADJCALLSTACKDOWN :
134 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
135 "${:comment} tADJCALLSTACKDOWN $amt",
136 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
139 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
140 [/* For disassembly only; pattern left blank */]>,
141 T1Encoding<0b101111> {
142 let Inst{9-8} = 0b11;
143 let Inst{7-0} = 0b00000000;
146 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
147 [/* For disassembly only; pattern left blank */]>,
148 T1Encoding<0b101111> {
149 let Inst{9-8} = 0b11;
150 let Inst{7-0} = 0b00010000;
153 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
154 [/* For disassembly only; pattern left blank */]>,
155 T1Encoding<0b101111> {
156 let Inst{9-8} = 0b11;
157 let Inst{7-0} = 0b00100000;
160 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
161 [/* For disassembly only; pattern left blank */]>,
162 T1Encoding<0b101111> {
163 let Inst{9-8} = 0b11;
164 let Inst{7-0} = 0b00110000;
167 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
168 [/* For disassembly only; pattern left blank */]>,
169 T1Encoding<0b101111> {
170 let Inst{9-8} = 0b11;
171 let Inst{7-0} = 0b01000000;
174 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
175 [/* For disassembly only; pattern left blank */]>,
176 T1Encoding<0b101101> {
177 let Inst{9-5} = 0b10010;
181 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
182 [/* For disassembly only; pattern left blank */]>,
183 T1Encoding<0b101101> {
184 let Inst{9-5} = 0b10010;
188 // The i32imm operand $val can be used by a debugger to store more information
189 // about the breakpoint.
190 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
191 [/* For disassembly only; pattern left blank */]>,
192 T1Encoding<0b101111> {
193 let Inst{9-8} = 0b10;
196 // Change Processor State is a system instruction -- for disassembly only.
197 // The singleton $opt operand contains the following information:
198 // opt{4-0} = mode ==> don't care
199 // opt{5} = changemode ==> 0 (false for 16-bit Thumb instr)
200 // opt{8-6} = AIF from Inst{2-0}
201 // opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
203 // The opt{4-0} and opt{5} sub-fields are to accommodate 32-bit Thumb and ARM
204 // CPS which has more options.
205 def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt",
206 [/* For disassembly only; pattern left blank */]>,
209 // For both thumb1 and thumb2.
210 let isNotDuplicable = 1 in
211 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr,
212 "\n$cp:\n\tadd\t$dst, pc",
213 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
214 T1Special<{0,0,?,?}> {
215 let Inst{6-3} = 0b1111; // A8.6.6 Rm = pc
219 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
220 "add\t$dst, pc, $rhs", []>,
221 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
224 // This is rematerializable, which is particularly useful for taking the
225 // address of locals.
226 let isReMaterializable = 1 in {
227 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
228 "add\t$dst, $sp, $rhs", []>,
229 T1Encoding<{1,0,1,0,1,?}>; // A6.2 & A8.6.8
233 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
234 "add\t$dst, $rhs", []>,
235 T1Misc<{0,0,0,0,0,?,?}>; // A6.2.5 & A8.6.8
238 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
239 "sub\t$dst, $rhs", []>,
240 T1Misc<{0,0,0,0,1,?,?}>; // A6.2.5 & A8.6.215
243 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
244 "add\t$dst, $rhs", []>,
245 T1Special<{0,0,?,?}> {
246 let Inst{6-3} = 0b1101; // A8.6.9 Encoding T1
250 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
251 "add\t$dst, $rhs", []>,
252 T1Special<{0,0,?,?}> {
253 // A8.6.9 Encoding T2
255 let Inst{2-0} = 0b101;
258 //===----------------------------------------------------------------------===//
259 // Control Flow Instructions.
262 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
263 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>,
264 T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25
265 let Inst{6-3} = 0b1110; // Rm = lr
267 // Alternative return instruction used by vararg functions.
268 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target",[]>,
269 T1Special<{1,1,0,?}>; // A6.2.3 & A8.6.25
273 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
274 def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "mov\tpc, $dst",
276 T1Special<{1,0,1,?}> {
277 // <Rd> = Inst{7:2-0} = pc
278 let Inst{2-0} = 0b111;
282 // FIXME: remove when we have a way to marking a MI with these properties.
283 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
284 hasExtraDefRegAllocReq = 1 in
285 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$dsts, variable_ops),
287 "pop${p}\t$dsts", []>,
288 T1Misc<{1,1,0,?,?,?,?}>;
291 Defs = [R0, R1, R2, R3, R12, LR,
292 D0, D1, D2, D3, D4, D5, D6, D7,
293 D16, D17, D18, D19, D20, D21, D22, D23,
294 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
295 // Also used for Thumb2
296 def tBL : TIx2<0b11110, 0b11, 1,
297 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
299 [(ARMtcall tglobaladdr:$func)]>,
300 Requires<[IsThumb, IsNotDarwin]>;
302 // ARMv5T and above, also used for Thumb2
303 def tBLXi : TIx2<0b11110, 0b11, 0,
304 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
306 [(ARMcall tglobaladdr:$func)]>,
307 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
309 // Also used for Thumb2
310 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
312 [(ARMtcall GPR:$func)]>,
313 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
314 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
317 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
318 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
319 "mov\tlr, pc\n\tbx\t$func",
320 [(ARMcall_nolink tGPR:$func)]>,
321 Requires<[IsThumb1Only, IsNotDarwin]>;
324 // On Darwin R9 is call-clobbered.
326 Defs = [R0, R1, R2, R3, R9, R12, LR,
327 D0, D1, D2, D3, D4, D5, D6, D7,
328 D16, D17, D18, D19, D20, D21, D22, D23,
329 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
330 // Also used for Thumb2
331 def tBLr9 : TIx2<0b11110, 0b11, 1,
332 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
334 [(ARMtcall tglobaladdr:$func)]>,
335 Requires<[IsThumb, IsDarwin]>;
337 // ARMv5T and above, also used for Thumb2
338 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
339 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
341 [(ARMcall tglobaladdr:$func)]>,
342 Requires<[IsThumb, HasV5T, IsDarwin]>;
344 // Also used for Thumb2
345 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
347 [(ARMtcall GPR:$func)]>,
348 Requires<[IsThumb, HasV5T, IsDarwin]>,
349 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24
352 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
353 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
354 "mov\tlr, pc\n\tbx\t$func",
355 [(ARMcall_nolink tGPR:$func)]>,
356 Requires<[IsThumb1Only, IsDarwin]>;
359 let isBranch = 1, isTerminator = 1 in {
360 let isBarrier = 1 in {
361 let isPredicable = 1 in
362 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
363 "b\t$target", [(br bb:$target)]>,
364 T1Encoding<{1,1,1,0,0,?}>;
368 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
369 "bl\t$target\t${:comment} far jump",[]>;
371 def tBR_JTr : T1JTI<(outs),
372 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
373 IIC_Br, "mov\tpc, $target\n\t.align\t2$jt",
374 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
376 let Inst{15-7} = 0b010001101;
377 let Inst{2-0} = 0b111;
382 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
383 // a two-value operand where a dag node expects two operands. :(
384 let isBranch = 1, isTerminator = 1 in
385 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
387 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
388 T1Encoding<{1,1,0,1,?,?}>;
390 // Compare and branch on zero / non-zero
391 let isBranch = 1, isTerminator = 1 in {
392 def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
393 "cbz\t$cmp, $target", []>,
394 T1Misc<{0,0,?,1,?,?,?}>;
396 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
397 "cbnz\t$cmp, $target", []>,
398 T1Misc<{1,0,?,1,?,?,?}>;
401 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
402 // A8.6.16 B: Encoding T1
403 // If Inst{11-8} == 0b1111 then SEE SVC
405 def tSVC : T1pI<(outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", []>,
407 let Inst{15-12} = 0b1101;
408 let Inst{11-8} = 0b1111;
412 // A8.6.16 B: Encoding T1
413 // If Inst{11-8} == 0b1110 then UNDEFINED
414 let isBarrier = 1, isTerminator = 1 in
415 def tTRAP : TI<(outs), (ins), IIC_Br,
416 "trap", [(trap)]>, Encoding16 {
417 let Inst{15-12} = 0b1101;
418 let Inst{11-8} = 0b1110;
421 //===----------------------------------------------------------------------===//
422 // Load Store Instructions.
425 let canFoldAsLoad = 1, isReMaterializable = 1 in
426 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoad_r,
427 "ldr", "\t$dst, $addr",
428 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>,
430 def tLDRi: T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoad_r,
431 "ldr", "\t$dst, $addr",
435 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoad_bh_r,
436 "ldrb", "\t$dst, $addr",
437 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>,
439 def tLDRBi: T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoad_bh_r,
440 "ldrb", "\t$dst, $addr",
444 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoad_bh_r,
445 "ldrh", "\t$dst, $addr",
446 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>,
448 def tLDRHi: T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoad_bh_r,
449 "ldrh", "\t$dst, $addr",
453 let AddedComplexity = 10 in
454 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad_bh_r,
455 "ldrsb", "\t$dst, $addr",
456 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>,
459 let AddedComplexity = 10 in
460 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad_bh_r,
461 "ldrsh", "\t$dst, $addr",
462 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>,
465 let canFoldAsLoad = 1 in
466 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
467 "ldr", "\t$dst, $addr",
468 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
471 // Special instruction for restore. It cannot clobber condition register
472 // when it's expanded by eliminateCallFramePseudoInstr().
473 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
474 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
475 "ldr", "\t$dst, $addr", []>,
479 // FIXME: Use ldr.n to work around a Darwin assembler bug.
480 let canFoldAsLoad = 1, isReMaterializable = 1 in
481 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
482 "ldr", ".n\t$dst, $addr",
483 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>,
484 T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59
486 // Special LDR for loads from non-pc-relative constpools.
487 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
488 isReMaterializable = 1 in
489 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
490 "ldr", "\t$dst, $addr", []>,
493 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStore_r,
494 "str", "\t$src, $addr",
495 [(store tGPR:$src, t_addrmode_s4:$addr)]>,
497 def tSTRi: T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStore_r,
498 "str", "\t$src, $addr",
502 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStore_bh_r,
503 "strb", "\t$src, $addr",
504 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>,
506 def tSTRBi: T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStore_bh_r,
507 "strb", "\t$src, $addr",
511 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStore_bh_r,
512 "strh", "\t$src, $addr",
513 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>,
515 def tSTRHi: T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStore_bh_r,
516 "strh", "\t$src, $addr",
520 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
521 "str", "\t$src, $addr",
522 [(store tGPR:$src, t_addrmode_sp:$addr)]>,
525 let mayStore = 1, neverHasSideEffects = 1 in {
526 // Special instruction for spill. It cannot clobber condition register
527 // when it's expanded by eliminateCallFramePseudoInstr().
528 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
529 "str", "\t$src, $addr", []>,
533 //===----------------------------------------------------------------------===//
534 // Load / store multiple Instructions.
537 // These require base address to be written back or one of the loaded regs.
538 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
539 def tLDM : T1I<(outs),
540 (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops),
542 "ldm${addr:submode}${p}\t$addr, $dsts", []>,
543 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
545 def tLDM_UPD : T1It<(outs tGPR:$wb),
546 (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops),
548 "ldm${addr:submode}${p}\t$addr!, $dsts",
549 "$addr.addr = $wb", []>,
550 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
551 } // mayLoad, neverHasSideEffects = 1, hasExtraDefRegAllocReq
553 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
554 def tSTM_UPD : T1It<(outs tGPR:$wb),
555 (ins addrmode4:$addr, pred:$p, reglist:$srcs, variable_ops),
557 "stm${addr:submode}${p}\t$addr!, $srcs",
558 "$addr.addr = $wb", []>,
559 T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189
561 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
562 def tPOP : T1I<(outs), (ins pred:$p, reglist:$dsts, variable_ops), IIC_iLoadmBr,
563 "pop${p}\t$dsts", []>,
564 T1Misc<{1,1,0,?,?,?,?}>;
566 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
567 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$srcs, variable_ops), IIC_iStorem,
568 "push${p}\t$srcs", []>,
569 T1Misc<{0,1,0,?,?,?,?}>;
571 //===----------------------------------------------------------------------===//
572 // Arithmetic Instructions.
575 // Add with carry register
576 let isCommutable = 1, Uses = [CPSR] in
577 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
578 "adc", "\t$dst, $rhs",
579 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>,
580 T1DataProcessing<0b0101>;
583 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
584 "add", "\t$dst, $lhs, $rhs",
585 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>,
588 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
589 "add", "\t$dst, $rhs",
590 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>,
591 T1General<{1,1,0,?,?}>;
594 let isCommutable = 1 in
595 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
596 "add", "\t$dst, $lhs, $rhs",
597 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>,
600 let neverHasSideEffects = 1 in
601 def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
602 "add", "\t$dst, $rhs", []>,
603 T1Special<{0,0,?,?}>;
606 let isCommutable = 1 in
607 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
608 "and", "\t$dst, $rhs",
609 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>,
610 T1DataProcessing<0b0000>;
613 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
614 "asr", "\t$dst, $lhs, $rhs",
615 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>,
616 T1General<{0,1,0,?,?}>;
619 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
620 "asr", "\t$dst, $rhs",
621 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>,
622 T1DataProcessing<0b0100>;
625 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
626 "bic", "\t$dst, $rhs",
627 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>,
628 T1DataProcessing<0b1110>;
631 let isCompare = 1, Defs = [CPSR] in {
632 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
633 // Compare-to-zero still works out, just not the relationals
634 //def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
635 // "cmn", "\t$lhs, $rhs",
636 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>,
637 // T1DataProcessing<0b1011>;
638 def tCMNz : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
639 "cmn", "\t$lhs, $rhs",
640 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>,
641 T1DataProcessing<0b1011>;
645 let isCompare = 1, Defs = [CPSR] in {
646 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
647 "cmp", "\t$lhs, $rhs",
648 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>,
649 T1General<{1,0,1,?,?}>;
650 def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
651 "cmp", "\t$lhs, $rhs",
652 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>,
653 T1General<{1,0,1,?,?}>;
657 let isCompare = 1, Defs = [CPSR] in {
658 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
659 "cmp", "\t$lhs, $rhs",
660 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>,
661 T1DataProcessing<0b1010>;
662 def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
663 "cmp", "\t$lhs, $rhs",
664 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>,
665 T1DataProcessing<0b1010>;
667 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
668 "cmp", "\t$lhs, $rhs", []>,
669 T1Special<{0,1,?,?}>;
670 def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
671 "cmp", "\t$lhs, $rhs", []>,
672 T1Special<{0,1,?,?}>;
677 let isCommutable = 1 in
678 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
679 "eor", "\t$dst, $rhs",
680 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>,
681 T1DataProcessing<0b0001>;
684 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
685 "lsl", "\t$dst, $lhs, $rhs",
686 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>,
687 T1General<{0,0,0,?,?}>;
690 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
691 "lsl", "\t$dst, $rhs",
692 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>,
693 T1DataProcessing<0b0010>;
696 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
697 "lsr", "\t$dst, $lhs, $rhs",
698 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>,
699 T1General<{0,0,1,?,?}>;
702 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
703 "lsr", "\t$dst, $rhs",
704 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>,
705 T1DataProcessing<0b0011>;
708 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
709 "mov", "\t$dst, $src",
710 [(set tGPR:$dst, imm0_255:$src)]>,
711 T1General<{1,0,0,?,?}>;
713 // TODO: A7-73: MOV(2) - mov setting flag.
716 let neverHasSideEffects = 1 in {
717 // FIXME: Make this predicable.
718 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
719 "mov\t$dst, $src", []>,
722 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
723 "movs\t$dst, $src", []>, Encoding16 {
724 let Inst{15-6} = 0b0000000000;
727 // FIXME: Make these predicable.
728 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
729 "mov\t$dst, $src", []>,
730 T1Special<{1,0,0,?}>;
731 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
732 "mov\t$dst, $src", []>,
733 T1Special<{1,0,?,0}>;
734 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
735 "mov\t$dst, $src", []>,
736 T1Special<{1,0,?,?}>;
737 } // neverHasSideEffects
740 let isCommutable = 1 in
741 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
742 "mul", "\t$dst, $rhs, $dst", /* A8.6.105 MUL Encoding T1 */
743 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>,
744 T1DataProcessing<0b1101>;
746 // move inverse register
747 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMVNr,
748 "mvn", "\t$dst, $src",
749 [(set tGPR:$dst, (not tGPR:$src))]>,
750 T1DataProcessing<0b1111>;
752 // bitwise or register
753 let isCommutable = 1 in
754 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
755 "orr", "\t$dst, $rhs",
756 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>,
757 T1DataProcessing<0b1100>;
760 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
761 "rev", "\t$dst, $src",
762 [(set tGPR:$dst, (bswap tGPR:$src))]>,
763 Requires<[IsThumb1Only, HasV6]>,
764 T1Misc<{1,0,1,0,0,0,?}>;
766 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
767 "rev16", "\t$dst, $src",
769 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
770 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
771 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
772 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
773 Requires<[IsThumb1Only, HasV6]>,
774 T1Misc<{1,0,1,0,0,1,?}>;
776 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
777 "revsh", "\t$dst, $src",
780 (or (srl (and tGPR:$src, 0xFF00), (i32 8)),
781 (shl tGPR:$src, (i32 8))), i16))]>,
782 Requires<[IsThumb1Only, HasV6]>,
783 T1Misc<{1,0,1,0,1,1,?}>;
785 // rotate right register
786 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
787 "ror", "\t$dst, $rhs",
788 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>,
789 T1DataProcessing<0b0111>;
792 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi,
793 "rsb", "\t$dst, $src, #0",
794 [(set tGPR:$dst, (ineg tGPR:$src))]>,
795 T1DataProcessing<0b1001>;
797 // Subtract with carry register
799 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
800 "sbc", "\t$dst, $rhs",
801 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>,
802 T1DataProcessing<0b0110>;
804 // Subtract immediate
805 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
806 "sub", "\t$dst, $lhs, $rhs",
807 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>,
810 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
811 "sub", "\t$dst, $rhs",
812 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>,
813 T1General<{1,1,1,?,?}>;
816 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
817 "sub", "\t$dst, $lhs, $rhs",
818 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>,
821 // TODO: A7-96: STMIA - store multiple.
824 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
825 "sxtb", "\t$dst, $src",
826 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
827 Requires<[IsThumb1Only, HasV6]>,
828 T1Misc<{0,0,1,0,0,1,?}>;
831 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
832 "sxth", "\t$dst, $src",
833 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
834 Requires<[IsThumb1Only, HasV6]>,
835 T1Misc<{0,0,1,0,0,0,?}>;
838 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
839 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iTSTr,
840 "tst", "\t$lhs, $rhs",
841 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>,
842 T1DataProcessing<0b1000>;
845 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
846 "uxtb", "\t$dst, $src",
847 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
848 Requires<[IsThumb1Only, HasV6]>,
849 T1Misc<{0,0,1,0,1,1,?}>;
852 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
853 "uxth", "\t$dst, $src",
854 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
855 Requires<[IsThumb1Only, HasV6]>,
856 T1Misc<{0,0,1,0,1,0,?}>;
859 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
860 // Expanded after instruction selection into a branch sequence.
861 let usesCustomInserter = 1 in // Expanded after instruction selection.
863 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
864 NoItinerary, "${:comment} tMOVCCr $cc",
865 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
868 // 16-bit movcc in IT blocks for Thumb2.
869 let neverHasSideEffects = 1 in {
870 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
871 "mov", "\t$dst, $rhs", []>,
872 T1Special<{1,0,?,?}>;
874 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
875 "mov", "\t$dst, $rhs", []>,
876 T1General<{1,0,0,?,?}>;
877 } // neverHasSideEffects
879 // tLEApcrel - Load a pc-relative address into a register without offending the
881 let neverHasSideEffects = 1 in {
882 let isReMaterializable = 1 in
883 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
884 "adr$p\t$dst, #$label", []>,
885 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
887 } // neverHasSideEffects
888 def tLEApcrelJT : T1I<(outs tGPR:$dst),
889 (ins i32imm:$label, nohash_imm:$id, pred:$p),
890 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>,
891 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
893 //===----------------------------------------------------------------------===//
897 // __aeabi_read_tp preserves the registers r1-r3.
900 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
901 "bl\t__aeabi_read_tp",
902 [(set R0, ARMthread_pointer)]>;
905 // SJLJ Exception handling intrinsics
906 // eh_sjlj_setjmp() is an instruction sequence to store the return
907 // address and save #0 in R0 for the non-longjmp case.
908 // Since by its nature we may be coming from some other function to get
909 // here, and we're using the stack frame for the containing function to
910 // save/restore registers, we can't keep anything live in regs across
911 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
912 // when we get here from a longjmp(). We force everthing out of registers
913 // except for our own input by listing the relevant registers in Defs. By
914 // doing so, we also cause the prologue/epilogue code to actively preserve
915 // all of the callee-saved resgisters, which is exactly what we want.
916 // $val is a scratch register for our use.
918 [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ], hasSideEffects = 1,
920 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
921 AddrModeNone, SizeSpecial, NoItinerary,
922 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
924 "str\t$val, [$src, #4]\n\t"
927 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
929 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
932 // FIXME: Non-Darwin version(s)
933 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
934 Defs = [ R7, LR, SP ] in {
935 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
936 AddrModeNone, SizeSpecial, IndexModeNone,
938 "ldr\t$scratch, [$src, #8]\n\t"
939 "mov\tsp, $scratch\n\t"
940 "ldr\t$scratch, [$src, #4]\n\t"
941 "ldr\tr7, [$src]\n\t"
943 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
944 Requires<[IsThumb, IsDarwin]>;
947 //===----------------------------------------------------------------------===//
948 // Non-Instruction Patterns
952 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
953 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
954 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
955 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
956 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
957 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
959 // Subtract with carry
960 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
961 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
962 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
963 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
964 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
965 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
967 // ConstantPool, GlobalAddress
968 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
969 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
972 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
973 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
976 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
977 Requires<[IsThumb, IsNotDarwin]>;
978 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
979 Requires<[IsThumb, IsDarwin]>;
981 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
982 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
983 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
984 Requires<[IsThumb, HasV5T, IsDarwin]>;
986 // Indirect calls to ARM routines
987 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
988 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
989 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
990 Requires<[IsThumb, HasV5T, IsDarwin]>;
992 // zextload i1 -> zextload i8
993 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
994 (tLDRB t_addrmode_s1:$addr)>;
996 // extload -> zextload
997 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
998 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
999 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
1001 // If it's impossible to use [r,r] address mode for sextload, select to
1002 // ldr{b|h} + sxt{b|h} instead.
1003 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1004 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
1005 Requires<[IsThumb1Only, HasV6]>;
1006 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
1007 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
1008 Requires<[IsThumb1Only, HasV6]>;
1010 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1011 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
1012 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
1013 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
1015 // Large immediate handling.
1018 def : T1Pat<(i32 thumb_immshifted:$src),
1019 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1020 (thumb_immshifted_shamt imm:$src))>;
1022 def : T1Pat<(i32 imm0_255_comp:$src),
1023 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1025 // Pseudo instruction that combines ldr from constpool and add pc. This should
1026 // be expanded into two instructions late to allow if-conversion and
1028 let isReMaterializable = 1 in
1029 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1031 "${:comment} ldr.n\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
1032 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1034 Requires<[IsThumb1Only]>;