1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // IT block condition mask
70 def it_mask : Operand<i32> {
71 let PrintMethod = "printThumbITMask";
74 // Define Thumb specific addressing modes.
76 // t_addrmode_rr := reg + reg
78 def t_addrmode_rr : Operand<i32>,
79 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
80 let PrintMethod = "printThumbAddrModeRROperand";
81 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
84 // t_addrmode_s4 := reg + reg
87 def t_addrmode_s4 : Operand<i32>,
88 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
89 let PrintMethod = "printThumbAddrModeS4Operand";
90 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
93 // t_addrmode_s2 := reg + reg
96 def t_addrmode_s2 : Operand<i32>,
97 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
98 let PrintMethod = "printThumbAddrModeS2Operand";
99 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
102 // t_addrmode_s1 := reg + reg
105 def t_addrmode_s1 : Operand<i32>,
106 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
107 let PrintMethod = "printThumbAddrModeS1Operand";
108 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
111 // t_addrmode_sp := sp + imm8 * 4
113 def t_addrmode_sp : Operand<i32>,
114 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
115 let PrintMethod = "printThumbAddrModeSPOperand";
116 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
119 //===----------------------------------------------------------------------===//
120 // Miscellaneous Instructions.
123 let Defs = [SP], Uses = [SP] in {
124 def tADJCALLSTACKUP :
125 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
126 "@ tADJCALLSTACKUP $amt1",
127 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
129 def tADJCALLSTACKDOWN :
130 PseudoInst<(outs), (ins i32imm:$amt),
131 "@ tADJCALLSTACKDOWN $amt",
132 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
135 let isNotDuplicable = 1 in
136 def tPICADD : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
137 "$cp:\n\tadd $dst, pc",
138 [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
141 def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs),
142 "add $dst, pc, $rhs * 4", []>;
145 // FIXME: hard code sp?
146 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs),
147 "add $dst, $sp, $rhs * 4 @ addrspi", []>;
150 // FIXME: hard code sp?
151 def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
152 "add $dst, $rhs * 4", []>;
154 // FIXME: Make use of the following?
158 //===----------------------------------------------------------------------===//
159 // Control Flow Instructions.
162 let isReturn = 1, isTerminator = 1 in {
163 def tBX_RET : T1I<(outs), (ins), "bx lr", [(ARMretflag)]>;
164 // Alternative return instruction used by vararg functions.
165 def tBX_RET_vararg : T1I<(outs), (ins tGPR:$target), "bx $target", []>;
168 // FIXME: remove when we have a way to marking a MI with these properties.
169 let isReturn = 1, isTerminator = 1 in
170 def tPOP_RET : T1I<(outs reglist:$dst1, variable_ops), (ins),
174 Defs = [R0, R1, R2, R3, LR,
175 D0, D1, D2, D3, D4, D5, D6, D7] in {
176 def tBL : T1Ix2<(outs), (ins i32imm:$func, variable_ops),
178 [(ARMtcall tglobaladdr:$func)]>;
180 def tBLXi : T1Ix2<(outs), (ins i32imm:$func, variable_ops),
182 [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
183 def tBLXr : T1I<(outs), (ins tGPR:$func, variable_ops),
185 [(ARMtcall tGPR:$func)]>, Requires<[HasV5T]>;
187 def tBX : T1Ix2<(outs), (ins tGPR:$func, variable_ops),
188 "cpy lr, pc\n\tbx $func",
189 [(ARMcall_nolink tGPR:$func)]>;
192 let isBranch = 1, isTerminator = 1 in {
193 let isBarrier = 1 in {
194 let isPredicable = 1 in
195 def tB : T1I<(outs), (ins brtarget:$target), "b $target",
199 def tBfar : T1Ix2<(outs), (ins brtarget:$target),
200 "bl $target\t@ far jump",[]>;
202 def tBR_JTr : T1JTI<(outs),
203 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
204 "cpy pc, $target \n\t.align\t2\n$jt",
205 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
209 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
210 // a two-value operand where a dag node expects two operands. :(
211 let isBranch = 1, isTerminator = 1 in
212 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target",
213 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
216 def tIT : TI<(outs), (ins pred:$cc, it_mask:$mask),
219 //===----------------------------------------------------------------------===//
220 // Load Store Instructions.
223 let canFoldAsLoad = 1 in
224 def tLDR : T1I4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr),
226 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
228 def tLDRB : T1I1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr),
230 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
232 def tLDRH : T1I2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr),
234 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
236 def tLDRSB : T1I1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
238 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
240 def tLDRSH : T1I2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
242 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
244 let canFoldAsLoad = 1 in
245 def tLDRspi : T1Is<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
247 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
249 // Special instruction for restore. It cannot clobber condition register
250 // when it's expanded by eliminateCallFramePseudoInstr().
251 let canFoldAsLoad = 1, mayLoad = 1 in
252 def tRestore : T1Is<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
253 "ldr $dst, $addr", []>;
256 let canFoldAsLoad = 1 in
257 def tLDRpci : T1Is<(outs tGPR:$dst), (ins i32imm:$addr),
259 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
261 // Special LDR for loads from non-pc-relative constpools.
262 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
263 def tLDRcp : T1Is<(outs tGPR:$dst), (ins i32imm:$addr),
264 "ldr $dst, $addr", []>;
266 def tSTR : T1I4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr),
268 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
270 def tSTRB : T1I1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr),
272 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
274 def tSTRH : T1I2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr),
276 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
278 def tSTRspi : T1Is<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
280 [(store tGPR:$src, t_addrmode_sp:$addr)]>;
282 let mayStore = 1 in {
283 // Special instruction for spill. It cannot clobber condition register
284 // when it's expanded by eliminateCallFramePseudoInstr().
285 def tSpill : T1Is<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
286 "str $src, $addr", []>;
289 //===----------------------------------------------------------------------===//
290 // Load / store multiple Instructions.
293 // TODO: A7-44: LDMIA - load multiple
296 def tPOP : T1I<(outs reglist:$dst1, variable_ops), (ins),
300 def tPUSH : T1I<(outs), (ins reglist:$src1, variable_ops),
303 //===----------------------------------------------------------------------===//
304 // Arithmetic Instructions.
307 // Add with carry register
308 let isCommutable = 1, Defs = [CPSR], Uses = [CPSR] in
309 def tADCS : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
311 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
314 let Defs = [CPSR] in {
315 def tADDi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
316 "add $dst, $lhs, $rhs",
317 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
318 def tADDSi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
319 "add $dst, $lhs, $rhs",
320 [(set tGPR:$dst, (addc tGPR:$lhs, imm0_7:$rhs))]>;
323 let Defs = [CPSR] in {
324 def tADDi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
326 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
327 def tADDSi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
329 [(set tGPR:$dst, (addc tGPR:$lhs, imm8_255:$rhs))]>;
333 let isCommutable = 1, Defs = [CPSR] in {
334 def tADDrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
335 "add $dst, $lhs, $rhs",
336 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
337 def tADDSrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
338 "add $dst, $lhs, $rhs",
339 [(set tGPR:$dst, (addc tGPR:$lhs, tGPR:$rhs))]>;
342 let neverHasSideEffects = 1 in
343 def tADDhirr : T1It<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs),
344 "add $dst, $rhs @ addhirr", []>;
347 let isCommutable = 1, Defs = [CPSR] in
348 def tAND : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
350 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
354 def tASRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
355 "asr $dst, $lhs, $rhs",
356 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
360 def tASRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
362 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
366 def tBIC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
368 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
371 let Defs = [CPSR] in {
372 def tCMN : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
374 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
375 def tCMNZ : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
377 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
381 let Defs = [CPSR] in {
382 def tCMPi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs),
384 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
385 def tCMPZi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs),
387 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>;
392 let Defs = [CPSR] in {
393 def tCMPr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
395 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
396 def tCMPZr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
398 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>;
401 // TODO: A7-37: CMP(3) - cmp hi regs
404 let isCommutable = 1, Defs = [CPSR] in
405 def tEOR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
407 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
411 def tLSLri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
412 "lsl $dst, $lhs, $rhs",
413 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
417 def tLSLrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
419 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
423 def tLSRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
424 "lsr $dst, $lhs, $rhs",
425 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
429 def tLSRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
431 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
435 def tMOVi8 : T1I<(outs tGPR:$dst), (ins i32imm:$src),
437 [(set tGPR:$dst, imm0_255:$src)]>;
439 // TODO: A7-73: MOV(2) - mov setting flag.
442 // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
443 // which is MOV(3). This also supports high registers.
444 let neverHasSideEffects = 1 in {
445 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src),
446 "cpy $dst, $src", []>;
447 def tMOVhir2lor : T1I<(outs tGPR:$dst), (ins GPR:$src),
448 "cpy $dst, $src\t@ hir2lor", []>;
449 def tMOVlor2hir : T1I<(outs GPR:$dst), (ins tGPR:$src),
450 "cpy $dst, $src\t@ lor2hir", []>;
451 def tMOVhir2hir : T1I<(outs GPR:$dst), (ins GPR:$src),
452 "cpy $dst, $src\t@ hir2hir", []>;
453 } // neverHasSideEffects
456 let isCommutable = 1, Defs = [CPSR] in
457 def tMUL : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
459 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
461 // move inverse register
463 def tMVN : T1I<(outs tGPR:$dst), (ins tGPR:$src),
465 [(set tGPR:$dst, (not tGPR:$src))]>;
469 def tNEG : T1I<(outs tGPR:$dst), (ins tGPR:$src),
471 [(set tGPR:$dst, (ineg tGPR:$src))]>;
473 // bitwise or register
474 let isCommutable = 1, Defs = [CPSR] in
475 def tORR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
477 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
480 def tREV : T1I<(outs tGPR:$dst), (ins tGPR:$src),
482 [(set tGPR:$dst, (bswap tGPR:$src))]>,
483 Requires<[IsThumb1Only, HasV6]>;
485 def tREV16 : T1I<(outs tGPR:$dst), (ins tGPR:$src),
488 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
489 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
490 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
491 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
492 Requires<[IsThumb1Only, HasV6]>;
494 def tREVSH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
498 (or (srl (and tGPR:$src, 0xFFFF), (i32 8)),
499 (shl tGPR:$src, (i32 8))), i16))]>,
500 Requires<[IsThumb1Only, HasV6]>;
502 // rotate right register
504 def tROR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
506 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
508 // Subtract with carry register
509 let Defs = [CPSR], Uses = [CPSR] in
510 def tSBCS : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
512 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
514 // Subtract immediate
515 let Defs = [CPSR] in {
516 def tSUBi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
517 "sub $dst, $lhs, $rhs",
518 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
519 def tSUBSi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
520 "sub $dst, $lhs, $rhs",
521 [(set tGPR:$dst, (addc tGPR:$lhs, imm0_7_neg:$rhs))]>;
524 let Defs = [CPSR] in {
525 def tSUBi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
527 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
528 def tSUBSi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
530 [(set tGPR:$dst, (addc tGPR:$lhs, imm8_255_neg:$rhs))]>;
534 let Defs = [CPSR] in {
535 def tSUBrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
536 "sub $dst, $lhs, $rhs",
537 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
538 def tSUBSrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
539 "sub $dst, $lhs, $rhs",
540 [(set tGPR:$dst, (subc tGPR:$lhs, tGPR:$rhs))]>;
543 // TODO: A7-96: STMIA - store multiple.
545 def tSUBspi : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
546 "sub $dst, $rhs * 4", []>;
549 def tSXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src),
551 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
552 Requires<[IsThumb1Only, HasV6]>;
555 def tSXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
557 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
558 Requires<[IsThumb1Only, HasV6]>;
561 let isCommutable = 1, Defs = [CPSR] in
562 def tTST : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
564 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
567 def tUXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src),
569 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
570 Requires<[IsThumb1Only, HasV6]>;
573 def tUXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
575 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
576 Requires<[IsThumb1Only, HasV6]>;
579 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
580 // Expanded by the scheduler into a branch sequence.
581 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
583 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
585 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
587 // tLEApcrel - Load a pc-relative address into a register without offending the
589 def tLEApcrel : T1Ix2<(outs tGPR:$dst), (ins i32imm:$label),
590 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
591 "${:private}PCRELL${:uid}+4))\n"),
592 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
593 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
596 def tLEApcrelJT : T1Ix2<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id),
597 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
598 "${:private}PCRELL${:uid}+4))\n"),
599 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
600 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
603 //===----------------------------------------------------------------------===//
607 // __aeabi_read_tp preserves the registers r1-r3.
610 def tTPsoft : T1Ix2<(outs), (ins),
611 "bl __aeabi_read_tp",
612 [(set R0, ARMthread_pointer)]>;
615 //===----------------------------------------------------------------------===//
616 // Non-Instruction Patterns
619 // ConstantPool, GlobalAddress
620 def : TPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
621 def : TPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
624 def : TPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
625 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
628 def : TPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
629 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
631 // Indirect calls to ARM routines
632 def : Tv5Pat<(ARMcall tGPR:$dst), (tBLXr tGPR:$dst)>;
634 // zextload i1 -> zextload i8
635 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
636 (tLDRB t_addrmode_s1:$addr)>;
638 // extload -> zextload
639 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
640 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
641 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
643 // Large immediate handling.
646 def : T1Pat<(i32 thumb_immshifted:$src),
647 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
648 (thumb_immshifted_shamt imm:$src))>;
650 def : T1Pat<(i32 imm0_255_comp:$src),
651 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;