1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
77 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
78 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
80 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
81 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
82 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
83 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
85 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
86 SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]>;
87 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
88 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
89 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
91 //===----------------------------------------------------------------------===//
92 // NEON operand definitions
93 //===----------------------------------------------------------------------===//
95 // addrmode_neonldstm := reg
97 /* TODO: Take advantage of vldm.
98 def addrmode_neonldstm : Operand<i32>,
99 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
100 let PrintMethod = "printAddrNeonLdStMOperand";
101 let MIOperandInfo = (ops GPR, i32imm);
105 //===----------------------------------------------------------------------===//
106 // NEON load / store instructions
107 //===----------------------------------------------------------------------===//
109 /* TODO: Take advantage of vldm.
111 def VLDMD : NI<(outs),
112 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
114 "vldm${addr:submode} ${addr:base}, $dst1",
116 let Inst{27-25} = 0b110;
118 let Inst{11-9} = 0b101;
121 def VLDMS : NI<(outs),
122 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
124 "vldm${addr:submode} ${addr:base}, $dst1",
126 let Inst{27-25} = 0b110;
128 let Inst{11-9} = 0b101;
133 // Use vldmia to load a Q register as a D register pair.
134 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
136 "vldmia $addr, ${dst:dregpair}",
137 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
138 let Inst{27-25} = 0b110;
139 let Inst{24} = 0; // P bit
140 let Inst{23} = 1; // U bit
142 let Inst{11-9} = 0b101;
145 // Use vstmia to store a Q register as a D register pair.
146 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
148 "vstmia $addr, ${src:dregpair}",
149 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
150 let Inst{27-25} = 0b110;
151 let Inst{24} = 0; // P bit
152 let Inst{23} = 1; // U bit
154 let Inst{11-9} = 0b101;
157 // VLD1 : Vector Load (multiple single elements)
158 class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
159 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr), NoItinerary,
160 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"), "",
161 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
162 class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
163 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr), NoItinerary,
164 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"), "",
165 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
167 def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1>;
168 def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1>;
169 def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1>;
170 def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1>;
171 def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1>;
173 def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1>;
174 def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1>;
175 def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1>;
176 def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1>;
177 def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1>;
181 // VLD2 : Vector Load (multiple 2-element structures)
182 class VLD2D<string OpcodeStr>
183 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr), NoItinerary,
184 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), "", []>;
186 def VLD2d8 : VLD2D<"vld2.8">;
187 def VLD2d16 : VLD2D<"vld2.16">;
188 def VLD2d32 : VLD2D<"vld2.32">;
190 // VLD3 : Vector Load (multiple 3-element structures)
191 class VLD3D<string OpcodeStr>
192 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
194 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), "", []>;
196 def VLD3d8 : VLD3D<"vld3.8">;
197 def VLD3d16 : VLD3D<"vld3.16">;
198 def VLD3d32 : VLD3D<"vld3.32">;
200 // VLD4 : Vector Load (multiple 4-element structures)
201 class VLD4D<string OpcodeStr>
202 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
203 (ins addrmode6:$addr), NoItinerary,
204 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"),
207 def VLD4d8 : VLD4D<"vld4.8">;
208 def VLD4d16 : VLD4D<"vld4.16">;
209 def VLD4d32 : VLD4D<"vld4.32">;
211 // VLD2LN : Vector Load (single 2-element structure to one lane)
212 class VLD2LND<string OpcodeStr>
213 : NLdSt<(outs DPR:$dst1, DPR:$dst2),
214 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
216 !strconcat(OpcodeStr, "\t\\{$dst1[$lane],$dst2[$lane]\\}, $addr"),
217 "$src1 = $dst1, $src2 = $dst2", []>;
219 def VLD2LNd8 : VLD2LND<"vld2.8">;
220 def VLD2LNd16 : VLD2LND<"vld2.16">;
221 def VLD2LNd32 : VLD2LND<"vld2.32">;
223 // VLD3LN : Vector Load (single 3-element structure to one lane)
224 class VLD3LND<string OpcodeStr>
225 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
226 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
227 nohash_imm:$lane), NoItinerary,
228 !strconcat(OpcodeStr,
229 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"),
230 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
232 def VLD3LNd8 : VLD3LND<"vld3.8">;
233 def VLD3LNd16 : VLD3LND<"vld3.16">;
234 def VLD3LNd32 : VLD3LND<"vld3.32">;
236 // VLD4LN : Vector Load (single 4-element structure to one lane)
237 class VLD4LND<string OpcodeStr>
238 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
239 (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
240 nohash_imm:$lane), NoItinerary,
241 !strconcat(OpcodeStr,
242 "\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane],$dst4[$lane]\\}, $addr"),
243 "$src1 = $dst1, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>;
245 def VLD4LNd8 : VLD4LND<"vld4.8">;
246 def VLD4LNd16 : VLD4LND<"vld4.16">;
247 def VLD4LNd32 : VLD4LND<"vld4.32">;
250 // VST1 : Vector Store (multiple single elements)
251 class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
252 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src), NoItinerary,
253 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"), "",
254 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
255 class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
256 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src), NoItinerary,
257 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), "",
258 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
260 def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1>;
261 def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1>;
262 def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1>;
263 def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1>;
264 def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1>;
266 def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1>;
267 def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1>;
268 def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1>;
269 def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1>;
270 def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1>;
272 let mayStore = 1 in {
274 // VST2 : Vector Store (multiple 2-element structures)
275 class VST2D<string OpcodeStr>
276 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary,
277 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), "", []>;
279 def VST2d8 : VST2D<"vst2.8">;
280 def VST2d16 : VST2D<"vst2.16">;
281 def VST2d32 : VST2D<"vst2.32">;
283 // VST3 : Vector Store (multiple 3-element structures)
284 class VST3D<string OpcodeStr>
285 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
287 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), "", []>;
289 def VST3d8 : VST3D<"vst3.8">;
290 def VST3d16 : VST3D<"vst3.16">;
291 def VST3d32 : VST3D<"vst3.32">;
293 // VST4 : Vector Store (multiple 4-element structures)
294 class VST4D<string OpcodeStr>
295 : NLdSt<(outs), (ins addrmode6:$addr,
296 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), NoItinerary,
297 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"),
300 def VST4d8 : VST4D<"vst4.8">;
301 def VST4d16 : VST4D<"vst4.16">;
302 def VST4d32 : VST4D<"vst4.32">;
304 // VST2LN : Vector Store (single 2-element structure from one lane)
305 class VST2LND<string OpcodeStr>
306 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, nohash_imm:$lane),
308 !strconcat(OpcodeStr, "\t\\{$src1[$lane],$src2[$lane]\\}, $addr"),
311 def VST2LNd8 : VST2LND<"vst2.8">;
312 def VST2LNd16 : VST2LND<"vst2.16">;
313 def VST2LNd32 : VST2LND<"vst2.32">;
315 // VST3LN : Vector Store (single 3-element structure from one lane)
316 class VST3LND<string OpcodeStr>
317 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
318 nohash_imm:$lane), NoItinerary,
319 !strconcat(OpcodeStr,
320 "\t\\{$src1[$lane],$src2[$lane],$src3[$lane]\\}, $addr"), "", []>;
322 def VST3LNd8 : VST3LND<"vst3.8">;
323 def VST3LNd16 : VST3LND<"vst3.16">;
324 def VST3LNd32 : VST3LND<"vst3.32">;
326 // VST4LN : Vector Store (single 4-element structure from one lane)
327 class VST4LND<string OpcodeStr>
328 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
329 DPR:$src4, nohash_imm:$lane), NoItinerary,
330 !strconcat(OpcodeStr,
331 "\t\\{$src1[$lane],$src2[$lane],$src3[$lane],$src4[$lane]\\}, $addr"),
334 def VST4LNd8 : VST4LND<"vst4.8">;
335 def VST4LNd16 : VST4LND<"vst4.16">;
336 def VST4LNd32 : VST4LND<"vst4.32">;
340 //===----------------------------------------------------------------------===//
341 // NEON pattern fragments
342 //===----------------------------------------------------------------------===//
344 // Extract D sub-registers of Q registers.
345 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
346 def DSubReg_i8_reg : SDNodeXForm<imm, [{
347 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
349 def DSubReg_i16_reg : SDNodeXForm<imm, [{
350 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
352 def DSubReg_i32_reg : SDNodeXForm<imm, [{
353 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
355 def DSubReg_f64_reg : SDNodeXForm<imm, [{
356 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
358 def DSubReg_f64_other_reg : SDNodeXForm<imm, [{
359 return CurDAG->getTargetConstant(5 + (1 - N->getZExtValue()), MVT::i32);
362 // Extract S sub-registers of Q/D registers.
363 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
364 def SSubReg_f32_reg : SDNodeXForm<imm, [{
365 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
368 // Translate lane numbers from Q registers to D subregs.
369 def SubReg_i8_lane : SDNodeXForm<imm, [{
370 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
372 def SubReg_i16_lane : SDNodeXForm<imm, [{
373 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
375 def SubReg_i32_lane : SDNodeXForm<imm, [{
376 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
379 //===----------------------------------------------------------------------===//
380 // Instruction Classes
381 //===----------------------------------------------------------------------===//
383 // Basic 2-register operations, both double- and quad-register.
384 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
385 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
386 ValueType ResTy, ValueType OpTy, SDNode OpNode>
387 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
388 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
389 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
390 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
391 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
392 ValueType ResTy, ValueType OpTy, SDNode OpNode>
393 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
394 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
395 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
397 // Basic 2-register operations, scalar single-precision.
398 class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
399 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
400 ValueType ResTy, ValueType OpTy, SDNode OpNode>
401 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
402 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
403 NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
405 class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
406 : NEONFPPat<(ResTy (OpNode SPR:$a)),
408 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
411 // Basic 2-register intrinsics, both double- and quad-register.
412 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
413 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
414 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
415 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
416 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
417 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
418 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
419 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
420 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
421 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
422 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
423 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
425 // Basic 2-register intrinsics, scalar single-precision
426 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
427 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
428 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
429 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
430 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
431 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
433 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
434 : NEONFPPat<(f32 (OpNode SPR:$a)),
436 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
439 // Narrow 2-register intrinsics.
440 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
441 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
442 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
443 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
444 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
445 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
447 // Long 2-register intrinsics. (This is currently only used for VMOVL and is
448 // derived from N2VImm instead of N2V because of the way the size is encoded.)
449 class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
450 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
452 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
453 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
454 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
456 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
457 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
458 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
459 (ins DPR:$src1, DPR:$src2), NoItinerary,
460 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
461 "$src1 = $dst1, $src2 = $dst2", []>;
462 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
463 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
464 (ins QPR:$src1, QPR:$src2), NoItinerary,
465 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
466 "$src1 = $dst1, $src2 = $dst2", []>;
468 // Basic 3-register operations, both double- and quad-register.
469 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
470 string OpcodeStr, ValueType ResTy, ValueType OpTy,
471 SDNode OpNode, bit Commutable>
472 : N3V<op24, op23, op21_20, op11_8, 0, op4,
473 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
474 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
475 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
476 let isCommutable = Commutable;
478 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
479 string OpcodeStr, ValueType ResTy, ValueType OpTy,
480 SDNode OpNode, bit Commutable>
481 : N3V<op24, op23, op21_20, op11_8, 1, op4,
482 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
483 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
484 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
485 let isCommutable = Commutable;
488 // Basic 3-register operations, scalar single-precision
489 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
490 string OpcodeStr, ValueType ResTy, ValueType OpTy,
491 SDNode OpNode, bit Commutable>
492 : N3V<op24, op23, op21_20, op11_8, 0, op4,
493 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), NoItinerary,
494 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
495 let isCommutable = Commutable;
497 class N3VDsPat<SDNode OpNode, NeonI Inst>
498 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
500 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
501 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
504 // Basic 3-register intrinsics, both double- and quad-register.
505 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
506 string OpcodeStr, ValueType ResTy, ValueType OpTy,
507 Intrinsic IntOp, bit Commutable>
508 : N3V<op24, op23, op21_20, op11_8, 0, op4,
509 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
510 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
511 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
512 let isCommutable = Commutable;
514 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
515 string OpcodeStr, ValueType ResTy, ValueType OpTy,
516 Intrinsic IntOp, bit Commutable>
517 : N3V<op24, op23, op21_20, op11_8, 1, op4,
518 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
519 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
520 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
521 let isCommutable = Commutable;
524 // Multiply-Add/Sub operations, both double- and quad-register.
525 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
526 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
527 : N3V<op24, op23, op21_20, op11_8, 0, op4,
528 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
529 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
530 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
531 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
532 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
533 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
534 : N3V<op24, op23, op21_20, op11_8, 1, op4,
535 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
536 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
537 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
538 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
540 // Multiply-Add/Sub operations, scalar single-precision
541 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
542 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
543 : N3V<op24, op23, op21_20, op11_8, 0, op4,
544 (outs DPR_VFP2:$dst),
545 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), NoItinerary,
546 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
548 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
549 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
551 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
552 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
553 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
556 // Neon 3-argument intrinsics, both double- and quad-register.
557 // The destination register is also used as the first source operand register.
558 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
559 string OpcodeStr, ValueType ResTy, ValueType OpTy,
561 : N3V<op24, op23, op21_20, op11_8, 0, op4,
562 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
563 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
564 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
565 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
566 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
567 string OpcodeStr, ValueType ResTy, ValueType OpTy,
569 : N3V<op24, op23, op21_20, op11_8, 1, op4,
570 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
571 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
572 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
573 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
575 // Neon Long 3-argument intrinsic. The destination register is
576 // a quad-register and is also used as the first source operand register.
577 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
578 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
579 : N3V<op24, op23, op21_20, op11_8, 0, op4,
580 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
581 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
583 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
585 // Narrowing 3-register intrinsics.
586 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
587 string OpcodeStr, ValueType TyD, ValueType TyQ,
588 Intrinsic IntOp, bit Commutable>
589 : N3V<op24, op23, op21_20, op11_8, 0, op4,
590 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
591 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
592 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
593 let isCommutable = Commutable;
596 // Long 3-register intrinsics.
597 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
598 string OpcodeStr, ValueType TyQ, ValueType TyD,
599 Intrinsic IntOp, bit Commutable>
600 : N3V<op24, op23, op21_20, op11_8, 0, op4,
601 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
602 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
603 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
604 let isCommutable = Commutable;
607 // Wide 3-register intrinsics.
608 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
609 string OpcodeStr, ValueType TyQ, ValueType TyD,
610 Intrinsic IntOp, bit Commutable>
611 : N3V<op24, op23, op21_20, op11_8, 0, op4,
612 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), NoItinerary,
613 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
614 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
615 let isCommutable = Commutable;
618 // Pairwise long 2-register intrinsics, both double- and quad-register.
619 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
620 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
621 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
622 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
623 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
624 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
625 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
626 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
627 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
628 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
629 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
630 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
632 // Pairwise long 2-register accumulate intrinsics,
633 // both double- and quad-register.
634 // The destination register is also used as the first source operand register.
635 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
636 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
637 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
638 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
639 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
640 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
641 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
642 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
643 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
644 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
645 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
646 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
647 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
648 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
650 // Shift by immediate,
651 // both double- and quad-register.
652 class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
653 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
654 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
655 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
656 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
657 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
658 class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
659 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
660 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
661 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
662 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
663 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
665 // Long shift by immediate.
666 class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
667 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
668 ValueType OpTy, SDNode OpNode>
669 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
670 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
671 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
672 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
673 (i32 imm:$SIMM))))]>;
675 // Narrow shift by immediate.
676 class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
677 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
678 ValueType OpTy, SDNode OpNode>
679 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
680 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
681 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
682 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
683 (i32 imm:$SIMM))))]>;
685 // Shift right by immediate and accumulate,
686 // both double- and quad-register.
687 class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
688 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
689 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
690 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
692 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
693 [(set DPR:$dst, (Ty (add DPR:$src1,
694 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
695 class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
696 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
697 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
698 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
700 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
701 [(set QPR:$dst, (Ty (add QPR:$src1,
702 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
704 // Shift by immediate and insert,
705 // both double- and quad-register.
706 class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
707 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
708 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
709 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
711 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
712 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
713 class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
714 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
715 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
716 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
718 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
719 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
721 // Convert, with fractional bits immediate,
722 // both double- and quad-register.
723 class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
724 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
726 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
727 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
728 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
729 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
730 class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
731 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
733 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
734 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
735 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
736 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
738 //===----------------------------------------------------------------------===//
740 //===----------------------------------------------------------------------===//
742 // Neon 3-register vector operations.
744 // First with only element sizes of 8, 16 and 32 bits:
745 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
746 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
747 // 64-bit vector types.
748 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
749 v8i8, v8i8, OpNode, Commutable>;
750 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
751 v4i16, v4i16, OpNode, Commutable>;
752 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
753 v2i32, v2i32, OpNode, Commutable>;
755 // 128-bit vector types.
756 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
757 v16i8, v16i8, OpNode, Commutable>;
758 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
759 v8i16, v8i16, OpNode, Commutable>;
760 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
761 v4i32, v4i32, OpNode, Commutable>;
764 // ....then also with element size 64 bits:
765 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
766 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
767 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
768 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
769 v1i64, v1i64, OpNode, Commutable>;
770 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
771 v2i64, v2i64, OpNode, Commutable>;
775 // Neon Narrowing 2-register vector intrinsics,
776 // source operand element sizes of 16, 32 and 64 bits:
777 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
778 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
780 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
781 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
782 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
783 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
784 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
785 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
789 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
790 // source operand element sizes of 16, 32 and 64 bits:
791 multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
792 bit op4, string OpcodeStr, Intrinsic IntOp> {
793 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
794 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
795 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
796 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
797 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
798 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
802 // Neon 3-register vector intrinsics.
804 // First with only element sizes of 16 and 32 bits:
805 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
806 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
807 // 64-bit vector types.
808 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
809 v4i16, v4i16, IntOp, Commutable>;
810 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
811 v2i32, v2i32, IntOp, Commutable>;
813 // 128-bit vector types.
814 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
815 v8i16, v8i16, IntOp, Commutable>;
816 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
817 v4i32, v4i32, IntOp, Commutable>;
820 // ....then also with element size of 8 bits:
821 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
822 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
823 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
824 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
825 v8i8, v8i8, IntOp, Commutable>;
826 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
827 v16i8, v16i8, IntOp, Commutable>;
830 // ....then also with element size of 64 bits:
831 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
832 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
833 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
834 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
835 v1i64, v1i64, IntOp, Commutable>;
836 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
837 v2i64, v2i64, IntOp, Commutable>;
841 // Neon Narrowing 3-register vector intrinsics,
842 // source operand element sizes of 16, 32 and 64 bits:
843 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
844 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
845 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
846 v8i8, v8i16, IntOp, Commutable>;
847 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
848 v4i16, v4i32, IntOp, Commutable>;
849 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
850 v2i32, v2i64, IntOp, Commutable>;
854 // Neon Long 3-register vector intrinsics.
856 // First with only element sizes of 16 and 32 bits:
857 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
858 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
859 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
860 v4i32, v4i16, IntOp, Commutable>;
861 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
862 v2i64, v2i32, IntOp, Commutable>;
865 // ....then also with element size of 8 bits:
866 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
867 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
868 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
869 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
870 v8i16, v8i8, IntOp, Commutable>;
874 // Neon Wide 3-register vector intrinsics,
875 // source operand element sizes of 8, 16 and 32 bits:
876 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
877 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
878 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
879 v8i16, v8i8, IntOp, Commutable>;
880 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
881 v4i32, v4i16, IntOp, Commutable>;
882 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
883 v2i64, v2i32, IntOp, Commutable>;
887 // Neon Multiply-Op vector operations,
888 // element sizes of 8, 16 and 32 bits:
889 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
890 string OpcodeStr, SDNode OpNode> {
891 // 64-bit vector types.
892 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
893 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
894 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
895 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
896 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
897 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
899 // 128-bit vector types.
900 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
901 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
902 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
903 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
904 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
905 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
909 // Neon 3-argument intrinsics,
910 // element sizes of 8, 16 and 32 bits:
911 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
912 string OpcodeStr, Intrinsic IntOp> {
913 // 64-bit vector types.
914 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
915 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
916 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
917 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
918 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
919 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
921 // 128-bit vector types.
922 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
923 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
924 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
925 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
926 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
927 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
931 // Neon Long 3-argument intrinsics.
933 // First with only element sizes of 16 and 32 bits:
934 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
935 string OpcodeStr, Intrinsic IntOp> {
936 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
937 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
938 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
939 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
942 // ....then also with element size of 8 bits:
943 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
944 string OpcodeStr, Intrinsic IntOp>
945 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
946 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
947 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
951 // Neon 2-register vector intrinsics,
952 // element sizes of 8, 16 and 32 bits:
953 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
954 bits<5> op11_7, bit op4, string OpcodeStr,
956 // 64-bit vector types.
957 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
958 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
959 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
960 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
961 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
962 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
964 // 128-bit vector types.
965 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
966 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
967 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
968 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
969 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
970 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
974 // Neon Pairwise long 2-register intrinsics,
975 // element sizes of 8, 16 and 32 bits:
976 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
977 bits<5> op11_7, bit op4,
978 string OpcodeStr, Intrinsic IntOp> {
979 // 64-bit vector types.
980 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
981 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
982 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
983 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
984 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
985 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
987 // 128-bit vector types.
988 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
989 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
990 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
991 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
992 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
993 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
997 // Neon Pairwise long 2-register accumulate intrinsics,
998 // element sizes of 8, 16 and 32 bits:
999 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
1000 bits<5> op11_7, bit op4,
1001 string OpcodeStr, Intrinsic IntOp> {
1002 // 64-bit vector types.
1003 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1004 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
1005 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1006 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
1007 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1008 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
1010 // 128-bit vector types.
1011 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
1012 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
1013 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
1014 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
1015 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
1016 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
1020 // Neon 2-register vector shift by immediate,
1021 // element sizes of 8, 16, 32 and 64 bits:
1022 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1023 string OpcodeStr, SDNode OpNode> {
1024 // 64-bit vector types.
1025 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
1026 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
1027 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
1028 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
1029 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
1030 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
1031 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
1032 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
1034 // 128-bit vector types.
1035 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
1036 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
1037 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
1038 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
1039 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
1040 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
1041 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
1042 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
1046 // Neon Shift-Accumulate vector operations,
1047 // element sizes of 8, 16, 32 and 64 bits:
1048 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1049 string OpcodeStr, SDNode ShOp> {
1050 // 64-bit vector types.
1051 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
1052 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1053 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
1054 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1055 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
1056 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1057 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1058 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1060 // 128-bit vector types.
1061 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
1062 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1063 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
1064 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1065 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
1066 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1067 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1068 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1072 // Neon Shift-Insert vector operations,
1073 // element sizes of 8, 16, 32 and 64 bits:
1074 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1075 string OpcodeStr, SDNode ShOp> {
1076 // 64-bit vector types.
1077 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
1078 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1079 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
1080 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1081 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
1082 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1083 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
1084 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1086 // 128-bit vector types.
1087 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
1088 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1089 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
1090 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1091 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
1092 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1093 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
1094 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1097 //===----------------------------------------------------------------------===//
1098 // Instruction Definitions.
1099 //===----------------------------------------------------------------------===//
1101 // Vector Add Operations.
1103 // VADD : Vector Add (integer and floating-point)
1104 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
1105 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
1106 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
1107 // VADDL : Vector Add Long (Q = D + D)
1108 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
1109 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
1110 // VADDW : Vector Add Wide (Q = Q + D)
1111 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
1112 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1113 // VHADD : Vector Halving Add
1114 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
1115 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
1116 // VRHADD : Vector Rounding Halving Add
1117 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1118 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1119 // VQADD : Vector Saturating Add
1120 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
1121 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
1122 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1123 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1124 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1125 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1127 // Vector Multiply Operations.
1129 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1130 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
1131 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
1132 int_arm_neon_vmulp, 1>;
1133 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
1134 int_arm_neon_vmulp, 1>;
1135 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
1136 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
1137 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1138 defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1139 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1140 defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1141 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1142 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
1143 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
1144 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
1145 int_arm_neon_vmullp, 1>;
1146 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1147 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
1149 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1151 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1152 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
1153 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
1154 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
1155 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1156 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1157 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1158 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1159 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1160 // VMLS : Vector Multiply Subtract (integer and floating-point)
1161 defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
1162 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
1163 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
1164 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1165 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1166 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1167 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1168 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1170 // Vector Subtract Operations.
1172 // VSUB : Vector Subtract (integer and floating-point)
1173 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
1174 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
1175 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
1176 // VSUBL : Vector Subtract Long (Q = D - D)
1177 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
1178 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
1179 // VSUBW : Vector Subtract Wide (Q = Q - D)
1180 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1181 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1182 // VHSUB : Vector Halving Subtract
1183 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
1184 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
1185 // VQSUB : Vector Saturing Subtract
1186 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
1187 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
1188 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1189 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1190 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1191 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1193 // Vector Comparisons.
1195 // VCEQ : Vector Compare Equal
1196 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
1197 def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1198 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1199 // VCGE : Vector Compare Greater Than or Equal
1200 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
1201 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
1202 def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1203 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1204 // VCGT : Vector Compare Greater Than
1205 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
1206 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
1207 def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1208 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1209 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1210 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
1211 int_arm_neon_vacged, 0>;
1212 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
1213 int_arm_neon_vacgeq, 0>;
1214 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1215 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
1216 int_arm_neon_vacgtd, 0>;
1217 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
1218 int_arm_neon_vacgtq, 0>;
1219 // VTST : Vector Test Bits
1220 defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
1222 // Vector Bitwise Operations.
1224 // VAND : Vector Bitwise AND
1225 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
1226 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
1228 // VEOR : Vector Bitwise Exclusive OR
1229 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
1230 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
1232 // VORR : Vector Bitwise OR
1233 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
1234 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
1236 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1237 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1238 (ins DPR:$src1, DPR:$src2), NoItinerary,
1239 "vbic\t$dst, $src1, $src2", "",
1240 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
1241 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1242 (ins QPR:$src1, QPR:$src2), NoItinerary,
1243 "vbic\t$dst, $src1, $src2", "",
1244 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
1246 // VORN : Vector Bitwise OR NOT
1247 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1248 (ins DPR:$src1, DPR:$src2), NoItinerary,
1249 "vorn\t$dst, $src1, $src2", "",
1250 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1251 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1252 (ins QPR:$src1, QPR:$src2), NoItinerary,
1253 "vorn\t$dst, $src1, $src2", "",
1254 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1256 // VMVN : Vector Bitwise NOT
1257 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1258 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1259 "vmvn\t$dst, $src", "",
1260 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1261 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1262 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1263 "vmvn\t$dst, $src", "",
1264 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1265 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1266 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1268 // VBSL : Vector Bitwise Select
1269 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1270 (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
1271 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1273 (v2i32 (or (and DPR:$src2, DPR:$src1),
1274 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1275 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1276 (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
1277 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1279 (v4i32 (or (and QPR:$src2, QPR:$src1),
1280 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1282 // VBIF : Vector Bitwise Insert if False
1283 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1284 // VBIT : Vector Bitwise Insert if True
1285 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1286 // These are not yet implemented. The TwoAddress pass will not go looking
1287 // for equivalent operations with different register constraints; it just
1290 // Vector Absolute Differences.
1292 // VABD : Vector Absolute Difference
1293 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1294 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1295 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1296 int_arm_neon_vabds, 0>;
1297 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1298 int_arm_neon_vabds, 0>;
1300 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1301 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1302 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1304 // VABA : Vector Absolute Difference and Accumulate
1305 defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1306 defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1308 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1309 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1310 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1312 // Vector Maximum and Minimum.
1314 // VMAX : Vector Maximum
1315 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1316 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1317 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1318 int_arm_neon_vmaxs, 1>;
1319 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1320 int_arm_neon_vmaxs, 1>;
1322 // VMIN : Vector Minimum
1323 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1324 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1325 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1326 int_arm_neon_vmins, 1>;
1327 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1328 int_arm_neon_vmins, 1>;
1330 // Vector Pairwise Operations.
1332 // VPADD : Vector Pairwise Add
1333 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1334 int_arm_neon_vpadd, 0>;
1335 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1336 int_arm_neon_vpadd, 0>;
1337 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1338 int_arm_neon_vpadd, 0>;
1339 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1340 int_arm_neon_vpadd, 0>;
1342 // VPADDL : Vector Pairwise Add Long
1343 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1344 int_arm_neon_vpaddls>;
1345 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1346 int_arm_neon_vpaddlu>;
1348 // VPADAL : Vector Pairwise Add and Accumulate Long
1349 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1350 int_arm_neon_vpadals>;
1351 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1352 int_arm_neon_vpadalu>;
1354 // VPMAX : Vector Pairwise Maximum
1355 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1356 int_arm_neon_vpmaxs, 0>;
1357 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1358 int_arm_neon_vpmaxs, 0>;
1359 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1360 int_arm_neon_vpmaxs, 0>;
1361 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1362 int_arm_neon_vpmaxu, 0>;
1363 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1364 int_arm_neon_vpmaxu, 0>;
1365 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1366 int_arm_neon_vpmaxu, 0>;
1367 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1368 int_arm_neon_vpmaxs, 0>;
1370 // VPMIN : Vector Pairwise Minimum
1371 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1372 int_arm_neon_vpmins, 0>;
1373 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1374 int_arm_neon_vpmins, 0>;
1375 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1376 int_arm_neon_vpmins, 0>;
1377 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1378 int_arm_neon_vpminu, 0>;
1379 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1380 int_arm_neon_vpminu, 0>;
1381 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1382 int_arm_neon_vpminu, 0>;
1383 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1384 int_arm_neon_vpmins, 0>;
1386 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1388 // VRECPE : Vector Reciprocal Estimate
1389 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1390 v2i32, v2i32, int_arm_neon_vrecpe>;
1391 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1392 v4i32, v4i32, int_arm_neon_vrecpe>;
1393 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1394 v2f32, v2f32, int_arm_neon_vrecpe>;
1395 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1396 v4f32, v4f32, int_arm_neon_vrecpe>;
1398 // VRECPS : Vector Reciprocal Step
1399 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1400 int_arm_neon_vrecps, 1>;
1401 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1402 int_arm_neon_vrecps, 1>;
1404 // VRSQRTE : Vector Reciprocal Square Root Estimate
1405 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1406 v2i32, v2i32, int_arm_neon_vrsqrte>;
1407 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1408 v4i32, v4i32, int_arm_neon_vrsqrte>;
1409 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1410 v2f32, v2f32, int_arm_neon_vrsqrte>;
1411 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1412 v4f32, v4f32, int_arm_neon_vrsqrte>;
1414 // VRSQRTS : Vector Reciprocal Square Root Step
1415 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1416 int_arm_neon_vrsqrts, 1>;
1417 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1418 int_arm_neon_vrsqrts, 1>;
1422 // VSHL : Vector Shift
1423 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1424 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1425 // VSHL : Vector Shift Left (Immediate)
1426 defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1427 // VSHR : Vector Shift Right (Immediate)
1428 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1429 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1431 // VSHLL : Vector Shift Left Long
1432 def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1433 v8i16, v8i8, NEONvshlls>;
1434 def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1435 v4i32, v4i16, NEONvshlls>;
1436 def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1437 v2i64, v2i32, NEONvshlls>;
1438 def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1439 v8i16, v8i8, NEONvshllu>;
1440 def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1441 v4i32, v4i16, NEONvshllu>;
1442 def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1443 v2i64, v2i32, NEONvshllu>;
1445 // VSHLL : Vector Shift Left Long (with maximum shift count)
1446 def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1447 v8i16, v8i8, NEONvshlli>;
1448 def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1449 v4i32, v4i16, NEONvshlli>;
1450 def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1451 v2i64, v2i32, NEONvshlli>;
1453 // VSHRN : Vector Shift Right and Narrow
1454 def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1455 v8i8, v8i16, NEONvshrn>;
1456 def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1457 v4i16, v4i32, NEONvshrn>;
1458 def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1459 v2i32, v2i64, NEONvshrn>;
1461 // VRSHL : Vector Rounding Shift
1462 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1463 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1464 // VRSHR : Vector Rounding Shift Right
1465 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1466 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1468 // VRSHRN : Vector Rounding Shift Right and Narrow
1469 def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1470 v8i8, v8i16, NEONvrshrn>;
1471 def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1472 v4i16, v4i32, NEONvrshrn>;
1473 def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1474 v2i32, v2i64, NEONvrshrn>;
1476 // VQSHL : Vector Saturating Shift
1477 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1478 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1479 // VQSHL : Vector Saturating Shift Left (Immediate)
1480 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1481 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1482 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1483 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1485 // VQSHRN : Vector Saturating Shift Right and Narrow
1486 def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1487 v8i8, v8i16, NEONvqshrns>;
1488 def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1489 v4i16, v4i32, NEONvqshrns>;
1490 def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1491 v2i32, v2i64, NEONvqshrns>;
1492 def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1493 v8i8, v8i16, NEONvqshrnu>;
1494 def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1495 v4i16, v4i32, NEONvqshrnu>;
1496 def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1497 v2i32, v2i64, NEONvqshrnu>;
1499 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1500 def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1501 v8i8, v8i16, NEONvqshrnsu>;
1502 def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1503 v4i16, v4i32, NEONvqshrnsu>;
1504 def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1505 v2i32, v2i64, NEONvqshrnsu>;
1507 // VQRSHL : Vector Saturating Rounding Shift
1508 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1509 int_arm_neon_vqrshifts, 0>;
1510 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1511 int_arm_neon_vqrshiftu, 0>;
1513 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1514 def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1515 v8i8, v8i16, NEONvqrshrns>;
1516 def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1517 v4i16, v4i32, NEONvqrshrns>;
1518 def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1519 v2i32, v2i64, NEONvqrshrns>;
1520 def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1521 v8i8, v8i16, NEONvqrshrnu>;
1522 def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1523 v4i16, v4i32, NEONvqrshrnu>;
1524 def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1525 v2i32, v2i64, NEONvqrshrnu>;
1527 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1528 def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1529 v8i8, v8i16, NEONvqrshrnsu>;
1530 def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1531 v4i16, v4i32, NEONvqrshrnsu>;
1532 def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1533 v2i32, v2i64, NEONvqrshrnsu>;
1535 // VSRA : Vector Shift Right and Accumulate
1536 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1537 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1538 // VRSRA : Vector Rounding Shift Right and Accumulate
1539 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1540 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1542 // VSLI : Vector Shift Left and Insert
1543 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1544 // VSRI : Vector Shift Right and Insert
1545 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1547 // Vector Absolute and Saturating Absolute.
1549 // VABS : Vector Absolute Value
1550 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1552 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1553 v2f32, v2f32, int_arm_neon_vabs>;
1554 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1555 v4f32, v4f32, int_arm_neon_vabs>;
1557 // VQABS : Vector Saturating Absolute Value
1558 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1559 int_arm_neon_vqabs>;
1563 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1564 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1566 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1567 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1569 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1570 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1571 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1572 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1574 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1575 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1577 // VNEG : Vector Negate
1578 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1579 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1580 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1581 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1582 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1583 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1585 // VNEG : Vector Negate (floating-point)
1586 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1587 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1588 "vneg.f32\t$dst, $src", "",
1589 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1590 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1591 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1592 "vneg.f32\t$dst, $src", "",
1593 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1595 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1596 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1597 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1598 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1599 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1600 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1602 // VQNEG : Vector Saturating Negate
1603 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1604 int_arm_neon_vqneg>;
1606 // Vector Bit Counting Operations.
1608 // VCLS : Vector Count Leading Sign Bits
1609 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1611 // VCLZ : Vector Count Leading Zeros
1612 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1614 // VCNT : Vector Count One Bits
1615 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1616 v8i8, v8i8, int_arm_neon_vcnt>;
1617 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1618 v16i8, v16i8, int_arm_neon_vcnt>;
1620 // Vector Move Operations.
1622 // VMOV : Vector Move (Register)
1624 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1625 NoItinerary, "vmov\t$dst, $src", "", []>;
1626 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1627 NoItinerary, "vmov\t$dst, $src", "", []>;
1629 // VMOV : Vector Move (Immediate)
1631 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1632 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1633 return ARM::getVMOVImm(N, 1, *CurDAG);
1635 def vmovImm8 : PatLeaf<(build_vector), [{
1636 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1639 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1640 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1641 return ARM::getVMOVImm(N, 2, *CurDAG);
1643 def vmovImm16 : PatLeaf<(build_vector), [{
1644 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1645 }], VMOV_get_imm16>;
1647 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1648 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1649 return ARM::getVMOVImm(N, 4, *CurDAG);
1651 def vmovImm32 : PatLeaf<(build_vector), [{
1652 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1653 }], VMOV_get_imm32>;
1655 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1656 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1657 return ARM::getVMOVImm(N, 8, *CurDAG);
1659 def vmovImm64 : PatLeaf<(build_vector), [{
1660 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1661 }], VMOV_get_imm64>;
1663 // Note: Some of the cmode bits in the following VMOV instructions need to
1664 // be encoded based on the immed values.
1666 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1667 (ins i8imm:$SIMM), NoItinerary,
1668 "vmov.i8\t$dst, $SIMM", "",
1669 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1670 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1671 (ins i8imm:$SIMM), NoItinerary,
1672 "vmov.i8\t$dst, $SIMM", "",
1673 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1675 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1676 (ins i16imm:$SIMM), NoItinerary,
1677 "vmov.i16\t$dst, $SIMM", "",
1678 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1679 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1680 (ins i16imm:$SIMM), NoItinerary,
1681 "vmov.i16\t$dst, $SIMM", "",
1682 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1684 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1685 (ins i32imm:$SIMM), NoItinerary,
1686 "vmov.i32\t$dst, $SIMM", "",
1687 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1688 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1689 (ins i32imm:$SIMM), NoItinerary,
1690 "vmov.i32\t$dst, $SIMM", "",
1691 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1693 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1694 (ins i64imm:$SIMM), NoItinerary,
1695 "vmov.i64\t$dst, $SIMM", "",
1696 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1697 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1698 (ins i64imm:$SIMM), NoItinerary,
1699 "vmov.i64\t$dst, $SIMM", "",
1700 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1702 // VMOV : Vector Get Lane (move scalar to ARM core register)
1704 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1705 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
1706 NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
1707 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1709 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1710 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
1711 NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
1712 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1714 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1715 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
1716 NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
1717 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1719 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1720 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
1721 NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
1722 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1724 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1725 (outs GPR:$dst), (ins DPR:$src, nohash_imm:$lane),
1726 NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
1727 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1729 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1730 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1731 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1732 (DSubReg_i8_reg imm:$lane))),
1733 (SubReg_i8_lane imm:$lane))>;
1734 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1735 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1736 (DSubReg_i16_reg imm:$lane))),
1737 (SubReg_i16_lane imm:$lane))>;
1738 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1739 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1740 (DSubReg_i8_reg imm:$lane))),
1741 (SubReg_i8_lane imm:$lane))>;
1742 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1743 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1744 (DSubReg_i16_reg imm:$lane))),
1745 (SubReg_i16_lane imm:$lane))>;
1746 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1747 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1748 (DSubReg_i32_reg imm:$lane))),
1749 (SubReg_i32_lane imm:$lane))>;
1750 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
1751 (EXTRACT_SUBREG DPR:$src1, (SSubReg_f32_reg imm:$src2))>;
1752 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
1753 (EXTRACT_SUBREG QPR:$src1, (SSubReg_f32_reg imm:$src2))>;
1754 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1755 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
1756 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1757 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
1760 // VMOV : Vector Set Lane (move ARM core register to scalar)
1762 let Constraints = "$src1 = $dst" in {
1763 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1764 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
1765 NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
1766 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1767 GPR:$src2, imm:$lane))]>;
1768 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1769 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
1770 NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
1771 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1772 GPR:$src2, imm:$lane))]>;
1773 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1774 (ins DPR:$src1, GPR:$src2, nohash_imm:$lane),
1775 NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
1776 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1777 GPR:$src2, imm:$lane))]>;
1779 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1780 (v16i8 (INSERT_SUBREG QPR:$src1,
1781 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1782 (DSubReg_i8_reg imm:$lane))),
1783 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1784 (DSubReg_i8_reg imm:$lane)))>;
1785 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1786 (v8i16 (INSERT_SUBREG QPR:$src1,
1787 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1788 (DSubReg_i16_reg imm:$lane))),
1789 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1790 (DSubReg_i16_reg imm:$lane)))>;
1791 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1792 (v4i32 (INSERT_SUBREG QPR:$src1,
1793 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1794 (DSubReg_i32_reg imm:$lane))),
1795 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1796 (DSubReg_i32_reg imm:$lane)))>;
1798 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
1799 (INSERT_SUBREG DPR:$src1, SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
1800 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
1801 (INSERT_SUBREG QPR:$src1, SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
1803 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1804 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
1805 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1806 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
1808 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
1809 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
1810 def : Pat<(v2f64 (scalar_to_vector DPR:$src)),
1811 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, arm_dsubreg_0)>;
1812 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
1813 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, arm_ssubreg_0)>;
1815 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
1816 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
1817 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
1818 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
1819 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
1820 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
1822 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
1823 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1824 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
1826 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
1827 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1828 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
1830 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
1831 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1832 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
1835 // VDUP : Vector Duplicate (from ARM core register to all elements)
1837 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1838 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1839 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1840 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
1841 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1842 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1843 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1844 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
1846 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1847 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1848 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1849 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1850 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1851 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1853 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1854 NoItinerary, "vdup", ".32\t$dst, $src",
1855 [(set DPR:$dst, (v2f32 (NEONvdup
1856 (f32 (bitconvert GPR:$src)))))]>;
1857 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1858 NoItinerary, "vdup", ".32\t$dst, $src",
1859 [(set QPR:$dst, (v4f32 (NEONvdup
1860 (f32 (bitconvert GPR:$src)))))]>;
1862 // VDUP : Vector Duplicate Lane (from scalar to all elements)
1864 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1865 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1866 (outs DPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary,
1867 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1868 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
1870 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1871 ValueType ResTy, ValueType OpTy>
1872 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1873 (outs QPR:$dst), (ins DPR:$src, nohash_imm:$lane), NoItinerary,
1874 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1875 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
1877 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1878 def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1879 def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1880 def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1881 def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1882 def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1883 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1884 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1886 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
1887 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
1888 (DSubReg_i8_reg imm:$lane))),
1889 (SubReg_i8_lane imm:$lane)))>;
1890 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
1891 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
1892 (DSubReg_i16_reg imm:$lane))),
1893 (SubReg_i16_lane imm:$lane)))>;
1894 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
1895 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
1896 (DSubReg_i32_reg imm:$lane))),
1897 (SubReg_i32_lane imm:$lane)))>;
1898 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
1899 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
1900 (DSubReg_i32_reg imm:$lane))),
1901 (SubReg_i32_lane imm:$lane)))>;
1903 def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
1904 (outs DPR:$dst), (ins SPR:$src),
1905 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1906 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
1908 def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
1909 (outs QPR:$dst), (ins SPR:$src),
1910 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1911 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
1913 def : Pat<(v2i64 (NEONvduplane (v2i64 QPR:$src), imm:$lane)),
1914 (INSERT_SUBREG QPR:$src,
1915 (i64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
1916 (DSubReg_f64_other_reg imm:$lane))>;
1917 def : Pat<(v2f64 (NEONvduplane (v2f64 QPR:$src), imm:$lane)),
1918 (INSERT_SUBREG QPR:$src,
1919 (f64 (EXTRACT_SUBREG QPR:$src, (DSubReg_f64_reg imm:$lane))),
1920 (DSubReg_f64_other_reg imm:$lane))>;
1922 // VMOVN : Vector Narrowing Move
1923 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1924 int_arm_neon_vmovn>;
1925 // VQMOVN : Vector Saturating Narrowing Move
1926 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1927 int_arm_neon_vqmovns>;
1928 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1929 int_arm_neon_vqmovnu>;
1930 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1931 int_arm_neon_vqmovnsu>;
1932 // VMOVL : Vector Lengthening Move
1933 defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1934 defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1936 // Vector Conversions.
1938 // VCVT : Vector Convert Between Floating-Point and Integers
1939 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1940 v2i32, v2f32, fp_to_sint>;
1941 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1942 v2i32, v2f32, fp_to_uint>;
1943 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1944 v2f32, v2i32, sint_to_fp>;
1945 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1946 v2f32, v2i32, uint_to_fp>;
1948 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1949 v4i32, v4f32, fp_to_sint>;
1950 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1951 v4i32, v4f32, fp_to_uint>;
1952 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1953 v4f32, v4i32, sint_to_fp>;
1954 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1955 v4f32, v4i32, uint_to_fp>;
1957 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1958 // Note: Some of the opcode bits in the following VCVT instructions need to
1959 // be encoded based on the immed values.
1960 def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1961 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1962 def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1963 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1964 def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1965 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1966 def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1967 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1969 def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1970 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1971 def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1972 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1973 def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1974 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1975 def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1976 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1980 // VREV64 : Vector Reverse elements within 64-bit doublewords
1982 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1983 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
1984 (ins DPR:$src), NoItinerary,
1985 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1986 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
1987 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1988 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
1989 (ins QPR:$src), NoItinerary,
1990 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1991 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
1993 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
1994 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
1995 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
1996 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
1998 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
1999 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
2000 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
2001 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
2003 // VREV32 : Vector Reverse elements within 32-bit words
2005 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2006 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
2007 (ins DPR:$src), NoItinerary,
2008 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2009 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
2010 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2011 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
2012 (ins QPR:$src), NoItinerary,
2013 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2014 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
2016 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
2017 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
2019 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
2020 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
2022 // VREV16 : Vector Reverse elements within 16-bit halfwords
2024 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2025 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
2026 (ins DPR:$src), NoItinerary,
2027 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2028 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
2029 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
2030 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
2031 (ins QPR:$src), NoItinerary,
2032 !strconcat(OpcodeStr, "\t$dst, $src"), "",
2033 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
2035 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
2036 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
2038 // Other Vector Shuffles.
2040 // VEXT : Vector Extract
2042 class VEXTd<string OpcodeStr, ValueType Ty>
2043 : N3V<0,1,0b11,0b0000,0,0, (outs DPR:$dst),
2044 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NoItinerary,
2045 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
2046 [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs),
2047 (Ty DPR:$rhs), imm:$index)))]>;
2049 class VEXTq<string OpcodeStr, ValueType Ty>
2050 : N3V<0,1,0b11,0b0000,1,0, (outs QPR:$dst),
2051 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NoItinerary,
2052 !strconcat(OpcodeStr, "\t$dst, $lhs, $rhs, $index"), "",
2053 [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs),
2054 (Ty QPR:$rhs), imm:$index)))]>;
2056 def VEXTd8 : VEXTd<"vext.8", v8i8>;
2057 def VEXTd16 : VEXTd<"vext.16", v4i16>;
2058 def VEXTd32 : VEXTd<"vext.32", v2i32>;
2059 def VEXTdf : VEXTd<"vext.32", v2f32>;
2061 def VEXTq8 : VEXTq<"vext.8", v16i8>;
2062 def VEXTq16 : VEXTq<"vext.16", v8i16>;
2063 def VEXTq32 : VEXTq<"vext.32", v4i32>;
2064 def VEXTqf : VEXTq<"vext.32", v4f32>;
2066 // VTRN : Vector Transpose
2068 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
2069 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">;
2070 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">;
2072 def VTRNq8 : N2VQShuffle<0b00, 0b00001, "vtrn.8">;
2073 def VTRNq16 : N2VQShuffle<0b01, 0b00001, "vtrn.16">;
2074 def VTRNq32 : N2VQShuffle<0b10, 0b00001, "vtrn.32">;
2076 // VUZP : Vector Unzip (Deinterleave)
2078 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">;
2079 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">;
2080 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">;
2082 def VUZPq8 : N2VQShuffle<0b00, 0b00010, "vuzp.8">;
2083 def VUZPq16 : N2VQShuffle<0b01, 0b00010, "vuzp.16">;
2084 def VUZPq32 : N2VQShuffle<0b10, 0b00010, "vuzp.32">;
2086 // VZIP : Vector Zip (Interleave)
2088 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">;
2089 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">;
2090 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">;
2092 def VZIPq8 : N2VQShuffle<0b00, 0b00011, "vzip.8">;
2093 def VZIPq16 : N2VQShuffle<0b01, 0b00011, "vzip.16">;
2094 def VZIPq32 : N2VQShuffle<0b10, 0b00011, "vzip.32">;
2096 // Vector Table Lookup and Table Extension.
2098 // VTBL : Vector Table Lookup
2100 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
2101 (ins DPR:$tbl1, DPR:$src), NoItinerary,
2102 "vtbl.8\t$dst, \\{$tbl1\\}, $src", "",
2103 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
2105 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
2106 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
2107 "vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "",
2108 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
2109 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2111 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
2112 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
2113 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "",
2114 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
2115 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2117 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
2118 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
2119 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
2120 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
2121 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2123 // VTBX : Vector Table Extension
2125 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
2126 (ins DPR:$orig, DPR:$tbl1, DPR:$src), NoItinerary,
2127 "vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
2128 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
2129 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
2131 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
2132 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
2133 "vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst",
2134 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
2135 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2137 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
2138 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
2139 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst",
2140 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
2141 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2143 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
2144 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
2145 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
2146 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
2147 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2149 //===----------------------------------------------------------------------===//
2150 // NEON instructions for single-precision FP math
2151 //===----------------------------------------------------------------------===//
2153 // These need separate instructions because they must use DPR_VFP2 register
2154 // class which have SPR sub-registers.
2156 // Vector Add Operations used for single-precision FP
2157 let neverHasSideEffects = 1 in
2158 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
2159 def : N3VDsPat<fadd, VADDfd_sfp>;
2161 // Vector Sub Operations used for single-precision FP
2162 let neverHasSideEffects = 1 in
2163 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
2164 def : N3VDsPat<fsub, VSUBfd_sfp>;
2166 // Vector Multiply Operations used for single-precision FP
2167 let neverHasSideEffects = 1 in
2168 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
2169 def : N3VDsPat<fmul, VMULfd_sfp>;
2171 // Vector Multiply-Accumulate/Subtract used for single-precision FP
2172 let neverHasSideEffects = 1 in
2173 def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32,fmul,fadd>;
2174 def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
2176 let neverHasSideEffects = 1 in
2177 def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32,fmul,fsub>;
2178 def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
2180 // Vector Absolute used for single-precision FP
2181 let neverHasSideEffects = 1 in
2182 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
2183 v2f32, v2f32, int_arm_neon_vabs>;
2184 def : N2VDIntsPat<fabs, VABSfd_sfp>;
2186 // Vector Negate used for single-precision FP
2187 let neverHasSideEffects = 1 in
2188 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2189 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
2190 "vneg.f32\t$dst, $src", "", []>;
2191 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
2193 // Vector Convert between single-precision FP and integer
2194 let neverHasSideEffects = 1 in
2195 def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2196 v2i32, v2f32, fp_to_sint>;
2197 def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
2199 let neverHasSideEffects = 1 in
2200 def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2201 v2i32, v2f32, fp_to_uint>;
2202 def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
2204 let neverHasSideEffects = 1 in
2205 def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2206 v2f32, v2i32, sint_to_fp>;
2207 def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
2209 let neverHasSideEffects = 1 in
2210 def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2211 v2f32, v2i32, uint_to_fp>;
2212 def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
2214 //===----------------------------------------------------------------------===//
2215 // Non-Instruction Patterns
2216 //===----------------------------------------------------------------------===//
2219 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
2220 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
2221 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
2222 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
2223 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
2224 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
2225 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
2226 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
2227 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
2228 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
2229 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
2230 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
2231 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
2232 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
2233 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
2234 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
2235 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
2236 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
2237 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
2238 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
2239 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
2240 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
2241 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
2242 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
2243 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
2244 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
2245 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
2246 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
2247 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
2248 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
2250 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
2251 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
2252 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
2253 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
2254 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
2255 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
2256 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
2257 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
2258 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
2259 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
2260 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
2261 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
2262 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
2263 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
2264 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
2265 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
2266 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
2267 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
2268 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
2269 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
2270 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
2271 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
2272 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
2273 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
2274 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
2275 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
2276 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
2277 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
2278 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
2279 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;