1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ",
69 SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>;
71 def SDTARMVLD2 : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
72 def SDTARMVLD3 : SDTypeProfile<3, 1, [SDTCisSameAs<0, 1>,
73 SDTCisSameAs<0, 2>, SDTCisPtrTy<3>]>;
74 def SDTARMVLD4 : SDTypeProfile<4, 1, [SDTCisSameAs<0, 1>,
76 SDTCisSameAs<0, 3>, SDTCisPtrTy<4>]>;
77 def NEONvld2d : SDNode<"ARMISD::VLD2D", SDTARMVLD2,
78 [SDNPHasChain, SDNPMayLoad]>;
79 def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD3,
80 [SDNPHasChain, SDNPMayLoad]>;
81 def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD4,
82 [SDNPHasChain, SDNPMayLoad]>;
84 def SDTARMVST2 : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>]>;
85 def SDTARMVST3 : SDTypeProfile<0, 4, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
87 def SDTARMVST4 : SDTypeProfile<0, 5, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
91 def NEONvst2d : SDNode<"ARMISD::VST2D", SDTARMVST2,
92 [SDNPHasChain, SDNPMayStore]>;
93 def NEONvst3d : SDNode<"ARMISD::VST3D", SDTARMVST3,
94 [SDNPHasChain, SDNPMayStore]>;
95 def NEONvst4d : SDNode<"ARMISD::VST4D", SDTARMVST4,
96 [SDNPHasChain, SDNPMayStore]>;
98 //===----------------------------------------------------------------------===//
99 // NEON operand definitions
100 //===----------------------------------------------------------------------===//
102 // addrmode_neonldstm := reg
104 /* TODO: Take advantage of vldm.
105 def addrmode_neonldstm : Operand<i32>,
106 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
107 let PrintMethod = "printAddrNeonLdStMOperand";
108 let MIOperandInfo = (ops GPR, i32imm);
112 //===----------------------------------------------------------------------===//
113 // NEON load / store instructions
114 //===----------------------------------------------------------------------===//
116 /* TODO: Take advantage of vldm.
118 def VLDMD : NI<(outs),
119 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
121 "vldm${addr:submode} ${addr:base}, $dst1",
123 let Inst{27-25} = 0b110;
125 let Inst{11-9} = 0b101;
128 def VLDMS : NI<(outs),
129 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
131 "vldm${addr:submode} ${addr:base}, $dst1",
133 let Inst{27-25} = 0b110;
135 let Inst{11-9} = 0b101;
140 // Use vldmia to load a Q register as a D register pair.
141 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
143 "vldmia $addr, ${dst:dregpair}",
144 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
145 let Inst{27-25} = 0b110;
146 let Inst{24} = 0; // P bit
147 let Inst{23} = 1; // U bit
149 let Inst{11-9} = 0b101;
152 // Use vstmia to store a Q register as a D register pair.
153 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
155 "vstmia $addr, ${src:dregpair}",
156 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
157 let Inst{27-25} = 0b110;
158 let Inst{24} = 0; // P bit
159 let Inst{23} = 1; // U bit
161 let Inst{11-9} = 0b101;
164 // VLD1 : Vector Load (multiple single elements)
165 class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
166 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
168 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"),
169 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
170 class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
171 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
173 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"),
174 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
176 def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1i>;
177 def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1i>;
178 def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1i>;
179 def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1f>;
180 def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1i>;
182 def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1i>;
183 def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1i>;
184 def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1i>;
185 def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1f>;
186 def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1i>;
188 // VLD2 : Vector Load (multiple 2-element structures)
189 class VLD2D<string OpcodeStr>
190 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr),
192 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), []>;
194 def VLD2d8 : VLD2D<"vld2.8">;
195 def VLD2d16 : VLD2D<"vld2.16">;
196 def VLD2d32 : VLD2D<"vld2.32">;
198 // VLD3 : Vector Load (multiple 3-element structures)
199 class VLD3D<string OpcodeStr>
200 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
202 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), []>;
204 def VLD3d8 : VLD3D<"vld3.8">;
205 def VLD3d16 : VLD3D<"vld3.16">;
206 def VLD3d32 : VLD3D<"vld3.32">;
208 // VLD4 : Vector Load (multiple 4-element structures)
209 class VLD4D<string OpcodeStr>
210 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
211 (ins addrmode6:$addr),
213 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), []>;
215 def VLD4d8 : VLD4D<"vld4.8">;
216 def VLD4d16 : VLD4D<"vld4.16">;
217 def VLD4d32 : VLD4D<"vld4.32">;
219 // VST1 : Vector Store (multiple single elements)
220 class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
221 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
223 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"),
224 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
225 class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
226 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
228 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
229 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
231 def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1i>;
232 def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1i>;
233 def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1i>;
234 def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1f>;
235 def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1i>;
237 def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1i>;
238 def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1i>;
239 def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1i>;
240 def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1f>;
241 def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1i>;
243 // VST2 : Vector Store (multiple 2-element structures)
244 class VST2D<string OpcodeStr>
245 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary,
246 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), []>;
248 def VST2d8 : VST2D<"vst2.8">;
249 def VST2d16 : VST2D<"vst2.16">;
250 def VST2d32 : VST2D<"vst2.32">;
252 // VST3 : Vector Store (multiple 3-element structures)
253 class VST3D<string OpcodeStr>
254 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
256 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), []>;
258 def VST3d8 : VST3D<"vst3.8">;
259 def VST3d16 : VST3D<"vst3.16">;
260 def VST3d32 : VST3D<"vst3.32">;
262 // VST4 : Vector Store (multiple 4-element structures)
263 class VST4D<string OpcodeStr>
264 : NLdSt<(outs), (ins addrmode6:$addr,
265 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), NoItinerary,
266 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), []>;
268 def VST4d8 : VST4D<"vst4.8">;
269 def VST4d16 : VST4D<"vst4.16">;
270 def VST4d32 : VST4D<"vst4.32">;
273 //===----------------------------------------------------------------------===//
274 // NEON pattern fragments
275 //===----------------------------------------------------------------------===//
277 // Extract D sub-registers of Q registers.
278 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
279 def SubReg_i8_reg : SDNodeXForm<imm, [{
280 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
282 def SubReg_i16_reg : SDNodeXForm<imm, [{
283 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
285 def SubReg_i32_reg : SDNodeXForm<imm, [{
286 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
288 def SubReg_f64_reg : SDNodeXForm<imm, [{
289 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
292 // Translate lane numbers from Q registers to D subregs.
293 def SubReg_i8_lane : SDNodeXForm<imm, [{
294 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
296 def SubReg_i16_lane : SDNodeXForm<imm, [{
297 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
299 def SubReg_i32_lane : SDNodeXForm<imm, [{
300 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
303 //===----------------------------------------------------------------------===//
304 // Instruction Classes
305 //===----------------------------------------------------------------------===//
307 // Basic 2-register operations, both double- and quad-register.
308 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
309 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
310 ValueType ResTy, ValueType OpTy, SDNode OpNode>
311 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
312 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
313 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
314 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
315 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
316 ValueType ResTy, ValueType OpTy, SDNode OpNode>
317 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
318 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
319 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
321 // Basic 2-register intrinsics, both double- and quad-register.
322 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
323 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
324 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
325 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
326 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
327 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
328 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
329 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
330 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
331 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
332 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
333 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
335 // Basic 2-register operations, scalar single-precision
336 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
337 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
338 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
339 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
340 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
341 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
343 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
344 : NEONFPPat<(f32 (OpNode SPR:$a)),
346 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
349 // Narrow 2-register intrinsics.
350 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
351 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
352 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
353 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
354 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
355 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
357 // Long 2-register intrinsics. (This is currently only used for VMOVL and is
358 // derived from N2VImm instead of N2V because of the way the size is encoded.)
359 class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
360 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
362 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
363 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
364 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
366 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
367 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
368 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
369 (ins DPR:$src1, DPR:$src2), NoItinerary,
370 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
371 "$src1 = $dst1, $src2 = $dst2", []>;
372 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
373 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
374 (ins QPR:$src1, QPR:$src2), NoItinerary,
375 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
376 "$src1 = $dst1, $src2 = $dst2", []>;
378 // Basic 3-register operations, both double- and quad-register.
379 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
380 string OpcodeStr, ValueType ResTy, ValueType OpTy,
381 SDNode OpNode, bit Commutable>
382 : N3V<op24, op23, op21_20, op11_8, 0, op4,
383 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
384 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
385 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
386 let isCommutable = Commutable;
388 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
389 string OpcodeStr, ValueType ResTy, ValueType OpTy,
390 SDNode OpNode, bit Commutable>
391 : N3V<op24, op23, op21_20, op11_8, 1, op4,
392 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
393 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
394 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
395 let isCommutable = Commutable;
398 // Basic 3-register operations, scalar single-precision
399 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
400 string OpcodeStr, ValueType ResTy, ValueType OpTy,
401 SDNode OpNode, bit Commutable>
402 : N3V<op24, op23, op21_20, op11_8, 0, op4,
403 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), NoItinerary,
404 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
405 let isCommutable = Commutable;
407 class N3VDsPat<SDNode OpNode, NeonI Inst>
408 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
410 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
411 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
414 // Basic 3-register intrinsics, both double- and quad-register.
415 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
416 string OpcodeStr, ValueType ResTy, ValueType OpTy,
417 Intrinsic IntOp, bit Commutable>
418 : N3V<op24, op23, op21_20, op11_8, 0, op4,
419 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
420 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
421 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
422 let isCommutable = Commutable;
424 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
425 string OpcodeStr, ValueType ResTy, ValueType OpTy,
426 Intrinsic IntOp, bit Commutable>
427 : N3V<op24, op23, op21_20, op11_8, 1, op4,
428 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
429 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
430 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
431 let isCommutable = Commutable;
434 // Multiply-Add/Sub operations, both double- and quad-register.
435 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
436 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
437 : N3V<op24, op23, op21_20, op11_8, 0, op4,
438 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
439 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
440 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
441 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
442 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
443 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
444 : N3V<op24, op23, op21_20, op11_8, 1, op4,
445 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
446 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
447 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
448 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
450 // Multiply-Add/Sub operations, scalar single-precision
451 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
452 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
453 : N3V<op24, op23, op21_20, op11_8, 0, op4,
454 (outs DPR_VFP2:$dst),
455 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), NoItinerary,
456 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
458 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
459 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
461 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
462 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
463 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
466 // Neon 3-argument intrinsics, both double- and quad-register.
467 // The destination register is also used as the first source operand register.
468 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
469 string OpcodeStr, ValueType ResTy, ValueType OpTy,
471 : N3V<op24, op23, op21_20, op11_8, 0, op4,
472 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
473 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
474 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
475 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
476 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
477 string OpcodeStr, ValueType ResTy, ValueType OpTy,
479 : N3V<op24, op23, op21_20, op11_8, 1, op4,
480 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
481 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
482 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
483 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
485 // Neon Long 3-argument intrinsic. The destination register is
486 // a quad-register and is also used as the first source operand register.
487 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
488 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
489 : N3V<op24, op23, op21_20, op11_8, 0, op4,
490 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
491 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
493 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
495 // Narrowing 3-register intrinsics.
496 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
497 string OpcodeStr, ValueType TyD, ValueType TyQ,
498 Intrinsic IntOp, bit Commutable>
499 : N3V<op24, op23, op21_20, op11_8, 0, op4,
500 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
501 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
502 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
503 let isCommutable = Commutable;
506 // Long 3-register intrinsics.
507 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
508 string OpcodeStr, ValueType TyQ, ValueType TyD,
509 Intrinsic IntOp, bit Commutable>
510 : N3V<op24, op23, op21_20, op11_8, 0, op4,
511 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
512 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
513 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
514 let isCommutable = Commutable;
517 // Wide 3-register intrinsics.
518 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
519 string OpcodeStr, ValueType TyQ, ValueType TyD,
520 Intrinsic IntOp, bit Commutable>
521 : N3V<op24, op23, op21_20, op11_8, 0, op4,
522 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), NoItinerary,
523 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
524 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
525 let isCommutable = Commutable;
528 // Pairwise long 2-register intrinsics, both double- and quad-register.
529 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
530 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
531 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
532 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
533 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
534 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
535 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
536 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
537 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
538 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
539 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
540 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
542 // Pairwise long 2-register accumulate intrinsics,
543 // both double- and quad-register.
544 // The destination register is also used as the first source operand register.
545 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
546 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
547 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
548 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
549 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
550 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
551 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
552 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
553 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
554 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
555 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
556 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
557 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
558 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
560 // Shift by immediate,
561 // both double- and quad-register.
562 class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
563 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
564 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
565 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
566 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
567 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
568 class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
569 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
570 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
571 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
572 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
573 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
575 // Long shift by immediate.
576 class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
577 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
578 ValueType OpTy, SDNode OpNode>
579 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
580 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
581 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
582 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
583 (i32 imm:$SIMM))))]>;
585 // Narrow shift by immediate.
586 class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
587 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
588 ValueType OpTy, SDNode OpNode>
589 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
590 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
591 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
592 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
593 (i32 imm:$SIMM))))]>;
595 // Shift right by immediate and accumulate,
596 // both double- and quad-register.
597 class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
598 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
599 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
600 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
602 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
603 [(set DPR:$dst, (Ty (add DPR:$src1,
604 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
605 class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
606 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
607 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
608 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
610 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
611 [(set QPR:$dst, (Ty (add QPR:$src1,
612 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
614 // Shift by immediate and insert,
615 // both double- and quad-register.
616 class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
617 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
618 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
619 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
621 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
622 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
623 class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
624 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
625 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
626 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
628 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
629 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
631 // Convert, with fractional bits immediate,
632 // both double- and quad-register.
633 class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
634 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
636 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
637 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
638 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
639 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
640 class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
641 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
643 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
644 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
645 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
646 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
648 //===----------------------------------------------------------------------===//
650 //===----------------------------------------------------------------------===//
652 // Neon 3-register vector operations.
654 // First with only element sizes of 8, 16 and 32 bits:
655 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
656 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
657 // 64-bit vector types.
658 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
659 v8i8, v8i8, OpNode, Commutable>;
660 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
661 v4i16, v4i16, OpNode, Commutable>;
662 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
663 v2i32, v2i32, OpNode, Commutable>;
665 // 128-bit vector types.
666 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
667 v16i8, v16i8, OpNode, Commutable>;
668 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
669 v8i16, v8i16, OpNode, Commutable>;
670 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
671 v4i32, v4i32, OpNode, Commutable>;
674 // ....then also with element size 64 bits:
675 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
676 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
677 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
678 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
679 v1i64, v1i64, OpNode, Commutable>;
680 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
681 v2i64, v2i64, OpNode, Commutable>;
685 // Neon Narrowing 2-register vector intrinsics,
686 // source operand element sizes of 16, 32 and 64 bits:
687 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
688 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
690 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
691 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
692 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
693 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
694 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
695 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
699 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
700 // source operand element sizes of 16, 32 and 64 bits:
701 multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
702 bit op4, string OpcodeStr, Intrinsic IntOp> {
703 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
704 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
705 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
706 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
707 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
708 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
712 // Neon 3-register vector intrinsics.
714 // First with only element sizes of 16 and 32 bits:
715 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
716 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
717 // 64-bit vector types.
718 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
719 v4i16, v4i16, IntOp, Commutable>;
720 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
721 v2i32, v2i32, IntOp, Commutable>;
723 // 128-bit vector types.
724 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
725 v8i16, v8i16, IntOp, Commutable>;
726 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
727 v4i32, v4i32, IntOp, Commutable>;
730 // ....then also with element size of 8 bits:
731 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
732 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
733 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
734 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
735 v8i8, v8i8, IntOp, Commutable>;
736 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
737 v16i8, v16i8, IntOp, Commutable>;
740 // ....then also with element size of 64 bits:
741 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
742 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
743 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
744 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
745 v1i64, v1i64, IntOp, Commutable>;
746 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
747 v2i64, v2i64, IntOp, Commutable>;
751 // Neon Narrowing 3-register vector intrinsics,
752 // source operand element sizes of 16, 32 and 64 bits:
753 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
754 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
755 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
756 v8i8, v8i16, IntOp, Commutable>;
757 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
758 v4i16, v4i32, IntOp, Commutable>;
759 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
760 v2i32, v2i64, IntOp, Commutable>;
764 // Neon Long 3-register vector intrinsics.
766 // First with only element sizes of 16 and 32 bits:
767 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
768 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
769 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
770 v4i32, v4i16, IntOp, Commutable>;
771 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
772 v2i64, v2i32, IntOp, Commutable>;
775 // ....then also with element size of 8 bits:
776 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
777 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
778 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
779 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
780 v8i16, v8i8, IntOp, Commutable>;
784 // Neon Wide 3-register vector intrinsics,
785 // source operand element sizes of 8, 16 and 32 bits:
786 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
787 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
788 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
789 v8i16, v8i8, IntOp, Commutable>;
790 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
791 v4i32, v4i16, IntOp, Commutable>;
792 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
793 v2i64, v2i32, IntOp, Commutable>;
797 // Neon Multiply-Op vector operations,
798 // element sizes of 8, 16 and 32 bits:
799 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
800 string OpcodeStr, SDNode OpNode> {
801 // 64-bit vector types.
802 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
803 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
804 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
805 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
806 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
807 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
809 // 128-bit vector types.
810 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
811 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
812 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
813 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
814 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
815 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
819 // Neon 3-argument intrinsics,
820 // element sizes of 8, 16 and 32 bits:
821 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
822 string OpcodeStr, Intrinsic IntOp> {
823 // 64-bit vector types.
824 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
825 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
826 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
827 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
828 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
829 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
831 // 128-bit vector types.
832 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
833 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
834 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
835 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
836 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
837 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
841 // Neon Long 3-argument intrinsics.
843 // First with only element sizes of 16 and 32 bits:
844 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
845 string OpcodeStr, Intrinsic IntOp> {
846 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
847 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
848 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
849 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
852 // ....then also with element size of 8 bits:
853 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
854 string OpcodeStr, Intrinsic IntOp>
855 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
856 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
857 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
861 // Neon 2-register vector intrinsics,
862 // element sizes of 8, 16 and 32 bits:
863 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
864 bits<5> op11_7, bit op4, string OpcodeStr,
866 // 64-bit vector types.
867 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
868 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
869 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
870 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
871 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
872 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
874 // 128-bit vector types.
875 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
876 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
877 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
878 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
879 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
880 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
884 // Neon Pairwise long 2-register intrinsics,
885 // element sizes of 8, 16 and 32 bits:
886 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
887 bits<5> op11_7, bit op4,
888 string OpcodeStr, Intrinsic IntOp> {
889 // 64-bit vector types.
890 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
891 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
892 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
893 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
894 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
895 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
897 // 128-bit vector types.
898 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
899 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
900 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
901 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
902 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
903 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
907 // Neon Pairwise long 2-register accumulate intrinsics,
908 // element sizes of 8, 16 and 32 bits:
909 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
910 bits<5> op11_7, bit op4,
911 string OpcodeStr, Intrinsic IntOp> {
912 // 64-bit vector types.
913 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
914 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
915 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
916 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
917 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
918 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
920 // 128-bit vector types.
921 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
922 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
923 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
924 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
925 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
926 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
930 // Neon 2-register vector shift by immediate,
931 // element sizes of 8, 16, 32 and 64 bits:
932 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
933 string OpcodeStr, SDNode OpNode> {
934 // 64-bit vector types.
935 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
936 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
937 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
938 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
939 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
940 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
941 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
942 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
944 // 128-bit vector types.
945 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
946 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
947 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
948 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
949 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
950 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
951 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
952 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
956 // Neon Shift-Accumulate vector operations,
957 // element sizes of 8, 16, 32 and 64 bits:
958 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
959 string OpcodeStr, SDNode ShOp> {
960 // 64-bit vector types.
961 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
962 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
963 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
964 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
965 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
966 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
967 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
968 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
970 // 128-bit vector types.
971 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
972 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
973 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
974 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
975 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
976 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
977 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
978 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
982 // Neon Shift-Insert vector operations,
983 // element sizes of 8, 16, 32 and 64 bits:
984 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
985 string OpcodeStr, SDNode ShOp> {
986 // 64-bit vector types.
987 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
988 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
989 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
990 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
991 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
992 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
993 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
994 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
996 // 128-bit vector types.
997 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
998 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
999 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
1000 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1001 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
1002 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1003 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
1004 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1007 //===----------------------------------------------------------------------===//
1008 // Instruction Definitions.
1009 //===----------------------------------------------------------------------===//
1011 // Vector Add Operations.
1013 // VADD : Vector Add (integer and floating-point)
1014 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
1015 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
1016 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
1017 // VADDL : Vector Add Long (Q = D + D)
1018 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
1019 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
1020 // VADDW : Vector Add Wide (Q = Q + D)
1021 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
1022 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1023 // VHADD : Vector Halving Add
1024 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
1025 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
1026 // VRHADD : Vector Rounding Halving Add
1027 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1028 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1029 // VQADD : Vector Saturating Add
1030 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
1031 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
1032 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1033 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1034 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1035 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1037 // Vector Multiply Operations.
1039 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1040 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
1041 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
1042 int_arm_neon_vmulp, 1>;
1043 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
1044 int_arm_neon_vmulp, 1>;
1045 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
1046 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
1047 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1048 defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1049 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1050 defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1051 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1052 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
1053 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
1054 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
1055 int_arm_neon_vmullp, 1>;
1056 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1057 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
1059 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1061 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1062 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
1063 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
1064 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
1065 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1066 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1067 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1068 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1069 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1070 // VMLS : Vector Multiply Subtract (integer and floating-point)
1071 defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
1072 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
1073 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
1074 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1075 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1076 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1077 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1078 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1080 // Vector Subtract Operations.
1082 // VSUB : Vector Subtract (integer and floating-point)
1083 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
1084 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
1085 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
1086 // VSUBL : Vector Subtract Long (Q = D - D)
1087 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
1088 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
1089 // VSUBW : Vector Subtract Wide (Q = Q - D)
1090 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1091 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1092 // VHSUB : Vector Halving Subtract
1093 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
1094 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
1095 // VQSUB : Vector Saturing Subtract
1096 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
1097 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
1098 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1099 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1100 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1101 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1103 // Vector Comparisons.
1105 // VCEQ : Vector Compare Equal
1106 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
1107 def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1108 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1109 // VCGE : Vector Compare Greater Than or Equal
1110 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
1111 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
1112 def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1113 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1114 // VCGT : Vector Compare Greater Than
1115 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
1116 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
1117 def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1118 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1119 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1120 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
1121 int_arm_neon_vacged, 0>;
1122 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
1123 int_arm_neon_vacgeq, 0>;
1124 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1125 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
1126 int_arm_neon_vacgtd, 0>;
1127 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
1128 int_arm_neon_vacgtq, 0>;
1129 // VTST : Vector Test Bits
1130 defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
1132 // Vector Bitwise Operations.
1134 // VAND : Vector Bitwise AND
1135 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
1136 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
1138 // VEOR : Vector Bitwise Exclusive OR
1139 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
1140 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
1142 // VORR : Vector Bitwise OR
1143 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
1144 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
1146 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1147 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1148 (ins DPR:$src1, DPR:$src2), NoItinerary,
1149 "vbic\t$dst, $src1, $src2", "",
1150 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
1151 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1152 (ins QPR:$src1, QPR:$src2), NoItinerary,
1153 "vbic\t$dst, $src1, $src2", "",
1154 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
1156 // VORN : Vector Bitwise OR NOT
1157 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1158 (ins DPR:$src1, DPR:$src2), NoItinerary,
1159 "vorn\t$dst, $src1, $src2", "",
1160 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1161 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1162 (ins QPR:$src1, QPR:$src2), NoItinerary,
1163 "vorn\t$dst, $src1, $src2", "",
1164 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1166 // VMVN : Vector Bitwise NOT
1167 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1168 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1169 "vmvn\t$dst, $src", "",
1170 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1171 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1172 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1173 "vmvn\t$dst, $src", "",
1174 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1175 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1176 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1178 // VBSL : Vector Bitwise Select
1179 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1180 (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
1181 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1183 (v2i32 (or (and DPR:$src2, DPR:$src1),
1184 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1185 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1186 (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
1187 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1189 (v4i32 (or (and QPR:$src2, QPR:$src1),
1190 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1192 // VBIF : Vector Bitwise Insert if False
1193 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1194 // VBIT : Vector Bitwise Insert if True
1195 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1196 // These are not yet implemented. The TwoAddress pass will not go looking
1197 // for equivalent operations with different register constraints; it just
1200 // Vector Absolute Differences.
1202 // VABD : Vector Absolute Difference
1203 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1204 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1205 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1206 int_arm_neon_vabdf, 0>;
1207 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1208 int_arm_neon_vabdf, 0>;
1210 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1211 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1212 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1214 // VABA : Vector Absolute Difference and Accumulate
1215 defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1216 defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1218 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1219 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1220 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1222 // Vector Maximum and Minimum.
1224 // VMAX : Vector Maximum
1225 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1226 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1227 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1228 int_arm_neon_vmaxf, 1>;
1229 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1230 int_arm_neon_vmaxf, 1>;
1232 // VMIN : Vector Minimum
1233 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1234 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1235 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1236 int_arm_neon_vminf, 1>;
1237 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1238 int_arm_neon_vminf, 1>;
1240 // Vector Pairwise Operations.
1242 // VPADD : Vector Pairwise Add
1243 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1244 int_arm_neon_vpaddi, 0>;
1245 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1246 int_arm_neon_vpaddi, 0>;
1247 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1248 int_arm_neon_vpaddi, 0>;
1249 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1250 int_arm_neon_vpaddf, 0>;
1252 // VPADDL : Vector Pairwise Add Long
1253 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1254 int_arm_neon_vpaddls>;
1255 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1256 int_arm_neon_vpaddlu>;
1258 // VPADAL : Vector Pairwise Add and Accumulate Long
1259 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1260 int_arm_neon_vpadals>;
1261 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1262 int_arm_neon_vpadalu>;
1264 // VPMAX : Vector Pairwise Maximum
1265 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1266 int_arm_neon_vpmaxs, 0>;
1267 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1268 int_arm_neon_vpmaxs, 0>;
1269 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1270 int_arm_neon_vpmaxs, 0>;
1271 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1272 int_arm_neon_vpmaxu, 0>;
1273 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1274 int_arm_neon_vpmaxu, 0>;
1275 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1276 int_arm_neon_vpmaxu, 0>;
1277 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1278 int_arm_neon_vpmaxf, 0>;
1280 // VPMIN : Vector Pairwise Minimum
1281 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1282 int_arm_neon_vpmins, 0>;
1283 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1284 int_arm_neon_vpmins, 0>;
1285 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1286 int_arm_neon_vpmins, 0>;
1287 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1288 int_arm_neon_vpminu, 0>;
1289 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1290 int_arm_neon_vpminu, 0>;
1291 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1292 int_arm_neon_vpminu, 0>;
1293 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1294 int_arm_neon_vpminf, 0>;
1296 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1298 // VRECPE : Vector Reciprocal Estimate
1299 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1300 v2i32, v2i32, int_arm_neon_vrecpe>;
1301 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1302 v4i32, v4i32, int_arm_neon_vrecpe>;
1303 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1304 v2f32, v2f32, int_arm_neon_vrecpef>;
1305 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1306 v4f32, v4f32, int_arm_neon_vrecpef>;
1308 // VRECPS : Vector Reciprocal Step
1309 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1310 int_arm_neon_vrecps, 1>;
1311 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1312 int_arm_neon_vrecps, 1>;
1314 // VRSQRTE : Vector Reciprocal Square Root Estimate
1315 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1316 v2i32, v2i32, int_arm_neon_vrsqrte>;
1317 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1318 v4i32, v4i32, int_arm_neon_vrsqrte>;
1319 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1320 v2f32, v2f32, int_arm_neon_vrsqrtef>;
1321 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1322 v4f32, v4f32, int_arm_neon_vrsqrtef>;
1324 // VRSQRTS : Vector Reciprocal Square Root Step
1325 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1326 int_arm_neon_vrsqrts, 1>;
1327 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1328 int_arm_neon_vrsqrts, 1>;
1332 // VSHL : Vector Shift
1333 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1334 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1335 // VSHL : Vector Shift Left (Immediate)
1336 defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1337 // VSHR : Vector Shift Right (Immediate)
1338 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1339 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1341 // VSHLL : Vector Shift Left Long
1342 def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1343 v8i16, v8i8, NEONvshlls>;
1344 def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1345 v4i32, v4i16, NEONvshlls>;
1346 def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1347 v2i64, v2i32, NEONvshlls>;
1348 def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1349 v8i16, v8i8, NEONvshllu>;
1350 def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1351 v4i32, v4i16, NEONvshllu>;
1352 def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1353 v2i64, v2i32, NEONvshllu>;
1355 // VSHLL : Vector Shift Left Long (with maximum shift count)
1356 def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1357 v8i16, v8i8, NEONvshlli>;
1358 def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1359 v4i32, v4i16, NEONvshlli>;
1360 def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1361 v2i64, v2i32, NEONvshlli>;
1363 // VSHRN : Vector Shift Right and Narrow
1364 def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1365 v8i8, v8i16, NEONvshrn>;
1366 def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1367 v4i16, v4i32, NEONvshrn>;
1368 def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1369 v2i32, v2i64, NEONvshrn>;
1371 // VRSHL : Vector Rounding Shift
1372 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1373 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1374 // VRSHR : Vector Rounding Shift Right
1375 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1376 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1378 // VRSHRN : Vector Rounding Shift Right and Narrow
1379 def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1380 v8i8, v8i16, NEONvrshrn>;
1381 def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1382 v4i16, v4i32, NEONvrshrn>;
1383 def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1384 v2i32, v2i64, NEONvrshrn>;
1386 // VQSHL : Vector Saturating Shift
1387 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1388 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1389 // VQSHL : Vector Saturating Shift Left (Immediate)
1390 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1391 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1392 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1393 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1395 // VQSHRN : Vector Saturating Shift Right and Narrow
1396 def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1397 v8i8, v8i16, NEONvqshrns>;
1398 def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1399 v4i16, v4i32, NEONvqshrns>;
1400 def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1401 v2i32, v2i64, NEONvqshrns>;
1402 def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1403 v8i8, v8i16, NEONvqshrnu>;
1404 def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1405 v4i16, v4i32, NEONvqshrnu>;
1406 def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1407 v2i32, v2i64, NEONvqshrnu>;
1409 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1410 def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1411 v8i8, v8i16, NEONvqshrnsu>;
1412 def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1413 v4i16, v4i32, NEONvqshrnsu>;
1414 def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1415 v2i32, v2i64, NEONvqshrnsu>;
1417 // VQRSHL : Vector Saturating Rounding Shift
1418 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1419 int_arm_neon_vqrshifts, 0>;
1420 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1421 int_arm_neon_vqrshiftu, 0>;
1423 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1424 def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1425 v8i8, v8i16, NEONvqrshrns>;
1426 def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1427 v4i16, v4i32, NEONvqrshrns>;
1428 def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1429 v2i32, v2i64, NEONvqrshrns>;
1430 def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1431 v8i8, v8i16, NEONvqrshrnu>;
1432 def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1433 v4i16, v4i32, NEONvqrshrnu>;
1434 def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1435 v2i32, v2i64, NEONvqrshrnu>;
1437 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1438 def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1439 v8i8, v8i16, NEONvqrshrnsu>;
1440 def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1441 v4i16, v4i32, NEONvqrshrnsu>;
1442 def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1443 v2i32, v2i64, NEONvqrshrnsu>;
1445 // VSRA : Vector Shift Right and Accumulate
1446 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1447 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1448 // VRSRA : Vector Rounding Shift Right and Accumulate
1449 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1450 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1452 // VSLI : Vector Shift Left and Insert
1453 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1454 // VSRI : Vector Shift Right and Insert
1455 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1457 // Vector Absolute and Saturating Absolute.
1459 // VABS : Vector Absolute Value
1460 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1462 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1463 v2f32, v2f32, int_arm_neon_vabsf>;
1464 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1465 v4f32, v4f32, int_arm_neon_vabsf>;
1467 // VQABS : Vector Saturating Absolute Value
1468 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1469 int_arm_neon_vqabs>;
1473 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1474 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1476 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1477 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1479 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1480 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1481 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1482 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1484 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1485 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1487 // VNEG : Vector Negate
1488 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1489 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1490 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1491 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1492 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1493 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1495 // VNEG : Vector Negate (floating-point)
1496 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1497 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1498 "vneg.f32\t$dst, $src", "",
1499 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1500 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1501 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1502 "vneg.f32\t$dst, $src", "",
1503 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1505 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1506 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1507 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1508 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1509 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1510 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1512 // VQNEG : Vector Saturating Negate
1513 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1514 int_arm_neon_vqneg>;
1516 // Vector Bit Counting Operations.
1518 // VCLS : Vector Count Leading Sign Bits
1519 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1521 // VCLZ : Vector Count Leading Zeros
1522 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1524 // VCNT : Vector Count One Bits
1525 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1526 v8i8, v8i8, int_arm_neon_vcnt>;
1527 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1528 v16i8, v16i8, int_arm_neon_vcnt>;
1530 // Vector Move Operations.
1532 // VMOV : Vector Move (Register)
1534 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1535 NoItinerary, "vmov\t$dst, $src", "", []>;
1536 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1537 NoItinerary, "vmov\t$dst, $src", "", []>;
1539 // VMOV : Vector Move (Immediate)
1541 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1542 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1543 return ARM::getVMOVImm(N, 1, *CurDAG);
1545 def vmovImm8 : PatLeaf<(build_vector), [{
1546 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1549 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1550 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1551 return ARM::getVMOVImm(N, 2, *CurDAG);
1553 def vmovImm16 : PatLeaf<(build_vector), [{
1554 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1555 }], VMOV_get_imm16>;
1557 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1558 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1559 return ARM::getVMOVImm(N, 4, *CurDAG);
1561 def vmovImm32 : PatLeaf<(build_vector), [{
1562 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1563 }], VMOV_get_imm32>;
1565 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1566 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1567 return ARM::getVMOVImm(N, 8, *CurDAG);
1569 def vmovImm64 : PatLeaf<(build_vector), [{
1570 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1571 }], VMOV_get_imm64>;
1573 // Note: Some of the cmode bits in the following VMOV instructions need to
1574 // be encoded based on the immed values.
1576 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1577 (ins i8imm:$SIMM), NoItinerary,
1578 "vmov.i8\t$dst, $SIMM", "",
1579 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1580 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1581 (ins i8imm:$SIMM), NoItinerary,
1582 "vmov.i8\t$dst, $SIMM", "",
1583 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1585 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1586 (ins i16imm:$SIMM), NoItinerary,
1587 "vmov.i16\t$dst, $SIMM", "",
1588 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1589 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1590 (ins i16imm:$SIMM), NoItinerary,
1591 "vmov.i16\t$dst, $SIMM", "",
1592 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1594 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1595 (ins i32imm:$SIMM), NoItinerary,
1596 "vmov.i32\t$dst, $SIMM", "",
1597 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1598 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1599 (ins i32imm:$SIMM), NoItinerary,
1600 "vmov.i32\t$dst, $SIMM", "",
1601 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1603 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1604 (ins i64imm:$SIMM), NoItinerary,
1605 "vmov.i64\t$dst, $SIMM", "",
1606 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1607 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1608 (ins i64imm:$SIMM), NoItinerary,
1609 "vmov.i64\t$dst, $SIMM", "",
1610 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1612 // VMOV : Vector Get Lane (move scalar to ARM core register)
1614 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1615 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1616 NoItinerary, "vmov", ".s8\t$dst, $src[${lane:no_hash}]",
1617 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1619 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1620 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1621 NoItinerary, "vmov", ".s16\t$dst, $src[${lane:no_hash}]",
1622 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1624 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1625 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1626 NoItinerary, "vmov", ".u8\t$dst, $src[${lane:no_hash}]",
1627 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1629 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1630 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1631 NoItinerary, "vmov", ".u16\t$dst, $src[${lane:no_hash}]",
1632 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1634 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1635 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane),
1636 NoItinerary, "vmov", ".32\t$dst, $src[${lane:no_hash}]",
1637 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1639 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1640 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1641 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1642 (SubReg_i8_reg imm:$lane))),
1643 (SubReg_i8_lane imm:$lane))>;
1644 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1645 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1646 (SubReg_i16_reg imm:$lane))),
1647 (SubReg_i16_lane imm:$lane))>;
1648 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1649 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1650 (SubReg_i8_reg imm:$lane))),
1651 (SubReg_i8_lane imm:$lane))>;
1652 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1653 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1654 (SubReg_i16_reg imm:$lane))),
1655 (SubReg_i16_lane imm:$lane))>;
1656 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1657 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1658 (SubReg_i32_reg imm:$lane))),
1659 (SubReg_i32_lane imm:$lane))>;
1660 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1661 // (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1662 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1663 (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>;
1666 // VMOV : Vector Set Lane (move ARM core register to scalar)
1668 let Constraints = "$src1 = $dst" in {
1669 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1670 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1671 NoItinerary, "vmov", ".8\t$dst[${lane:no_hash}], $src2",
1672 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1673 GPR:$src2, imm:$lane))]>;
1674 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1675 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1676 NoItinerary, "vmov", ".16\t$dst[${lane:no_hash}], $src2",
1677 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1678 GPR:$src2, imm:$lane))]>;
1679 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1680 (ins DPR:$src1, GPR:$src2, i32imm:$lane),
1681 NoItinerary, "vmov", ".32\t$dst[${lane:no_hash}], $src2",
1682 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1683 GPR:$src2, imm:$lane))]>;
1685 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1686 (v16i8 (INSERT_SUBREG QPR:$src1,
1687 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1688 (SubReg_i8_reg imm:$lane))),
1689 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1690 (SubReg_i8_reg imm:$lane)))>;
1691 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1692 (v8i16 (INSERT_SUBREG QPR:$src1,
1693 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1694 (SubReg_i16_reg imm:$lane))),
1695 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1696 (SubReg_i16_reg imm:$lane)))>;
1697 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1698 (v4i32 (INSERT_SUBREG QPR:$src1,
1699 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1700 (SubReg_i32_reg imm:$lane))),
1701 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1702 (SubReg_i32_reg imm:$lane)))>;
1704 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1705 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1706 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1707 (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>;
1709 // VDUP : Vector Duplicate (from ARM core register to all elements)
1711 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
1712 (vector_shuffle node:$lhs, node:$rhs), [{
1713 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1714 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
1717 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1718 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1719 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1720 [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1721 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1722 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1723 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1724 [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>;
1726 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1727 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1728 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1729 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1730 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1731 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1733 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1734 NoItinerary, "vdup", ".32\t$dst, $src",
1735 [(set DPR:$dst, (v2f32 (splat_lo
1737 (f32 (bitconvert GPR:$src))),
1739 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1740 NoItinerary, "vdup", ".32\t$dst, $src",
1741 [(set QPR:$dst, (v4f32 (splat_lo
1743 (f32 (bitconvert GPR:$src))),
1746 // VDUP : Vector Duplicate Lane (from scalar to all elements)
1748 def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{
1749 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1750 return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32);
1753 def splat_lane : PatFrag<(ops node:$lhs, node:$rhs),
1754 (vector_shuffle node:$lhs, node:$rhs), [{
1755 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1756 return SVOp->isSplat();
1757 }], SHUFFLE_get_splat_lane>;
1759 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1760 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1761 (outs DPR:$dst), (ins DPR:$src, i32imm:$lane), NoItinerary,
1762 !strconcat(OpcodeStr, "\t$dst, $src[${lane:no_hash}]"), "",
1763 [(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>;
1765 // vector_shuffle requires that the source and destination types match, so
1766 // VDUP to a 128-bit result uses a target-specific VDUPLANEQ node.
1767 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1768 ValueType ResTy, ValueType OpTy>
1769 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1770 (outs QPR:$dst), (ins DPR:$src, i32imm:$lane), NoItinerary,
1771 !strconcat(OpcodeStr, "\t$dst, $src[${lane:no_hash}]"), "",
1772 [(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>;
1774 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1775 def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1776 def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1777 def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1778 def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1779 def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1780 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1781 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1783 def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
1784 (outs DPR:$dst), (ins SPR:$src),
1785 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1786 [(set DPR:$dst, (v2f32 (splat_lo
1787 (scalar_to_vector SPR:$src),
1790 def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
1791 (outs QPR:$dst), (ins SPR:$src),
1792 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1793 [(set QPR:$dst, (v4f32 (splat_lo
1794 (scalar_to_vector SPR:$src),
1797 // VMOVN : Vector Narrowing Move
1798 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1799 int_arm_neon_vmovn>;
1800 // VQMOVN : Vector Saturating Narrowing Move
1801 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1802 int_arm_neon_vqmovns>;
1803 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1804 int_arm_neon_vqmovnu>;
1805 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1806 int_arm_neon_vqmovnsu>;
1807 // VMOVL : Vector Lengthening Move
1808 defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1809 defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1811 // Vector Conversions.
1813 // VCVT : Vector Convert Between Floating-Point and Integers
1814 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1815 v2i32, v2f32, fp_to_sint>;
1816 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1817 v2i32, v2f32, fp_to_uint>;
1818 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1819 v2f32, v2i32, sint_to_fp>;
1820 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1821 v2f32, v2i32, uint_to_fp>;
1823 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1824 v4i32, v4f32, fp_to_sint>;
1825 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1826 v4i32, v4f32, fp_to_uint>;
1827 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1828 v4f32, v4i32, sint_to_fp>;
1829 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1830 v4f32, v4i32, uint_to_fp>;
1832 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1833 // Note: Some of the opcode bits in the following VCVT instructions need to
1834 // be encoded based on the immed values.
1835 def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1836 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1837 def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1838 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1839 def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1840 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1841 def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1842 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1844 def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1845 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1846 def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1847 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1848 def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1849 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1850 def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1851 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1853 // VREV : Vector Reverse
1855 def vrev64_shuffle : PatFrag<(ops node:$in),
1856 (vector_shuffle node:$in, undef), [{
1857 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1858 return ARM::isVREVMask(SVOp, 64);
1861 def vrev32_shuffle : PatFrag<(ops node:$in),
1862 (vector_shuffle node:$in, undef), [{
1863 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1864 return ARM::isVREVMask(SVOp, 32);
1867 def vrev16_shuffle : PatFrag<(ops node:$in),
1868 (vector_shuffle node:$in, undef), [{
1869 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1870 return ARM::isVREVMask(SVOp, 16);
1873 // VREV64 : Vector Reverse elements within 64-bit doublewords
1875 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1876 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
1877 (ins DPR:$src), NoItinerary,
1878 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1879 [(set DPR:$dst, (Ty (vrev64_shuffle (Ty DPR:$src))))]>;
1880 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1881 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
1882 (ins QPR:$src), NoItinerary,
1883 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1884 [(set QPR:$dst, (Ty (vrev64_shuffle (Ty QPR:$src))))]>;
1886 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
1887 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
1888 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
1889 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
1891 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
1892 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
1893 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
1894 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
1896 // VREV32 : Vector Reverse elements within 32-bit words
1898 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1899 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
1900 (ins DPR:$src), NoItinerary,
1901 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1902 [(set DPR:$dst, (Ty (vrev32_shuffle (Ty DPR:$src))))]>;
1903 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1904 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
1905 (ins QPR:$src), NoItinerary,
1906 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1907 [(set QPR:$dst, (Ty (vrev32_shuffle (Ty QPR:$src))))]>;
1909 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
1910 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
1912 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
1913 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
1915 // VREV16 : Vector Reverse elements within 16-bit halfwords
1917 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1918 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
1919 (ins DPR:$src), NoItinerary,
1920 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1921 [(set DPR:$dst, (Ty (vrev16_shuffle (Ty DPR:$src))))]>;
1922 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1923 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
1924 (ins QPR:$src), NoItinerary,
1925 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1926 [(set QPR:$dst, (Ty (vrev16_shuffle (Ty QPR:$src))))]>;
1928 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
1929 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
1931 // VTRN : Vector Transpose
1933 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
1934 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">;
1935 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">;
1937 def VTRNq8 : N2VQShuffle<0b00, 0b00001, "vtrn.8">;
1938 def VTRNq16 : N2VQShuffle<0b01, 0b00001, "vtrn.16">;
1939 def VTRNq32 : N2VQShuffle<0b10, 0b00001, "vtrn.32">;
1941 // VUZP : Vector Unzip (Deinterleave)
1943 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">;
1944 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">;
1945 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">;
1947 def VUZPq8 : N2VQShuffle<0b00, 0b00010, "vuzp.8">;
1948 def VUZPq16 : N2VQShuffle<0b01, 0b00010, "vuzp.16">;
1949 def VUZPq32 : N2VQShuffle<0b10, 0b00010, "vuzp.32">;
1951 // VZIP : Vector Zip (Interleave)
1953 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">;
1954 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">;
1955 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">;
1957 def VZIPq8 : N2VQShuffle<0b00, 0b00011, "vzip.8">;
1958 def VZIPq16 : N2VQShuffle<0b01, 0b00011, "vzip.16">;
1959 def VZIPq32 : N2VQShuffle<0b10, 0b00011, "vzip.32">;
1961 //===----------------------------------------------------------------------===//
1962 // NEON instructions for single-precision FP math
1963 //===----------------------------------------------------------------------===//
1965 // These need separate instructions because they must use DPR_VFP2 register
1966 // class which have SPR sub-registers.
1968 // Vector Add Operations used for single-precision FP
1969 let neverHasSideEffects = 1 in
1970 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
1971 def : N3VDsPat<fadd, VADDfd_sfp>;
1973 // Vector Multiply Operations used for single-precision FP
1974 let neverHasSideEffects = 1 in
1975 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
1976 def : N3VDsPat<fmul, VMULfd_sfp>;
1978 // Vector Multiply-Accumulate/Subtract used for single-precision FP
1979 let neverHasSideEffects = 1 in
1980 def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32,fmul,fadd>;
1981 def : N3VDMulOpsPat<fmul, fadd, VMLAfd>;
1983 let neverHasSideEffects = 1 in
1984 def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32,fmul,fsub>;
1985 def : N3VDMulOpsPat<fmul, fsub, VMLSfd>;
1987 // Vector Sub Operations used for single-precision FP
1988 let neverHasSideEffects = 1 in
1989 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
1990 def : N3VDsPat<fsub, VSUBfd_sfp>;
1992 // Vector Absolute for single-precision FP
1993 let neverHasSideEffects = 1 in
1994 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1995 v2f32, v2f32, int_arm_neon_vabsf>;
1996 def : N2VDIntsPat<fabs, VABSfd_sfp>;
1998 // Vector Negate for single-precision FP
2000 let neverHasSideEffects = 1 in
2001 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2002 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
2003 "vneg.f32\t$dst, $src", "", []>;
2004 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
2006 //===----------------------------------------------------------------------===//
2007 // Non-Instruction Patterns
2008 //===----------------------------------------------------------------------===//
2011 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
2012 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
2013 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
2014 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
2015 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
2016 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
2017 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
2018 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
2019 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
2020 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
2021 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
2022 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
2023 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
2024 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
2025 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
2026 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
2027 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
2028 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
2029 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
2030 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
2031 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
2032 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
2033 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
2034 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
2035 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
2036 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
2037 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
2038 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
2039 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
2040 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
2042 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
2043 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
2044 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
2045 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
2046 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
2047 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
2048 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
2049 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
2050 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
2051 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
2052 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
2053 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
2054 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
2055 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
2056 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
2057 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
2058 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
2059 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
2060 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
2061 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
2062 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
2063 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
2064 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
2065 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
2066 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
2067 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
2068 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
2069 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
2070 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
2071 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
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