1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
42 def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
43 def nImmVMOVI32Neg : Operand<i32> {
44 let PrintMethod = "printNEONModImmOperand";
45 let ParserMatchClass = nImmVMOVI32NegAsmOperand;
47 def nImmVMOVF32 : Operand<i32> {
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
51 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
52 def nImmSplatI64 : Operand<i32> {
53 let PrintMethod = "printNEONModImmOperand";
54 let ParserMatchClass = nImmSplatI64AsmOperand;
57 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
58 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
59 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
60 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
61 return ((uint64_t)Imm) < 8;
63 let ParserMatchClass = VectorIndex8Operand;
64 let PrintMethod = "printVectorIndex";
65 let MIOperandInfo = (ops i32imm);
67 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
68 return ((uint64_t)Imm) < 4;
70 let ParserMatchClass = VectorIndex16Operand;
71 let PrintMethod = "printVectorIndex";
72 let MIOperandInfo = (ops i32imm);
74 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
75 return ((uint64_t)Imm) < 2;
77 let ParserMatchClass = VectorIndex32Operand;
78 let PrintMethod = "printVectorIndex";
79 let MIOperandInfo = (ops i32imm);
82 // Register list of one D register.
83 def VecListOneDAsmOperand : AsmOperandClass {
84 let Name = "VecListOneD";
85 let ParserMethod = "parseVectorList";
86 let RenderMethod = "addVecListOperands";
88 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
89 let ParserMatchClass = VecListOneDAsmOperand;
91 // Register list of two sequential D registers.
92 def VecListTwoDAsmOperand : AsmOperandClass {
93 let Name = "VecListTwoD";
94 let ParserMethod = "parseVectorList";
95 let RenderMethod = "addVecListOperands";
97 def VecListTwoD : RegisterOperand<DPR, "printVectorListTwo"> {
98 let ParserMatchClass = VecListTwoDAsmOperand;
100 // Register list of three sequential D registers.
101 def VecListThreeDAsmOperand : AsmOperandClass {
102 let Name = "VecListThreeD";
103 let ParserMethod = "parseVectorList";
104 let RenderMethod = "addVecListOperands";
106 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
107 let ParserMatchClass = VecListThreeDAsmOperand;
109 // Register list of four sequential D registers.
110 def VecListFourDAsmOperand : AsmOperandClass {
111 let Name = "VecListFourD";
112 let ParserMethod = "parseVectorList";
113 let RenderMethod = "addVecListOperands";
115 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
116 let ParserMatchClass = VecListFourDAsmOperand;
118 // Register list of two D registers spaced by 2 (two sequential Q registers).
119 def VecListTwoQAsmOperand : AsmOperandClass {
120 let Name = "VecListTwoQ";
121 let ParserMethod = "parseVectorList";
122 let RenderMethod = "addVecListOperands";
124 def VecListTwoQ : RegisterOperand<DPR, "printVectorListTwoSpaced"> {
125 let ParserMatchClass = VecListTwoQAsmOperand;
128 // Register list of one D register, with "all lanes" subscripting.
129 def VecListOneDAllLanesAsmOperand : AsmOperandClass {
130 let Name = "VecListOneDAllLanes";
131 let ParserMethod = "parseVectorList";
132 let RenderMethod = "addVecListOperands";
134 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
135 let ParserMatchClass = VecListOneDAllLanesAsmOperand;
137 // Register list of two D registers, with "all lanes" subscripting.
138 def VecListTwoDAllLanesAsmOperand : AsmOperandClass {
139 let Name = "VecListTwoDAllLanes";
140 let ParserMethod = "parseVectorList";
141 let RenderMethod = "addVecListOperands";
143 def VecListTwoDAllLanes : RegisterOperand<DPR, "printVectorListTwoAllLanes"> {
144 let ParserMatchClass = VecListTwoDAllLanesAsmOperand;
146 // Register list of two D registers spaced by 2 (two sequential Q registers).
147 def VecListTwoQAllLanesAsmOperand : AsmOperandClass {
148 let Name = "VecListTwoQAllLanes";
149 let ParserMethod = "parseVectorList";
150 let RenderMethod = "addVecListOperands";
152 def VecListTwoQAllLanes : RegisterOperand<DPR,
153 "printVectorListTwoSpacedAllLanes"> {
154 let ParserMatchClass = VecListTwoQAllLanesAsmOperand;
157 // Register list of one D register, with byte lane subscripting.
158 def VecListOneDByteIndexAsmOperand : AsmOperandClass {
159 let Name = "VecListOneDByteIndexed";
160 let ParserMethod = "parseVectorList";
161 let RenderMethod = "addVecListIndexedOperands";
163 def VecListOneDByteIndexed : Operand<i32> {
164 let ParserMatchClass = VecListOneDByteIndexAsmOperand;
165 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
167 // ...with half-word lane subscripting.
168 def VecListOneDHWordIndexAsmOperand : AsmOperandClass {
169 let Name = "VecListOneDHWordIndexed";
170 let ParserMethod = "parseVectorList";
171 let RenderMethod = "addVecListIndexedOperands";
173 def VecListOneDHWordIndexed : Operand<i32> {
174 let ParserMatchClass = VecListOneDHWordIndexAsmOperand;
175 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
177 // ...with word lane subscripting.
178 def VecListOneDWordIndexAsmOperand : AsmOperandClass {
179 let Name = "VecListOneDWordIndexed";
180 let ParserMethod = "parseVectorList";
181 let RenderMethod = "addVecListIndexedOperands";
183 def VecListOneDWordIndexed : Operand<i32> {
184 let ParserMatchClass = VecListOneDWordIndexAsmOperand;
185 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
187 // Register list of two D registers with byte lane subscripting.
188 def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
189 let Name = "VecListTwoDByteIndexed";
190 let ParserMethod = "parseVectorList";
191 let RenderMethod = "addVecListIndexedOperands";
193 def VecListTwoDByteIndexed : Operand<i32> {
194 let ParserMatchClass = VecListTwoDByteIndexAsmOperand;
195 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
197 // ...with half-word lane subscripting.
198 def VecListTwoDHWordIndexAsmOperand : AsmOperandClass {
199 let Name = "VecListTwoDHWordIndexed";
200 let ParserMethod = "parseVectorList";
201 let RenderMethod = "addVecListIndexedOperands";
203 def VecListTwoDHWordIndexed : Operand<i32> {
204 let ParserMatchClass = VecListTwoDHWordIndexAsmOperand;
205 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
207 // ...with word lane subscripting.
208 def VecListTwoDWordIndexAsmOperand : AsmOperandClass {
209 let Name = "VecListTwoDWordIndexed";
210 let ParserMethod = "parseVectorList";
211 let RenderMethod = "addVecListIndexedOperands";
213 def VecListTwoDWordIndexed : Operand<i32> {
214 let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
215 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
217 // Register list of two Q registers with half-word lane subscripting.
218 def VecListTwoQHWordIndexAsmOperand : AsmOperandClass {
219 let Name = "VecListTwoQHWordIndexed";
220 let ParserMethod = "parseVectorList";
221 let RenderMethod = "addVecListIndexedOperands";
223 def VecListTwoQHWordIndexed : Operand<i32> {
224 let ParserMatchClass = VecListTwoQHWordIndexAsmOperand;
225 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
227 // ...with word lane subscripting.
228 def VecListTwoQWordIndexAsmOperand : AsmOperandClass {
229 let Name = "VecListTwoQWordIndexed";
230 let ParserMethod = "parseVectorList";
231 let RenderMethod = "addVecListIndexedOperands";
233 def VecListTwoQWordIndexed : Operand<i32> {
234 let ParserMatchClass = VecListTwoQWordIndexAsmOperand;
235 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
238 //===----------------------------------------------------------------------===//
239 // NEON-specific DAG Nodes.
240 //===----------------------------------------------------------------------===//
242 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
243 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
245 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
246 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
247 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
248 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
249 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
250 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
251 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
252 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
253 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
254 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
255 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
257 // Types for vector shift by immediates. The "SHX" version is for long and
258 // narrow operations where the source and destination vectors have different
259 // types. The "SHINS" version is for shift and insert operations.
260 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
262 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
264 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
265 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
267 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
268 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
269 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
270 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
271 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
272 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
273 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
275 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
276 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
277 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
279 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
280 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
281 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
282 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
283 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
284 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
286 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
287 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
288 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
290 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
291 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
293 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
295 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
296 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
298 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
299 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
300 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
301 def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
303 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
305 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
306 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
308 def NEONvbsl : SDNode<"ARMISD::VBSL",
309 SDTypeProfile<1, 3, [SDTCisVec<0>,
312 SDTCisSameAs<0, 3>]>>;
314 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
316 // VDUPLANE can produce a quad-register result from a double-register source,
317 // so the result is not constrained to match the source.
318 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
319 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
322 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
323 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
324 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
326 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
327 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
328 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
329 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
331 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
333 SDTCisSameAs<0, 3>]>;
334 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
335 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
336 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
338 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
339 SDTCisSameAs<1, 2>]>;
340 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
341 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
343 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
344 SDTCisSameAs<0, 2>]>;
345 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
346 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
348 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
349 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
350 unsigned EltBits = 0;
351 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
352 return (EltBits == 32 && EltVal == 0);
355 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
356 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
357 unsigned EltBits = 0;
358 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
359 return (EltBits == 8 && EltVal == 0xff);
362 //===----------------------------------------------------------------------===//
363 // NEON load / store instructions
364 //===----------------------------------------------------------------------===//
366 // Use VLDM to load a Q register as a D register pair.
367 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
369 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
371 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
373 // Use VSTM to store a Q register as a D register pair.
374 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
376 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
378 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
380 // Classes for VLD* pseudo-instructions with multi-register operands.
381 // These are expanded to real instructions after register allocation.
382 class VLDQPseudo<InstrItinClass itin>
383 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
384 class VLDQWBPseudo<InstrItinClass itin>
385 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
386 (ins addrmode6:$addr, am6offset:$offset), itin,
388 class VLDQWBfixedPseudo<InstrItinClass itin>
389 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
390 (ins addrmode6:$addr), itin,
392 class VLDQWBregisterPseudo<InstrItinClass itin>
393 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
394 (ins addrmode6:$addr, rGPR:$offset), itin,
397 class VLDQQPseudo<InstrItinClass itin>
398 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
399 class VLDQQWBPseudo<InstrItinClass itin>
400 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
401 (ins addrmode6:$addr, am6offset:$offset), itin,
403 class VLDQQWBfixedPseudo<InstrItinClass itin>
404 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
405 (ins addrmode6:$addr), itin,
407 class VLDQQWBregisterPseudo<InstrItinClass itin>
408 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
409 (ins addrmode6:$addr, rGPR:$offset), itin,
413 class VLDQQQQPseudo<InstrItinClass itin>
414 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
416 class VLDQQQQWBPseudo<InstrItinClass itin>
417 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
418 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
419 "$addr.addr = $wb, $src = $dst">;
421 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
423 // VLD1 : Vector Load (multiple single elements)
424 class VLD1D<bits<4> op7_4, string Dt>
425 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
426 (ins addrmode6:$Rn), IIC_VLD1,
427 "vld1", Dt, "$Vd, $Rn", "", []> {
430 let DecoderMethod = "DecodeVLDInstruction";
432 class VLD1Q<bits<4> op7_4, string Dt>
433 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd),
434 (ins addrmode6:$Rn), IIC_VLD1x2,
435 "vld1", Dt, "$Vd, $Rn", "", []> {
437 let Inst{5-4} = Rn{5-4};
438 let DecoderMethod = "DecodeVLDInstruction";
441 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
442 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
443 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
444 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
446 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
447 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
448 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
449 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
451 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
452 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
453 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
454 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
456 // ...with address register writeback:
457 multiclass VLD1DWB<bits<4> op7_4, string Dt> {
458 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
459 (ins addrmode6:$Rn), IIC_VLD1u,
460 "vld1", Dt, "$Vd, $Rn!",
461 "$Rn.addr = $wb", []> {
462 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
464 let DecoderMethod = "DecodeVLDInstruction";
465 let AsmMatchConverter = "cvtVLDwbFixed";
467 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
468 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
469 "vld1", Dt, "$Vd, $Rn, $Rm",
470 "$Rn.addr = $wb", []> {
472 let DecoderMethod = "DecodeVLDInstruction";
473 let AsmMatchConverter = "cvtVLDwbRegister";
476 multiclass VLD1QWB<bits<4> op7_4, string Dt> {
477 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
478 (ins addrmode6:$Rn), IIC_VLD1x2u,
479 "vld1", Dt, "$Vd, $Rn!",
480 "$Rn.addr = $wb", []> {
481 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
482 let Inst{5-4} = Rn{5-4};
483 let DecoderMethod = "DecodeVLDInstruction";
484 let AsmMatchConverter = "cvtVLDwbFixed";
486 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
487 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
488 "vld1", Dt, "$Vd, $Rn, $Rm",
489 "$Rn.addr = $wb", []> {
490 let Inst{5-4} = Rn{5-4};
491 let DecoderMethod = "DecodeVLDInstruction";
492 let AsmMatchConverter = "cvtVLDwbRegister";
496 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
497 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
498 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
499 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
500 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
501 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
502 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
503 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
505 def VLD1q8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
506 def VLD1q16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
507 def VLD1q32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
508 def VLD1q64PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
509 def VLD1q8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
510 def VLD1q16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
511 def VLD1q32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
512 def VLD1q64PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
514 // ...with 3 registers
515 class VLD1D3<bits<4> op7_4, string Dt>
516 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
517 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
518 "$Vd, $Rn", "", []> {
521 let DecoderMethod = "DecodeVLDInstruction";
523 multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
524 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
525 (ins addrmode6:$Rn), IIC_VLD1x2u,
526 "vld1", Dt, "$Vd, $Rn!",
527 "$Rn.addr = $wb", []> {
528 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
530 let DecoderMethod = "DecodeVLDInstruction";
531 let AsmMatchConverter = "cvtVLDwbFixed";
533 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
534 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
535 "vld1", Dt, "$Vd, $Rn, $Rm",
536 "$Rn.addr = $wb", []> {
538 let DecoderMethod = "DecodeVLDInstruction";
539 let AsmMatchConverter = "cvtVLDwbRegister";
543 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
544 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
545 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
546 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
548 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">;
549 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;
550 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;
551 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;
553 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
555 // ...with 4 registers
556 class VLD1D4<bits<4> op7_4, string Dt>
557 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
558 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
559 "$Vd, $Rn", "", []> {
561 let Inst{5-4} = Rn{5-4};
562 let DecoderMethod = "DecodeVLDInstruction";
564 multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
565 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
566 (ins addrmode6:$Rn), IIC_VLD1x2u,
567 "vld1", Dt, "$Vd, $Rn!",
568 "$Rn.addr = $wb", []> {
569 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
570 let Inst{5-4} = Rn{5-4};
571 let DecoderMethod = "DecodeVLDInstruction";
572 let AsmMatchConverter = "cvtVLDwbFixed";
574 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
575 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
576 "vld1", Dt, "$Vd, $Rn, $Rm",
577 "$Rn.addr = $wb", []> {
578 let Inst{5-4} = Rn{5-4};
579 let DecoderMethod = "DecodeVLDInstruction";
580 let AsmMatchConverter = "cvtVLDwbRegister";
584 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
585 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
586 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
587 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
589 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">;
590 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">;
591 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">;
592 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;
594 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
596 // VLD2 : Vector Load (multiple 2-element structures)
597 class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
599 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
600 (ins addrmode6:$Rn), itin,
601 "vld2", Dt, "$Vd, $Rn", "", []> {
603 let Inst{5-4} = Rn{5-4};
604 let DecoderMethod = "DecodeVLDInstruction";
607 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VLD2>;
608 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VLD2>;
609 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VLD2>;
611 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>;
612 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>;
613 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>;
615 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
616 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
617 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
619 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
620 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
621 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
623 // ...with address register writeback:
624 multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
625 RegisterOperand VdTy, InstrItinClass itin> {
626 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
627 (ins addrmode6:$Rn), itin,
628 "vld2", Dt, "$Vd, $Rn!",
629 "$Rn.addr = $wb", []> {
630 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
631 let Inst{5-4} = Rn{5-4};
632 let DecoderMethod = "DecodeVLDInstruction";
633 let AsmMatchConverter = "cvtVLDwbFixed";
635 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
636 (ins addrmode6:$Rn, rGPR:$Rm), itin,
637 "vld2", Dt, "$Vd, $Rn, $Rm",
638 "$Rn.addr = $wb", []> {
639 let Inst{5-4} = Rn{5-4};
640 let DecoderMethod = "DecodeVLDInstruction";
641 let AsmMatchConverter = "cvtVLDwbRegister";
645 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VLD2u>;
646 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VLD2u>;
647 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VLD2u>;
649 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>;
650 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>;
651 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>;
653 def VLD2d8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD2u>;
654 def VLD2d16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD2u>;
655 def VLD2d32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD2u>;
656 def VLD2d8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2u>;
657 def VLD2d16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2u>;
658 def VLD2d32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2u>;
660 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
661 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
662 def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
663 def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
664 def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
665 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
667 // ...with double-spaced registers
668 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VLD2>;
669 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VLD2>;
670 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VLD2>;
671 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VLD2u>;
672 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VLD2u>;
673 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VLD2u>;
675 // VLD3 : Vector Load (multiple 3-element structures)
676 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
677 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
678 (ins addrmode6:$Rn), IIC_VLD3,
679 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
682 let DecoderMethod = "DecodeVLDInstruction";
685 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
686 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
687 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
689 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
690 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
691 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
693 // ...with address register writeback:
694 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
695 : NLdSt<0, 0b10, op11_8, op7_4,
696 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
697 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
698 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
699 "$Rn.addr = $wb", []> {
701 let DecoderMethod = "DecodeVLDInstruction";
704 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
705 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
706 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
708 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
709 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
710 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
712 // ...with double-spaced registers:
713 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
714 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
715 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
716 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
717 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
718 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
720 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
721 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
722 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
724 // ...alternate versions to be allocated odd register numbers:
725 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
726 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
727 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
729 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
730 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
731 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
733 // VLD4 : Vector Load (multiple 4-element structures)
734 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
735 : NLdSt<0, 0b10, op11_8, op7_4,
736 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
737 (ins addrmode6:$Rn), IIC_VLD4,
738 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
740 let Inst{5-4} = Rn{5-4};
741 let DecoderMethod = "DecodeVLDInstruction";
744 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
745 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
746 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
748 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
749 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
750 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
752 // ...with address register writeback:
753 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
754 : NLdSt<0, 0b10, op11_8, op7_4,
755 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
756 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
757 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
758 "$Rn.addr = $wb", []> {
759 let Inst{5-4} = Rn{5-4};
760 let DecoderMethod = "DecodeVLDInstruction";
763 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
764 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
765 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
767 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
768 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
769 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
771 // ...with double-spaced registers:
772 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
773 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
774 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
775 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
776 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
777 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
779 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
780 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
781 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
783 // ...alternate versions to be allocated odd register numbers:
784 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
785 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
786 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
788 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
789 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
790 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
792 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
794 // Classes for VLD*LN pseudo-instructions with multi-register operands.
795 // These are expanded to real instructions after register allocation.
796 class VLDQLNPseudo<InstrItinClass itin>
797 : PseudoNLdSt<(outs QPR:$dst),
798 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
799 itin, "$src = $dst">;
800 class VLDQLNWBPseudo<InstrItinClass itin>
801 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
802 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
803 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
804 class VLDQQLNPseudo<InstrItinClass itin>
805 : PseudoNLdSt<(outs QQPR:$dst),
806 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
807 itin, "$src = $dst">;
808 class VLDQQLNWBPseudo<InstrItinClass itin>
809 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
810 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
811 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
812 class VLDQQQQLNPseudo<InstrItinClass itin>
813 : PseudoNLdSt<(outs QQQQPR:$dst),
814 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
815 itin, "$src = $dst">;
816 class VLDQQQQLNWBPseudo<InstrItinClass itin>
817 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
818 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
819 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
821 // VLD1LN : Vector Load (single element to one lane)
822 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
824 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
825 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
826 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
828 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
829 (i32 (LoadOp addrmode6:$Rn)),
832 let DecoderMethod = "DecodeVLD1LN";
834 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
836 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
837 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
838 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
840 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
841 (i32 (LoadOp addrmode6oneL32:$Rn)),
844 let DecoderMethod = "DecodeVLD1LN";
846 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
847 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
848 (i32 (LoadOp addrmode6:$addr)),
852 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
853 let Inst{7-5} = lane{2-0};
855 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
856 let Inst{7-6} = lane{1-0};
857 let Inst{5-4} = Rn{5-4};
859 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
860 let Inst{7} = lane{0};
861 let Inst{5-4} = Rn{5-4};
864 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
865 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
866 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
868 def : Pat<(vector_insert (v2f32 DPR:$src),
869 (f32 (load addrmode6:$addr)), imm:$lane),
870 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
871 def : Pat<(vector_insert (v4f32 QPR:$src),
872 (f32 (load addrmode6:$addr)), imm:$lane),
873 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
875 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
877 // ...with address register writeback:
878 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
879 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
880 (ins addrmode6:$Rn, am6offset:$Rm,
881 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
882 "\\{$Vd[$lane]\\}, $Rn$Rm",
883 "$src = $Vd, $Rn.addr = $wb", []> {
884 let DecoderMethod = "DecodeVLD1LN";
887 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
888 let Inst{7-5} = lane{2-0};
890 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
891 let Inst{7-6} = lane{1-0};
894 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
895 let Inst{7} = lane{0};
900 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
901 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
902 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
904 // VLD2LN : Vector Load (single 2-element structure to one lane)
905 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
906 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
907 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
908 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
909 "$src1 = $Vd, $src2 = $dst2", []> {
912 let DecoderMethod = "DecodeVLD2LN";
915 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
916 let Inst{7-5} = lane{2-0};
918 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
919 let Inst{7-6} = lane{1-0};
921 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
922 let Inst{7} = lane{0};
925 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
926 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
927 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
929 // ...with double-spaced registers:
930 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
931 let Inst{7-6} = lane{1-0};
933 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
934 let Inst{7} = lane{0};
937 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
938 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
940 // ...with address register writeback:
941 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
942 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
943 (ins addrmode6:$Rn, am6offset:$Rm,
944 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
945 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
946 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
948 let DecoderMethod = "DecodeVLD2LN";
951 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
952 let Inst{7-5} = lane{2-0};
954 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
955 let Inst{7-6} = lane{1-0};
957 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
958 let Inst{7} = lane{0};
961 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
962 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
963 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
965 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
966 let Inst{7-6} = lane{1-0};
968 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
969 let Inst{7} = lane{0};
972 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
973 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
975 // VLD3LN : Vector Load (single 3-element structure to one lane)
976 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
977 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
978 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
979 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
980 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
981 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
983 let DecoderMethod = "DecodeVLD3LN";
986 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
987 let Inst{7-5} = lane{2-0};
989 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
990 let Inst{7-6} = lane{1-0};
992 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
993 let Inst{7} = lane{0};
996 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
997 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
998 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1000 // ...with double-spaced registers:
1001 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
1002 let Inst{7-6} = lane{1-0};
1004 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
1005 let Inst{7} = lane{0};
1008 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1009 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1011 // ...with address register writeback:
1012 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1013 : NLdStLn<1, 0b10, op11_8, op7_4,
1014 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1015 (ins addrmode6:$Rn, am6offset:$Rm,
1016 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1017 IIC_VLD3lnu, "vld3", Dt,
1018 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1019 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1021 let DecoderMethod = "DecodeVLD3LN";
1024 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
1025 let Inst{7-5} = lane{2-0};
1027 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
1028 let Inst{7-6} = lane{1-0};
1030 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
1031 let Inst{7} = lane{0};
1034 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1035 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1036 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1038 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
1039 let Inst{7-6} = lane{1-0};
1041 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
1042 let Inst{7} = lane{0};
1045 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1046 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1048 // VLD4LN : Vector Load (single 4-element structure to one lane)
1049 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1050 : NLdStLn<1, 0b10, op11_8, op7_4,
1051 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1052 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1053 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1054 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1055 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1057 let Inst{4} = Rn{4};
1058 let DecoderMethod = "DecodeVLD4LN";
1061 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1062 let Inst{7-5} = lane{2-0};
1064 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1065 let Inst{7-6} = lane{1-0};
1067 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1068 let Inst{7} = lane{0};
1069 let Inst{5} = Rn{5};
1072 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1073 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1074 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1076 // ...with double-spaced registers:
1077 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1078 let Inst{7-6} = lane{1-0};
1080 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1081 let Inst{7} = lane{0};
1082 let Inst{5} = Rn{5};
1085 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1086 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1088 // ...with address register writeback:
1089 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1090 : NLdStLn<1, 0b10, op11_8, op7_4,
1091 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1092 (ins addrmode6:$Rn, am6offset:$Rm,
1093 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1094 IIC_VLD4lnu, "vld4", Dt,
1095 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1096 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1098 let Inst{4} = Rn{4};
1099 let DecoderMethod = "DecodeVLD4LN" ;
1102 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1103 let Inst{7-5} = lane{2-0};
1105 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1106 let Inst{7-6} = lane{1-0};
1108 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1109 let Inst{7} = lane{0};
1110 let Inst{5} = Rn{5};
1113 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1114 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1115 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1117 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1118 let Inst{7-6} = lane{1-0};
1120 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
1121 let Inst{7} = lane{0};
1122 let Inst{5} = Rn{5};
1125 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1126 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1128 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1130 // VLD1DUP : Vector Load (single element to all lanes)
1131 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1132 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1133 (ins addrmode6dup:$Rn),
1134 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1135 [(set VecListOneDAllLanes:$Vd,
1136 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1138 let Inst{4} = Rn{4};
1139 let DecoderMethod = "DecodeVLD1DupInstruction";
1141 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
1142 let Pattern = [(set QPR:$dst,
1143 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
1146 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
1147 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
1148 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
1150 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
1151 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
1152 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
1154 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1155 (VLD1DUPd32 addrmode6:$addr)>;
1156 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1157 (VLD1DUPq32Pseudo addrmode6:$addr)>;
1159 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1161 class VLD1QDUP<bits<4> op7_4, string Dt>
1162 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListTwoDAllLanes:$Vd),
1163 (ins addrmode6dup:$Rn), IIC_VLD1dup,
1164 "vld1", Dt, "$Vd, $Rn", "", []> {
1166 let Inst{4} = Rn{4};
1167 let DecoderMethod = "DecodeVLD1DupInstruction";
1170 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
1171 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
1172 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
1174 // ...with address register writeback:
1175 multiclass VLD1DUPWB<bits<4> op7_4, string Dt> {
1176 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1177 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1178 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1179 "vld1", Dt, "$Vd, $Rn!",
1180 "$Rn.addr = $wb", []> {
1181 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1182 let Inst{4} = Rn{4};
1183 let DecoderMethod = "DecodeVLD1DupInstruction";
1184 let AsmMatchConverter = "cvtVLDwbFixed";
1186 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1187 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1188 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1189 "vld1", Dt, "$Vd, $Rn, $Rm",
1190 "$Rn.addr = $wb", []> {
1191 let Inst{4} = Rn{4};
1192 let DecoderMethod = "DecodeVLD1DupInstruction";
1193 let AsmMatchConverter = "cvtVLDwbRegister";
1196 multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
1197 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1198 (outs VecListTwoDAllLanes:$Vd, GPR:$wb),
1199 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1200 "vld1", Dt, "$Vd, $Rn!",
1201 "$Rn.addr = $wb", []> {
1202 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1203 let Inst{4} = Rn{4};
1204 let DecoderMethod = "DecodeVLD1DupInstruction";
1205 let AsmMatchConverter = "cvtVLDwbFixed";
1207 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1208 (outs VecListTwoDAllLanes:$Vd, GPR:$wb),
1209 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1210 "vld1", Dt, "$Vd, $Rn, $Rm",
1211 "$Rn.addr = $wb", []> {
1212 let Inst{4} = Rn{4};
1213 let DecoderMethod = "DecodeVLD1DupInstruction";
1214 let AsmMatchConverter = "cvtVLDwbRegister";
1218 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8">;
1219 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16">;
1220 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32">;
1222 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">;
1223 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">;
1224 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">;
1226 def VLD1DUPq8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1dupu>;
1227 def VLD1DUPq16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1dupu>;
1228 def VLD1DUPq32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1dupu>;
1229 def VLD1DUPq8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1dupu>;
1230 def VLD1DUPq16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1dupu>;
1231 def VLD1DUPq32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1dupu>;
1233 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1234 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy>
1235 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1236 (ins addrmode6dup:$Rn), IIC_VLD2dup,
1237 "vld2", Dt, "$Vd, $Rn", "", []> {
1239 let Inst{4} = Rn{4};
1240 let DecoderMethod = "DecodeVLD2DupInstruction";
1243 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListTwoDAllLanes>;
1244 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListTwoDAllLanes>;
1245 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListTwoDAllLanes>;
1247 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
1248 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
1249 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
1251 // ...with double-spaced registers (not used for codegen):
1252 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListTwoQAllLanes>;
1253 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListTwoQAllLanes>;
1254 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListTwoQAllLanes>;
1256 // ...with address register writeback:
1257 multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy> {
1258 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
1259 (outs VdTy:$Vd, GPR:$wb),
1260 (ins addrmode6dup:$Rn), IIC_VLD2dupu,
1261 "vld2", Dt, "$Vd, $Rn!",
1262 "$Rn.addr = $wb", []> {
1263 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1264 let Inst{4} = Rn{4};
1265 let DecoderMethod = "DecodeVLD2DupInstruction";
1266 let AsmMatchConverter = "cvtVLDwbFixed";
1268 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
1269 (outs VdTy:$Vd, GPR:$wb),
1270 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1271 "vld2", Dt, "$Vd, $Rn, $Rm",
1272 "$Rn.addr = $wb", []> {
1273 let Inst{4} = Rn{4};
1274 let DecoderMethod = "DecodeVLD2DupInstruction";
1275 let AsmMatchConverter = "cvtVLDwbRegister";
1279 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListTwoDAllLanes>;
1280 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListTwoDAllLanes>;
1281 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListTwoDAllLanes>;
1283 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListTwoQAllLanes>;
1284 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListTwoQAllLanes>;
1285 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListTwoQAllLanes>;
1287 def VLD2DUPd8PseudoWB_fixed : VLDQWBfixedPseudo <IIC_VLD2dupu>;
1288 def VLD2DUPd8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2dupu>;
1289 def VLD2DUPd16PseudoWB_fixed : VLDQWBfixedPseudo <IIC_VLD2dupu>;
1290 def VLD2DUPd16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2dupu>;
1291 def VLD2DUPd32PseudoWB_fixed : VLDQWBfixedPseudo <IIC_VLD2dupu>;
1292 def VLD2DUPd32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2dupu>;
1294 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1295 class VLD3DUP<bits<4> op7_4, string Dt>
1296 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1297 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1298 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1301 let DecoderMethod = "DecodeVLD3DupInstruction";
1304 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1305 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1306 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1308 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1309 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1310 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1312 // ...with double-spaced registers (not used for codegen):
1313 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
1314 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
1315 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
1317 // ...with address register writeback:
1318 class VLD3DUPWB<bits<4> op7_4, string Dt>
1319 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1320 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1321 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1322 "$Rn.addr = $wb", []> {
1324 let DecoderMethod = "DecodeVLD3DupInstruction";
1327 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1328 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1329 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1331 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1332 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1333 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1335 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1336 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1337 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1339 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1340 class VLD4DUP<bits<4> op7_4, string Dt>
1341 : NLdSt<1, 0b10, 0b1111, op7_4,
1342 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1343 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1344 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1346 let Inst{4} = Rn{4};
1347 let DecoderMethod = "DecodeVLD4DupInstruction";
1350 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1351 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1352 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1354 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1355 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1356 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1358 // ...with double-spaced registers (not used for codegen):
1359 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
1360 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
1361 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1363 // ...with address register writeback:
1364 class VLD4DUPWB<bits<4> op7_4, string Dt>
1365 : NLdSt<1, 0b10, 0b1111, op7_4,
1366 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1367 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1368 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1369 "$Rn.addr = $wb", []> {
1370 let Inst{4} = Rn{4};
1371 let DecoderMethod = "DecodeVLD4DupInstruction";
1374 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1375 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1376 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1378 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1379 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1380 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1382 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1383 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1384 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1386 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1388 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1390 // Classes for VST* pseudo-instructions with multi-register operands.
1391 // These are expanded to real instructions after register allocation.
1392 class VSTQPseudo<InstrItinClass itin>
1393 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1394 class VSTQWBPseudo<InstrItinClass itin>
1395 : PseudoNLdSt<(outs GPR:$wb),
1396 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1397 "$addr.addr = $wb">;
1398 class VSTQWBfixedPseudo<InstrItinClass itin>
1399 : PseudoNLdSt<(outs GPR:$wb),
1400 (ins addrmode6:$addr, QPR:$src), itin,
1401 "$addr.addr = $wb">;
1402 class VSTQWBregisterPseudo<InstrItinClass itin>
1403 : PseudoNLdSt<(outs GPR:$wb),
1404 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1405 "$addr.addr = $wb">;
1406 class VSTQQPseudo<InstrItinClass itin>
1407 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1408 class VSTQQWBPseudo<InstrItinClass itin>
1409 : PseudoNLdSt<(outs GPR:$wb),
1410 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1411 "$addr.addr = $wb">;
1412 class VSTQQWBfixedPseudo<InstrItinClass itin>
1413 : PseudoNLdSt<(outs GPR:$wb),
1414 (ins addrmode6:$addr, QQPR:$src), itin,
1415 "$addr.addr = $wb">;
1416 class VSTQQWBregisterPseudo<InstrItinClass itin>
1417 : PseudoNLdSt<(outs GPR:$wb),
1418 (ins addrmode6:$addr, rGPR:$offset, QQPR:$src), itin,
1419 "$addr.addr = $wb">;
1421 class VSTQQQQPseudo<InstrItinClass itin>
1422 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1423 class VSTQQQQWBPseudo<InstrItinClass itin>
1424 : PseudoNLdSt<(outs GPR:$wb),
1425 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1426 "$addr.addr = $wb">;
1428 // VST1 : Vector Store (multiple single elements)
1429 class VST1D<bits<4> op7_4, string Dt>
1430 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
1431 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1433 let Inst{4} = Rn{4};
1434 let DecoderMethod = "DecodeVSTInstruction";
1436 class VST1Q<bits<4> op7_4, string Dt>
1437 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListTwoD:$Vd),
1438 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1440 let Inst{5-4} = Rn{5-4};
1441 let DecoderMethod = "DecodeVSTInstruction";
1444 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1445 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1446 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1447 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1449 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1450 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1451 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1452 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1454 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1455 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1456 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1457 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1459 // ...with address register writeback:
1460 multiclass VST1DWB<bits<4> op7_4, string Dt> {
1461 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1462 (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1463 "vst1", Dt, "$Vd, $Rn!",
1464 "$Rn.addr = $wb", []> {
1465 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1466 let Inst{4} = Rn{4};
1467 let DecoderMethod = "DecodeVSTInstruction";
1468 let AsmMatchConverter = "cvtVSTwbFixed";
1470 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1471 (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1473 "vst1", Dt, "$Vd, $Rn, $Rm",
1474 "$Rn.addr = $wb", []> {
1475 let Inst{4} = Rn{4};
1476 let DecoderMethod = "DecodeVSTInstruction";
1477 let AsmMatchConverter = "cvtVSTwbRegister";
1480 multiclass VST1QWB<bits<4> op7_4, string Dt> {
1481 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1482 (ins addrmode6:$Rn, VecListTwoD:$Vd), IIC_VLD1x2u,
1483 "vst1", Dt, "$Vd, $Rn!",
1484 "$Rn.addr = $wb", []> {
1485 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1486 let Inst{5-4} = Rn{5-4};
1487 let DecoderMethod = "DecodeVSTInstruction";
1488 let AsmMatchConverter = "cvtVSTwbFixed";
1490 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1491 (ins addrmode6:$Rn, rGPR:$Rm, VecListTwoD:$Vd),
1493 "vst1", Dt, "$Vd, $Rn, $Rm",
1494 "$Rn.addr = $wb", []> {
1495 let Inst{5-4} = Rn{5-4};
1496 let DecoderMethod = "DecodeVSTInstruction";
1497 let AsmMatchConverter = "cvtVSTwbRegister";
1501 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;
1502 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;
1503 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;
1504 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;
1506 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;
1507 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
1508 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
1509 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
1511 def VST1q8PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1512 def VST1q16PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1513 def VST1q32PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1514 def VST1q64PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1515 def VST1q8PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1516 def VST1q16PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1517 def VST1q32PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1518 def VST1q64PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1520 // ...with 3 registers
1521 class VST1D3<bits<4> op7_4, string Dt>
1522 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1523 (ins addrmode6:$Rn, VecListThreeD:$Vd),
1524 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
1526 let Inst{4} = Rn{4};
1527 let DecoderMethod = "DecodeVSTInstruction";
1529 multiclass VST1D3WB<bits<4> op7_4, string Dt> {
1530 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1531 (ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1532 "vst1", Dt, "$Vd, $Rn!",
1533 "$Rn.addr = $wb", []> {
1534 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1535 let Inst{5-4} = Rn{5-4};
1536 let DecoderMethod = "DecodeVSTInstruction";
1537 let AsmMatchConverter = "cvtVSTwbFixed";
1539 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1540 (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1542 "vst1", Dt, "$Vd, $Rn, $Rm",
1543 "$Rn.addr = $wb", []> {
1544 let Inst{5-4} = Rn{5-4};
1545 let DecoderMethod = "DecodeVSTInstruction";
1546 let AsmMatchConverter = "cvtVSTwbRegister";
1550 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1551 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1552 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1553 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1555 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">;
1556 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">;
1557 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">;
1558 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">;
1560 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1561 def VST1d64TPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x3u>;
1562 def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
1564 // ...with 4 registers
1565 class VST1D4<bits<4> op7_4, string Dt>
1566 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1567 (ins addrmode6:$Rn, VecListFourD:$Vd),
1568 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1571 let Inst{5-4} = Rn{5-4};
1572 let DecoderMethod = "DecodeVSTInstruction";
1574 multiclass VST1D4WB<bits<4> op7_4, string Dt> {
1575 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1576 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1577 "vst1", Dt, "$Vd, $Rn!",
1578 "$Rn.addr = $wb", []> {
1579 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1580 let Inst{5-4} = Rn{5-4};
1581 let DecoderMethod = "DecodeVSTInstruction";
1582 let AsmMatchConverter = "cvtVSTwbFixed";
1584 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1585 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1587 "vst1", Dt, "$Vd, $Rn, $Rm",
1588 "$Rn.addr = $wb", []> {
1589 let Inst{5-4} = Rn{5-4};
1590 let DecoderMethod = "DecodeVSTInstruction";
1591 let AsmMatchConverter = "cvtVSTwbRegister";
1595 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1596 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1597 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1598 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1600 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">;
1601 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">;
1602 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">;
1603 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">;
1605 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1606 def VST1d64QPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x4u>;
1607 def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>;
1609 // VST2 : Vector Store (multiple 2-element structures)
1610 class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1611 InstrItinClass itin>
1612 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, VdTy:$Vd),
1613 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1615 let Inst{5-4} = Rn{5-4};
1616 let DecoderMethod = "DecodeVSTInstruction";
1619 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VST2>;
1620 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VST2>;
1621 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VST2>;
1623 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>;
1624 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>;
1625 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>;
1627 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1628 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1629 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1631 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1632 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1633 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1635 // ...with address register writeback:
1636 multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
1637 RegisterOperand VdTy> {
1638 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1639 (ins addrmode6:$Rn, VdTy:$Vd), IIC_VLD1u,
1640 "vst2", Dt, "$Vd, $Rn!",
1641 "$Rn.addr = $wb", []> {
1642 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1643 let Inst{5-4} = Rn{5-4};
1644 let DecoderMethod = "DecodeVSTInstruction";
1645 let AsmMatchConverter = "cvtVSTwbFixed";
1647 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1648 (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1649 "vst2", Dt, "$Vd, $Rn, $Rm",
1650 "$Rn.addr = $wb", []> {
1651 let Inst{5-4} = Rn{5-4};
1652 let DecoderMethod = "DecodeVSTInstruction";
1653 let AsmMatchConverter = "cvtVSTwbRegister";
1656 multiclass VST2QWB<bits<4> op7_4, string Dt> {
1657 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1658 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1659 "vst2", Dt, "$Vd, $Rn!",
1660 "$Rn.addr = $wb", []> {
1661 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1662 let Inst{5-4} = Rn{5-4};
1663 let DecoderMethod = "DecodeVSTInstruction";
1664 let AsmMatchConverter = "cvtVSTwbFixed";
1666 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1667 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1669 "vst2", Dt, "$Vd, $Rn, $Rm",
1670 "$Rn.addr = $wb", []> {
1671 let Inst{5-4} = Rn{5-4};
1672 let DecoderMethod = "DecodeVSTInstruction";
1673 let AsmMatchConverter = "cvtVSTwbRegister";
1677 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListTwoD>;
1678 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListTwoD>;
1679 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListTwoD>;
1681 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">;
1682 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">;
1683 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">;
1685 def VST2d8PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST2u>;
1686 def VST2d16PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST2u>;
1687 def VST2d32PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST2u>;
1688 def VST2d8PseudoWB_register : VSTQWBregisterPseudo<IIC_VST2u>;
1689 def VST2d16PseudoWB_register : VSTQWBregisterPseudo<IIC_VST2u>;
1690 def VST2d32PseudoWB_register : VSTQWBregisterPseudo<IIC_VST2u>;
1692 def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1693 def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1694 def VST2q32PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1695 def VST2q8PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1696 def VST2q16PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1697 def VST2q32PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1699 // ...with double-spaced registers
1700 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VST2>;
1701 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VST2>;
1702 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VST2>;
1703 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListTwoQ>;
1704 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListTwoQ>;
1705 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListTwoQ>;
1707 // VST3 : Vector Store (multiple 3-element structures)
1708 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1709 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1710 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1711 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1713 let Inst{4} = Rn{4};
1714 let DecoderMethod = "DecodeVSTInstruction";
1717 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1718 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1719 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1721 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1722 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1723 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1725 // ...with address register writeback:
1726 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1727 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1728 (ins addrmode6:$Rn, am6offset:$Rm,
1729 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1730 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1731 "$Rn.addr = $wb", []> {
1732 let Inst{4} = Rn{4};
1733 let DecoderMethod = "DecodeVSTInstruction";
1736 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1737 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1738 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1740 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1741 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1742 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1744 // ...with double-spaced registers:
1745 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1746 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1747 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1748 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1749 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1750 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1752 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1753 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1754 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1756 // ...alternate versions to be allocated odd register numbers:
1757 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1758 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1759 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1761 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1762 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1763 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1765 // VST4 : Vector Store (multiple 4-element structures)
1766 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1767 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1768 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1769 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1772 let Inst{5-4} = Rn{5-4};
1773 let DecoderMethod = "DecodeVSTInstruction";
1776 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1777 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1778 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1780 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1781 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1782 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1784 // ...with address register writeback:
1785 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1786 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1787 (ins addrmode6:$Rn, am6offset:$Rm,
1788 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1789 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1790 "$Rn.addr = $wb", []> {
1791 let Inst{5-4} = Rn{5-4};
1792 let DecoderMethod = "DecodeVSTInstruction";
1795 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1796 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1797 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1799 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1800 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1801 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1803 // ...with double-spaced registers:
1804 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1805 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1806 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1807 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1808 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1809 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1811 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1812 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1813 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1815 // ...alternate versions to be allocated odd register numbers:
1816 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1817 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1818 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1820 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1821 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1822 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1824 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1826 // Classes for VST*LN pseudo-instructions with multi-register operands.
1827 // These are expanded to real instructions after register allocation.
1828 class VSTQLNPseudo<InstrItinClass itin>
1829 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1831 class VSTQLNWBPseudo<InstrItinClass itin>
1832 : PseudoNLdSt<(outs GPR:$wb),
1833 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1834 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1835 class VSTQQLNPseudo<InstrItinClass itin>
1836 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1838 class VSTQQLNWBPseudo<InstrItinClass itin>
1839 : PseudoNLdSt<(outs GPR:$wb),
1840 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1841 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1842 class VSTQQQQLNPseudo<InstrItinClass itin>
1843 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1845 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1846 : PseudoNLdSt<(outs GPR:$wb),
1847 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1848 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1850 // VST1LN : Vector Store (single element from one lane)
1851 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1852 PatFrag StoreOp, SDNode ExtractOp>
1853 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1854 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1855 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1856 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1858 let DecoderMethod = "DecodeVST1LN";
1860 class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1861 PatFrag StoreOp, SDNode ExtractOp>
1862 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1863 (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane),
1864 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1865 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
1867 let DecoderMethod = "DecodeVST1LN";
1869 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1870 : VSTQLNPseudo<IIC_VST1ln> {
1871 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1875 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1877 let Inst{7-5} = lane{2-0};
1879 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1881 let Inst{7-6} = lane{1-0};
1882 let Inst{4} = Rn{5};
1885 def VST1LNd32 : VST1LN32<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1886 let Inst{7} = lane{0};
1887 let Inst{5-4} = Rn{5-4};
1890 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1891 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1892 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1894 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1895 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1896 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1897 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1899 // ...with address register writeback:
1900 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1901 PatFrag StoreOp, SDNode ExtractOp>
1902 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1903 (ins addrmode6:$Rn, am6offset:$Rm,
1904 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1905 "\\{$Vd[$lane]\\}, $Rn$Rm",
1907 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1908 addrmode6:$Rn, am6offset:$Rm))]> {
1909 let DecoderMethod = "DecodeVST1LN";
1911 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1912 : VSTQLNWBPseudo<IIC_VST1lnu> {
1913 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1914 addrmode6:$addr, am6offset:$offset))];
1917 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
1919 let Inst{7-5} = lane{2-0};
1921 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
1923 let Inst{7-6} = lane{1-0};
1924 let Inst{4} = Rn{5};
1926 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
1928 let Inst{7} = lane{0};
1929 let Inst{5-4} = Rn{5-4};
1932 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
1933 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
1934 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
1936 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1938 // VST2LN : Vector Store (single 2-element structure from one lane)
1939 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1940 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1941 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1942 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1945 let Inst{4} = Rn{4};
1946 let DecoderMethod = "DecodeVST2LN";
1949 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1950 let Inst{7-5} = lane{2-0};
1952 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1953 let Inst{7-6} = lane{1-0};
1955 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1956 let Inst{7} = lane{0};
1959 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1960 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1961 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1963 // ...with double-spaced registers:
1964 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1965 let Inst{7-6} = lane{1-0};
1966 let Inst{4} = Rn{4};
1968 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1969 let Inst{7} = lane{0};
1970 let Inst{4} = Rn{4};
1973 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1974 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1976 // ...with address register writeback:
1977 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1978 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1979 (ins addrmode6:$Rn, am6offset:$Rm,
1980 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1981 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
1982 "$Rn.addr = $wb", []> {
1983 let Inst{4} = Rn{4};
1984 let DecoderMethod = "DecodeVST2LN";
1987 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1988 let Inst{7-5} = lane{2-0};
1990 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1991 let Inst{7-6} = lane{1-0};
1993 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1994 let Inst{7} = lane{0};
1997 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1998 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1999 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2001 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
2002 let Inst{7-6} = lane{1-0};
2004 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
2005 let Inst{7} = lane{0};
2008 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2009 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2011 // VST3LN : Vector Store (single 3-element structure from one lane)
2012 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2013 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2014 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2015 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
2016 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2018 let DecoderMethod = "DecodeVST3LN";
2021 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
2022 let Inst{7-5} = lane{2-0};
2024 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
2025 let Inst{7-6} = lane{1-0};
2027 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
2028 let Inst{7} = lane{0};
2031 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2032 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2033 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2035 // ...with double-spaced registers:
2036 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
2037 let Inst{7-6} = lane{1-0};
2039 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
2040 let Inst{7} = lane{0};
2043 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2044 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2046 // ...with address register writeback:
2047 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2048 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2049 (ins addrmode6:$Rn, am6offset:$Rm,
2050 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2051 IIC_VST3lnu, "vst3", Dt,
2052 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2053 "$Rn.addr = $wb", []> {
2054 let DecoderMethod = "DecodeVST3LN";
2057 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
2058 let Inst{7-5} = lane{2-0};
2060 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
2061 let Inst{7-6} = lane{1-0};
2063 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
2064 let Inst{7} = lane{0};
2067 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2068 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2069 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2071 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
2072 let Inst{7-6} = lane{1-0};
2074 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
2075 let Inst{7} = lane{0};
2078 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2079 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2081 // VST4LN : Vector Store (single 4-element structure from one lane)
2082 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2083 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2084 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2085 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2086 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2089 let Inst{4} = Rn{4};
2090 let DecoderMethod = "DecodeVST4LN";
2093 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
2094 let Inst{7-5} = lane{2-0};
2096 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
2097 let Inst{7-6} = lane{1-0};
2099 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2100 let Inst{7} = lane{0};
2101 let Inst{5} = Rn{5};
2104 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2105 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2106 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2108 // ...with double-spaced registers:
2109 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
2110 let Inst{7-6} = lane{1-0};
2112 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2113 let Inst{7} = lane{0};
2114 let Inst{5} = Rn{5};
2117 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2118 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2120 // ...with address register writeback:
2121 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2122 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2123 (ins addrmode6:$Rn, am6offset:$Rm,
2124 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2125 IIC_VST4lnu, "vst4", Dt,
2126 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2127 "$Rn.addr = $wb", []> {
2128 let Inst{4} = Rn{4};
2129 let DecoderMethod = "DecodeVST4LN";
2132 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
2133 let Inst{7-5} = lane{2-0};
2135 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
2136 let Inst{7-6} = lane{1-0};
2138 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2139 let Inst{7} = lane{0};
2140 let Inst{5} = Rn{5};
2143 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2144 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2145 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2147 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
2148 let Inst{7-6} = lane{1-0};
2150 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
2151 let Inst{7} = lane{0};
2152 let Inst{5} = Rn{5};
2155 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2156 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2158 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2161 //===----------------------------------------------------------------------===//
2162 // NEON pattern fragments
2163 //===----------------------------------------------------------------------===//
2165 // Extract D sub-registers of Q registers.
2166 def DSubReg_i8_reg : SDNodeXForm<imm, [{
2167 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2168 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
2170 def DSubReg_i16_reg : SDNodeXForm<imm, [{
2171 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2172 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
2174 def DSubReg_i32_reg : SDNodeXForm<imm, [{
2175 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2176 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
2178 def DSubReg_f64_reg : SDNodeXForm<imm, [{
2179 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2180 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
2183 // Extract S sub-registers of Q/D registers.
2184 def SSubReg_f32_reg : SDNodeXForm<imm, [{
2185 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
2186 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
2189 // Translate lane numbers from Q registers to D subregs.
2190 def SubReg_i8_lane : SDNodeXForm<imm, [{
2191 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
2193 def SubReg_i16_lane : SDNodeXForm<imm, [{
2194 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
2196 def SubReg_i32_lane : SDNodeXForm<imm, [{
2197 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
2200 //===----------------------------------------------------------------------===//
2201 // Instruction Classes
2202 //===----------------------------------------------------------------------===//
2204 // Basic 2-register operations: double- and quad-register.
2205 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2206 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2207 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2208 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2209 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2210 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2211 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2212 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2213 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2214 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2215 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2216 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2218 // Basic 2-register intrinsics, both double- and quad-register.
2219 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2220 bits<2> op17_16, bits<5> op11_7, bit op4,
2221 InstrItinClass itin, string OpcodeStr, string Dt,
2222 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2223 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2224 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2225 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2226 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2227 bits<2> op17_16, bits<5> op11_7, bit op4,
2228 InstrItinClass itin, string OpcodeStr, string Dt,
2229 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2230 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2231 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2232 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2234 // Narrow 2-register operations.
2235 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2236 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2237 InstrItinClass itin, string OpcodeStr, string Dt,
2238 ValueType TyD, ValueType TyQ, SDNode OpNode>
2239 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2240 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2241 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2243 // Narrow 2-register intrinsics.
2244 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2245 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2246 InstrItinClass itin, string OpcodeStr, string Dt,
2247 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
2248 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2249 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2250 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2252 // Long 2-register operations (currently only used for VMOVL).
2253 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2254 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2255 InstrItinClass itin, string OpcodeStr, string Dt,
2256 ValueType TyQ, ValueType TyD, SDNode OpNode>
2257 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2258 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2259 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2261 // Long 2-register intrinsics.
2262 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2263 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2264 InstrItinClass itin, string OpcodeStr, string Dt,
2265 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2266 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2267 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2268 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2270 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2271 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
2272 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2273 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2274 OpcodeStr, Dt, "$Vd, $Vm",
2275 "$src1 = $Vd, $src2 = $Vm", []>;
2276 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
2277 InstrItinClass itin, string OpcodeStr, string Dt>
2278 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2279 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2280 "$src1 = $Vd, $src2 = $Vm", []>;
2282 // Basic 3-register operations: double- and quad-register.
2283 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2284 InstrItinClass itin, string OpcodeStr, string Dt,
2285 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2286 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2287 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2288 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2289 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2290 let isCommutable = Commutable;
2292 // Same as N3VD but no data type.
2293 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2294 InstrItinClass itin, string OpcodeStr,
2295 ValueType ResTy, ValueType OpTy,
2296 SDNode OpNode, bit Commutable>
2297 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
2298 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2299 OpcodeStr, "$Vd, $Vn, $Vm", "",
2300 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2301 let isCommutable = Commutable;
2304 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2305 InstrItinClass itin, string OpcodeStr, string Dt,
2306 ValueType Ty, SDNode ShOp>
2307 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2308 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2309 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2311 (Ty (ShOp (Ty DPR:$Vn),
2312 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2313 let isCommutable = 0;
2315 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2316 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2317 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2318 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2319 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2321 (Ty (ShOp (Ty DPR:$Vn),
2322 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2323 let isCommutable = 0;
2326 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2327 InstrItinClass itin, string OpcodeStr, string Dt,
2328 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2329 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2330 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2331 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2332 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2333 let isCommutable = Commutable;
2335 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2336 InstrItinClass itin, string OpcodeStr,
2337 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2338 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2339 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2340 OpcodeStr, "$Vd, $Vn, $Vm", "",
2341 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2342 let isCommutable = Commutable;
2344 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2345 InstrItinClass itin, string OpcodeStr, string Dt,
2346 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2347 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2348 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2349 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2350 [(set (ResTy QPR:$Vd),
2351 (ResTy (ShOp (ResTy QPR:$Vn),
2352 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2354 let isCommutable = 0;
2356 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2357 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2358 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2359 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2360 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2361 [(set (ResTy QPR:$Vd),
2362 (ResTy (ShOp (ResTy QPR:$Vn),
2363 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2365 let isCommutable = 0;
2368 // Basic 3-register intrinsics, both double- and quad-register.
2369 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2370 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2371 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2372 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2373 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2374 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2375 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2376 let isCommutable = Commutable;
2378 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2379 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2380 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2381 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2382 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2384 (Ty (IntOp (Ty DPR:$Vn),
2385 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2387 let isCommutable = 0;
2389 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2390 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2391 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2392 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2393 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2395 (Ty (IntOp (Ty DPR:$Vn),
2396 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2397 let isCommutable = 0;
2399 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2400 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2401 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2402 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2403 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2404 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2405 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2406 let isCommutable = 0;
2409 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2410 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2411 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2412 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2413 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2414 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2415 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2416 let isCommutable = Commutable;
2418 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2419 string OpcodeStr, string Dt,
2420 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2421 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2422 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2423 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2424 [(set (ResTy QPR:$Vd),
2425 (ResTy (IntOp (ResTy QPR:$Vn),
2426 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2428 let isCommutable = 0;
2430 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2431 string OpcodeStr, string Dt,
2432 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2433 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2434 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2435 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2436 [(set (ResTy QPR:$Vd),
2437 (ResTy (IntOp (ResTy QPR:$Vn),
2438 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2440 let isCommutable = 0;
2442 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2443 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2444 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2445 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2446 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2447 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2448 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2449 let isCommutable = 0;
2452 // Multiply-Add/Sub operations: double- and quad-register.
2453 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2454 InstrItinClass itin, string OpcodeStr, string Dt,
2455 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2456 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2457 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2458 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2459 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2460 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2462 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2463 string OpcodeStr, string Dt,
2464 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2465 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2467 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2469 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2471 (Ty (ShOp (Ty DPR:$src1),
2473 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2475 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2476 string OpcodeStr, string Dt,
2477 ValueType Ty, SDNode MulOp, SDNode ShOp>
2478 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2480 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2482 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2484 (Ty (ShOp (Ty DPR:$src1),
2486 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2489 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2490 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2491 SDPatternOperator MulOp, SDPatternOperator OpNode>
2492 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2493 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2494 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2495 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2496 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2497 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2498 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2499 SDPatternOperator MulOp, SDPatternOperator ShOp>
2500 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2502 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2504 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2505 [(set (ResTy QPR:$Vd),
2506 (ResTy (ShOp (ResTy QPR:$src1),
2507 (ResTy (MulOp QPR:$Vn,
2508 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2510 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2511 string OpcodeStr, string Dt,
2512 ValueType ResTy, ValueType OpTy,
2513 SDNode MulOp, SDNode ShOp>
2514 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2516 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2518 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2519 [(set (ResTy QPR:$Vd),
2520 (ResTy (ShOp (ResTy QPR:$src1),
2521 (ResTy (MulOp QPR:$Vn,
2522 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2525 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2526 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2527 InstrItinClass itin, string OpcodeStr, string Dt,
2528 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2529 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2530 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2531 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2532 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2533 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2534 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2535 InstrItinClass itin, string OpcodeStr, string Dt,
2536 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2537 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2538 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2539 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2540 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2541 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2543 // Neon 3-argument intrinsics, both double- and quad-register.
2544 // The destination register is also used as the first source operand register.
2545 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2546 InstrItinClass itin, string OpcodeStr, string Dt,
2547 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2548 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2549 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2550 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2551 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2552 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2553 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2554 InstrItinClass itin, string OpcodeStr, string Dt,
2555 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2556 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2557 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2558 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2559 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2560 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2562 // Long Multiply-Add/Sub operations.
2563 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2564 InstrItinClass itin, string OpcodeStr, string Dt,
2565 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2566 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2567 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2568 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2569 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2570 (TyQ (MulOp (TyD DPR:$Vn),
2571 (TyD DPR:$Vm)))))]>;
2572 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2573 InstrItinClass itin, string OpcodeStr, string Dt,
2574 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2575 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2576 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2578 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2580 (OpNode (TyQ QPR:$src1),
2581 (TyQ (MulOp (TyD DPR:$Vn),
2582 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2584 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2585 InstrItinClass itin, string OpcodeStr, string Dt,
2586 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2587 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2588 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2590 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2592 (OpNode (TyQ QPR:$src1),
2593 (TyQ (MulOp (TyD DPR:$Vn),
2594 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2597 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2598 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2599 InstrItinClass itin, string OpcodeStr, string Dt,
2600 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2602 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2603 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2604 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2605 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2606 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2607 (TyD DPR:$Vm)))))))]>;
2609 // Neon Long 3-argument intrinsic. The destination register is
2610 // a quad-register and is also used as the first source operand register.
2611 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2612 InstrItinClass itin, string OpcodeStr, string Dt,
2613 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2614 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2615 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2616 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2618 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2619 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2620 string OpcodeStr, string Dt,
2621 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2622 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2624 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2626 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2627 [(set (ResTy QPR:$Vd),
2628 (ResTy (IntOp (ResTy QPR:$src1),
2630 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2632 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2633 InstrItinClass itin, string OpcodeStr, string Dt,
2634 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2635 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2637 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2639 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2640 [(set (ResTy QPR:$Vd),
2641 (ResTy (IntOp (ResTy QPR:$src1),
2643 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2646 // Narrowing 3-register intrinsics.
2647 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2648 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2649 Intrinsic IntOp, bit Commutable>
2650 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2651 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2652 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2653 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2654 let isCommutable = Commutable;
2657 // Long 3-register operations.
2658 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2659 InstrItinClass itin, string OpcodeStr, string Dt,
2660 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2661 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2662 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2663 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2664 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2665 let isCommutable = Commutable;
2667 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2668 InstrItinClass itin, string OpcodeStr, string Dt,
2669 ValueType TyQ, ValueType TyD, SDNode OpNode>
2670 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2671 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2672 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2674 (TyQ (OpNode (TyD DPR:$Vn),
2675 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2676 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2677 InstrItinClass itin, string OpcodeStr, string Dt,
2678 ValueType TyQ, ValueType TyD, SDNode OpNode>
2679 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2680 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2681 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2683 (TyQ (OpNode (TyD DPR:$Vn),
2684 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2686 // Long 3-register operations with explicitly extended operands.
2687 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2688 InstrItinClass itin, string OpcodeStr, string Dt,
2689 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2691 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2692 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2693 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2694 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2695 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2696 let isCommutable = Commutable;
2699 // Long 3-register intrinsics with explicit extend (VABDL).
2700 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2701 InstrItinClass itin, string OpcodeStr, string Dt,
2702 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2704 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2705 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2706 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2707 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2708 (TyD DPR:$Vm))))))]> {
2709 let isCommutable = Commutable;
2712 // Long 3-register intrinsics.
2713 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2714 InstrItinClass itin, string OpcodeStr, string Dt,
2715 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2716 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2717 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2718 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2719 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2720 let isCommutable = Commutable;
2722 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2723 string OpcodeStr, string Dt,
2724 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2725 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2726 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2727 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2728 [(set (ResTy QPR:$Vd),
2729 (ResTy (IntOp (OpTy DPR:$Vn),
2730 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2732 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2733 InstrItinClass itin, string OpcodeStr, string Dt,
2734 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2735 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2736 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2737 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2738 [(set (ResTy QPR:$Vd),
2739 (ResTy (IntOp (OpTy DPR:$Vn),
2740 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2743 // Wide 3-register operations.
2744 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2745 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2746 SDNode OpNode, SDNode ExtOp, bit Commutable>
2747 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2748 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2749 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2750 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2751 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2752 let isCommutable = Commutable;
2755 // Pairwise long 2-register intrinsics, both double- and quad-register.
2756 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2757 bits<2> op17_16, bits<5> op11_7, bit op4,
2758 string OpcodeStr, string Dt,
2759 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2760 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2761 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2762 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2763 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2764 bits<2> op17_16, bits<5> op11_7, bit op4,
2765 string OpcodeStr, string Dt,
2766 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2767 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2768 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2769 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2771 // Pairwise long 2-register accumulate intrinsics,
2772 // both double- and quad-register.
2773 // The destination register is also used as the first source operand register.
2774 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2775 bits<2> op17_16, bits<5> op11_7, bit op4,
2776 string OpcodeStr, string Dt,
2777 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2778 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2779 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2780 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2781 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2782 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2783 bits<2> op17_16, bits<5> op11_7, bit op4,
2784 string OpcodeStr, string Dt,
2785 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2786 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2787 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2788 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2789 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2791 // Shift by immediate,
2792 // both double- and quad-register.
2793 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2794 Format f, InstrItinClass itin, Operand ImmTy,
2795 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2796 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2797 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2798 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2799 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2800 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2801 Format f, InstrItinClass itin, Operand ImmTy,
2802 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2803 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2804 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2805 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2806 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2808 // Long shift by immediate.
2809 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2810 string OpcodeStr, string Dt,
2811 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2812 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2813 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
2814 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2815 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2816 (i32 imm:$SIMM))))]>;
2818 // Narrow shift by immediate.
2819 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2820 InstrItinClass itin, string OpcodeStr, string Dt,
2821 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2822 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2823 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2824 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2825 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2826 (i32 imm:$SIMM))))]>;
2828 // Shift right by immediate and accumulate,
2829 // both double- and quad-register.
2830 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2831 Operand ImmTy, string OpcodeStr, string Dt,
2832 ValueType Ty, SDNode ShOp>
2833 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2834 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2835 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2836 [(set DPR:$Vd, (Ty (add DPR:$src1,
2837 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2838 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2839 Operand ImmTy, string OpcodeStr, string Dt,
2840 ValueType Ty, SDNode ShOp>
2841 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2842 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2843 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2844 [(set QPR:$Vd, (Ty (add QPR:$src1,
2845 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2847 // Shift by immediate and insert,
2848 // both double- and quad-register.
2849 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2850 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2851 ValueType Ty,SDNode ShOp>
2852 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2853 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2854 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2855 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2856 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2857 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2858 ValueType Ty,SDNode ShOp>
2859 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2860 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2861 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2862 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2864 // Convert, with fractional bits immediate,
2865 // both double- and quad-register.
2866 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2867 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2869 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2870 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2871 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2872 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2873 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2874 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2876 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2877 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2878 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2879 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2881 //===----------------------------------------------------------------------===//
2883 //===----------------------------------------------------------------------===//
2885 // Abbreviations used in multiclass suffixes:
2886 // Q = quarter int (8 bit) elements
2887 // H = half int (16 bit) elements
2888 // S = single int (32 bit) elements
2889 // D = double int (64 bit) elements
2891 // Neon 2-register vector operations and intrinsics.
2893 // Neon 2-register comparisons.
2894 // source operand element sizes of 8, 16 and 32 bits:
2895 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2896 bits<5> op11_7, bit op4, string opc, string Dt,
2897 string asm, SDNode OpNode> {
2898 // 64-bit vector types.
2899 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2900 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2901 opc, !strconcat(Dt, "8"), asm, "",
2902 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2903 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2904 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2905 opc, !strconcat(Dt, "16"), asm, "",
2906 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2907 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2908 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2909 opc, !strconcat(Dt, "32"), asm, "",
2910 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2911 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2912 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2913 opc, "f32", asm, "",
2914 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2915 let Inst{10} = 1; // overwrite F = 1
2918 // 128-bit vector types.
2919 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2920 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2921 opc, !strconcat(Dt, "8"), asm, "",
2922 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2923 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2924 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2925 opc, !strconcat(Dt, "16"), asm, "",
2926 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2927 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2928 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2929 opc, !strconcat(Dt, "32"), asm, "",
2930 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2931 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2932 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2933 opc, "f32", asm, "",
2934 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2935 let Inst{10} = 1; // overwrite F = 1
2940 // Neon 2-register vector intrinsics,
2941 // element sizes of 8, 16 and 32 bits:
2942 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2943 bits<5> op11_7, bit op4,
2944 InstrItinClass itinD, InstrItinClass itinQ,
2945 string OpcodeStr, string Dt, Intrinsic IntOp> {
2946 // 64-bit vector types.
2947 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2948 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2949 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2950 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2951 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2952 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2954 // 128-bit vector types.
2955 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2956 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2957 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2958 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2959 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2960 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2964 // Neon Narrowing 2-register vector operations,
2965 // source operand element sizes of 16, 32 and 64 bits:
2966 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2967 bits<5> op11_7, bit op6, bit op4,
2968 InstrItinClass itin, string OpcodeStr, string Dt,
2970 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2971 itin, OpcodeStr, !strconcat(Dt, "16"),
2972 v8i8, v8i16, OpNode>;
2973 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2974 itin, OpcodeStr, !strconcat(Dt, "32"),
2975 v4i16, v4i32, OpNode>;
2976 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2977 itin, OpcodeStr, !strconcat(Dt, "64"),
2978 v2i32, v2i64, OpNode>;
2981 // Neon Narrowing 2-register vector intrinsics,
2982 // source operand element sizes of 16, 32 and 64 bits:
2983 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2984 bits<5> op11_7, bit op6, bit op4,
2985 InstrItinClass itin, string OpcodeStr, string Dt,
2987 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2988 itin, OpcodeStr, !strconcat(Dt, "16"),
2989 v8i8, v8i16, IntOp>;
2990 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2991 itin, OpcodeStr, !strconcat(Dt, "32"),
2992 v4i16, v4i32, IntOp>;
2993 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2994 itin, OpcodeStr, !strconcat(Dt, "64"),
2995 v2i32, v2i64, IntOp>;
2999 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
3000 // source operand element sizes of 16, 32 and 64 bits:
3001 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
3002 string OpcodeStr, string Dt, SDNode OpNode> {
3003 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3004 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
3005 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3006 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3007 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3008 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3012 // Neon 3-register vector operations.
3014 // First with only element sizes of 8, 16 and 32 bits:
3015 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3016 InstrItinClass itinD16, InstrItinClass itinD32,
3017 InstrItinClass itinQ16, InstrItinClass itinQ32,
3018 string OpcodeStr, string Dt,
3019 SDNode OpNode, bit Commutable = 0> {
3020 // 64-bit vector types.
3021 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
3022 OpcodeStr, !strconcat(Dt, "8"),
3023 v8i8, v8i8, OpNode, Commutable>;
3024 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
3025 OpcodeStr, !strconcat(Dt, "16"),
3026 v4i16, v4i16, OpNode, Commutable>;
3027 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
3028 OpcodeStr, !strconcat(Dt, "32"),
3029 v2i32, v2i32, OpNode, Commutable>;
3031 // 128-bit vector types.
3032 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
3033 OpcodeStr, !strconcat(Dt, "8"),
3034 v16i8, v16i8, OpNode, Commutable>;
3035 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3036 OpcodeStr, !strconcat(Dt, "16"),
3037 v8i16, v8i16, OpNode, Commutable>;
3038 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
3039 OpcodeStr, !strconcat(Dt, "32"),
3040 v4i32, v4i32, OpNode, Commutable>;
3043 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
3044 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
3045 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>;
3046 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3047 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
3048 v4i32, v2i32, ShOp>;
3051 // ....then also with element size 64 bits:
3052 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3053 InstrItinClass itinD, InstrItinClass itinQ,
3054 string OpcodeStr, string Dt,
3055 SDNode OpNode, bit Commutable = 0>
3056 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
3057 OpcodeStr, Dt, OpNode, Commutable> {
3058 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
3059 OpcodeStr, !strconcat(Dt, "64"),
3060 v1i64, v1i64, OpNode, Commutable>;
3061 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
3062 OpcodeStr, !strconcat(Dt, "64"),
3063 v2i64, v2i64, OpNode, Commutable>;
3067 // Neon 3-register vector intrinsics.
3069 // First with only element sizes of 16 and 32 bits:
3070 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3071 InstrItinClass itinD16, InstrItinClass itinD32,
3072 InstrItinClass itinQ16, InstrItinClass itinQ32,
3073 string OpcodeStr, string Dt,
3074 Intrinsic IntOp, bit Commutable = 0> {
3075 // 64-bit vector types.
3076 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
3077 OpcodeStr, !strconcat(Dt, "16"),
3078 v4i16, v4i16, IntOp, Commutable>;
3079 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
3080 OpcodeStr, !strconcat(Dt, "32"),
3081 v2i32, v2i32, IntOp, Commutable>;
3083 // 128-bit vector types.
3084 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3085 OpcodeStr, !strconcat(Dt, "16"),
3086 v8i16, v8i16, IntOp, Commutable>;
3087 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3088 OpcodeStr, !strconcat(Dt, "32"),
3089 v4i32, v4i32, IntOp, Commutable>;
3091 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3092 InstrItinClass itinD16, InstrItinClass itinD32,
3093 InstrItinClass itinQ16, InstrItinClass itinQ32,
3094 string OpcodeStr, string Dt,
3096 // 64-bit vector types.
3097 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3098 OpcodeStr, !strconcat(Dt, "16"),
3099 v4i16, v4i16, IntOp>;
3100 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
3101 OpcodeStr, !strconcat(Dt, "32"),
3102 v2i32, v2i32, IntOp>;
3104 // 128-bit vector types.
3105 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3106 OpcodeStr, !strconcat(Dt, "16"),
3107 v8i16, v8i16, IntOp>;
3108 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3109 OpcodeStr, !strconcat(Dt, "32"),
3110 v4i32, v4i32, IntOp>;
3113 multiclass N3VIntSL_HS<bits<4> op11_8,
3114 InstrItinClass itinD16, InstrItinClass itinD32,
3115 InstrItinClass itinQ16, InstrItinClass itinQ32,
3116 string OpcodeStr, string Dt, Intrinsic IntOp> {
3117 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
3118 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
3119 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
3120 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
3121 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3122 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3123 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
3124 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
3127 // ....then also with element size of 8 bits:
3128 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3129 InstrItinClass itinD16, InstrItinClass itinD32,
3130 InstrItinClass itinQ16, InstrItinClass itinQ32,
3131 string OpcodeStr, string Dt,
3132 Intrinsic IntOp, bit Commutable = 0>
3133 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3134 OpcodeStr, Dt, IntOp, Commutable> {
3135 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
3136 OpcodeStr, !strconcat(Dt, "8"),
3137 v8i8, v8i8, IntOp, Commutable>;
3138 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3139 OpcodeStr, !strconcat(Dt, "8"),
3140 v16i8, v16i8, IntOp, Commutable>;
3142 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3143 InstrItinClass itinD16, InstrItinClass itinD32,
3144 InstrItinClass itinQ16, InstrItinClass itinQ32,
3145 string OpcodeStr, string Dt,
3147 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3148 OpcodeStr, Dt, IntOp> {
3149 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
3150 OpcodeStr, !strconcat(Dt, "8"),
3152 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3153 OpcodeStr, !strconcat(Dt, "8"),
3154 v16i8, v16i8, IntOp>;
3158 // ....then also with element size of 64 bits:
3159 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3160 InstrItinClass itinD16, InstrItinClass itinD32,
3161 InstrItinClass itinQ16, InstrItinClass itinQ32,
3162 string OpcodeStr, string Dt,
3163 Intrinsic IntOp, bit Commutable = 0>
3164 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3165 OpcodeStr, Dt, IntOp, Commutable> {
3166 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3167 OpcodeStr, !strconcat(Dt, "64"),
3168 v1i64, v1i64, IntOp, Commutable>;
3169 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3170 OpcodeStr, !strconcat(Dt, "64"),
3171 v2i64, v2i64, IntOp, Commutable>;
3173 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3174 InstrItinClass itinD16, InstrItinClass itinD32,
3175 InstrItinClass itinQ16, InstrItinClass itinQ32,
3176 string OpcodeStr, string Dt,
3178 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3179 OpcodeStr, Dt, IntOp> {
3180 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3181 OpcodeStr, !strconcat(Dt, "64"),
3182 v1i64, v1i64, IntOp>;
3183 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3184 OpcodeStr, !strconcat(Dt, "64"),
3185 v2i64, v2i64, IntOp>;
3188 // Neon Narrowing 3-register vector intrinsics,
3189 // source operand element sizes of 16, 32 and 64 bits:
3190 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3191 string OpcodeStr, string Dt,
3192 Intrinsic IntOp, bit Commutable = 0> {
3193 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
3194 OpcodeStr, !strconcat(Dt, "16"),
3195 v8i8, v8i16, IntOp, Commutable>;
3196 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3197 OpcodeStr, !strconcat(Dt, "32"),
3198 v4i16, v4i32, IntOp, Commutable>;
3199 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
3200 OpcodeStr, !strconcat(Dt, "64"),
3201 v2i32, v2i64, IntOp, Commutable>;
3205 // Neon Long 3-register vector operations.
3207 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3208 InstrItinClass itin16, InstrItinClass itin32,
3209 string OpcodeStr, string Dt,
3210 SDNode OpNode, bit Commutable = 0> {
3211 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3212 OpcodeStr, !strconcat(Dt, "8"),
3213 v8i16, v8i8, OpNode, Commutable>;
3214 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3215 OpcodeStr, !strconcat(Dt, "16"),
3216 v4i32, v4i16, OpNode, Commutable>;
3217 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
3218 OpcodeStr, !strconcat(Dt, "32"),
3219 v2i64, v2i32, OpNode, Commutable>;
3222 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
3223 InstrItinClass itin, string OpcodeStr, string Dt,
3225 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3226 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3227 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
3228 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3231 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3232 InstrItinClass itin16, InstrItinClass itin32,
3233 string OpcodeStr, string Dt,
3234 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3235 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3236 OpcodeStr, !strconcat(Dt, "8"),
3237 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3238 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3239 OpcodeStr, !strconcat(Dt, "16"),
3240 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3241 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3242 OpcodeStr, !strconcat(Dt, "32"),
3243 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3246 // Neon Long 3-register vector intrinsics.
3248 // First with only element sizes of 16 and 32 bits:
3249 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3250 InstrItinClass itin16, InstrItinClass itin32,
3251 string OpcodeStr, string Dt,
3252 Intrinsic IntOp, bit Commutable = 0> {
3253 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3254 OpcodeStr, !strconcat(Dt, "16"),
3255 v4i32, v4i16, IntOp, Commutable>;
3256 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
3257 OpcodeStr, !strconcat(Dt, "32"),
3258 v2i64, v2i32, IntOp, Commutable>;
3261 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
3262 InstrItinClass itin, string OpcodeStr, string Dt,
3264 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3265 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3266 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3267 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3270 // ....then also with element size of 8 bits:
3271 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3272 InstrItinClass itin16, InstrItinClass itin32,
3273 string OpcodeStr, string Dt,
3274 Intrinsic IntOp, bit Commutable = 0>
3275 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
3276 IntOp, Commutable> {
3277 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3278 OpcodeStr, !strconcat(Dt, "8"),
3279 v8i16, v8i8, IntOp, Commutable>;
3282 // ....with explicit extend (VABDL).
3283 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3284 InstrItinClass itin, string OpcodeStr, string Dt,
3285 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
3286 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3287 OpcodeStr, !strconcat(Dt, "8"),
3288 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3289 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3290 OpcodeStr, !strconcat(Dt, "16"),
3291 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3292 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3293 OpcodeStr, !strconcat(Dt, "32"),
3294 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3298 // Neon Wide 3-register vector intrinsics,
3299 // source operand element sizes of 8, 16 and 32 bits:
3300 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3301 string OpcodeStr, string Dt,
3302 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3303 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3304 OpcodeStr, !strconcat(Dt, "8"),
3305 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3306 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3307 OpcodeStr, !strconcat(Dt, "16"),
3308 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3309 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3310 OpcodeStr, !strconcat(Dt, "32"),
3311 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3315 // Neon Multiply-Op vector operations,
3316 // element sizes of 8, 16 and 32 bits:
3317 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3318 InstrItinClass itinD16, InstrItinClass itinD32,
3319 InstrItinClass itinQ16, InstrItinClass itinQ32,
3320 string OpcodeStr, string Dt, SDNode OpNode> {
3321 // 64-bit vector types.
3322 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3323 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3324 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3325 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3326 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3327 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3329 // 128-bit vector types.
3330 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3331 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3332 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3333 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3334 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3335 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3338 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3339 InstrItinClass itinD16, InstrItinClass itinD32,
3340 InstrItinClass itinQ16, InstrItinClass itinQ32,
3341 string OpcodeStr, string Dt, SDNode ShOp> {
3342 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3343 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3344 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3345 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3346 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3347 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3349 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3350 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3354 // Neon Intrinsic-Op vector operations,
3355 // element sizes of 8, 16 and 32 bits:
3356 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3357 InstrItinClass itinD, InstrItinClass itinQ,
3358 string OpcodeStr, string Dt, Intrinsic IntOp,
3360 // 64-bit vector types.
3361 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3362 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3363 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3364 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3365 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3366 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3368 // 128-bit vector types.
3369 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3370 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3371 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3372 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3373 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3374 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3377 // Neon 3-argument intrinsics,
3378 // element sizes of 8, 16 and 32 bits:
3379 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3380 InstrItinClass itinD, InstrItinClass itinQ,
3381 string OpcodeStr, string Dt, Intrinsic IntOp> {
3382 // 64-bit vector types.
3383 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3384 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3385 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3386 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3387 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3388 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3390 // 128-bit vector types.
3391 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3392 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3393 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3394 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3395 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3396 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3400 // Neon Long Multiply-Op vector operations,
3401 // element sizes of 8, 16 and 32 bits:
3402 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3403 InstrItinClass itin16, InstrItinClass itin32,
3404 string OpcodeStr, string Dt, SDNode MulOp,
3406 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3407 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3408 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3409 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3410 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3411 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3414 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3415 string Dt, SDNode MulOp, SDNode OpNode> {
3416 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3417 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3418 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3419 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3423 // Neon Long 3-argument intrinsics.
3425 // First with only element sizes of 16 and 32 bits:
3426 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3427 InstrItinClass itin16, InstrItinClass itin32,
3428 string OpcodeStr, string Dt, Intrinsic IntOp> {
3429 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3430 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3431 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3432 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3435 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3436 string OpcodeStr, string Dt, Intrinsic IntOp> {
3437 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3438 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3439 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3440 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3443 // ....then also with element size of 8 bits:
3444 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3445 InstrItinClass itin16, InstrItinClass itin32,
3446 string OpcodeStr, string Dt, Intrinsic IntOp>
3447 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3448 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3449 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3452 // ....with explicit extend (VABAL).
3453 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3454 InstrItinClass itin, string OpcodeStr, string Dt,
3455 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
3456 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3457 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3458 IntOp, ExtOp, OpNode>;
3459 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3460 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3461 IntOp, ExtOp, OpNode>;
3462 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3463 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3464 IntOp, ExtOp, OpNode>;
3468 // Neon Pairwise long 2-register intrinsics,
3469 // element sizes of 8, 16 and 32 bits:
3470 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3471 bits<5> op11_7, bit op4,
3472 string OpcodeStr, string Dt, Intrinsic IntOp> {
3473 // 64-bit vector types.
3474 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3475 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3476 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3477 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3478 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3479 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3481 // 128-bit vector types.
3482 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3483 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3484 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3485 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3486 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3487 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3491 // Neon Pairwise long 2-register accumulate intrinsics,
3492 // element sizes of 8, 16 and 32 bits:
3493 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3494 bits<5> op11_7, bit op4,
3495 string OpcodeStr, string Dt, Intrinsic IntOp> {
3496 // 64-bit vector types.
3497 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3498 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3499 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3500 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3501 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3502 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3504 // 128-bit vector types.
3505 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3506 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3507 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3508 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3509 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3510 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3514 // Neon 2-register vector shift by immediate,
3515 // with f of either N2RegVShLFrm or N2RegVShRFrm
3516 // element sizes of 8, 16, 32 and 64 bits:
3517 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3518 InstrItinClass itin, string OpcodeStr, string Dt,
3520 // 64-bit vector types.
3521 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3522 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3523 let Inst{21-19} = 0b001; // imm6 = 001xxx
3525 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3526 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3527 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3529 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3530 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3531 let Inst{21} = 0b1; // imm6 = 1xxxxx
3533 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3534 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3537 // 128-bit vector types.
3538 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3539 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3540 let Inst{21-19} = 0b001; // imm6 = 001xxx
3542 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3543 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3544 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3546 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3547 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3548 let Inst{21} = 0b1; // imm6 = 1xxxxx
3550 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3551 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3554 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3555 InstrItinClass itin, string OpcodeStr, string Dt,
3557 // 64-bit vector types.
3558 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3559 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3560 let Inst{21-19} = 0b001; // imm6 = 001xxx
3562 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3563 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3564 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3566 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3567 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3568 let Inst{21} = 0b1; // imm6 = 1xxxxx
3570 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3571 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3574 // 128-bit vector types.
3575 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3576 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3577 let Inst{21-19} = 0b001; // imm6 = 001xxx
3579 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3580 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3581 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3583 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3584 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3585 let Inst{21} = 0b1; // imm6 = 1xxxxx
3587 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3588 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3592 // Neon Shift-Accumulate vector operations,
3593 // element sizes of 8, 16, 32 and 64 bits:
3594 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3595 string OpcodeStr, string Dt, SDNode ShOp> {
3596 // 64-bit vector types.
3597 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3598 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3599 let Inst{21-19} = 0b001; // imm6 = 001xxx
3601 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3602 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3603 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3605 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3606 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3607 let Inst{21} = 0b1; // imm6 = 1xxxxx
3609 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3610 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3613 // 128-bit vector types.
3614 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3615 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3616 let Inst{21-19} = 0b001; // imm6 = 001xxx
3618 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3619 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3620 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3622 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3623 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3624 let Inst{21} = 0b1; // imm6 = 1xxxxx
3626 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3627 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3631 // Neon Shift-Insert vector operations,
3632 // with f of either N2RegVShLFrm or N2RegVShRFrm
3633 // element sizes of 8, 16, 32 and 64 bits:
3634 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3636 // 64-bit vector types.
3637 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3638 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3639 let Inst{21-19} = 0b001; // imm6 = 001xxx
3641 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3642 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3643 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3645 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3646 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3647 let Inst{21} = 0b1; // imm6 = 1xxxxx
3649 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3650 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3653 // 128-bit vector types.
3654 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3655 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3656 let Inst{21-19} = 0b001; // imm6 = 001xxx
3658 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3659 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3660 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3662 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3663 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3664 let Inst{21} = 0b1; // imm6 = 1xxxxx
3666 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3667 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3670 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3672 // 64-bit vector types.
3673 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3674 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3675 let Inst{21-19} = 0b001; // imm6 = 001xxx
3677 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3678 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3679 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3681 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3682 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3683 let Inst{21} = 0b1; // imm6 = 1xxxxx
3685 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3686 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3689 // 128-bit vector types.
3690 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3691 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3692 let Inst{21-19} = 0b001; // imm6 = 001xxx
3694 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3695 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3696 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3698 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3699 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3700 let Inst{21} = 0b1; // imm6 = 1xxxxx
3702 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3703 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3707 // Neon Shift Long operations,
3708 // element sizes of 8, 16, 32 bits:
3709 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3710 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3711 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3712 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
3713 let Inst{21-19} = 0b001; // imm6 = 001xxx
3715 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3716 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
3717 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3719 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3720 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> {
3721 let Inst{21} = 0b1; // imm6 = 1xxxxx
3725 // Neon Shift Narrow operations,
3726 // element sizes of 16, 32, 64 bits:
3727 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3728 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3730 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3731 OpcodeStr, !strconcat(Dt, "16"),
3732 v8i8, v8i16, shr_imm8, OpNode> {
3733 let Inst{21-19} = 0b001; // imm6 = 001xxx
3735 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3736 OpcodeStr, !strconcat(Dt, "32"),
3737 v4i16, v4i32, shr_imm16, OpNode> {
3738 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3740 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3741 OpcodeStr, !strconcat(Dt, "64"),
3742 v2i32, v2i64, shr_imm32, OpNode> {
3743 let Inst{21} = 0b1; // imm6 = 1xxxxx
3747 //===----------------------------------------------------------------------===//
3748 // Instruction Definitions.
3749 //===----------------------------------------------------------------------===//
3751 // Vector Add Operations.
3753 // VADD : Vector Add (integer and floating-point)
3754 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3756 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3757 v2f32, v2f32, fadd, 1>;
3758 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3759 v4f32, v4f32, fadd, 1>;
3760 // VADDL : Vector Add Long (Q = D + D)
3761 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3762 "vaddl", "s", add, sext, 1>;
3763 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3764 "vaddl", "u", add, zext, 1>;
3765 // VADDW : Vector Add Wide (Q = Q + D)
3766 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3767 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3768 // VHADD : Vector Halving Add
3769 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3770 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3771 "vhadd", "s", int_arm_neon_vhadds, 1>;
3772 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3773 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3774 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3775 // VRHADD : Vector Rounding Halving Add
3776 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3777 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3778 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3779 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3780 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3781 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3782 // VQADD : Vector Saturating Add
3783 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3784 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3785 "vqadd", "s", int_arm_neon_vqadds, 1>;
3786 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3787 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3788 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3789 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3790 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3791 int_arm_neon_vaddhn, 1>;
3792 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3793 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3794 int_arm_neon_vraddhn, 1>;
3796 // Vector Multiply Operations.
3798 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3799 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3800 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3801 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3802 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3803 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3804 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3805 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3806 v2f32, v2f32, fmul, 1>;
3807 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3808 v4f32, v4f32, fmul, 1>;
3809 defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>;
3810 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3811 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3814 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3815 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3816 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3817 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3818 (DSubReg_i16_reg imm:$lane))),
3819 (SubReg_i16_lane imm:$lane)))>;
3820 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3821 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3822 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3823 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3824 (DSubReg_i32_reg imm:$lane))),
3825 (SubReg_i32_lane imm:$lane)))>;
3826 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3827 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3828 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3829 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3830 (DSubReg_i32_reg imm:$lane))),
3831 (SubReg_i32_lane imm:$lane)))>;
3833 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3834 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3835 IIC_VMULi16Q, IIC_VMULi32Q,
3836 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3837 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3838 IIC_VMULi16Q, IIC_VMULi32Q,
3839 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3840 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3841 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3843 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3844 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3845 (DSubReg_i16_reg imm:$lane))),
3846 (SubReg_i16_lane imm:$lane)))>;
3847 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3848 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3850 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3851 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3852 (DSubReg_i32_reg imm:$lane))),
3853 (SubReg_i32_lane imm:$lane)))>;
3855 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3856 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3857 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3858 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3859 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3860 IIC_VMULi16Q, IIC_VMULi32Q,
3861 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3862 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3863 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3865 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3866 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3867 (DSubReg_i16_reg imm:$lane))),
3868 (SubReg_i16_lane imm:$lane)))>;
3869 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3870 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3872 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3873 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3874 (DSubReg_i32_reg imm:$lane))),
3875 (SubReg_i32_lane imm:$lane)))>;
3877 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3878 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3879 "vmull", "s", NEONvmulls, 1>;
3880 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3881 "vmull", "u", NEONvmullu, 1>;
3882 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3883 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3884 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3885 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3887 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3888 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3889 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3890 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3891 "vqdmull", "s", int_arm_neon_vqdmull>;
3893 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3895 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3896 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3897 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3898 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3899 v2f32, fmul_su, fadd_mlx>,
3900 Requires<[HasNEON, UseFPVMLx]>;
3901 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3902 v4f32, fmul_su, fadd_mlx>,
3903 Requires<[HasNEON, UseFPVMLx]>;
3904 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3905 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3906 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3907 v2f32, fmul_su, fadd_mlx>,
3908 Requires<[HasNEON, UseFPVMLx]>;
3909 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3910 v4f32, v2f32, fmul_su, fadd_mlx>,
3911 Requires<[HasNEON, UseFPVMLx]>;
3913 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3914 (mul (v8i16 QPR:$src2),
3915 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3916 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3917 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3918 (DSubReg_i16_reg imm:$lane))),
3919 (SubReg_i16_lane imm:$lane)))>;
3921 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3922 (mul (v4i32 QPR:$src2),
3923 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3924 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3925 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3926 (DSubReg_i32_reg imm:$lane))),
3927 (SubReg_i32_lane imm:$lane)))>;
3929 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3930 (fmul_su (v4f32 QPR:$src2),
3931 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3932 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3934 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3935 (DSubReg_i32_reg imm:$lane))),
3936 (SubReg_i32_lane imm:$lane)))>,
3937 Requires<[HasNEON, UseFPVMLx]>;
3939 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3940 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3941 "vmlal", "s", NEONvmulls, add>;
3942 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3943 "vmlal", "u", NEONvmullu, add>;
3945 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3946 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3948 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3949 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3950 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3951 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3953 // VMLS : Vector Multiply Subtract (integer and floating-point)
3954 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3955 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3956 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3957 v2f32, fmul_su, fsub_mlx>,
3958 Requires<[HasNEON, UseFPVMLx]>;
3959 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3960 v4f32, fmul_su, fsub_mlx>,
3961 Requires<[HasNEON, UseFPVMLx]>;
3962 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3963 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3964 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3965 v2f32, fmul_su, fsub_mlx>,
3966 Requires<[HasNEON, UseFPVMLx]>;
3967 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3968 v4f32, v2f32, fmul_su, fsub_mlx>,
3969 Requires<[HasNEON, UseFPVMLx]>;
3971 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3972 (mul (v8i16 QPR:$src2),
3973 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3974 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3975 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3976 (DSubReg_i16_reg imm:$lane))),
3977 (SubReg_i16_lane imm:$lane)))>;
3979 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3980 (mul (v4i32 QPR:$src2),
3981 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3982 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3983 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3984 (DSubReg_i32_reg imm:$lane))),
3985 (SubReg_i32_lane imm:$lane)))>;
3987 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3988 (fmul_su (v4f32 QPR:$src2),
3989 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3990 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3991 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3992 (DSubReg_i32_reg imm:$lane))),
3993 (SubReg_i32_lane imm:$lane)))>,
3994 Requires<[HasNEON, UseFPVMLx]>;
3996 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3997 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3998 "vmlsl", "s", NEONvmulls, sub>;
3999 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4000 "vmlsl", "u", NEONvmullu, sub>;
4002 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
4003 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
4005 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
4006 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
4007 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
4008 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
4010 // Vector Subtract Operations.
4012 // VSUB : Vector Subtract (integer and floating-point)
4013 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
4014 "vsub", "i", sub, 0>;
4015 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
4016 v2f32, v2f32, fsub, 0>;
4017 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
4018 v4f32, v4f32, fsub, 0>;
4019 // VSUBL : Vector Subtract Long (Q = D - D)
4020 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4021 "vsubl", "s", sub, sext, 0>;
4022 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4023 "vsubl", "u", sub, zext, 0>;
4024 // VSUBW : Vector Subtract Wide (Q = Q - D)
4025 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
4026 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
4027 // VHSUB : Vector Halving Subtract
4028 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
4029 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4030 "vhsub", "s", int_arm_neon_vhsubs, 0>;
4031 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
4032 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4033 "vhsub", "u", int_arm_neon_vhsubu, 0>;
4034 // VQSUB : Vector Saturing Subtract
4035 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
4036 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4037 "vqsub", "s", int_arm_neon_vqsubs, 0>;
4038 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
4039 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4040 "vqsub", "u", int_arm_neon_vqsubu, 0>;
4041 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
4042 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
4043 int_arm_neon_vsubhn, 0>;
4044 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
4045 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
4046 int_arm_neon_vrsubhn, 0>;
4048 // Vector Comparisons.
4050 // VCEQ : Vector Compare Equal
4051 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4052 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
4053 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
4055 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
4058 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
4059 "$Vd, $Vm, #0", NEONvceqz>;
4061 // VCGE : Vector Compare Greater Than or Equal
4062 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4063 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
4064 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4065 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
4066 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
4068 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
4071 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
4072 "$Vd, $Vm, #0", NEONvcgez>;
4073 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
4074 "$Vd, $Vm, #0", NEONvclez>;
4076 // VCGT : Vector Compare Greater Than
4077 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4078 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
4079 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4080 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
4081 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
4083 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
4086 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
4087 "$Vd, $Vm, #0", NEONvcgtz>;
4088 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
4089 "$Vd, $Vm, #0", NEONvcltz>;
4091 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
4092 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
4093 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
4094 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
4095 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
4096 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
4097 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
4098 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
4099 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
4100 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
4101 // VTST : Vector Test Bits
4102 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
4103 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
4105 // Vector Bitwise Operations.
4107 def vnotd : PatFrag<(ops node:$in),
4108 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
4109 def vnotq : PatFrag<(ops node:$in),
4110 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
4113 // VAND : Vector Bitwise AND
4114 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
4115 v2i32, v2i32, and, 1>;
4116 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
4117 v4i32, v4i32, and, 1>;
4119 // VEOR : Vector Bitwise Exclusive OR
4120 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
4121 v2i32, v2i32, xor, 1>;
4122 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
4123 v4i32, v4i32, xor, 1>;
4125 // VORR : Vector Bitwise OR
4126 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
4127 v2i32, v2i32, or, 1>;
4128 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
4129 v4i32, v4i32, or, 1>;
4131 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
4132 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4134 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4136 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4137 let Inst{9} = SIMM{9};
4140 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
4141 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4143 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4145 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4146 let Inst{10-9} = SIMM{10-9};
4149 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
4150 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4152 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4154 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4155 let Inst{9} = SIMM{9};
4158 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
4159 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4161 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4163 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4164 let Inst{10-9} = SIMM{10-9};
4168 // VBIC : Vector Bitwise Bit Clear (AND NOT)
4169 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4170 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4171 "vbic", "$Vd, $Vn, $Vm", "",
4172 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4173 (vnotd DPR:$Vm))))]>;
4174 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4175 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4176 "vbic", "$Vd, $Vn, $Vm", "",
4177 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4178 (vnotq QPR:$Vm))))]>;
4180 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
4181 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4183 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4185 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4186 let Inst{9} = SIMM{9};
4189 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
4190 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4192 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4194 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4195 let Inst{10-9} = SIMM{10-9};
4198 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
4199 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4201 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4203 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4204 let Inst{9} = SIMM{9};
4207 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
4208 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4210 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4212 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4213 let Inst{10-9} = SIMM{10-9};
4216 // VORN : Vector Bitwise OR NOT
4217 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4218 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4219 "vorn", "$Vd, $Vn, $Vm", "",
4220 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4221 (vnotd DPR:$Vm))))]>;
4222 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4223 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4224 "vorn", "$Vd, $Vn, $Vm", "",
4225 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4226 (vnotq QPR:$Vm))))]>;
4228 // VMVN : Vector Bitwise NOT (Immediate)
4230 let isReMaterializable = 1 in {
4232 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4233 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4234 "vmvn", "i16", "$Vd, $SIMM", "",
4235 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4236 let Inst{9} = SIMM{9};
4239 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4240 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4241 "vmvn", "i16", "$Vd, $SIMM", "",
4242 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4243 let Inst{9} = SIMM{9};
4246 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4247 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4248 "vmvn", "i32", "$Vd, $SIMM", "",
4249 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4250 let Inst{11-8} = SIMM{11-8};
4253 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4254 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4255 "vmvn", "i32", "$Vd, $SIMM", "",
4256 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4257 let Inst{11-8} = SIMM{11-8};
4261 // VMVN : Vector Bitwise NOT
4262 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
4263 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4264 "vmvn", "$Vd, $Vm", "",
4265 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
4266 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
4267 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4268 "vmvn", "$Vd, $Vm", "",
4269 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4270 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4271 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4273 // VBSL : Vector Bitwise Select
4274 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4275 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4276 N3RegFrm, IIC_VCNTiD,
4277 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4279 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
4281 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4282 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4283 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
4285 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4286 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4287 N3RegFrm, IIC_VCNTiQ,
4288 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4290 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4292 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4293 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4294 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
4296 // VBIF : Vector Bitwise Insert if False
4297 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4298 // FIXME: This instruction's encoding MAY NOT BE correct.
4299 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4300 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4301 N3RegFrm, IIC_VBINiD,
4302 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4304 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4305 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4306 N3RegFrm, IIC_VBINiQ,
4307 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4310 // VBIT : Vector Bitwise Insert if True
4311 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4312 // FIXME: This instruction's encoding MAY NOT BE correct.
4313 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4314 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4315 N3RegFrm, IIC_VBINiD,
4316 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4318 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4319 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4320 N3RegFrm, IIC_VBINiQ,
4321 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4324 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4325 // for equivalent operations with different register constraints; it just
4328 // Vector Absolute Differences.
4330 // VABD : Vector Absolute Difference
4331 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
4332 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4333 "vabd", "s", int_arm_neon_vabds, 1>;
4334 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
4335 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4336 "vabd", "u", int_arm_neon_vabdu, 1>;
4337 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
4338 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
4339 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
4340 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
4342 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
4343 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4344 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4345 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4346 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
4348 // VABA : Vector Absolute Difference and Accumulate
4349 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4350 "vaba", "s", int_arm_neon_vabds, add>;
4351 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4352 "vaba", "u", int_arm_neon_vabdu, add>;
4354 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
4355 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4356 "vabal", "s", int_arm_neon_vabds, zext, add>;
4357 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4358 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4360 // Vector Maximum and Minimum.
4362 // VMAX : Vector Maximum
4363 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4364 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4365 "vmax", "s", int_arm_neon_vmaxs, 1>;
4366 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4367 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4368 "vmax", "u", int_arm_neon_vmaxu, 1>;
4369 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4371 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4372 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4374 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4376 // VMIN : Vector Minimum
4377 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4378 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4379 "vmin", "s", int_arm_neon_vmins, 1>;
4380 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4381 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4382 "vmin", "u", int_arm_neon_vminu, 1>;
4383 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4385 v2f32, v2f32, int_arm_neon_vmins, 1>;
4386 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4388 v4f32, v4f32, int_arm_neon_vmins, 1>;
4390 // Vector Pairwise Operations.
4392 // VPADD : Vector Pairwise Add
4393 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4395 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4396 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4398 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4399 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4401 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4402 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4403 IIC_VPBIND, "vpadd", "f32",
4404 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4406 // VPADDL : Vector Pairwise Add Long
4407 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4408 int_arm_neon_vpaddls>;
4409 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4410 int_arm_neon_vpaddlu>;
4412 // VPADAL : Vector Pairwise Add and Accumulate Long
4413 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4414 int_arm_neon_vpadals>;
4415 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4416 int_arm_neon_vpadalu>;
4418 // VPMAX : Vector Pairwise Maximum
4419 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4420 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4421 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4422 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4423 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4424 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4425 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4426 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4427 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4428 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4429 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4430 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4431 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4432 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4434 // VPMIN : Vector Pairwise Minimum
4435 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4436 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4437 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4438 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4439 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4440 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4441 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4442 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4443 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4444 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4445 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4446 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4447 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4448 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4450 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4452 // VRECPE : Vector Reciprocal Estimate
4453 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4454 IIC_VUNAD, "vrecpe", "u32",
4455 v2i32, v2i32, int_arm_neon_vrecpe>;
4456 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4457 IIC_VUNAQ, "vrecpe", "u32",
4458 v4i32, v4i32, int_arm_neon_vrecpe>;
4459 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4460 IIC_VUNAD, "vrecpe", "f32",
4461 v2f32, v2f32, int_arm_neon_vrecpe>;
4462 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4463 IIC_VUNAQ, "vrecpe", "f32",
4464 v4f32, v4f32, int_arm_neon_vrecpe>;
4466 // VRECPS : Vector Reciprocal Step
4467 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4468 IIC_VRECSD, "vrecps", "f32",
4469 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4470 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4471 IIC_VRECSQ, "vrecps", "f32",
4472 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4474 // VRSQRTE : Vector Reciprocal Square Root Estimate
4475 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4476 IIC_VUNAD, "vrsqrte", "u32",
4477 v2i32, v2i32, int_arm_neon_vrsqrte>;
4478 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4479 IIC_VUNAQ, "vrsqrte", "u32",
4480 v4i32, v4i32, int_arm_neon_vrsqrte>;
4481 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4482 IIC_VUNAD, "vrsqrte", "f32",
4483 v2f32, v2f32, int_arm_neon_vrsqrte>;
4484 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4485 IIC_VUNAQ, "vrsqrte", "f32",
4486 v4f32, v4f32, int_arm_neon_vrsqrte>;
4488 // VRSQRTS : Vector Reciprocal Square Root Step
4489 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4490 IIC_VRECSD, "vrsqrts", "f32",
4491 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4492 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4493 IIC_VRECSQ, "vrsqrts", "f32",
4494 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4498 // VSHL : Vector Shift
4499 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4500 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4501 "vshl", "s", int_arm_neon_vshifts>;
4502 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4503 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4504 "vshl", "u", int_arm_neon_vshiftu>;
4506 // VSHL : Vector Shift Left (Immediate)
4507 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4509 // VSHR : Vector Shift Right (Immediate)
4510 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
4511 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
4513 // VSHLL : Vector Shift Left Long
4514 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4515 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4517 // VSHLL : Vector Shift Left Long (with maximum shift count)
4518 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4519 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4520 ValueType OpTy, Operand ImmTy, SDNode OpNode>
4521 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4522 ResTy, OpTy, ImmTy, OpNode> {
4523 let Inst{21-16} = op21_16;
4524 let DecoderMethod = "DecodeVSHLMaxInstruction";
4526 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4527 v8i16, v8i8, imm8, NEONvshlli>;
4528 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4529 v4i32, v4i16, imm16, NEONvshlli>;
4530 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4531 v2i64, v2i32, imm32, NEONvshlli>;
4533 // VSHRN : Vector Shift Right and Narrow
4534 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4537 // VRSHL : Vector Rounding Shift
4538 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4539 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4540 "vrshl", "s", int_arm_neon_vrshifts>;
4541 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4542 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4543 "vrshl", "u", int_arm_neon_vrshiftu>;
4544 // VRSHR : Vector Rounding Shift Right
4545 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
4546 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
4548 // VRSHRN : Vector Rounding Shift Right and Narrow
4549 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4552 // VQSHL : Vector Saturating Shift
4553 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4554 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4555 "vqshl", "s", int_arm_neon_vqshifts>;
4556 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4557 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4558 "vqshl", "u", int_arm_neon_vqshiftu>;
4559 // VQSHL : Vector Saturating Shift Left (Immediate)
4560 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4561 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4563 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4564 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4566 // VQSHRN : Vector Saturating Shift Right and Narrow
4567 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4569 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4572 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4573 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4576 // VQRSHL : Vector Saturating Rounding Shift
4577 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4578 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4579 "vqrshl", "s", int_arm_neon_vqrshifts>;
4580 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4581 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4582 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4584 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4585 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4587 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4590 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4591 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4594 // VSRA : Vector Shift Right and Accumulate
4595 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4596 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4597 // VRSRA : Vector Rounding Shift Right and Accumulate
4598 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4599 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4601 // VSLI : Vector Shift Left and Insert
4602 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4604 // VSRI : Vector Shift Right and Insert
4605 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4607 // Vector Absolute and Saturating Absolute.
4609 // VABS : Vector Absolute Value
4610 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4611 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4613 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4614 IIC_VUNAD, "vabs", "f32",
4615 v2f32, v2f32, int_arm_neon_vabs>;
4616 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4617 IIC_VUNAQ, "vabs", "f32",
4618 v4f32, v4f32, int_arm_neon_vabs>;
4620 // VQABS : Vector Saturating Absolute Value
4621 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4622 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4623 int_arm_neon_vqabs>;
4627 def vnegd : PatFrag<(ops node:$in),
4628 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4629 def vnegq : PatFrag<(ops node:$in),
4630 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4632 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4633 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4634 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4635 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4636 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4637 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4638 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4639 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4641 // VNEG : Vector Negate (integer)
4642 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4643 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4644 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4645 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4646 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4647 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4649 // VNEG : Vector Negate (floating-point)
4650 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4651 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4652 "vneg", "f32", "$Vd, $Vm", "",
4653 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4654 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4655 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4656 "vneg", "f32", "$Vd, $Vm", "",
4657 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4659 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4660 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4661 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4662 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4663 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4664 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4666 // VQNEG : Vector Saturating Negate
4667 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4668 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4669 int_arm_neon_vqneg>;
4671 // Vector Bit Counting Operations.
4673 // VCLS : Vector Count Leading Sign Bits
4674 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4675 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4677 // VCLZ : Vector Count Leading Zeros
4678 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4679 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4681 // VCNT : Vector Count One Bits
4682 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4683 IIC_VCNTiD, "vcnt", "8",
4684 v8i8, v8i8, int_arm_neon_vcnt>;
4685 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4686 IIC_VCNTiQ, "vcnt", "8",
4687 v16i8, v16i8, int_arm_neon_vcnt>;
4690 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4691 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4692 "vswp", "$Vd, $Vm", "", []>;
4693 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4694 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4695 "vswp", "$Vd, $Vm", "", []>;
4697 // Vector Move Operations.
4699 // VMOV : Vector Move (Register)
4700 def : InstAlias<"vmov${p} $Vd, $Vm",
4701 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
4702 def : InstAlias<"vmov${p} $Vd, $Vm",
4703 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
4705 // VMOV : Vector Move (Immediate)
4707 let isReMaterializable = 1 in {
4708 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4709 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4710 "vmov", "i8", "$Vd, $SIMM", "",
4711 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4712 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4713 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4714 "vmov", "i8", "$Vd, $SIMM", "",
4715 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4717 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4718 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4719 "vmov", "i16", "$Vd, $SIMM", "",
4720 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4721 let Inst{9} = SIMM{9};
4724 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4725 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4726 "vmov", "i16", "$Vd, $SIMM", "",
4727 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4728 let Inst{9} = SIMM{9};
4731 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4732 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4733 "vmov", "i32", "$Vd, $SIMM", "",
4734 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4735 let Inst{11-8} = SIMM{11-8};
4738 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4739 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4740 "vmov", "i32", "$Vd, $SIMM", "",
4741 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4742 let Inst{11-8} = SIMM{11-8};
4745 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4746 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4747 "vmov", "i64", "$Vd, $SIMM", "",
4748 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4749 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4750 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4751 "vmov", "i64", "$Vd, $SIMM", "",
4752 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4754 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
4755 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
4756 "vmov", "f32", "$Vd, $SIMM", "",
4757 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
4758 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
4759 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
4760 "vmov", "f32", "$Vd, $SIMM", "",
4761 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
4762 } // isReMaterializable
4764 // VMOV : Vector Get Lane (move scalar to ARM core register)
4766 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4767 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4768 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
4769 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4771 let Inst{21} = lane{2};
4772 let Inst{6-5} = lane{1-0};
4774 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4775 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4776 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
4777 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4779 let Inst{21} = lane{1};
4780 let Inst{6} = lane{0};
4782 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4783 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4784 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
4785 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4787 let Inst{21} = lane{2};
4788 let Inst{6-5} = lane{1-0};
4790 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4791 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4792 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
4793 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4795 let Inst{21} = lane{1};
4796 let Inst{6} = lane{0};
4798 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4799 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
4800 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
4801 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4803 let Inst{21} = lane{0};
4805 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4806 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4807 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4808 (DSubReg_i8_reg imm:$lane))),
4809 (SubReg_i8_lane imm:$lane))>;
4810 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4811 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4812 (DSubReg_i16_reg imm:$lane))),
4813 (SubReg_i16_lane imm:$lane))>;
4814 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4815 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4816 (DSubReg_i8_reg imm:$lane))),
4817 (SubReg_i8_lane imm:$lane))>;
4818 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4819 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4820 (DSubReg_i16_reg imm:$lane))),
4821 (SubReg_i16_lane imm:$lane))>;
4822 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4823 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4824 (DSubReg_i32_reg imm:$lane))),
4825 (SubReg_i32_lane imm:$lane))>;
4826 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4827 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4828 (SSubReg_f32_reg imm:$src2))>;
4829 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4830 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4831 (SSubReg_f32_reg imm:$src2))>;
4832 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4833 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4834 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4835 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4838 // VMOV : Vector Set Lane (move ARM core register to scalar)
4840 let Constraints = "$src1 = $V" in {
4841 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4842 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
4843 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
4844 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4845 GPR:$R, imm:$lane))]> {
4846 let Inst{21} = lane{2};
4847 let Inst{6-5} = lane{1-0};
4849 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4850 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
4851 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
4852 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4853 GPR:$R, imm:$lane))]> {
4854 let Inst{21} = lane{1};
4855 let Inst{6} = lane{0};
4857 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4858 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
4859 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
4860 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4861 GPR:$R, imm:$lane))]> {
4862 let Inst{21} = lane{0};
4865 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4866 (v16i8 (INSERT_SUBREG QPR:$src1,
4867 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4868 (DSubReg_i8_reg imm:$lane))),
4869 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4870 (DSubReg_i8_reg imm:$lane)))>;
4871 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4872 (v8i16 (INSERT_SUBREG QPR:$src1,
4873 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4874 (DSubReg_i16_reg imm:$lane))),
4875 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4876 (DSubReg_i16_reg imm:$lane)))>;
4877 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4878 (v4i32 (INSERT_SUBREG QPR:$src1,
4879 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4880 (DSubReg_i32_reg imm:$lane))),
4881 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4882 (DSubReg_i32_reg imm:$lane)))>;
4884 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4885 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4886 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4887 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4888 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4889 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4891 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4892 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4893 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4894 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4896 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4897 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4898 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4899 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4900 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4901 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4903 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4904 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4905 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4906 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4907 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4908 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4910 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4911 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4912 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4914 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4915 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4916 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4918 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4919 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4920 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4923 // VDUP : Vector Duplicate (from ARM core register to all elements)
4925 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4926 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4927 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4928 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4929 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4930 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4931 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4932 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4934 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4935 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4936 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4937 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4938 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4939 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4941 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
4942 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
4944 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4946 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4947 ValueType Ty, Operand IdxTy>
4948 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4949 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
4950 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4952 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4953 ValueType ResTy, ValueType OpTy, Operand IdxTy>
4954 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4955 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
4956 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4957 VectorIndex32:$lane)))]>;
4959 // Inst{19-16} is partially specified depending on the element size.
4961 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
4963 let Inst{19-17} = lane{2-0};
4965 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
4967 let Inst{19-18} = lane{1-0};
4969 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
4971 let Inst{19} = lane{0};
4973 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
4975 let Inst{19-17} = lane{2-0};
4977 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
4979 let Inst{19-18} = lane{1-0};
4981 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
4983 let Inst{19} = lane{0};
4986 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4987 (VDUPLN32d DPR:$Vm, imm:$lane)>;
4989 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4990 (VDUPLN32q DPR:$Vm, imm:$lane)>;
4992 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4993 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4994 (DSubReg_i8_reg imm:$lane))),
4995 (SubReg_i8_lane imm:$lane)))>;
4996 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4997 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4998 (DSubReg_i16_reg imm:$lane))),
4999 (SubReg_i16_lane imm:$lane)))>;
5000 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
5001 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
5002 (DSubReg_i32_reg imm:$lane))),
5003 (SubReg_i32_lane imm:$lane)))>;
5004 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
5005 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
5006 (DSubReg_i32_reg imm:$lane))),
5007 (SubReg_i32_lane imm:$lane)))>;
5009 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
5010 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
5011 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
5012 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
5014 // VMOVN : Vector Narrowing Move
5015 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
5016 "vmovn", "i", trunc>;
5017 // VQMOVN : Vector Saturating Narrowing Move
5018 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
5019 "vqmovn", "s", int_arm_neon_vqmovns>;
5020 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
5021 "vqmovn", "u", int_arm_neon_vqmovnu>;
5022 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
5023 "vqmovun", "s", int_arm_neon_vqmovnsu>;
5024 // VMOVL : Vector Lengthening Move
5025 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
5026 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
5027 def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
5028 def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>;
5029 def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>;
5031 // Vector Conversions.
5033 // VCVT : Vector Convert Between Floating-Point and Integers
5034 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5035 v2i32, v2f32, fp_to_sint>;
5036 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5037 v2i32, v2f32, fp_to_uint>;
5038 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5039 v2f32, v2i32, sint_to_fp>;
5040 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5041 v2f32, v2i32, uint_to_fp>;
5043 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5044 v4i32, v4f32, fp_to_sint>;
5045 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5046 v4i32, v4f32, fp_to_uint>;
5047 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5048 v4f32, v4i32, sint_to_fp>;
5049 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5050 v4f32, v4i32, uint_to_fp>;
5052 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
5053 let DecoderMethod = "DecodeVCVTD" in {
5054 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5055 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
5056 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5057 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
5058 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5059 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
5060 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5061 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
5064 let DecoderMethod = "DecodeVCVTQ" in {
5065 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5066 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
5067 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5068 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
5069 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5070 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
5071 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5072 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
5075 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
5076 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
5077 IIC_VUNAQ, "vcvt", "f16.f32",
5078 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
5079 Requires<[HasNEON, HasFP16]>;
5080 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
5081 IIC_VUNAQ, "vcvt", "f32.f16",
5082 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
5083 Requires<[HasNEON, HasFP16]>;
5087 // VREV64 : Vector Reverse elements within 64-bit doublewords
5089 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5090 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
5091 (ins DPR:$Vm), IIC_VMOVD,
5092 OpcodeStr, Dt, "$Vd, $Vm", "",
5093 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
5094 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5095 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
5096 (ins QPR:$Vm), IIC_VMOVQ,
5097 OpcodeStr, Dt, "$Vd, $Vm", "",
5098 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
5100 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
5101 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
5102 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
5103 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
5105 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
5106 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5107 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
5108 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
5110 // VREV32 : Vector Reverse elements within 32-bit words
5112 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5113 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
5114 (ins DPR:$Vm), IIC_VMOVD,
5115 OpcodeStr, Dt, "$Vd, $Vm", "",
5116 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
5117 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5118 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
5119 (ins QPR:$Vm), IIC_VMOVQ,
5120 OpcodeStr, Dt, "$Vd, $Vm", "",
5121 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
5123 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
5124 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
5126 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
5127 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
5129 // VREV16 : Vector Reverse elements within 16-bit halfwords
5131 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5132 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
5133 (ins DPR:$Vm), IIC_VMOVD,
5134 OpcodeStr, Dt, "$Vd, $Vm", "",
5135 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
5136 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5137 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
5138 (ins QPR:$Vm), IIC_VMOVQ,
5139 OpcodeStr, Dt, "$Vd, $Vm", "",
5140 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
5142 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
5143 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
5145 // Other Vector Shuffles.
5147 // Aligned extractions: really just dropping registers
5149 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
5150 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
5151 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
5153 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
5155 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
5157 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
5159 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
5161 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
5164 // VEXT : Vector Extract
5166 class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5167 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
5168 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
5169 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5170 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
5171 (Ty DPR:$Vm), imm:$index)))]> {
5173 let Inst{11-8} = index{3-0};
5176 class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5177 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
5178 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
5179 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5180 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
5181 (Ty QPR:$Vm), imm:$index)))]> {
5183 let Inst{11-8} = index{3-0};
5186 def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> {
5187 let Inst{11-8} = index{3-0};
5189 def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> {
5190 let Inst{11-9} = index{2-0};
5193 def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> {
5194 let Inst{11-10} = index{1-0};
5195 let Inst{9-8} = 0b00;
5197 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
5200 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
5202 def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> {
5203 let Inst{11-8} = index{3-0};
5205 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
5206 let Inst{11-9} = index{2-0};
5209 def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
5210 let Inst{11-10} = index{1-0};
5211 let Inst{9-8} = 0b00;
5213 def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> {
5214 let Inst{11} = index{0};
5215 let Inst{10-8} = 0b000;
5217 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
5220 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
5222 // VTRN : Vector Transpose
5224 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
5225 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
5226 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
5228 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
5229 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
5230 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
5232 // VUZP : Vector Unzip (Deinterleave)
5234 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
5235 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
5236 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
5238 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
5239 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
5240 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
5242 // VZIP : Vector Zip (Interleave)
5244 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
5245 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
5246 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
5248 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
5249 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
5250 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
5252 // Vector Table Lookup and Table Extension.
5254 // VTBL : Vector Table Lookup
5255 let DecoderMethod = "DecodeTBLInstruction" in {
5257 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
5258 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
5259 "vtbl", "8", "$Vd, $Vn, $Vm", "",
5260 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
5261 let hasExtraSrcRegAllocReq = 1 in {
5263 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
5264 (ins VecListTwoD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
5265 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5267 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
5268 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
5269 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5271 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
5272 (ins VecListFourD:$Vn, DPR:$Vm),
5274 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5275 } // hasExtraSrcRegAllocReq = 1
5278 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
5280 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
5282 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
5284 // VTBX : Vector Table Extension
5286 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
5287 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
5288 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
5289 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
5290 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
5291 let hasExtraSrcRegAllocReq = 1 in {
5293 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
5294 (ins DPR:$orig, VecListTwoD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
5295 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
5297 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
5298 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
5299 NVTBLFrm, IIC_VTBX3,
5300 "vtbx", "8", "$Vd, $Vn, $Vm",
5303 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
5304 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
5305 "vtbx", "8", "$Vd, $Vn, $Vm",
5307 } // hasExtraSrcRegAllocReq = 1
5310 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
5311 IIC_VTBX2, "$orig = $dst", []>;
5313 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5314 IIC_VTBX3, "$orig = $dst", []>;
5316 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5317 IIC_VTBX4, "$orig = $dst", []>;
5318 } // DecoderMethod = "DecodeTBLInstruction"
5320 //===----------------------------------------------------------------------===//
5321 // NEON instructions for single-precision FP math
5322 //===----------------------------------------------------------------------===//
5324 class N2VSPat<SDNode OpNode, NeonI Inst>
5325 : NEONFPPat<(f32 (OpNode SPR:$a)),
5327 (v2f32 (COPY_TO_REGCLASS (Inst
5329 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5330 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
5332 class N3VSPat<SDNode OpNode, NeonI Inst>
5333 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
5335 (v2f32 (COPY_TO_REGCLASS (Inst
5337 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5340 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5341 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5343 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
5344 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
5346 (v2f32 (COPY_TO_REGCLASS (Inst
5348 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5351 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5354 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5355 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5357 def : N3VSPat<fadd, VADDfd>;
5358 def : N3VSPat<fsub, VSUBfd>;
5359 def : N3VSPat<fmul, VMULfd>;
5360 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
5361 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
5362 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
5363 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
5364 def : N2VSPat<fabs, VABSfd>;
5365 def : N2VSPat<fneg, VNEGfd>;
5366 def : N3VSPat<NEONfmax, VMAXfd>;
5367 def : N3VSPat<NEONfmin, VMINfd>;
5368 def : N2VSPat<arm_ftosi, VCVTf2sd>;
5369 def : N2VSPat<arm_ftoui, VCVTf2ud>;
5370 def : N2VSPat<arm_sitof, VCVTs2fd>;
5371 def : N2VSPat<arm_uitof, VCVTu2fd>;
5373 //===----------------------------------------------------------------------===//
5374 // Non-Instruction Patterns
5375 //===----------------------------------------------------------------------===//
5378 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
5379 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
5380 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
5381 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
5382 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
5383 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
5384 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
5385 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
5386 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
5387 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
5388 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
5389 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
5390 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
5391 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
5392 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
5393 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
5394 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
5395 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
5396 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
5397 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
5398 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
5399 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
5400 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
5401 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
5402 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
5403 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
5404 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
5405 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
5406 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
5407 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
5409 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
5410 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
5411 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
5412 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
5413 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
5414 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
5415 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5416 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
5417 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
5418 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
5419 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5420 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5421 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5422 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5423 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5424 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
5425 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
5426 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5427 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
5428 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
5429 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
5430 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
5431 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5432 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
5433 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
5434 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
5435 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
5436 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5437 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
5438 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
5441 //===----------------------------------------------------------------------===//
5442 // Assembler aliases
5445 def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
5446 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
5447 def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
5448 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;
5451 // VADD two-operand aliases.
5452 def : NEONInstAlias<"vadd${p}.i8 $Vdn, $Vm",
5453 (VADDv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5454 def : NEONInstAlias<"vadd${p}.i16 $Vdn, $Vm",
5455 (VADDv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5456 def : NEONInstAlias<"vadd${p}.i32 $Vdn, $Vm",
5457 (VADDv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5458 def : NEONInstAlias<"vadd${p}.i64 $Vdn, $Vm",
5459 (VADDv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5461 def : NEONInstAlias<"vadd${p}.i8 $Vdn, $Vm",
5462 (VADDv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5463 def : NEONInstAlias<"vadd${p}.i16 $Vdn, $Vm",
5464 (VADDv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5465 def : NEONInstAlias<"vadd${p}.i32 $Vdn, $Vm",
5466 (VADDv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5467 def : NEONInstAlias<"vadd${p}.i64 $Vdn, $Vm",
5468 (VADDv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5470 def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm",
5471 (VADDfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5472 def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm",
5473 (VADDfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5475 // VSUB two-operand aliases.
5476 def : NEONInstAlias<"vsub${p}.i8 $Vdn, $Vm",
5477 (VSUBv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5478 def : NEONInstAlias<"vsub${p}.i16 $Vdn, $Vm",
5479 (VSUBv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5480 def : NEONInstAlias<"vsub${p}.i32 $Vdn, $Vm",
5481 (VSUBv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5482 def : NEONInstAlias<"vsub${p}.i64 $Vdn, $Vm",
5483 (VSUBv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5485 def : NEONInstAlias<"vsub${p}.i8 $Vdn, $Vm",
5486 (VSUBv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5487 def : NEONInstAlias<"vsub${p}.i16 $Vdn, $Vm",
5488 (VSUBv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5489 def : NEONInstAlias<"vsub${p}.i32 $Vdn, $Vm",
5490 (VSUBv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5491 def : NEONInstAlias<"vsub${p}.i64 $Vdn, $Vm",
5492 (VSUBv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5494 def : NEONInstAlias<"vsub${p}.f32 $Vdn, $Vm",
5495 (VSUBfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5496 def : NEONInstAlias<"vsub${p}.f32 $Vdn, $Vm",
5497 (VSUBfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5499 // VADDW two-operand aliases.
5500 def : NEONInstAlias<"vaddw${p}.s8 $Vdn, $Vm",
5501 (VADDWsv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5502 def : NEONInstAlias<"vaddw${p}.s16 $Vdn, $Vm",
5503 (VADDWsv4i32 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5504 def : NEONInstAlias<"vaddw${p}.s32 $Vdn, $Vm",
5505 (VADDWsv2i64 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5506 def : NEONInstAlias<"vaddw${p}.u8 $Vdn, $Vm",
5507 (VADDWuv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5508 def : NEONInstAlias<"vaddw${p}.u16 $Vdn, $Vm",
5509 (VADDWuv4i32 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5510 def : NEONInstAlias<"vaddw${p}.u32 $Vdn, $Vm",
5511 (VADDWuv2i64 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5513 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
5514 defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
5515 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5516 defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
5517 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5518 defm : VFPDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
5519 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5520 defm : VFPDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
5521 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5522 defm : VFPDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
5523 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5524 defm : VFPDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
5525 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5526 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
5527 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5528 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
5529 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5530 // ... two-operand aliases
5531 def : NEONInstAlias<"vand${p} $Vdn, $Vm",
5532 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5533 def : NEONInstAlias<"vand${p} $Vdn, $Vm",
5534 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5535 def : NEONInstAlias<"vbic${p} $Vdn, $Vm",
5536 (VBICd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5537 def : NEONInstAlias<"vbic${p} $Vdn, $Vm",
5538 (VBICq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5539 def : NEONInstAlias<"veor${p} $Vdn, $Vm",
5540 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5541 def : NEONInstAlias<"veor${p} $Vdn, $Vm",
5542 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5543 def : NEONInstAlias<"vorr${p} $Vdn, $Vm",
5544 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5545 def : NEONInstAlias<"vorr${p} $Vdn, $Vm",
5546 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5548 defm : VFPDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
5549 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5550 defm : VFPDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
5551 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5552 defm : VFPDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
5553 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5554 defm : VFPDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
5555 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5556 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
5557 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5558 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
5559 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5561 // VMUL two-operand aliases.
5562 def : NEONInstAlias<"vmul${p}.p8 $Qdn, $Qm",
5563 (VMULpq QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5564 def : NEONInstAlias<"vmul${p}.i8 $Qdn, $Qm",
5565 (VMULv16i8 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5566 def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Qm",
5567 (VMULv8i16 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5568 def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Qm",
5569 (VMULv4i32 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5571 def : NEONInstAlias<"vmul${p}.p8 $Ddn, $Dm",
5572 (VMULpd DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5573 def : NEONInstAlias<"vmul${p}.i8 $Ddn, $Dm",
5574 (VMULv8i8 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5575 def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm",
5576 (VMULv4i16 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5577 def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm",
5578 (VMULv2i32 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5580 def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Qm",
5581 (VMULfq QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5582 def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm",
5583 (VMULfd DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5585 def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm$lane",
5586 (VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm,
5587 VectorIndex16:$lane, pred:$p)>;
5588 def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Dm$lane",
5589 (VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm,
5590 VectorIndex16:$lane, pred:$p)>;
5592 def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm$lane",
5593 (VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
5594 VectorIndex32:$lane, pred:$p)>;
5595 def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Dm$lane",
5596 (VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
5597 VectorIndex32:$lane, pred:$p)>;
5599 def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm$lane",
5600 (VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
5601 VectorIndex32:$lane, pred:$p)>;
5602 def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Dm$lane",
5603 (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
5604 VectorIndex32:$lane, pred:$p)>;
5606 // VQADD (register) two-operand aliases.
5607 def : NEONInstAlias<"vqadd${p}.s8 $Vdn, $Vm",
5608 (VQADDsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5609 def : NEONInstAlias<"vqadd${p}.s16 $Vdn, $Vm",
5610 (VQADDsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5611 def : NEONInstAlias<"vqadd${p}.s32 $Vdn, $Vm",
5612 (VQADDsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5613 def : NEONInstAlias<"vqadd${p}.s64 $Vdn, $Vm",
5614 (VQADDsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5615 def : NEONInstAlias<"vqadd${p}.u8 $Vdn, $Vm",
5616 (VQADDuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5617 def : NEONInstAlias<"vqadd${p}.u16 $Vdn, $Vm",
5618 (VQADDuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5619 def : NEONInstAlias<"vqadd${p}.u32 $Vdn, $Vm",
5620 (VQADDuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5621 def : NEONInstAlias<"vqadd${p}.u64 $Vdn, $Vm",
5622 (VQADDuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5624 def : NEONInstAlias<"vqadd${p}.s8 $Vdn, $Vm",
5625 (VQADDsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5626 def : NEONInstAlias<"vqadd${p}.s16 $Vdn, $Vm",
5627 (VQADDsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5628 def : NEONInstAlias<"vqadd${p}.s32 $Vdn, $Vm",
5629 (VQADDsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5630 def : NEONInstAlias<"vqadd${p}.s64 $Vdn, $Vm",
5631 (VQADDsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5632 def : NEONInstAlias<"vqadd${p}.u8 $Vdn, $Vm",
5633 (VQADDuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5634 def : NEONInstAlias<"vqadd${p}.u16 $Vdn, $Vm",
5635 (VQADDuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5636 def : NEONInstAlias<"vqadd${p}.u32 $Vdn, $Vm",
5637 (VQADDuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5638 def : NEONInstAlias<"vqadd${p}.u64 $Vdn, $Vm",
5639 (VQADDuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5641 // VSHL (immediate) two-operand aliases.
5642 def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
5643 (VSHLiv8i8 DPR:$Vdn, DPR:$Vdn, imm0_7:$imm, pred:$p)>;
5644 def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm",
5645 (VSHLiv4i16 DPR:$Vdn, DPR:$Vdn, imm0_15:$imm, pred:$p)>;
5646 def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm",
5647 (VSHLiv2i32 DPR:$Vdn, DPR:$Vdn, imm0_31:$imm, pred:$p)>;
5648 def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm",
5649 (VSHLiv1i64 DPR:$Vdn, DPR:$Vdn, imm0_63:$imm, pred:$p)>;
5651 def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
5652 (VSHLiv16i8 QPR:$Vdn, QPR:$Vdn, imm0_7:$imm, pred:$p)>;
5653 def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm",
5654 (VSHLiv8i16 QPR:$Vdn, QPR:$Vdn, imm0_15:$imm, pred:$p)>;
5655 def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm",
5656 (VSHLiv4i32 QPR:$Vdn, QPR:$Vdn, imm0_31:$imm, pred:$p)>;
5657 def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm",
5658 (VSHLiv2i64 QPR:$Vdn, QPR:$Vdn, imm0_63:$imm, pred:$p)>;
5660 // VSHL (register) two-operand aliases.
5661 def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm",
5662 (VSHLsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5663 def : NEONInstAlias<"vshl${p}.s16 $Vdn, $Vm",
5664 (VSHLsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5665 def : NEONInstAlias<"vshl${p}.s32 $Vdn, $Vm",
5666 (VSHLsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5667 def : NEONInstAlias<"vshl${p}.s64 $Vdn, $Vm",
5668 (VSHLsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5669 def : NEONInstAlias<"vshl${p}.u8 $Vdn, $Vm",
5670 (VSHLuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5671 def : NEONInstAlias<"vshl${p}.u16 $Vdn, $Vm",
5672 (VSHLuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5673 def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm",
5674 (VSHLuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5675 def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm",
5676 (VSHLuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5678 def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm",
5679 (VSHLsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5680 def : NEONInstAlias<"vshl${p}.s16 $Vdn, $Vm",
5681 (VSHLsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5682 def : NEONInstAlias<"vshl${p}.s32 $Vdn, $Vm",
5683 (VSHLsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5684 def : NEONInstAlias<"vshl${p}.s64 $Vdn, $Vm",
5685 (VSHLsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5686 def : NEONInstAlias<"vshl${p}.u8 $Vdn, $Vm",
5687 (VSHLuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5688 def : NEONInstAlias<"vshl${p}.u16 $Vdn, $Vm",
5689 (VSHLuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5690 def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm",
5691 (VSHLuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5692 def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm",
5693 (VSHLuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5695 // VSHL (immediate) two-operand aliases.
5696 def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm",
5697 (VSHRsv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5698 def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm",
5699 (VSHRsv4i16 DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5700 def : NEONInstAlias<"vshr${p}.s32 $Vdn, $imm",
5701 (VSHRsv2i32 DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5702 def : NEONInstAlias<"vshr${p}.s64 $Vdn, $imm",
5703 (VSHRsv1i64 DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5705 def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm",
5706 (VSHRsv16i8 QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5707 def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm",
5708 (VSHRsv8i16 QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5709 def : NEONInstAlias<"vshr${p}.s32 $Vdn, $imm",
5710 (VSHRsv4i32 QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5711 def : NEONInstAlias<"vshr${p}.s64 $Vdn, $imm",
5712 (VSHRsv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5714 def : NEONInstAlias<"vshr${p}.u8 $Vdn, $imm",
5715 (VSHRuv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5716 def : NEONInstAlias<"vshr${p}.u16 $Vdn, $imm",
5717 (VSHRuv4i16 DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5718 def : NEONInstAlias<"vshr${p}.u32 $Vdn, $imm",
5719 (VSHRuv2i32 DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5720 def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm",
5721 (VSHRuv1i64 DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5723 def : NEONInstAlias<"vshr${p}.u8 $Vdn, $imm",
5724 (VSHRuv16i8 QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5725 def : NEONInstAlias<"vshr${p}.u16 $Vdn, $imm",
5726 (VSHRuv8i16 QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5727 def : NEONInstAlias<"vshr${p}.u32 $Vdn, $imm",
5728 (VSHRuv4i32 QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5729 def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm",
5730 (VSHRuv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5732 // VLD1 single-lane pseudo-instructions. These need special handling for
5733 // the lane index that an InstAlias can't handle, so we use these instead.
5734 defm VLD1LNdAsm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr",
5735 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5736 defm VLD1LNdAsm : NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr",
5737 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5738 defm VLD1LNdAsm : NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr",
5739 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5741 defm VLD1LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr!",
5742 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5743 defm VLD1LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr!",
5744 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5745 defm VLD1LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr!",
5746 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5747 defm VLD1LNdWB_register_Asm :
5748 NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
5749 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
5750 rGPR:$Rm, pred:$p)>;
5751 defm VLD1LNdWB_register_Asm :
5752 NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
5753 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
5754 rGPR:$Rm, pred:$p)>;
5755 defm VLD1LNdWB_register_Asm :
5756 NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
5757 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
5758 rGPR:$Rm, pred:$p)>;
5761 // VST1 single-lane pseudo-instructions. These need special handling for
5762 // the lane index that an InstAlias can't handle, so we use these instead.
5763 defm VST1LNdAsm : NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr",
5764 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5765 defm VST1LNdAsm : NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr",
5766 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5767 defm VST1LNdAsm : NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr",
5768 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5770 defm VST1LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr!",
5771 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5772 defm VST1LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr!",
5773 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5774 defm VST1LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr!",
5775 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5776 defm VST1LNdWB_register_Asm :
5777 NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
5778 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
5779 rGPR:$Rm, pred:$p)>;
5780 defm VST1LNdWB_register_Asm :
5781 NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
5782 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
5783 rGPR:$Rm, pred:$p)>;
5784 defm VST1LNdWB_register_Asm :
5785 NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
5786 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
5787 rGPR:$Rm, pred:$p)>;
5789 // VLD2 single-lane pseudo-instructions. These need special handling for
5790 // the lane index that an InstAlias can't handle, so we use these instead.
5791 defm VLD2LNdAsm : NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr",
5792 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5793 defm VLD2LNdAsm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr",
5794 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5795 defm VLD2LNdAsm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr",
5796 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5797 defm VLD2LNqAsm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr",
5798 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5799 defm VLD2LNqAsm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr",
5800 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5802 defm VLD2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr!",
5803 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5804 defm VLD2LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr!",
5805 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5806 defm VLD2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr!",
5807 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5808 defm VLD2LNqWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr!",
5809 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5810 defm VLD2LNqWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr!",
5811 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5812 defm VLD2LNdWB_register_Asm :
5813 NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
5814 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
5815 rGPR:$Rm, pred:$p)>;
5816 defm VLD2LNdWB_register_Asm :
5817 NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
5818 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
5819 rGPR:$Rm, pred:$p)>;
5820 defm VLD2LNdWB_register_Asm :
5821 NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
5822 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
5823 rGPR:$Rm, pred:$p)>;
5824 defm VLD2LNqWB_register_Asm :
5825 NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
5826 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
5827 rGPR:$Rm, pred:$p)>;
5828 defm VLD2LNqWB_register_Asm :
5829 NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
5830 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
5831 rGPR:$Rm, pred:$p)>;
5834 // VST2 single-lane pseudo-instructions. These need special handling for
5835 // the lane index that an InstAlias can't handle, so we use these instead.
5836 defm VST2LNdAsm : NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr",
5837 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5838 defm VST2LNdAsm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr",
5839 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5840 defm VST2LNdAsm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr",
5841 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5842 defm VST2LNqAsm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr",
5843 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5844 defm VST2LNqAsm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr",
5845 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5847 defm VST2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr!",
5848 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5849 defm VST2LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr!",
5850 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5851 defm VST2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr!",
5852 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5853 defm VST2LNqWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr!",
5854 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5855 defm VST2LNqWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr!",
5856 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5857 defm VST2LNdWB_register_Asm :
5858 NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
5859 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
5860 rGPR:$Rm, pred:$p)>;
5861 defm VST2LNdWB_register_Asm :
5862 NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
5863 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
5864 rGPR:$Rm, pred:$p)>;
5865 defm VST2LNdWB_register_Asm :
5866 NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
5867 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
5868 rGPR:$Rm, pred:$p)>;
5869 defm VST2LNqWB_register_Asm :
5870 NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
5871 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
5872 rGPR:$Rm, pred:$p)>;
5873 defm VST2LNqWB_register_Asm :
5874 NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
5875 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
5876 rGPR:$Rm, pred:$p)>;
5878 // VMOV takes an optional datatype suffix
5879 defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
5880 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
5881 defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
5882 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
5884 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
5885 // D-register versions.
5886 def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm",
5887 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5888 def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm",
5889 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5890 def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm",
5891 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5892 def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm",
5893 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5894 def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm",
5895 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5896 def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm",
5897 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5898 def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm",
5899 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5900 // Q-register versions.
5901 def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
5902 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5903 def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
5904 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5905 def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
5906 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5907 def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
5908 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5909 def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
5910 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5911 def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
5912 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5913 def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
5914 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5916 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
5917 // D-register versions.
5918 def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
5919 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5920 def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
5921 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5922 def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
5923 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5924 def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
5925 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5926 def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
5927 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5928 def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
5929 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5930 def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
5931 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5932 // Q-register versions.
5933 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
5934 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5935 def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
5936 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5937 def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm",
5938 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5939 def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm",
5940 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5941 def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm",
5942 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5943 def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
5944 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5945 def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
5946 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5948 // Two-operand variants for VEXT
5949 def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
5950 (VEXTd8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_7:$imm, pred:$p)>;
5951 def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
5952 (VEXTd16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_3:$imm, pred:$p)>;
5953 def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
5954 (VEXTd32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_1:$imm, pred:$p)>;
5956 def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
5957 (VEXTq8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_15:$imm, pred:$p)>;
5958 def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
5959 (VEXTq16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_7:$imm, pred:$p)>;
5960 def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
5961 (VEXTq32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_3:$imm, pred:$p)>;
5962 def : NEONInstAlias<"vext${p}.64 $Vdn, $Vm, $imm",
5963 (VEXTq64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_1:$imm, pred:$p)>;
5965 // Two-operand variants for VQDMULH
5966 def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm",
5967 (VQDMULHv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5968 def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm",
5969 (VQDMULHv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5971 def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm",
5972 (VQDMULHv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5973 def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm",
5974 (VQDMULHv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5976 // Two-operand variants for VMAX.
5977 def : NEONInstAlias<"vmax${p}.s8 $Vdn, $Vm",
5978 (VMAXsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5979 def : NEONInstAlias<"vmax${p}.s16 $Vdn, $Vm",
5980 (VMAXsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5981 def : NEONInstAlias<"vmax${p}.s32 $Vdn, $Vm",
5982 (VMAXsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5983 def : NEONInstAlias<"vmax${p}.u8 $Vdn, $Vm",
5984 (VMAXuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5985 def : NEONInstAlias<"vmax${p}.u16 $Vdn, $Vm",
5986 (VMAXuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5987 def : NEONInstAlias<"vmax${p}.u32 $Vdn, $Vm",
5988 (VMAXuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5989 def : NEONInstAlias<"vmax${p}.f32 $Vdn, $Vm",
5990 (VMAXfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5992 def : NEONInstAlias<"vmax${p}.s8 $Vdn, $Vm",
5993 (VMAXsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5994 def : NEONInstAlias<"vmax${p}.s16 $Vdn, $Vm",
5995 (VMAXsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5996 def : NEONInstAlias<"vmax${p}.s32 $Vdn, $Vm",
5997 (VMAXsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5998 def : NEONInstAlias<"vmax${p}.u8 $Vdn, $Vm",
5999 (VMAXuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6000 def : NEONInstAlias<"vmax${p}.u16 $Vdn, $Vm",
6001 (VMAXuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6002 def : NEONInstAlias<"vmax${p}.u32 $Vdn, $Vm",
6003 (VMAXuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6004 def : NEONInstAlias<"vmax${p}.f32 $Vdn, $Vm",
6005 (VMAXfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6007 // Two-operand variants for VMIN.
6008 def : NEONInstAlias<"vmin${p}.s8 $Vdn, $Vm",
6009 (VMINsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6010 def : NEONInstAlias<"vmin${p}.s16 $Vdn, $Vm",
6011 (VMINsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6012 def : NEONInstAlias<"vmin${p}.s32 $Vdn, $Vm",
6013 (VMINsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6014 def : NEONInstAlias<"vmin${p}.u8 $Vdn, $Vm",
6015 (VMINuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6016 def : NEONInstAlias<"vmin${p}.u16 $Vdn, $Vm",
6017 (VMINuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6018 def : NEONInstAlias<"vmin${p}.u32 $Vdn, $Vm",
6019 (VMINuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6020 def : NEONInstAlias<"vmin${p}.f32 $Vdn, $Vm",
6021 (VMINfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6023 def : NEONInstAlias<"vmin${p}.s8 $Vdn, $Vm",
6024 (VMINsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6025 def : NEONInstAlias<"vmin${p}.s16 $Vdn, $Vm",
6026 (VMINsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6027 def : NEONInstAlias<"vmin${p}.s32 $Vdn, $Vm",
6028 (VMINsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6029 def : NEONInstAlias<"vmin${p}.u8 $Vdn, $Vm",
6030 (VMINuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6031 def : NEONInstAlias<"vmin${p}.u16 $Vdn, $Vm",
6032 (VMINuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6033 def : NEONInstAlias<"vmin${p}.u32 $Vdn, $Vm",
6034 (VMINuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6035 def : NEONInstAlias<"vmin${p}.f32 $Vdn, $Vm",
6036 (VMINfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6038 // Two-operand variants for VPADD.
6039 def : NEONInstAlias<"vpadd${p}.i8 $Vdn, $Vm",
6040 (VPADDi8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6041 def : NEONInstAlias<"vpadd${p}.i16 $Vdn, $Vm",
6042 (VPADDi16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6043 def : NEONInstAlias<"vpadd${p}.i32 $Vdn, $Vm",
6044 (VPADDi32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6045 def : NEONInstAlias<"vpadd${p}.f32 $Vdn, $Vm",
6046 (VPADDf DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6048 // VSWP allows, but does not require, a type suffix.
6049 defm : VFPDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
6050 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
6051 defm : VFPDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
6052 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
6054 // "vmov Rd, #-imm" can be handled via "vmvn".
6055 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
6056 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6057 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
6058 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6059 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
6060 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6061 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
6062 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
6064 // 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
6065 // these should restrict to just the Q register variants, but the register
6066 // classes are enough to match correctly regardless, so we keep it simple
6067 // and just use MnemonicAlias.
6068 def : NEONMnemonicAlias<"vbicq", "vbic">;
6069 def : NEONMnemonicAlias<"vandq", "vand">;
6070 def : NEONMnemonicAlias<"veorq", "veor">;
6071 def : NEONMnemonicAlias<"vorrq", "vorr">;
6073 def : NEONMnemonicAlias<"vmovq", "vmov">;
6074 def : NEONMnemonicAlias<"vmvnq", "vmvn">;
6075 // Explicit versions for floating point so that the FPImm variants get
6076 // handled early. The parser gets confused otherwise.
6077 def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">;
6078 def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">;
6080 def : NEONMnemonicAlias<"vaddq", "vadd">;
6081 def : NEONMnemonicAlias<"vsubq", "vsub">;
6083 def : NEONMnemonicAlias<"vminq", "vmin">;
6084 def : NEONMnemonicAlias<"vmaxq", "vmax">;
6086 def : NEONMnemonicAlias<"vmulq", "vmul">;
6088 def : NEONMnemonicAlias<"vabsq", "vabs">;
6090 def : NEONMnemonicAlias<"vshlq", "vshl">;
6091 def : NEONMnemonicAlias<"vshrq", "vshr">;
6093 def : NEONMnemonicAlias<"vcvtq", "vcvt">;
6095 def : NEONMnemonicAlias<"vcleq", "vcle">;
6096 def : NEONMnemonicAlias<"vceqq", "vceq">;
6098 def : NEONMnemonicAlias<"vzipq", "vzip">;
6099 def : NEONMnemonicAlias<"vswpq", "vswp">;
6101 def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">;
6102 def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">;
6105 // Alias for loading floating point immediates that aren't representable
6106 // using the vmov.f32 encoding but the bitpattern is representable using
6107 // the .i32 encoding.
6108 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
6109 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
6110 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
6111 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;