1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
42 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
43 def nImmSplatI64 : Operand<i32> {
44 let PrintMethod = "printNEONModImmOperand";
45 let ParserMatchClass = nImmSplatI64AsmOperand;
48 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
49 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
50 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
51 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
52 return ((uint64_t)Imm) < 8;
54 let ParserMatchClass = VectorIndex8Operand;
55 let PrintMethod = "printVectorIndex";
56 let MIOperandInfo = (ops i32imm);
58 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
59 return ((uint64_t)Imm) < 4;
61 let ParserMatchClass = VectorIndex16Operand;
62 let PrintMethod = "printVectorIndex";
63 let MIOperandInfo = (ops i32imm);
65 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
66 return ((uint64_t)Imm) < 2;
68 let ParserMatchClass = VectorIndex32Operand;
69 let PrintMethod = "printVectorIndex";
70 let MIOperandInfo = (ops i32imm);
73 //===----------------------------------------------------------------------===//
74 // NEON-specific DAG Nodes.
75 //===----------------------------------------------------------------------===//
77 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
78 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
80 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
81 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
82 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
83 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
84 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
85 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
86 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
87 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
88 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
89 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
90 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
92 // Types for vector shift by immediates. The "SHX" version is for long and
93 // narrow operations where the source and destination vectors have different
94 // types. The "SHINS" version is for shift and insert operations.
95 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
97 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
99 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
100 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
102 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
103 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
104 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
105 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
106 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
107 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
108 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
110 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
111 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
112 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
114 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
115 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
116 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
117 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
118 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
119 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
121 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
122 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
123 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
125 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
126 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
128 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
130 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
131 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
133 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
134 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
135 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
137 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
139 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
140 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
142 def NEONvbsl : SDNode<"ARMISD::VBSL",
143 SDTypeProfile<1, 3, [SDTCisVec<0>,
146 SDTCisSameAs<0, 3>]>>;
148 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
150 // VDUPLANE can produce a quad-register result from a double-register source,
151 // so the result is not constrained to match the source.
152 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
153 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
156 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
157 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
158 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
160 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
161 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
162 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
163 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
165 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
167 SDTCisSameAs<0, 3>]>;
168 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
169 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
170 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
172 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
173 SDTCisSameAs<1, 2>]>;
174 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
175 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
177 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
178 SDTCisSameAs<0, 2>]>;
179 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
180 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
182 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
183 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
184 unsigned EltBits = 0;
185 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
186 return (EltBits == 32 && EltVal == 0);
189 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
190 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
191 unsigned EltBits = 0;
192 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
193 return (EltBits == 8 && EltVal == 0xff);
196 //===----------------------------------------------------------------------===//
197 // NEON load / store instructions
198 //===----------------------------------------------------------------------===//
200 // Use VLDM to load a Q register as a D register pair.
201 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
203 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
205 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
207 // Use VSTM to store a Q register as a D register pair.
208 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
210 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
212 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
214 // Classes for VLD* pseudo-instructions with multi-register operands.
215 // These are expanded to real instructions after register allocation.
216 class VLDQPseudo<InstrItinClass itin>
217 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
218 class VLDQWBPseudo<InstrItinClass itin>
219 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
220 (ins addrmode6:$addr, am6offset:$offset), itin,
222 class VLDQQPseudo<InstrItinClass itin>
223 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
224 class VLDQQWBPseudo<InstrItinClass itin>
225 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
226 (ins addrmode6:$addr, am6offset:$offset), itin,
228 class VLDQQQQPseudo<InstrItinClass itin>
229 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
231 class VLDQQQQWBPseudo<InstrItinClass itin>
232 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
233 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
234 "$addr.addr = $wb, $src = $dst">;
236 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
238 // VLD1 : Vector Load (multiple single elements)
239 class VLD1D<bits<4> op7_4, string Dt>
240 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
241 (ins addrmode6:$Rn), IIC_VLD1,
242 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
245 let DecoderMethod = "DecodeVLDInstruction";
247 class VLD1Q<bits<4> op7_4, string Dt>
248 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
249 (ins addrmode6:$Rn), IIC_VLD1x2,
250 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
252 let Inst{5-4} = Rn{5-4};
253 let DecoderMethod = "DecodeVLDInstruction";
256 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
257 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
258 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
259 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
261 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
262 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
263 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
264 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
266 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
267 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
268 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
269 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
271 // ...with address register writeback:
272 class VLD1DWB<bits<4> op7_4, string Dt>
273 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
274 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
275 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
276 "$Rn.addr = $wb", []> {
278 let DecoderMethod = "DecodeVLDInstruction";
280 class VLD1QWB<bits<4> op7_4, string Dt>
281 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
282 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
283 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
284 "$Rn.addr = $wb", []> {
285 let Inst{5-4} = Rn{5-4};
286 let DecoderMethod = "DecodeVLDInstruction";
289 def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
290 def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
291 def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
292 def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
294 def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
295 def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
296 def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
297 def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
299 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
300 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
301 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
302 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
304 // ...with 3 registers (some of these are only for the disassembler):
305 class VLD1D3<bits<4> op7_4, string Dt>
306 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
307 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
308 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
311 let DecoderMethod = "DecodeVLDInstruction";
313 class VLD1D3WB<bits<4> op7_4, string Dt>
314 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
315 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
316 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
318 let DecoderMethod = "DecodeVLDInstruction";
321 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
322 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
323 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
324 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
326 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
327 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
328 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
329 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
331 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
332 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
334 // ...with 4 registers (some of these are only for the disassembler):
335 class VLD1D4<bits<4> op7_4, string Dt>
336 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
337 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
338 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
340 let Inst{5-4} = Rn{5-4};
341 let DecoderMethod = "DecodeVLDInstruction";
343 class VLD1D4WB<bits<4> op7_4, string Dt>
344 : NLdSt<0,0b10,0b0010,op7_4,
345 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
346 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x4u, "vld1", Dt,
347 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
349 let Inst{5-4} = Rn{5-4};
350 let DecoderMethod = "DecodeVLDInstruction";
353 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
354 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
355 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
356 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
358 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
359 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
360 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
361 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
363 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
364 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
366 // VLD2 : Vector Load (multiple 2-element structures)
367 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
368 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
369 (ins addrmode6:$Rn), IIC_VLD2,
370 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
372 let Inst{5-4} = Rn{5-4};
373 let DecoderMethod = "DecodeVLDInstruction";
375 class VLD2Q<bits<4> op7_4, string Dt>
376 : NLdSt<0, 0b10, 0b0011, op7_4,
377 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
378 (ins addrmode6:$Rn), IIC_VLD2x2,
379 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
381 let Inst{5-4} = Rn{5-4};
382 let DecoderMethod = "DecodeVLDInstruction";
385 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
386 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
387 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
389 def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
390 def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
391 def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
393 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
394 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
395 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
397 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
398 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
399 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
401 // ...with address register writeback:
402 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
403 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
404 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
405 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
406 "$Rn.addr = $wb", []> {
407 let Inst{5-4} = Rn{5-4};
408 let DecoderMethod = "DecodeVLDInstruction";
410 class VLD2QWB<bits<4> op7_4, string Dt>
411 : NLdSt<0, 0b10, 0b0011, op7_4,
412 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
413 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
414 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
415 "$Rn.addr = $wb", []> {
416 let Inst{5-4} = Rn{5-4};
417 let DecoderMethod = "DecodeVLDInstruction";
420 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
421 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
422 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
424 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
425 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
426 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
428 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
429 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
430 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
432 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
433 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
434 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
436 // ...with double-spaced registers (for disassembly only):
437 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
438 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
439 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
440 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
441 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
442 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
444 // VLD3 : Vector Load (multiple 3-element structures)
445 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
446 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
447 (ins addrmode6:$Rn), IIC_VLD3,
448 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
451 let DecoderMethod = "DecodeVLDInstruction";
454 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
455 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
456 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
458 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
459 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
460 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
462 // ...with address register writeback:
463 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
464 : NLdSt<0, 0b10, op11_8, op7_4,
465 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
466 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
467 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
468 "$Rn.addr = $wb", []> {
470 let DecoderMethod = "DecodeVLDInstruction";
473 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
474 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
475 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
477 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
478 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
479 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
481 // ...with double-spaced registers:
482 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
483 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
484 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
485 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
486 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
487 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
489 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
490 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
491 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
493 // ...alternate versions to be allocated odd register numbers:
494 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
495 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
496 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
498 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
499 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
500 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
502 // VLD4 : Vector Load (multiple 4-element structures)
503 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
504 : NLdSt<0, 0b10, op11_8, op7_4,
505 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
506 (ins addrmode6:$Rn), IIC_VLD4,
507 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
509 let Inst{5-4} = Rn{5-4};
510 let DecoderMethod = "DecodeVLDInstruction";
513 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
514 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
515 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
517 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
518 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
519 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
521 // ...with address register writeback:
522 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
523 : NLdSt<0, 0b10, op11_8, op7_4,
524 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
525 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
526 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
527 "$Rn.addr = $wb", []> {
528 let Inst{5-4} = Rn{5-4};
529 let DecoderMethod = "DecodeVLDInstruction";
532 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
533 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
534 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
536 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
537 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
538 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
540 // ...with double-spaced registers:
541 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
542 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
543 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
544 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
545 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
546 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
548 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
549 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
550 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
552 // ...alternate versions to be allocated odd register numbers:
553 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
554 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
555 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
557 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
558 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
559 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
561 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
563 // Classes for VLD*LN pseudo-instructions with multi-register operands.
564 // These are expanded to real instructions after register allocation.
565 class VLDQLNPseudo<InstrItinClass itin>
566 : PseudoNLdSt<(outs QPR:$dst),
567 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
568 itin, "$src = $dst">;
569 class VLDQLNWBPseudo<InstrItinClass itin>
570 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
571 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
572 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
573 class VLDQQLNPseudo<InstrItinClass itin>
574 : PseudoNLdSt<(outs QQPR:$dst),
575 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
576 itin, "$src = $dst">;
577 class VLDQQLNWBPseudo<InstrItinClass itin>
578 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
579 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
580 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
581 class VLDQQQQLNPseudo<InstrItinClass itin>
582 : PseudoNLdSt<(outs QQQQPR:$dst),
583 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
584 itin, "$src = $dst">;
585 class VLDQQQQLNWBPseudo<InstrItinClass itin>
586 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
587 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
588 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
590 // VLD1LN : Vector Load (single element to one lane)
591 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
593 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
594 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
595 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
597 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
598 (i32 (LoadOp addrmode6:$Rn)),
601 let DecoderMethod = "DecodeVLD1LN";
603 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
605 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
606 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
607 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
609 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
610 (i32 (LoadOp addrmode6oneL32:$Rn)),
613 let DecoderMethod = "DecodeVLD1LN";
615 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
616 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
617 (i32 (LoadOp addrmode6:$addr)),
621 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
622 let Inst{7-5} = lane{2-0};
624 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
625 let Inst{7-6} = lane{1-0};
628 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
629 let Inst{7} = lane{0};
634 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
635 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
636 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
638 def : Pat<(vector_insert (v2f32 DPR:$src),
639 (f32 (load addrmode6:$addr)), imm:$lane),
640 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
641 def : Pat<(vector_insert (v4f32 QPR:$src),
642 (f32 (load addrmode6:$addr)), imm:$lane),
643 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
645 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
647 // ...with address register writeback:
648 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
649 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
650 (ins addrmode6:$Rn, am6offset:$Rm,
651 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
652 "\\{$Vd[$lane]\\}, $Rn$Rm",
653 "$src = $Vd, $Rn.addr = $wb", []> {
654 let DecoderMethod = "DecodeVLD1LN";
657 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
658 let Inst{7-5} = lane{2-0};
660 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
661 let Inst{7-6} = lane{1-0};
664 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
665 let Inst{7} = lane{0};
670 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
671 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
672 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
674 // VLD2LN : Vector Load (single 2-element structure to one lane)
675 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
676 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
677 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
678 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
679 "$src1 = $Vd, $src2 = $dst2", []> {
682 let DecoderMethod = "DecodeVLD2LN";
685 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
686 let Inst{7-5} = lane{2-0};
688 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
689 let Inst{7-6} = lane{1-0};
691 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
692 let Inst{7} = lane{0};
695 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
696 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
697 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
699 // ...with double-spaced registers:
700 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
701 let Inst{7-6} = lane{1-0};
703 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
704 let Inst{7} = lane{0};
707 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
708 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
710 // ...with address register writeback:
711 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
712 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
713 (ins addrmode6:$Rn, am6offset:$Rm,
714 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
715 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
716 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
718 let DecoderMethod = "DecodeVLD2LN";
721 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
722 let Inst{7-5} = lane{2-0};
724 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
725 let Inst{7-6} = lane{1-0};
727 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
728 let Inst{7} = lane{0};
731 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
732 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
733 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
735 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
736 let Inst{7-6} = lane{1-0};
738 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
739 let Inst{7} = lane{0};
742 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
743 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
745 // VLD3LN : Vector Load (single 3-element structure to one lane)
746 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
747 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
748 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
749 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
750 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
751 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
753 let DecoderMethod = "DecodeVLD3LN";
756 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
757 let Inst{7-5} = lane{2-0};
759 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
760 let Inst{7-6} = lane{1-0};
762 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
763 let Inst{7} = lane{0};
766 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
767 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
768 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
770 // ...with double-spaced registers:
771 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
772 let Inst{7-6} = lane{1-0};
774 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
775 let Inst{7} = lane{0};
778 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
779 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
781 // ...with address register writeback:
782 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
783 : NLdStLn<1, 0b10, op11_8, op7_4,
784 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
785 (ins addrmode6:$Rn, am6offset:$Rm,
786 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
787 IIC_VLD3lnu, "vld3", Dt,
788 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
789 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
791 let DecoderMethod = "DecodeVLD3LN";
794 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
795 let Inst{7-5} = lane{2-0};
797 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
798 let Inst{7-6} = lane{1-0};
800 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
801 let Inst{7} = lane{0};
804 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
805 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
806 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
808 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
809 let Inst{7-6} = lane{1-0};
811 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
812 let Inst{7} = lane{0};
815 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
816 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
818 // VLD4LN : Vector Load (single 4-element structure to one lane)
819 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
820 : NLdStLn<1, 0b10, op11_8, op7_4,
821 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
822 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
823 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
824 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
825 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
828 let DecoderMethod = "DecodeVLD4LN";
831 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
832 let Inst{7-5} = lane{2-0};
834 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
835 let Inst{7-6} = lane{1-0};
837 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
838 let Inst{7} = lane{0};
842 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
843 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
844 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
846 // ...with double-spaced registers:
847 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
848 let Inst{7-6} = lane{1-0};
850 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
851 let Inst{7} = lane{0};
855 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
856 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
858 // ...with address register writeback:
859 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
860 : NLdStLn<1, 0b10, op11_8, op7_4,
861 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
862 (ins addrmode6:$Rn, am6offset:$Rm,
863 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
864 IIC_VLD4lnu, "vld4", Dt,
865 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
866 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
869 let DecoderMethod = "DecodeVLD4LN" ;
872 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
873 let Inst{7-5} = lane{2-0};
875 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
876 let Inst{7-6} = lane{1-0};
878 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
879 let Inst{7} = lane{0};
883 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
884 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
885 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
887 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
888 let Inst{7-6} = lane{1-0};
890 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
891 let Inst{7} = lane{0};
895 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
896 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
898 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
900 // VLD1DUP : Vector Load (single element to all lanes)
901 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
902 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6dup:$Rn),
903 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
904 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
907 let DecoderMethod = "DecodeVLD1DupInstruction";
909 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
910 let Pattern = [(set QPR:$dst,
911 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
914 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
915 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
916 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
918 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
919 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
920 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
922 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
923 (VLD1DUPd32 addrmode6:$addr)>;
924 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
925 (VLD1DUPq32Pseudo addrmode6:$addr)>;
927 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
929 class VLD1QDUP<bits<4> op7_4, string Dt>
930 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
931 (ins addrmode6dup:$Rn), IIC_VLD1dup,
932 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
935 let DecoderMethod = "DecodeVLD1DupInstruction";
938 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
939 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
940 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
942 // ...with address register writeback:
943 class VLD1DUPWB<bits<4> op7_4, string Dt>
944 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
945 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
946 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
948 let DecoderMethod = "DecodeVLD1DupInstruction";
950 class VLD1QDUPWB<bits<4> op7_4, string Dt>
951 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
952 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
953 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
955 let DecoderMethod = "DecodeVLD1DupInstruction";
958 def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
959 def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
960 def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
962 def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
963 def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
964 def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
966 def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
967 def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
968 def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
970 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
971 class VLD2DUP<bits<4> op7_4, string Dt>
972 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
973 (ins addrmode6dup:$Rn), IIC_VLD2dup,
974 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
977 let DecoderMethod = "DecodeVLD2DupInstruction";
980 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
981 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
982 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
984 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
985 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
986 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
988 // ...with double-spaced registers (not used for codegen):
989 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
990 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
991 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
993 // ...with address register writeback:
994 class VLD2DUPWB<bits<4> op7_4, string Dt>
995 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
996 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
997 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
999 let DecoderMethod = "DecodeVLD2DupInstruction";
1002 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
1003 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
1004 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
1006 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
1007 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
1008 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
1010 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1011 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1012 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1014 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1015 class VLD3DUP<bits<4> op7_4, string Dt>
1016 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1017 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1018 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1021 let DecoderMethod = "DecodeVLD3DupInstruction";
1024 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1025 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1026 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1028 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1029 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1030 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1032 // ...with double-spaced registers (not used for codegen):
1033 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
1034 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
1035 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
1037 // ...with address register writeback:
1038 class VLD3DUPWB<bits<4> op7_4, string Dt>
1039 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1040 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1041 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1042 "$Rn.addr = $wb", []> {
1044 let DecoderMethod = "DecodeVLD3DupInstruction";
1047 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1048 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1049 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1051 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1052 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1053 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1055 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1056 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1057 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1059 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1060 class VLD4DUP<bits<4> op7_4, string Dt>
1061 : NLdSt<1, 0b10, 0b1111, op7_4,
1062 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1063 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1064 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1066 let Inst{4} = Rn{4};
1067 let DecoderMethod = "DecodeVLD4DupInstruction";
1070 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1071 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1072 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1074 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1075 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1076 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1078 // ...with double-spaced registers (not used for codegen):
1079 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
1080 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
1081 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1083 // ...with address register writeback:
1084 class VLD4DUPWB<bits<4> op7_4, string Dt>
1085 : NLdSt<1, 0b10, 0b1111, op7_4,
1086 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1087 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1088 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1089 "$Rn.addr = $wb", []> {
1090 let Inst{4} = Rn{4};
1091 let DecoderMethod = "DecodeVLD4DupInstruction";
1094 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1095 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1096 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1098 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1099 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1100 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1102 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1103 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1104 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1106 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1108 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1110 // Classes for VST* pseudo-instructions with multi-register operands.
1111 // These are expanded to real instructions after register allocation.
1112 class VSTQPseudo<InstrItinClass itin>
1113 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1114 class VSTQWBPseudo<InstrItinClass itin>
1115 : PseudoNLdSt<(outs GPR:$wb),
1116 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1117 "$addr.addr = $wb">;
1118 class VSTQQPseudo<InstrItinClass itin>
1119 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1120 class VSTQQWBPseudo<InstrItinClass itin>
1121 : PseudoNLdSt<(outs GPR:$wb),
1122 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1123 "$addr.addr = $wb">;
1124 class VSTQQQQPseudo<InstrItinClass itin>
1125 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1126 class VSTQQQQWBPseudo<InstrItinClass itin>
1127 : PseudoNLdSt<(outs GPR:$wb),
1128 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1129 "$addr.addr = $wb">;
1131 // VST1 : Vector Store (multiple single elements)
1132 class VST1D<bits<4> op7_4, string Dt>
1133 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
1134 IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> {
1136 let Inst{4} = Rn{4};
1137 let DecoderMethod = "DecodeVSTInstruction";
1139 class VST1Q<bits<4> op7_4, string Dt>
1140 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1141 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
1142 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1144 let Inst{5-4} = Rn{5-4};
1145 let DecoderMethod = "DecodeVSTInstruction";
1148 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1149 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1150 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1151 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1153 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1154 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1155 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1156 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1158 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1159 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1160 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1161 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1163 // ...with address register writeback:
1164 class VST1DWB<bits<4> op7_4, string Dt>
1165 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1166 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
1167 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1168 let Inst{4} = Rn{4};
1169 let DecoderMethod = "DecodeVSTInstruction";
1171 class VST1QWB<bits<4> op7_4, string Dt>
1172 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
1173 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1174 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1175 "$Rn.addr = $wb", []> {
1176 let Inst{5-4} = Rn{5-4};
1177 let DecoderMethod = "DecodeVSTInstruction";
1180 def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
1181 def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
1182 def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
1183 def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
1185 def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
1186 def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
1187 def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
1188 def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
1190 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1191 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1192 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1193 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1195 // ...with 3 registers (some of these are only for the disassembler):
1196 class VST1D3<bits<4> op7_4, string Dt>
1197 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1198 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1199 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1201 let Inst{4} = Rn{4};
1202 let DecoderMethod = "DecodeVSTInstruction";
1204 class VST1D3WB<bits<4> op7_4, string Dt>
1205 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1206 (ins addrmode6:$Rn, am6offset:$Rm,
1207 DPR:$Vd, DPR:$src2, DPR:$src3),
1208 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1209 "$Rn.addr = $wb", []> {
1210 let Inst{4} = Rn{4};
1211 let DecoderMethod = "DecodeVSTInstruction";
1214 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1215 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1216 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1217 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1219 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
1220 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
1221 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
1222 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
1224 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1225 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
1227 // ...with 4 registers (some of these are only for the disassembler):
1228 class VST1D4<bits<4> op7_4, string Dt>
1229 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1230 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1231 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1234 let Inst{5-4} = Rn{5-4};
1235 let DecoderMethod = "DecodeVSTInstruction";
1237 class VST1D4WB<bits<4> op7_4, string Dt>
1238 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1239 (ins addrmode6:$Rn, am6offset:$Rm,
1240 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1241 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1242 "$Rn.addr = $wb", []> {
1243 let Inst{5-4} = Rn{5-4};
1244 let DecoderMethod = "DecodeVSTInstruction";
1247 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1248 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1249 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1250 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1252 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
1253 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
1254 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
1255 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
1257 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1258 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
1260 // VST2 : Vector Store (multiple 2-element structures)
1261 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
1262 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1263 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1264 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1266 let Inst{5-4} = Rn{5-4};
1267 let DecoderMethod = "DecodeVSTInstruction";
1269 class VST2Q<bits<4> op7_4, string Dt>
1270 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1271 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1272 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1275 let Inst{5-4} = Rn{5-4};
1276 let DecoderMethod = "DecodeVSTInstruction";
1279 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1280 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
1281 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
1283 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
1284 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
1285 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
1287 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1288 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1289 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1291 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1292 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1293 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1295 // ...with address register writeback:
1296 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1297 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1298 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1299 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1300 "$Rn.addr = $wb", []> {
1301 let Inst{5-4} = Rn{5-4};
1302 let DecoderMethod = "DecodeVSTInstruction";
1304 class VST2QWB<bits<4> op7_4, string Dt>
1305 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1306 (ins addrmode6:$Rn, am6offset:$Rm,
1307 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1308 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1309 "$Rn.addr = $wb", []> {
1310 let Inst{5-4} = Rn{5-4};
1311 let DecoderMethod = "DecodeVSTInstruction";
1314 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
1315 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
1316 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
1318 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
1319 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
1320 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1322 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1323 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1324 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1326 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1327 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1328 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1330 // ...with double-spaced registers (for disassembly only):
1331 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1332 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1333 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1334 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1335 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1336 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1338 // VST3 : Vector Store (multiple 3-element structures)
1339 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1340 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1341 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1342 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1344 let Inst{4} = Rn{4};
1345 let DecoderMethod = "DecodeVSTInstruction";
1348 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1349 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1350 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1352 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1353 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1354 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1356 // ...with address register writeback:
1357 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1358 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1359 (ins addrmode6:$Rn, am6offset:$Rm,
1360 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1361 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1362 "$Rn.addr = $wb", []> {
1363 let Inst{4} = Rn{4};
1364 let DecoderMethod = "DecodeVSTInstruction";
1367 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1368 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1369 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1371 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1372 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1373 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1375 // ...with double-spaced registers:
1376 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1377 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1378 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1379 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1380 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1381 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1383 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1384 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1385 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1387 // ...alternate versions to be allocated odd register numbers:
1388 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1389 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1390 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1392 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1393 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1394 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1396 // VST4 : Vector Store (multiple 4-element structures)
1397 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1398 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1399 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1400 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1403 let Inst{5-4} = Rn{5-4};
1404 let DecoderMethod = "DecodeVSTInstruction";
1407 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1408 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1409 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1411 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1412 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1413 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1415 // ...with address register writeback:
1416 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1417 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1418 (ins addrmode6:$Rn, am6offset:$Rm,
1419 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1420 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1421 "$Rn.addr = $wb", []> {
1422 let Inst{5-4} = Rn{5-4};
1423 let DecoderMethod = "DecodeVSTInstruction";
1426 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1427 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1428 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1430 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1431 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1432 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1434 // ...with double-spaced registers:
1435 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1436 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1437 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1438 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1439 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1440 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1442 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1443 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1444 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1446 // ...alternate versions to be allocated odd register numbers:
1447 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1448 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1449 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1451 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1452 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1453 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1455 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1457 // Classes for VST*LN pseudo-instructions with multi-register operands.
1458 // These are expanded to real instructions after register allocation.
1459 class VSTQLNPseudo<InstrItinClass itin>
1460 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1462 class VSTQLNWBPseudo<InstrItinClass itin>
1463 : PseudoNLdSt<(outs GPR:$wb),
1464 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1465 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1466 class VSTQQLNPseudo<InstrItinClass itin>
1467 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1469 class VSTQQLNWBPseudo<InstrItinClass itin>
1470 : PseudoNLdSt<(outs GPR:$wb),
1471 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1472 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1473 class VSTQQQQLNPseudo<InstrItinClass itin>
1474 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1476 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1477 : PseudoNLdSt<(outs GPR:$wb),
1478 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1479 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1481 // VST1LN : Vector Store (single element from one lane)
1482 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1483 PatFrag StoreOp, SDNode ExtractOp>
1484 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1485 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1486 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1487 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1489 let DecoderMethod = "DecodeVST1LN";
1491 class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1492 PatFrag StoreOp, SDNode ExtractOp>
1493 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1494 (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane),
1495 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1496 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
1498 let DecoderMethod = "DecodeVST1LN";
1500 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1501 : VSTQLNPseudo<IIC_VST1ln> {
1502 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1506 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1508 let Inst{7-5} = lane{2-0};
1510 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1512 let Inst{7-6} = lane{1-0};
1513 let Inst{4} = Rn{5};
1516 def VST1LNd32 : VST1LN32<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1517 let Inst{7} = lane{0};
1518 let Inst{5-4} = Rn{5-4};
1521 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1522 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1523 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1525 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1526 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1527 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1528 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1530 // ...with address register writeback:
1531 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1532 PatFrag StoreOp, SDNode ExtractOp>
1533 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1534 (ins addrmode6:$Rn, am6offset:$Rm,
1535 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1536 "\\{$Vd[$lane]\\}, $Rn$Rm",
1538 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1539 addrmode6:$Rn, am6offset:$Rm))]> {
1540 let DecoderMethod = "DecodeVST1LN";
1542 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1543 : VSTQLNWBPseudo<IIC_VST1lnu> {
1544 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1545 addrmode6:$addr, am6offset:$offset))];
1548 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
1550 let Inst{7-5} = lane{2-0};
1552 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
1554 let Inst{7-6} = lane{1-0};
1555 let Inst{4} = Rn{5};
1557 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
1559 let Inst{7} = lane{0};
1560 let Inst{5-4} = Rn{5-4};
1563 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
1564 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
1565 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
1567 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1569 // VST2LN : Vector Store (single 2-element structure from one lane)
1570 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1571 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1572 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1573 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1576 let Inst{4} = Rn{4};
1577 let DecoderMethod = "DecodeVST2LN";
1580 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1581 let Inst{7-5} = lane{2-0};
1583 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1584 let Inst{7-6} = lane{1-0};
1586 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1587 let Inst{7} = lane{0};
1590 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1591 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1592 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1594 // ...with double-spaced registers:
1595 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1596 let Inst{7-6} = lane{1-0};
1597 let Inst{4} = Rn{4};
1599 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1600 let Inst{7} = lane{0};
1601 let Inst{4} = Rn{4};
1604 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1605 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1607 // ...with address register writeback:
1608 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1609 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1610 (ins addrmode6:$addr, am6offset:$offset,
1611 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1612 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1613 "$addr.addr = $wb", []> {
1614 let Inst{4} = Rn{4};
1615 let DecoderMethod = "DecodeVST2LN";
1618 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1619 let Inst{7-5} = lane{2-0};
1621 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1622 let Inst{7-6} = lane{1-0};
1624 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1625 let Inst{7} = lane{0};
1628 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1629 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1630 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1632 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1633 let Inst{7-6} = lane{1-0};
1635 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1636 let Inst{7} = lane{0};
1639 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1640 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1642 // VST3LN : Vector Store (single 3-element structure from one lane)
1643 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1644 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1645 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1646 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1647 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1649 let DecoderMethod = "DecodeVST3LN";
1652 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1653 let Inst{7-5} = lane{2-0};
1655 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1656 let Inst{7-6} = lane{1-0};
1658 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1659 let Inst{7} = lane{0};
1662 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1663 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1664 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1666 // ...with double-spaced registers:
1667 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1668 let Inst{7-6} = lane{1-0};
1670 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1671 let Inst{7} = lane{0};
1674 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1675 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1677 // ...with address register writeback:
1678 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1679 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1680 (ins addrmode6:$Rn, am6offset:$Rm,
1681 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1682 IIC_VST3lnu, "vst3", Dt,
1683 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1684 "$Rn.addr = $wb", []> {
1685 let DecoderMethod = "DecodeVST3LN";
1688 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1689 let Inst{7-5} = lane{2-0};
1691 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1692 let Inst{7-6} = lane{1-0};
1694 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1695 let Inst{7} = lane{0};
1698 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1699 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1700 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1702 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1703 let Inst{7-6} = lane{1-0};
1705 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1706 let Inst{7} = lane{0};
1709 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1710 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1712 // VST4LN : Vector Store (single 4-element structure from one lane)
1713 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1714 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1715 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1716 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1717 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1720 let Inst{4} = Rn{4};
1721 let DecoderMethod = "DecodeVST4LN";
1724 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1725 let Inst{7-5} = lane{2-0};
1727 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1728 let Inst{7-6} = lane{1-0};
1730 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1731 let Inst{7} = lane{0};
1732 let Inst{5} = Rn{5};
1735 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1736 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1737 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1739 // ...with double-spaced registers:
1740 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1741 let Inst{7-6} = lane{1-0};
1743 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1744 let Inst{7} = lane{0};
1745 let Inst{5} = Rn{5};
1748 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1749 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1751 // ...with address register writeback:
1752 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1753 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1754 (ins addrmode6:$Rn, am6offset:$Rm,
1755 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1756 IIC_VST4lnu, "vst4", Dt,
1757 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1758 "$Rn.addr = $wb", []> {
1759 let Inst{4} = Rn{4};
1760 let DecoderMethod = "DecodeVST4LN";
1763 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1764 let Inst{7-5} = lane{2-0};
1766 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1767 let Inst{7-6} = lane{1-0};
1769 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1770 let Inst{7} = lane{0};
1771 let Inst{5} = Rn{5};
1774 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1775 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1776 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1778 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1779 let Inst{7-6} = lane{1-0};
1781 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1782 let Inst{7} = lane{0};
1783 let Inst{5} = Rn{5};
1786 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1787 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1789 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1792 //===----------------------------------------------------------------------===//
1793 // NEON pattern fragments
1794 //===----------------------------------------------------------------------===//
1796 // Extract D sub-registers of Q registers.
1797 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1798 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1799 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1801 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1802 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1803 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1805 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1806 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1807 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1809 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1810 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1811 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1814 // Extract S sub-registers of Q/D registers.
1815 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1816 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1817 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1820 // Translate lane numbers from Q registers to D subregs.
1821 def SubReg_i8_lane : SDNodeXForm<imm, [{
1822 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1824 def SubReg_i16_lane : SDNodeXForm<imm, [{
1825 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1827 def SubReg_i32_lane : SDNodeXForm<imm, [{
1828 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1831 //===----------------------------------------------------------------------===//
1832 // Instruction Classes
1833 //===----------------------------------------------------------------------===//
1835 // Basic 2-register operations: double- and quad-register.
1836 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1837 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1838 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1839 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1840 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
1841 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1842 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1843 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1844 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1845 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1846 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
1847 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1849 // Basic 2-register intrinsics, both double- and quad-register.
1850 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1851 bits<2> op17_16, bits<5> op11_7, bit op4,
1852 InstrItinClass itin, string OpcodeStr, string Dt,
1853 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1854 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1855 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1856 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1857 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1858 bits<2> op17_16, bits<5> op11_7, bit op4,
1859 InstrItinClass itin, string OpcodeStr, string Dt,
1860 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1861 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1862 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1863 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1865 // Narrow 2-register operations.
1866 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1867 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1868 InstrItinClass itin, string OpcodeStr, string Dt,
1869 ValueType TyD, ValueType TyQ, SDNode OpNode>
1870 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1871 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1872 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
1874 // Narrow 2-register intrinsics.
1875 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1876 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1877 InstrItinClass itin, string OpcodeStr, string Dt,
1878 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1879 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1880 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1881 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
1883 // Long 2-register operations (currently only used for VMOVL).
1884 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1885 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1886 InstrItinClass itin, string OpcodeStr, string Dt,
1887 ValueType TyQ, ValueType TyD, SDNode OpNode>
1888 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1889 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1890 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
1892 // Long 2-register intrinsics.
1893 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1894 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1895 InstrItinClass itin, string OpcodeStr, string Dt,
1896 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1897 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1898 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1899 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
1901 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1902 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1903 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
1904 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1905 OpcodeStr, Dt, "$Vd, $Vm",
1906 "$src1 = $Vd, $src2 = $Vm", []>;
1907 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1908 InstrItinClass itin, string OpcodeStr, string Dt>
1909 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
1910 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
1911 "$src1 = $Vd, $src2 = $Vm", []>;
1913 // Basic 3-register operations: double- and quad-register.
1914 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1915 InstrItinClass itin, string OpcodeStr, string Dt,
1916 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1917 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1918 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1919 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1920 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1921 let isCommutable = Commutable;
1923 // Same as N3VD but no data type.
1924 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1925 InstrItinClass itin, string OpcodeStr,
1926 ValueType ResTy, ValueType OpTy,
1927 SDNode OpNode, bit Commutable>
1928 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1929 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1930 OpcodeStr, "$Vd, $Vn, $Vm", "",
1931 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
1932 let isCommutable = Commutable;
1935 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1936 InstrItinClass itin, string OpcodeStr, string Dt,
1937 ValueType Ty, SDNode ShOp>
1938 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
1939 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
1940 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
1942 (Ty (ShOp (Ty DPR:$Vn),
1943 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
1944 let isCommutable = 0;
1946 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1947 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1948 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
1949 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
1950 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
1952 (Ty (ShOp (Ty DPR:$Vn),
1953 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1954 let isCommutable = 0;
1957 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1958 InstrItinClass itin, string OpcodeStr, string Dt,
1959 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1960 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1961 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1962 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1963 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1964 let isCommutable = Commutable;
1966 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1967 InstrItinClass itin, string OpcodeStr,
1968 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1969 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1970 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1971 OpcodeStr, "$Vd, $Vn, $Vm", "",
1972 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
1973 let isCommutable = Commutable;
1975 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1976 InstrItinClass itin, string OpcodeStr, string Dt,
1977 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1978 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
1979 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1980 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1981 [(set (ResTy QPR:$Vd),
1982 (ResTy (ShOp (ResTy QPR:$Vn),
1983 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1985 let isCommutable = 0;
1987 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1988 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1989 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
1990 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1991 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1992 [(set (ResTy QPR:$Vd),
1993 (ResTy (ShOp (ResTy QPR:$Vn),
1994 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1996 let isCommutable = 0;
1999 // Basic 3-register intrinsics, both double- and quad-register.
2000 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2001 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2002 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2003 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2004 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2005 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2006 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2007 let isCommutable = Commutable;
2009 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2010 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2011 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2012 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2013 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2015 (Ty (IntOp (Ty DPR:$Vn),
2016 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2018 let isCommutable = 0;
2020 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2021 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2022 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2023 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2024 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2026 (Ty (IntOp (Ty DPR:$Vn),
2027 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2028 let isCommutable = 0;
2030 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2031 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2032 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2033 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2034 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2035 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2036 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2037 let isCommutable = 0;
2040 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2041 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2042 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2043 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2044 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2045 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2046 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2047 let isCommutable = Commutable;
2049 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2050 string OpcodeStr, string Dt,
2051 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2052 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2053 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2054 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2055 [(set (ResTy QPR:$Vd),
2056 (ResTy (IntOp (ResTy QPR:$Vn),
2057 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2059 let isCommutable = 0;
2061 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2062 string OpcodeStr, string Dt,
2063 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2064 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2065 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2066 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2067 [(set (ResTy QPR:$Vd),
2068 (ResTy (IntOp (ResTy QPR:$Vn),
2069 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2071 let isCommutable = 0;
2073 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2074 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2075 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2076 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2077 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2078 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2079 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2080 let isCommutable = 0;
2083 // Multiply-Add/Sub operations: double- and quad-register.
2084 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2085 InstrItinClass itin, string OpcodeStr, string Dt,
2086 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2087 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2088 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2089 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2090 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2091 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2093 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2094 string OpcodeStr, string Dt,
2095 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2096 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2098 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2100 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2102 (Ty (ShOp (Ty DPR:$src1),
2104 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2106 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2107 string OpcodeStr, string Dt,
2108 ValueType Ty, SDNode MulOp, SDNode ShOp>
2109 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2111 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2113 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2115 (Ty (ShOp (Ty DPR:$src1),
2117 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2120 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2121 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2122 SDPatternOperator MulOp, SDPatternOperator OpNode>
2123 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2124 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2125 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2126 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2127 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2128 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2129 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2130 SDPatternOperator MulOp, SDPatternOperator ShOp>
2131 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2133 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2135 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2136 [(set (ResTy QPR:$Vd),
2137 (ResTy (ShOp (ResTy QPR:$src1),
2138 (ResTy (MulOp QPR:$Vn,
2139 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2141 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2142 string OpcodeStr, string Dt,
2143 ValueType ResTy, ValueType OpTy,
2144 SDNode MulOp, SDNode ShOp>
2145 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2147 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2149 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2150 [(set (ResTy QPR:$Vd),
2151 (ResTy (ShOp (ResTy QPR:$src1),
2152 (ResTy (MulOp QPR:$Vn,
2153 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2156 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2157 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2158 InstrItinClass itin, string OpcodeStr, string Dt,
2159 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2160 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2161 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2162 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2163 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2164 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2165 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2166 InstrItinClass itin, string OpcodeStr, string Dt,
2167 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2168 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2169 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2170 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2171 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2172 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2174 // Neon 3-argument intrinsics, both double- and quad-register.
2175 // The destination register is also used as the first source operand register.
2176 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2177 InstrItinClass itin, string OpcodeStr, string Dt,
2178 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2179 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2180 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2181 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2182 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2183 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2184 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2185 InstrItinClass itin, string OpcodeStr, string Dt,
2186 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2187 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2188 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2189 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2190 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2191 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2193 // Long Multiply-Add/Sub operations.
2194 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2195 InstrItinClass itin, string OpcodeStr, string Dt,
2196 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2197 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2198 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2199 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2200 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2201 (TyQ (MulOp (TyD DPR:$Vn),
2202 (TyD DPR:$Vm)))))]>;
2203 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2204 InstrItinClass itin, string OpcodeStr, string Dt,
2205 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2206 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2207 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2209 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2211 (OpNode (TyQ QPR:$src1),
2212 (TyQ (MulOp (TyD DPR:$Vn),
2213 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2215 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2216 InstrItinClass itin, string OpcodeStr, string Dt,
2217 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2218 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2219 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2221 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2223 (OpNode (TyQ QPR:$src1),
2224 (TyQ (MulOp (TyD DPR:$Vn),
2225 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2228 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2229 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2230 InstrItinClass itin, string OpcodeStr, string Dt,
2231 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2233 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2234 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2235 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2236 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2237 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2238 (TyD DPR:$Vm)))))))]>;
2240 // Neon Long 3-argument intrinsic. The destination register is
2241 // a quad-register and is also used as the first source operand register.
2242 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2243 InstrItinClass itin, string OpcodeStr, string Dt,
2244 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2245 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2246 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2247 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2249 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2250 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2251 string OpcodeStr, string Dt,
2252 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2253 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2255 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2257 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2258 [(set (ResTy QPR:$Vd),
2259 (ResTy (IntOp (ResTy QPR:$src1),
2261 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2263 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2264 InstrItinClass itin, string OpcodeStr, string Dt,
2265 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2266 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2268 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2270 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2271 [(set (ResTy QPR:$Vd),
2272 (ResTy (IntOp (ResTy QPR:$src1),
2274 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2277 // Narrowing 3-register intrinsics.
2278 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2279 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2280 Intrinsic IntOp, bit Commutable>
2281 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2282 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2283 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2284 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2285 let isCommutable = Commutable;
2288 // Long 3-register operations.
2289 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2290 InstrItinClass itin, string OpcodeStr, string Dt,
2291 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2292 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2293 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2294 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2295 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2296 let isCommutable = Commutable;
2298 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2299 InstrItinClass itin, string OpcodeStr, string Dt,
2300 ValueType TyQ, ValueType TyD, SDNode OpNode>
2301 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2302 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2303 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2305 (TyQ (OpNode (TyD DPR:$Vn),
2306 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2307 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2308 InstrItinClass itin, string OpcodeStr, string Dt,
2309 ValueType TyQ, ValueType TyD, SDNode OpNode>
2310 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2311 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2312 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2314 (TyQ (OpNode (TyD DPR:$Vn),
2315 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2317 // Long 3-register operations with explicitly extended operands.
2318 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2319 InstrItinClass itin, string OpcodeStr, string Dt,
2320 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2322 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2323 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2324 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2325 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2326 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2327 let isCommutable = Commutable;
2330 // Long 3-register intrinsics with explicit extend (VABDL).
2331 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2332 InstrItinClass itin, string OpcodeStr, string Dt,
2333 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2335 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2336 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2337 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2338 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2339 (TyD DPR:$Vm))))))]> {
2340 let isCommutable = Commutable;
2343 // Long 3-register intrinsics.
2344 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2345 InstrItinClass itin, string OpcodeStr, string Dt,
2346 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2347 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2348 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2349 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2350 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2351 let isCommutable = Commutable;
2353 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2354 string OpcodeStr, string Dt,
2355 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2356 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2357 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2358 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2359 [(set (ResTy QPR:$Vd),
2360 (ResTy (IntOp (OpTy DPR:$Vn),
2361 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2363 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2364 InstrItinClass itin, string OpcodeStr, string Dt,
2365 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2366 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2367 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2368 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2369 [(set (ResTy QPR:$Vd),
2370 (ResTy (IntOp (OpTy DPR:$Vn),
2371 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2374 // Wide 3-register operations.
2375 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2376 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2377 SDNode OpNode, SDNode ExtOp, bit Commutable>
2378 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2379 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2380 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2381 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2382 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2383 let isCommutable = Commutable;
2386 // Pairwise long 2-register intrinsics, both double- and quad-register.
2387 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2388 bits<2> op17_16, bits<5> op11_7, bit op4,
2389 string OpcodeStr, string Dt,
2390 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2391 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2392 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2393 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2394 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2395 bits<2> op17_16, bits<5> op11_7, bit op4,
2396 string OpcodeStr, string Dt,
2397 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2398 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2399 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2400 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2402 // Pairwise long 2-register accumulate intrinsics,
2403 // both double- and quad-register.
2404 // The destination register is also used as the first source operand register.
2405 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2406 bits<2> op17_16, bits<5> op11_7, bit op4,
2407 string OpcodeStr, string Dt,
2408 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2409 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2410 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2411 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2412 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2413 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2414 bits<2> op17_16, bits<5> op11_7, bit op4,
2415 string OpcodeStr, string Dt,
2416 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2417 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2418 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2419 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2420 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2422 // Shift by immediate,
2423 // both double- and quad-register.
2424 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2425 Format f, InstrItinClass itin, Operand ImmTy,
2426 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2427 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2428 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2429 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2430 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2431 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2432 Format f, InstrItinClass itin, Operand ImmTy,
2433 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2434 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2435 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2436 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2437 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2439 // Long shift by immediate.
2440 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2441 string OpcodeStr, string Dt,
2442 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2443 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2444 (outs QPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), N2RegVShLFrm,
2445 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2446 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2447 (i32 imm:$SIMM))))]>;
2449 // Narrow shift by immediate.
2450 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2451 InstrItinClass itin, string OpcodeStr, string Dt,
2452 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2453 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2454 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2455 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2456 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2457 (i32 imm:$SIMM))))]>;
2459 // Shift right by immediate and accumulate,
2460 // both double- and quad-register.
2461 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2462 Operand ImmTy, string OpcodeStr, string Dt,
2463 ValueType Ty, SDNode ShOp>
2464 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2465 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2466 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2467 [(set DPR:$Vd, (Ty (add DPR:$src1,
2468 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2469 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2470 Operand ImmTy, string OpcodeStr, string Dt,
2471 ValueType Ty, SDNode ShOp>
2472 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2473 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2474 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2475 [(set QPR:$Vd, (Ty (add QPR:$src1,
2476 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2478 // Shift by immediate and insert,
2479 // both double- and quad-register.
2480 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2481 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2482 ValueType Ty,SDNode ShOp>
2483 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2484 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2485 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2486 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2487 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2488 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2489 ValueType Ty,SDNode ShOp>
2490 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2491 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2492 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2493 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2495 // Convert, with fractional bits immediate,
2496 // both double- and quad-register.
2497 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2498 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2500 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2501 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2502 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2503 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2504 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2505 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2507 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2508 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2509 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2510 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2512 //===----------------------------------------------------------------------===//
2514 //===----------------------------------------------------------------------===//
2516 // Abbreviations used in multiclass suffixes:
2517 // Q = quarter int (8 bit) elements
2518 // H = half int (16 bit) elements
2519 // S = single int (32 bit) elements
2520 // D = double int (64 bit) elements
2522 // Neon 2-register vector operations and intrinsics.
2524 // Neon 2-register comparisons.
2525 // source operand element sizes of 8, 16 and 32 bits:
2526 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2527 bits<5> op11_7, bit op4, string opc, string Dt,
2528 string asm, SDNode OpNode> {
2529 // 64-bit vector types.
2530 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2531 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2532 opc, !strconcat(Dt, "8"), asm, "",
2533 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2534 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2535 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2536 opc, !strconcat(Dt, "16"), asm, "",
2537 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2538 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2539 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2540 opc, !strconcat(Dt, "32"), asm, "",
2541 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2542 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2543 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2544 opc, "f32", asm, "",
2545 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2546 let Inst{10} = 1; // overwrite F = 1
2549 // 128-bit vector types.
2550 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2551 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2552 opc, !strconcat(Dt, "8"), asm, "",
2553 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2554 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2555 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2556 opc, !strconcat(Dt, "16"), asm, "",
2557 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2558 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2559 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2560 opc, !strconcat(Dt, "32"), asm, "",
2561 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2562 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2563 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2564 opc, "f32", asm, "",
2565 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2566 let Inst{10} = 1; // overwrite F = 1
2571 // Neon 2-register vector intrinsics,
2572 // element sizes of 8, 16 and 32 bits:
2573 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2574 bits<5> op11_7, bit op4,
2575 InstrItinClass itinD, InstrItinClass itinQ,
2576 string OpcodeStr, string Dt, Intrinsic IntOp> {
2577 // 64-bit vector types.
2578 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2579 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2580 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2581 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2582 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2583 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2585 // 128-bit vector types.
2586 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2587 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2588 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2589 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2590 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2591 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2595 // Neon Narrowing 2-register vector operations,
2596 // source operand element sizes of 16, 32 and 64 bits:
2597 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2598 bits<5> op11_7, bit op6, bit op4,
2599 InstrItinClass itin, string OpcodeStr, string Dt,
2601 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2602 itin, OpcodeStr, !strconcat(Dt, "16"),
2603 v8i8, v8i16, OpNode>;
2604 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2605 itin, OpcodeStr, !strconcat(Dt, "32"),
2606 v4i16, v4i32, OpNode>;
2607 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2608 itin, OpcodeStr, !strconcat(Dt, "64"),
2609 v2i32, v2i64, OpNode>;
2612 // Neon Narrowing 2-register vector intrinsics,
2613 // source operand element sizes of 16, 32 and 64 bits:
2614 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2615 bits<5> op11_7, bit op6, bit op4,
2616 InstrItinClass itin, string OpcodeStr, string Dt,
2618 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2619 itin, OpcodeStr, !strconcat(Dt, "16"),
2620 v8i8, v8i16, IntOp>;
2621 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2622 itin, OpcodeStr, !strconcat(Dt, "32"),
2623 v4i16, v4i32, IntOp>;
2624 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2625 itin, OpcodeStr, !strconcat(Dt, "64"),
2626 v2i32, v2i64, IntOp>;
2630 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2631 // source operand element sizes of 16, 32 and 64 bits:
2632 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2633 string OpcodeStr, string Dt, SDNode OpNode> {
2634 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2635 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2636 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2637 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2638 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2639 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2643 // Neon 3-register vector operations.
2645 // First with only element sizes of 8, 16 and 32 bits:
2646 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2647 InstrItinClass itinD16, InstrItinClass itinD32,
2648 InstrItinClass itinQ16, InstrItinClass itinQ32,
2649 string OpcodeStr, string Dt,
2650 SDNode OpNode, bit Commutable = 0> {
2651 // 64-bit vector types.
2652 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2653 OpcodeStr, !strconcat(Dt, "8"),
2654 v8i8, v8i8, OpNode, Commutable>;
2655 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2656 OpcodeStr, !strconcat(Dt, "16"),
2657 v4i16, v4i16, OpNode, Commutable>;
2658 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2659 OpcodeStr, !strconcat(Dt, "32"),
2660 v2i32, v2i32, OpNode, Commutable>;
2662 // 128-bit vector types.
2663 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2664 OpcodeStr, !strconcat(Dt, "8"),
2665 v16i8, v16i8, OpNode, Commutable>;
2666 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2667 OpcodeStr, !strconcat(Dt, "16"),
2668 v8i16, v8i16, OpNode, Commutable>;
2669 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2670 OpcodeStr, !strconcat(Dt, "32"),
2671 v4i32, v4i32, OpNode, Commutable>;
2674 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2675 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2677 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2679 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2680 v8i16, v4i16, ShOp>;
2681 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2682 v4i32, v2i32, ShOp>;
2685 // ....then also with element size 64 bits:
2686 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2687 InstrItinClass itinD, InstrItinClass itinQ,
2688 string OpcodeStr, string Dt,
2689 SDNode OpNode, bit Commutable = 0>
2690 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2691 OpcodeStr, Dt, OpNode, Commutable> {
2692 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2693 OpcodeStr, !strconcat(Dt, "64"),
2694 v1i64, v1i64, OpNode, Commutable>;
2695 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2696 OpcodeStr, !strconcat(Dt, "64"),
2697 v2i64, v2i64, OpNode, Commutable>;
2701 // Neon 3-register vector intrinsics.
2703 // First with only element sizes of 16 and 32 bits:
2704 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2705 InstrItinClass itinD16, InstrItinClass itinD32,
2706 InstrItinClass itinQ16, InstrItinClass itinQ32,
2707 string OpcodeStr, string Dt,
2708 Intrinsic IntOp, bit Commutable = 0> {
2709 // 64-bit vector types.
2710 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2711 OpcodeStr, !strconcat(Dt, "16"),
2712 v4i16, v4i16, IntOp, Commutable>;
2713 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2714 OpcodeStr, !strconcat(Dt, "32"),
2715 v2i32, v2i32, IntOp, Commutable>;
2717 // 128-bit vector types.
2718 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2719 OpcodeStr, !strconcat(Dt, "16"),
2720 v8i16, v8i16, IntOp, Commutable>;
2721 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2722 OpcodeStr, !strconcat(Dt, "32"),
2723 v4i32, v4i32, IntOp, Commutable>;
2725 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2726 InstrItinClass itinD16, InstrItinClass itinD32,
2727 InstrItinClass itinQ16, InstrItinClass itinQ32,
2728 string OpcodeStr, string Dt,
2730 // 64-bit vector types.
2731 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2732 OpcodeStr, !strconcat(Dt, "16"),
2733 v4i16, v4i16, IntOp>;
2734 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2735 OpcodeStr, !strconcat(Dt, "32"),
2736 v2i32, v2i32, IntOp>;
2738 // 128-bit vector types.
2739 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2740 OpcodeStr, !strconcat(Dt, "16"),
2741 v8i16, v8i16, IntOp>;
2742 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2743 OpcodeStr, !strconcat(Dt, "32"),
2744 v4i32, v4i32, IntOp>;
2747 multiclass N3VIntSL_HS<bits<4> op11_8,
2748 InstrItinClass itinD16, InstrItinClass itinD32,
2749 InstrItinClass itinQ16, InstrItinClass itinQ32,
2750 string OpcodeStr, string Dt, Intrinsic IntOp> {
2751 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2752 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2753 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2754 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2755 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2756 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2757 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2758 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2761 // ....then also with element size of 8 bits:
2762 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2763 InstrItinClass itinD16, InstrItinClass itinD32,
2764 InstrItinClass itinQ16, InstrItinClass itinQ32,
2765 string OpcodeStr, string Dt,
2766 Intrinsic IntOp, bit Commutable = 0>
2767 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2768 OpcodeStr, Dt, IntOp, Commutable> {
2769 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2770 OpcodeStr, !strconcat(Dt, "8"),
2771 v8i8, v8i8, IntOp, Commutable>;
2772 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2773 OpcodeStr, !strconcat(Dt, "8"),
2774 v16i8, v16i8, IntOp, Commutable>;
2776 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2777 InstrItinClass itinD16, InstrItinClass itinD32,
2778 InstrItinClass itinQ16, InstrItinClass itinQ32,
2779 string OpcodeStr, string Dt,
2781 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2782 OpcodeStr, Dt, IntOp> {
2783 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2784 OpcodeStr, !strconcat(Dt, "8"),
2786 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2787 OpcodeStr, !strconcat(Dt, "8"),
2788 v16i8, v16i8, IntOp>;
2792 // ....then also with element size of 64 bits:
2793 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2794 InstrItinClass itinD16, InstrItinClass itinD32,
2795 InstrItinClass itinQ16, InstrItinClass itinQ32,
2796 string OpcodeStr, string Dt,
2797 Intrinsic IntOp, bit Commutable = 0>
2798 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2799 OpcodeStr, Dt, IntOp, Commutable> {
2800 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2801 OpcodeStr, !strconcat(Dt, "64"),
2802 v1i64, v1i64, IntOp, Commutable>;
2803 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2804 OpcodeStr, !strconcat(Dt, "64"),
2805 v2i64, v2i64, IntOp, Commutable>;
2807 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2808 InstrItinClass itinD16, InstrItinClass itinD32,
2809 InstrItinClass itinQ16, InstrItinClass itinQ32,
2810 string OpcodeStr, string Dt,
2812 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2813 OpcodeStr, Dt, IntOp> {
2814 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2815 OpcodeStr, !strconcat(Dt, "64"),
2816 v1i64, v1i64, IntOp>;
2817 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2818 OpcodeStr, !strconcat(Dt, "64"),
2819 v2i64, v2i64, IntOp>;
2822 // Neon Narrowing 3-register vector intrinsics,
2823 // source operand element sizes of 16, 32 and 64 bits:
2824 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2825 string OpcodeStr, string Dt,
2826 Intrinsic IntOp, bit Commutable = 0> {
2827 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2828 OpcodeStr, !strconcat(Dt, "16"),
2829 v8i8, v8i16, IntOp, Commutable>;
2830 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2831 OpcodeStr, !strconcat(Dt, "32"),
2832 v4i16, v4i32, IntOp, Commutable>;
2833 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2834 OpcodeStr, !strconcat(Dt, "64"),
2835 v2i32, v2i64, IntOp, Commutable>;
2839 // Neon Long 3-register vector operations.
2841 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2842 InstrItinClass itin16, InstrItinClass itin32,
2843 string OpcodeStr, string Dt,
2844 SDNode OpNode, bit Commutable = 0> {
2845 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2846 OpcodeStr, !strconcat(Dt, "8"),
2847 v8i16, v8i8, OpNode, Commutable>;
2848 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2849 OpcodeStr, !strconcat(Dt, "16"),
2850 v4i32, v4i16, OpNode, Commutable>;
2851 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2852 OpcodeStr, !strconcat(Dt, "32"),
2853 v2i64, v2i32, OpNode, Commutable>;
2856 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2857 InstrItinClass itin, string OpcodeStr, string Dt,
2859 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2860 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2861 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2862 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2865 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2866 InstrItinClass itin16, InstrItinClass itin32,
2867 string OpcodeStr, string Dt,
2868 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2869 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2870 OpcodeStr, !strconcat(Dt, "8"),
2871 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2872 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2873 OpcodeStr, !strconcat(Dt, "16"),
2874 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2875 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2876 OpcodeStr, !strconcat(Dt, "32"),
2877 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2880 // Neon Long 3-register vector intrinsics.
2882 // First with only element sizes of 16 and 32 bits:
2883 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2884 InstrItinClass itin16, InstrItinClass itin32,
2885 string OpcodeStr, string Dt,
2886 Intrinsic IntOp, bit Commutable = 0> {
2887 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2888 OpcodeStr, !strconcat(Dt, "16"),
2889 v4i32, v4i16, IntOp, Commutable>;
2890 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2891 OpcodeStr, !strconcat(Dt, "32"),
2892 v2i64, v2i32, IntOp, Commutable>;
2895 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2896 InstrItinClass itin, string OpcodeStr, string Dt,
2898 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2899 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2900 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2901 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2904 // ....then also with element size of 8 bits:
2905 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2906 InstrItinClass itin16, InstrItinClass itin32,
2907 string OpcodeStr, string Dt,
2908 Intrinsic IntOp, bit Commutable = 0>
2909 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2910 IntOp, Commutable> {
2911 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2912 OpcodeStr, !strconcat(Dt, "8"),
2913 v8i16, v8i8, IntOp, Commutable>;
2916 // ....with explicit extend (VABDL).
2917 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2918 InstrItinClass itin, string OpcodeStr, string Dt,
2919 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2920 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2921 OpcodeStr, !strconcat(Dt, "8"),
2922 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2923 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2924 OpcodeStr, !strconcat(Dt, "16"),
2925 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2926 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2927 OpcodeStr, !strconcat(Dt, "32"),
2928 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2932 // Neon Wide 3-register vector intrinsics,
2933 // source operand element sizes of 8, 16 and 32 bits:
2934 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2935 string OpcodeStr, string Dt,
2936 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2937 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2938 OpcodeStr, !strconcat(Dt, "8"),
2939 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2940 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2941 OpcodeStr, !strconcat(Dt, "16"),
2942 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2943 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2944 OpcodeStr, !strconcat(Dt, "32"),
2945 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2949 // Neon Multiply-Op vector operations,
2950 // element sizes of 8, 16 and 32 bits:
2951 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2952 InstrItinClass itinD16, InstrItinClass itinD32,
2953 InstrItinClass itinQ16, InstrItinClass itinQ32,
2954 string OpcodeStr, string Dt, SDNode OpNode> {
2955 // 64-bit vector types.
2956 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2957 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2958 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2959 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2960 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2961 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2963 // 128-bit vector types.
2964 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2965 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2966 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2967 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2968 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2969 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2972 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2973 InstrItinClass itinD16, InstrItinClass itinD32,
2974 InstrItinClass itinQ16, InstrItinClass itinQ32,
2975 string OpcodeStr, string Dt, SDNode ShOp> {
2976 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2977 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2978 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2979 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2980 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2981 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2983 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2984 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2988 // Neon Intrinsic-Op vector operations,
2989 // element sizes of 8, 16 and 32 bits:
2990 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2991 InstrItinClass itinD, InstrItinClass itinQ,
2992 string OpcodeStr, string Dt, Intrinsic IntOp,
2994 // 64-bit vector types.
2995 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2996 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2997 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2998 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2999 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3000 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3002 // 128-bit vector types.
3003 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3004 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3005 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3006 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3007 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3008 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3011 // Neon 3-argument intrinsics,
3012 // element sizes of 8, 16 and 32 bits:
3013 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3014 InstrItinClass itinD, InstrItinClass itinQ,
3015 string OpcodeStr, string Dt, Intrinsic IntOp> {
3016 // 64-bit vector types.
3017 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3018 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3019 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3020 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3021 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3022 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3024 // 128-bit vector types.
3025 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3026 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3027 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3028 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3029 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3030 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3034 // Neon Long Multiply-Op vector operations,
3035 // element sizes of 8, 16 and 32 bits:
3036 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3037 InstrItinClass itin16, InstrItinClass itin32,
3038 string OpcodeStr, string Dt, SDNode MulOp,
3040 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3041 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3042 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3043 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3044 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3045 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3048 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3049 string Dt, SDNode MulOp, SDNode OpNode> {
3050 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3051 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3052 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3053 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3057 // Neon Long 3-argument intrinsics.
3059 // First with only element sizes of 16 and 32 bits:
3060 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3061 InstrItinClass itin16, InstrItinClass itin32,
3062 string OpcodeStr, string Dt, Intrinsic IntOp> {
3063 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3064 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3065 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3066 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3069 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3070 string OpcodeStr, string Dt, Intrinsic IntOp> {
3071 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3072 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3073 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3074 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3077 // ....then also with element size of 8 bits:
3078 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3079 InstrItinClass itin16, InstrItinClass itin32,
3080 string OpcodeStr, string Dt, Intrinsic IntOp>
3081 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3082 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3083 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3086 // ....with explicit extend (VABAL).
3087 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3088 InstrItinClass itin, string OpcodeStr, string Dt,
3089 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
3090 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3091 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3092 IntOp, ExtOp, OpNode>;
3093 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3094 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3095 IntOp, ExtOp, OpNode>;
3096 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3097 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3098 IntOp, ExtOp, OpNode>;
3102 // Neon Pairwise long 2-register intrinsics,
3103 // element sizes of 8, 16 and 32 bits:
3104 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3105 bits<5> op11_7, bit op4,
3106 string OpcodeStr, string Dt, Intrinsic IntOp> {
3107 // 64-bit vector types.
3108 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3109 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3110 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3111 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3112 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3113 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3115 // 128-bit vector types.
3116 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3117 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3118 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3119 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3120 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3121 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3125 // Neon Pairwise long 2-register accumulate intrinsics,
3126 // element sizes of 8, 16 and 32 bits:
3127 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3128 bits<5> op11_7, bit op4,
3129 string OpcodeStr, string Dt, Intrinsic IntOp> {
3130 // 64-bit vector types.
3131 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3132 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3133 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3134 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3135 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3136 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3138 // 128-bit vector types.
3139 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3140 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3141 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3142 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3143 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3144 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3148 // Neon 2-register vector shift by immediate,
3149 // with f of either N2RegVShLFrm or N2RegVShRFrm
3150 // element sizes of 8, 16, 32 and 64 bits:
3151 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3152 InstrItinClass itin, string OpcodeStr, string Dt,
3154 // 64-bit vector types.
3155 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3156 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3157 let Inst{21-19} = 0b001; // imm6 = 001xxx
3159 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3160 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3161 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3163 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3164 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3165 let Inst{21} = 0b1; // imm6 = 1xxxxx
3167 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3168 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3171 // 128-bit vector types.
3172 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3173 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3174 let Inst{21-19} = 0b001; // imm6 = 001xxx
3176 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3177 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3178 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3180 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3181 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3182 let Inst{21} = 0b1; // imm6 = 1xxxxx
3184 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3185 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3188 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3189 InstrItinClass itin, string OpcodeStr, string Dt,
3191 // 64-bit vector types.
3192 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3193 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3194 let Inst{21-19} = 0b001; // imm6 = 001xxx
3196 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3197 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3198 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3200 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3201 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3202 let Inst{21} = 0b1; // imm6 = 1xxxxx
3204 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3205 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3208 // 128-bit vector types.
3209 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3210 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3211 let Inst{21-19} = 0b001; // imm6 = 001xxx
3213 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3214 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3215 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3217 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3218 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3219 let Inst{21} = 0b1; // imm6 = 1xxxxx
3221 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3222 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3226 // Neon Shift-Accumulate vector operations,
3227 // element sizes of 8, 16, 32 and 64 bits:
3228 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3229 string OpcodeStr, string Dt, SDNode ShOp> {
3230 // 64-bit vector types.
3231 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3232 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3233 let Inst{21-19} = 0b001; // imm6 = 001xxx
3235 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3236 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3237 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3239 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3240 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3241 let Inst{21} = 0b1; // imm6 = 1xxxxx
3243 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3244 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3247 // 128-bit vector types.
3248 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3249 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3250 let Inst{21-19} = 0b001; // imm6 = 001xxx
3252 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3253 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3254 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3256 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3257 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3258 let Inst{21} = 0b1; // imm6 = 1xxxxx
3260 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3261 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3265 // Neon Shift-Insert vector operations,
3266 // with f of either N2RegVShLFrm or N2RegVShRFrm
3267 // element sizes of 8, 16, 32 and 64 bits:
3268 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3270 // 64-bit vector types.
3271 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3272 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3273 let Inst{21-19} = 0b001; // imm6 = 001xxx
3275 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3276 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3277 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3279 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3280 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3281 let Inst{21} = 0b1; // imm6 = 1xxxxx
3283 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3284 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3287 // 128-bit vector types.
3288 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3289 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3290 let Inst{21-19} = 0b001; // imm6 = 001xxx
3292 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3293 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3294 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3296 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3297 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3298 let Inst{21} = 0b1; // imm6 = 1xxxxx
3300 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3301 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3304 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3306 // 64-bit vector types.
3307 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3308 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3309 let Inst{21-19} = 0b001; // imm6 = 001xxx
3311 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3312 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3313 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3315 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3316 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3317 let Inst{21} = 0b1; // imm6 = 1xxxxx
3319 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3320 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3323 // 128-bit vector types.
3324 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3325 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3326 let Inst{21-19} = 0b001; // imm6 = 001xxx
3328 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3329 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3330 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3332 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3333 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3334 let Inst{21} = 0b1; // imm6 = 1xxxxx
3336 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3337 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3341 // Neon Shift Long operations,
3342 // element sizes of 8, 16, 32 bits:
3343 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3344 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3345 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3346 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
3347 let Inst{21-19} = 0b001; // imm6 = 001xxx
3349 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3350 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
3351 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3353 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3354 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
3355 let Inst{21} = 0b1; // imm6 = 1xxxxx
3359 // Neon Shift Narrow operations,
3360 // element sizes of 16, 32, 64 bits:
3361 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3362 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3364 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3365 OpcodeStr, !strconcat(Dt, "16"),
3366 v8i8, v8i16, shr_imm8, OpNode> {
3367 let Inst{21-19} = 0b001; // imm6 = 001xxx
3369 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3370 OpcodeStr, !strconcat(Dt, "32"),
3371 v4i16, v4i32, shr_imm16, OpNode> {
3372 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3374 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3375 OpcodeStr, !strconcat(Dt, "64"),
3376 v2i32, v2i64, shr_imm32, OpNode> {
3377 let Inst{21} = 0b1; // imm6 = 1xxxxx
3381 //===----------------------------------------------------------------------===//
3382 // Instruction Definitions.
3383 //===----------------------------------------------------------------------===//
3385 // Vector Add Operations.
3387 // VADD : Vector Add (integer and floating-point)
3388 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3390 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3391 v2f32, v2f32, fadd, 1>;
3392 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3393 v4f32, v4f32, fadd, 1>;
3394 // VADDL : Vector Add Long (Q = D + D)
3395 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3396 "vaddl", "s", add, sext, 1>;
3397 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3398 "vaddl", "u", add, zext, 1>;
3399 // VADDW : Vector Add Wide (Q = Q + D)
3400 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3401 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3402 // VHADD : Vector Halving Add
3403 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3404 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3405 "vhadd", "s", int_arm_neon_vhadds, 1>;
3406 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3407 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3408 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3409 // VRHADD : Vector Rounding Halving Add
3410 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3411 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3412 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3413 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3414 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3415 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3416 // VQADD : Vector Saturating Add
3417 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3418 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3419 "vqadd", "s", int_arm_neon_vqadds, 1>;
3420 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3421 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3422 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3423 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3424 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3425 int_arm_neon_vaddhn, 1>;
3426 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3427 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3428 int_arm_neon_vraddhn, 1>;
3430 // Vector Multiply Operations.
3432 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3433 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3434 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3435 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3436 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3437 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3438 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3439 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3440 v2f32, v2f32, fmul, 1>;
3441 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3442 v4f32, v4f32, fmul, 1>;
3443 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3444 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3445 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3448 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3449 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3450 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3451 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3452 (DSubReg_i16_reg imm:$lane))),
3453 (SubReg_i16_lane imm:$lane)))>;
3454 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3455 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3456 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3457 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3458 (DSubReg_i32_reg imm:$lane))),
3459 (SubReg_i32_lane imm:$lane)))>;
3460 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3461 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3462 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3463 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3464 (DSubReg_i32_reg imm:$lane))),
3465 (SubReg_i32_lane imm:$lane)))>;
3467 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3468 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3469 IIC_VMULi16Q, IIC_VMULi32Q,
3470 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3471 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3472 IIC_VMULi16Q, IIC_VMULi32Q,
3473 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3474 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3475 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3477 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3478 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3479 (DSubReg_i16_reg imm:$lane))),
3480 (SubReg_i16_lane imm:$lane)))>;
3481 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3482 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3484 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3485 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3486 (DSubReg_i32_reg imm:$lane))),
3487 (SubReg_i32_lane imm:$lane)))>;
3489 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3490 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3491 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3492 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3493 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3494 IIC_VMULi16Q, IIC_VMULi32Q,
3495 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3496 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3497 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3499 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3500 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3501 (DSubReg_i16_reg imm:$lane))),
3502 (SubReg_i16_lane imm:$lane)))>;
3503 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3504 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3506 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3507 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3508 (DSubReg_i32_reg imm:$lane))),
3509 (SubReg_i32_lane imm:$lane)))>;
3511 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3512 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3513 "vmull", "s", NEONvmulls, 1>;
3514 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3515 "vmull", "u", NEONvmullu, 1>;
3516 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3517 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3518 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3519 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3521 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3522 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3523 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3524 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3525 "vqdmull", "s", int_arm_neon_vqdmull>;
3527 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3529 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3530 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3531 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3532 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3533 v2f32, fmul_su, fadd_mlx>,
3534 Requires<[HasNEON, UseFPVMLx]>;
3535 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3536 v4f32, fmul_su, fadd_mlx>,
3537 Requires<[HasNEON, UseFPVMLx]>;
3538 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3539 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3540 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3541 v2f32, fmul_su, fadd_mlx>,
3542 Requires<[HasNEON, UseFPVMLx]>;
3543 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3544 v4f32, v2f32, fmul_su, fadd_mlx>,
3545 Requires<[HasNEON, UseFPVMLx]>;
3547 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3548 (mul (v8i16 QPR:$src2),
3549 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3550 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3551 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3552 (DSubReg_i16_reg imm:$lane))),
3553 (SubReg_i16_lane imm:$lane)))>;
3555 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3556 (mul (v4i32 QPR:$src2),
3557 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3558 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3559 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3560 (DSubReg_i32_reg imm:$lane))),
3561 (SubReg_i32_lane imm:$lane)))>;
3563 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3564 (fmul_su (v4f32 QPR:$src2),
3565 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3566 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3568 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3569 (DSubReg_i32_reg imm:$lane))),
3570 (SubReg_i32_lane imm:$lane)))>,
3571 Requires<[HasNEON, UseFPVMLx]>;
3573 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3574 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3575 "vmlal", "s", NEONvmulls, add>;
3576 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3577 "vmlal", "u", NEONvmullu, add>;
3579 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3580 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3582 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3583 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3584 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3585 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3587 // VMLS : Vector Multiply Subtract (integer and floating-point)
3588 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3589 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3590 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3591 v2f32, fmul_su, fsub_mlx>,
3592 Requires<[HasNEON, UseFPVMLx]>;
3593 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3594 v4f32, fmul_su, fsub_mlx>,
3595 Requires<[HasNEON, UseFPVMLx]>;
3596 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3597 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3598 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3599 v2f32, fmul_su, fsub_mlx>,
3600 Requires<[HasNEON, UseFPVMLx]>;
3601 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3602 v4f32, v2f32, fmul_su, fsub_mlx>,
3603 Requires<[HasNEON, UseFPVMLx]>;
3605 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3606 (mul (v8i16 QPR:$src2),
3607 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3608 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3609 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3610 (DSubReg_i16_reg imm:$lane))),
3611 (SubReg_i16_lane imm:$lane)))>;
3613 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3614 (mul (v4i32 QPR:$src2),
3615 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3616 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3617 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3618 (DSubReg_i32_reg imm:$lane))),
3619 (SubReg_i32_lane imm:$lane)))>;
3621 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3622 (fmul_su (v4f32 QPR:$src2),
3623 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3624 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3625 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3626 (DSubReg_i32_reg imm:$lane))),
3627 (SubReg_i32_lane imm:$lane)))>,
3628 Requires<[HasNEON, UseFPVMLx]>;
3630 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3631 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3632 "vmlsl", "s", NEONvmulls, sub>;
3633 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3634 "vmlsl", "u", NEONvmullu, sub>;
3636 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3637 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3639 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3640 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3641 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3642 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3644 // Vector Subtract Operations.
3646 // VSUB : Vector Subtract (integer and floating-point)
3647 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3648 "vsub", "i", sub, 0>;
3649 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3650 v2f32, v2f32, fsub, 0>;
3651 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3652 v4f32, v4f32, fsub, 0>;
3653 // VSUBL : Vector Subtract Long (Q = D - D)
3654 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3655 "vsubl", "s", sub, sext, 0>;
3656 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3657 "vsubl", "u", sub, zext, 0>;
3658 // VSUBW : Vector Subtract Wide (Q = Q - D)
3659 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3660 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3661 // VHSUB : Vector Halving Subtract
3662 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3663 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3664 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3665 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3666 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3667 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3668 // VQSUB : Vector Saturing Subtract
3669 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3670 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3671 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3672 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3673 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3674 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3675 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3676 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3677 int_arm_neon_vsubhn, 0>;
3678 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3679 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3680 int_arm_neon_vrsubhn, 0>;
3682 // Vector Comparisons.
3684 // VCEQ : Vector Compare Equal
3685 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3686 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3687 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3689 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3692 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3693 "$Vd, $Vm, #0", NEONvceqz>;
3695 // VCGE : Vector Compare Greater Than or Equal
3696 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3697 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3698 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3699 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3700 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3702 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3705 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3706 "$Vd, $Vm, #0", NEONvcgez>;
3707 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3708 "$Vd, $Vm, #0", NEONvclez>;
3710 // VCGT : Vector Compare Greater Than
3711 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3712 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3713 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3714 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3715 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3717 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3720 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3721 "$Vd, $Vm, #0", NEONvcgtz>;
3722 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3723 "$Vd, $Vm, #0", NEONvcltz>;
3725 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3726 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3727 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3728 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3729 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3730 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3731 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3732 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3733 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3734 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3735 // VTST : Vector Test Bits
3736 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3737 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3739 // Vector Bitwise Operations.
3741 def vnotd : PatFrag<(ops node:$in),
3742 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3743 def vnotq : PatFrag<(ops node:$in),
3744 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3747 // VAND : Vector Bitwise AND
3748 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3749 v2i32, v2i32, and, 1>;
3750 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3751 v4i32, v4i32, and, 1>;
3753 // VEOR : Vector Bitwise Exclusive OR
3754 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3755 v2i32, v2i32, xor, 1>;
3756 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3757 v4i32, v4i32, xor, 1>;
3759 // VORR : Vector Bitwise OR
3760 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3761 v2i32, v2i32, or, 1>;
3762 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3763 v4i32, v4i32, or, 1>;
3765 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3766 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
3768 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3770 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3771 let Inst{9} = SIMM{9};
3774 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3775 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
3777 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3779 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3780 let Inst{10-9} = SIMM{10-9};
3783 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3784 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
3786 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3788 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3789 let Inst{9} = SIMM{9};
3792 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3793 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
3795 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3797 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3798 let Inst{10-9} = SIMM{10-9};
3802 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3803 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3804 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3805 "vbic", "$Vd, $Vn, $Vm", "",
3806 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
3807 (vnotd DPR:$Vm))))]>;
3808 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3809 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3810 "vbic", "$Vd, $Vn, $Vm", "",
3811 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
3812 (vnotq QPR:$Vm))))]>;
3814 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3815 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
3817 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3819 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3820 let Inst{9} = SIMM{9};
3823 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3824 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
3826 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3828 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3829 let Inst{10-9} = SIMM{10-9};
3832 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3833 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
3835 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3837 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3838 let Inst{9} = SIMM{9};
3841 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3842 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
3844 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3846 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3847 let Inst{10-9} = SIMM{10-9};
3850 // VORN : Vector Bitwise OR NOT
3851 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
3852 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3853 "vorn", "$Vd, $Vn, $Vm", "",
3854 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
3855 (vnotd DPR:$Vm))))]>;
3856 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
3857 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3858 "vorn", "$Vd, $Vn, $Vm", "",
3859 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
3860 (vnotq QPR:$Vm))))]>;
3862 // VMVN : Vector Bitwise NOT (Immediate)
3864 let isReMaterializable = 1 in {
3866 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
3867 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
3868 "vmvn", "i16", "$Vd, $SIMM", "",
3869 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3870 let Inst{9} = SIMM{9};
3873 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
3874 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
3875 "vmvn", "i16", "$Vd, $SIMM", "",
3876 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3877 let Inst{9} = SIMM{9};
3880 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
3881 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
3882 "vmvn", "i32", "$Vd, $SIMM", "",
3883 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3884 let Inst{11-8} = SIMM{11-8};
3887 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
3888 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
3889 "vmvn", "i32", "$Vd, $SIMM", "",
3890 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3891 let Inst{11-8} = SIMM{11-8};
3895 // VMVN : Vector Bitwise NOT
3896 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3897 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
3898 "vmvn", "$Vd, $Vm", "",
3899 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
3900 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3901 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
3902 "vmvn", "$Vd, $Vm", "",
3903 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
3904 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3905 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3907 // VBSL : Vector Bitwise Select
3908 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3909 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3910 N3RegFrm, IIC_VCNTiD,
3911 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3913 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
3915 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
3916 (and DPR:$Vm, (vnotd DPR:$Vd)))),
3917 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
3919 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3920 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3921 N3RegFrm, IIC_VCNTiQ,
3922 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3924 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
3926 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
3927 (and QPR:$Vm, (vnotq QPR:$Vd)))),
3928 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
3930 // VBIF : Vector Bitwise Insert if False
3931 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3932 // FIXME: This instruction's encoding MAY NOT BE correct.
3933 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
3934 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3935 N3RegFrm, IIC_VBINiD,
3936 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3937 [/* For disassembly only; pattern left blank */]>;
3938 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
3939 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3940 N3RegFrm, IIC_VBINiQ,
3941 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3942 [/* For disassembly only; pattern left blank */]>;
3944 // VBIT : Vector Bitwise Insert if True
3945 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
3946 // FIXME: This instruction's encoding MAY NOT BE correct.
3947 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
3948 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3949 N3RegFrm, IIC_VBINiD,
3950 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3951 [/* For disassembly only; pattern left blank */]>;
3952 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
3953 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3954 N3RegFrm, IIC_VBINiQ,
3955 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3956 [/* For disassembly only; pattern left blank */]>;
3958 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
3959 // for equivalent operations with different register constraints; it just
3962 // Vector Absolute Differences.
3964 // VABD : Vector Absolute Difference
3965 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
3966 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3967 "vabd", "s", int_arm_neon_vabds, 1>;
3968 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
3969 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3970 "vabd", "u", int_arm_neon_vabdu, 1>;
3971 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
3972 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
3973 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
3974 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
3976 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
3977 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
3978 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
3979 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3980 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3982 // VABA : Vector Absolute Difference and Accumulate
3983 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3984 "vaba", "s", int_arm_neon_vabds, add>;
3985 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3986 "vaba", "u", int_arm_neon_vabdu, add>;
3988 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3989 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3990 "vabal", "s", int_arm_neon_vabds, zext, add>;
3991 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3992 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3994 // Vector Maximum and Minimum.
3996 // VMAX : Vector Maximum
3997 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3998 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3999 "vmax", "s", int_arm_neon_vmaxs, 1>;
4000 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4001 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4002 "vmax", "u", int_arm_neon_vmaxu, 1>;
4003 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4005 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4006 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4008 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4010 // VMIN : Vector Minimum
4011 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4012 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4013 "vmin", "s", int_arm_neon_vmins, 1>;
4014 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4015 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4016 "vmin", "u", int_arm_neon_vminu, 1>;
4017 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4019 v2f32, v2f32, int_arm_neon_vmins, 1>;
4020 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4022 v4f32, v4f32, int_arm_neon_vmins, 1>;
4024 // Vector Pairwise Operations.
4026 // VPADD : Vector Pairwise Add
4027 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4029 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4030 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4032 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4033 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4035 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4036 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4037 IIC_VPBIND, "vpadd", "f32",
4038 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4040 // VPADDL : Vector Pairwise Add Long
4041 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4042 int_arm_neon_vpaddls>;
4043 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4044 int_arm_neon_vpaddlu>;
4046 // VPADAL : Vector Pairwise Add and Accumulate Long
4047 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4048 int_arm_neon_vpadals>;
4049 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4050 int_arm_neon_vpadalu>;
4052 // VPMAX : Vector Pairwise Maximum
4053 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4054 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4055 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4056 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4057 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4058 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4059 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4060 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4061 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4062 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4063 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4064 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4065 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4066 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4068 // VPMIN : Vector Pairwise Minimum
4069 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4070 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4071 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4072 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4073 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4074 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4075 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4076 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4077 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4078 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4079 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4080 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4081 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4082 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4084 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4086 // VRECPE : Vector Reciprocal Estimate
4087 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4088 IIC_VUNAD, "vrecpe", "u32",
4089 v2i32, v2i32, int_arm_neon_vrecpe>;
4090 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4091 IIC_VUNAQ, "vrecpe", "u32",
4092 v4i32, v4i32, int_arm_neon_vrecpe>;
4093 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4094 IIC_VUNAD, "vrecpe", "f32",
4095 v2f32, v2f32, int_arm_neon_vrecpe>;
4096 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4097 IIC_VUNAQ, "vrecpe", "f32",
4098 v4f32, v4f32, int_arm_neon_vrecpe>;
4100 // VRECPS : Vector Reciprocal Step
4101 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4102 IIC_VRECSD, "vrecps", "f32",
4103 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4104 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4105 IIC_VRECSQ, "vrecps", "f32",
4106 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4108 // VRSQRTE : Vector Reciprocal Square Root Estimate
4109 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4110 IIC_VUNAD, "vrsqrte", "u32",
4111 v2i32, v2i32, int_arm_neon_vrsqrte>;
4112 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4113 IIC_VUNAQ, "vrsqrte", "u32",
4114 v4i32, v4i32, int_arm_neon_vrsqrte>;
4115 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4116 IIC_VUNAD, "vrsqrte", "f32",
4117 v2f32, v2f32, int_arm_neon_vrsqrte>;
4118 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4119 IIC_VUNAQ, "vrsqrte", "f32",
4120 v4f32, v4f32, int_arm_neon_vrsqrte>;
4122 // VRSQRTS : Vector Reciprocal Square Root Step
4123 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4124 IIC_VRECSD, "vrsqrts", "f32",
4125 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4126 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4127 IIC_VRECSQ, "vrsqrts", "f32",
4128 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4132 // VSHL : Vector Shift
4133 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4134 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4135 "vshl", "s", int_arm_neon_vshifts>;
4136 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4137 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4138 "vshl", "u", int_arm_neon_vshiftu>;
4140 // VSHL : Vector Shift Left (Immediate)
4141 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4143 // VSHR : Vector Shift Right (Immediate)
4144 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
4145 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
4147 // VSHLL : Vector Shift Left Long
4148 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4149 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4151 // VSHLL : Vector Shift Left Long (with maximum shift count)
4152 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4153 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4154 ValueType OpTy, SDNode OpNode>
4155 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4156 ResTy, OpTy, OpNode> {
4157 let Inst{21-16} = op21_16;
4158 let DecoderMethod = "DecodeVSHLMaxInstruction";
4160 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4161 v8i16, v8i8, NEONvshlli>;
4162 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4163 v4i32, v4i16, NEONvshlli>;
4164 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4165 v2i64, v2i32, NEONvshlli>;
4167 // VSHRN : Vector Shift Right and Narrow
4168 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4171 // VRSHL : Vector Rounding Shift
4172 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4173 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4174 "vrshl", "s", int_arm_neon_vrshifts>;
4175 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4176 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4177 "vrshl", "u", int_arm_neon_vrshiftu>;
4178 // VRSHR : Vector Rounding Shift Right
4179 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
4180 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
4182 // VRSHRN : Vector Rounding Shift Right and Narrow
4183 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4186 // VQSHL : Vector Saturating Shift
4187 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4188 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4189 "vqshl", "s", int_arm_neon_vqshifts>;
4190 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4191 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4192 "vqshl", "u", int_arm_neon_vqshiftu>;
4193 // VQSHL : Vector Saturating Shift Left (Immediate)
4194 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4195 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4197 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4198 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4200 // VQSHRN : Vector Saturating Shift Right and Narrow
4201 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4203 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4206 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4207 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4210 // VQRSHL : Vector Saturating Rounding Shift
4211 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4212 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4213 "vqrshl", "s", int_arm_neon_vqrshifts>;
4214 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4215 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4216 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4218 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4219 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4221 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4224 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4225 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4228 // VSRA : Vector Shift Right and Accumulate
4229 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4230 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4231 // VRSRA : Vector Rounding Shift Right and Accumulate
4232 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4233 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4235 // VSLI : Vector Shift Left and Insert
4236 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4238 // VSRI : Vector Shift Right and Insert
4239 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4241 // Vector Absolute and Saturating Absolute.
4243 // VABS : Vector Absolute Value
4244 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4245 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4247 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4248 IIC_VUNAD, "vabs", "f32",
4249 v2f32, v2f32, int_arm_neon_vabs>;
4250 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4251 IIC_VUNAQ, "vabs", "f32",
4252 v4f32, v4f32, int_arm_neon_vabs>;
4254 // VQABS : Vector Saturating Absolute Value
4255 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4256 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4257 int_arm_neon_vqabs>;
4261 def vnegd : PatFrag<(ops node:$in),
4262 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4263 def vnegq : PatFrag<(ops node:$in),
4264 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4266 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4267 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4268 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4269 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4270 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4271 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4272 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4273 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4275 // VNEG : Vector Negate (integer)
4276 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4277 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4278 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4279 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4280 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4281 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4283 // VNEG : Vector Negate (floating-point)
4284 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4285 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4286 "vneg", "f32", "$Vd, $Vm", "",
4287 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4288 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4289 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4290 "vneg", "f32", "$Vd, $Vm", "",
4291 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4293 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4294 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4295 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4296 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4297 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4298 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4300 // VQNEG : Vector Saturating Negate
4301 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4302 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4303 int_arm_neon_vqneg>;
4305 // Vector Bit Counting Operations.
4307 // VCLS : Vector Count Leading Sign Bits
4308 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4309 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4311 // VCLZ : Vector Count Leading Zeros
4312 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4313 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4315 // VCNT : Vector Count One Bits
4316 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4317 IIC_VCNTiD, "vcnt", "8",
4318 v8i8, v8i8, int_arm_neon_vcnt>;
4319 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4320 IIC_VCNTiQ, "vcnt", "8",
4321 v16i8, v16i8, int_arm_neon_vcnt>;
4323 // Vector Swap -- for disassembly only.
4324 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4325 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4326 "vswp", "$Vd, $Vm", "", []>;
4327 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4328 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4329 "vswp", "$Vd, $Vm", "", []>;
4331 // Vector Move Operations.
4333 // VMOV : Vector Move (Register)
4334 def : InstAlias<"vmov${p} $Vd, $Vm",
4335 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
4336 def : InstAlias<"vmov${p} $Vd, $Vm",
4337 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
4339 // VMOV : Vector Move (Immediate)
4341 let isReMaterializable = 1 in {
4342 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4343 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4344 "vmov", "i8", "$Vd, $SIMM", "",
4345 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4346 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4347 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4348 "vmov", "i8", "$Vd, $SIMM", "",
4349 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4351 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4352 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4353 "vmov", "i16", "$Vd, $SIMM", "",
4354 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4355 let Inst{9} = SIMM{9};
4358 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4359 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4360 "vmov", "i16", "$Vd, $SIMM", "",
4361 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4362 let Inst{9} = SIMM{9};
4365 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4366 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4367 "vmov", "i32", "$Vd, $SIMM", "",
4368 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4369 let Inst{11-8} = SIMM{11-8};
4372 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4373 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4374 "vmov", "i32", "$Vd, $SIMM", "",
4375 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4376 let Inst{11-8} = SIMM{11-8};
4379 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4380 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4381 "vmov", "i64", "$Vd, $SIMM", "",
4382 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4383 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4384 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4385 "vmov", "i64", "$Vd, $SIMM", "",
4386 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4387 } // isReMaterializable
4389 // VMOV : Vector Get Lane (move scalar to ARM core register)
4391 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4392 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4393 IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
4394 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4396 let Inst{21} = lane{2};
4397 let Inst{6-5} = lane{1-0};
4399 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4400 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4401 IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
4402 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4404 let Inst{21} = lane{1};
4405 let Inst{6} = lane{0};
4407 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4408 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4409 IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
4410 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4412 let Inst{21} = lane{2};
4413 let Inst{6-5} = lane{1-0};
4415 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4416 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4417 IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
4418 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4420 let Inst{21} = lane{1};
4421 let Inst{6} = lane{0};
4423 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4424 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4425 IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
4426 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4428 let Inst{21} = lane{0};
4430 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4431 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4432 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4433 (DSubReg_i8_reg imm:$lane))),
4434 (SubReg_i8_lane imm:$lane))>;
4435 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4436 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4437 (DSubReg_i16_reg imm:$lane))),
4438 (SubReg_i16_lane imm:$lane))>;
4439 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4440 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4441 (DSubReg_i8_reg imm:$lane))),
4442 (SubReg_i8_lane imm:$lane))>;
4443 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4444 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4445 (DSubReg_i16_reg imm:$lane))),
4446 (SubReg_i16_lane imm:$lane))>;
4447 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4448 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4449 (DSubReg_i32_reg imm:$lane))),
4450 (SubReg_i32_lane imm:$lane))>;
4451 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4452 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4453 (SSubReg_f32_reg imm:$src2))>;
4454 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4455 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4456 (SSubReg_f32_reg imm:$src2))>;
4457 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4458 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4459 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4460 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4463 // VMOV : Vector Set Lane (move ARM core register to scalar)
4465 let Constraints = "$src1 = $V" in {
4466 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4467 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4468 IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
4469 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4470 GPR:$R, imm:$lane))]> {
4471 let Inst{21} = lane{2};
4472 let Inst{6-5} = lane{1-0};
4474 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4475 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4476 IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
4477 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4478 GPR:$R, imm:$lane))]> {
4479 let Inst{21} = lane{1};
4480 let Inst{6} = lane{0};
4482 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4483 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4484 IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
4485 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4486 GPR:$R, imm:$lane))]> {
4487 let Inst{21} = lane{0};
4490 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4491 (v16i8 (INSERT_SUBREG QPR:$src1,
4492 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4493 (DSubReg_i8_reg imm:$lane))),
4494 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4495 (DSubReg_i8_reg imm:$lane)))>;
4496 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4497 (v8i16 (INSERT_SUBREG QPR:$src1,
4498 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4499 (DSubReg_i16_reg imm:$lane))),
4500 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4501 (DSubReg_i16_reg imm:$lane)))>;
4502 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4503 (v4i32 (INSERT_SUBREG QPR:$src1,
4504 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4505 (DSubReg_i32_reg imm:$lane))),
4506 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4507 (DSubReg_i32_reg imm:$lane)))>;
4509 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4510 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4511 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4512 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4513 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4514 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4516 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4517 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4518 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4519 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4521 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4522 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4523 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4524 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4525 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4526 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4528 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4529 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4530 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4531 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4532 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4533 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4535 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4536 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4537 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4539 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4540 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4541 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4543 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4544 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4545 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4548 // VDUP : Vector Duplicate (from ARM core register to all elements)
4550 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4551 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4552 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4553 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4554 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4555 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4556 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4557 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4559 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4560 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4561 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4562 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4563 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4564 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4566 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
4567 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
4569 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4571 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4572 ValueType Ty, Operand IdxTy>
4573 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4574 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
4575 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4577 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4578 ValueType ResTy, ValueType OpTy, Operand IdxTy>
4579 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4580 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
4581 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4582 VectorIndex32:$lane)))]>;
4584 // Inst{19-16} is partially specified depending on the element size.
4586 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
4588 let Inst{19-17} = lane{2-0};
4590 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
4592 let Inst{19-18} = lane{1-0};
4594 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
4596 let Inst{19} = lane{0};
4598 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
4600 let Inst{19-17} = lane{2-0};
4602 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
4604 let Inst{19-18} = lane{1-0};
4606 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
4608 let Inst{19} = lane{0};
4611 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4612 (VDUPLN32d DPR:$Vm, imm:$lane)>;
4614 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4615 (VDUPLN32q DPR:$Vm, imm:$lane)>;
4617 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4618 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4619 (DSubReg_i8_reg imm:$lane))),
4620 (SubReg_i8_lane imm:$lane)))>;
4621 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4622 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4623 (DSubReg_i16_reg imm:$lane))),
4624 (SubReg_i16_lane imm:$lane)))>;
4625 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4626 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4627 (DSubReg_i32_reg imm:$lane))),
4628 (SubReg_i32_lane imm:$lane)))>;
4629 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4630 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
4631 (DSubReg_i32_reg imm:$lane))),
4632 (SubReg_i32_lane imm:$lane)))>;
4634 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4635 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4636 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4637 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4639 // VMOVN : Vector Narrowing Move
4640 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4641 "vmovn", "i", trunc>;
4642 // VQMOVN : Vector Saturating Narrowing Move
4643 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4644 "vqmovn", "s", int_arm_neon_vqmovns>;
4645 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4646 "vqmovn", "u", int_arm_neon_vqmovnu>;
4647 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4648 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4649 // VMOVL : Vector Lengthening Move
4650 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4651 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4653 // Vector Conversions.
4655 // VCVT : Vector Convert Between Floating-Point and Integers
4656 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4657 v2i32, v2f32, fp_to_sint>;
4658 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4659 v2i32, v2f32, fp_to_uint>;
4660 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4661 v2f32, v2i32, sint_to_fp>;
4662 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4663 v2f32, v2i32, uint_to_fp>;
4665 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4666 v4i32, v4f32, fp_to_sint>;
4667 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4668 v4i32, v4f32, fp_to_uint>;
4669 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4670 v4f32, v4i32, sint_to_fp>;
4671 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4672 v4f32, v4i32, uint_to_fp>;
4674 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4675 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4676 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4677 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4678 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4679 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4680 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4681 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4682 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4684 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4685 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4686 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4687 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4688 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4689 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4690 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4691 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4693 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
4694 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
4695 IIC_VUNAQ, "vcvt", "f16.f32",
4696 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
4697 Requires<[HasNEON, HasFP16]>;
4698 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
4699 IIC_VUNAQ, "vcvt", "f32.f16",
4700 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
4701 Requires<[HasNEON, HasFP16]>;
4705 // VREV64 : Vector Reverse elements within 64-bit doublewords
4707 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4708 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4709 (ins DPR:$Vm), IIC_VMOVD,
4710 OpcodeStr, Dt, "$Vd, $Vm", "",
4711 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4712 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4713 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4714 (ins QPR:$Vm), IIC_VMOVQ,
4715 OpcodeStr, Dt, "$Vd, $Vm", "",
4716 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4718 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4719 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4720 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4721 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
4723 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4724 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4725 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4726 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
4728 // VREV32 : Vector Reverse elements within 32-bit words
4730 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4731 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4732 (ins DPR:$Vm), IIC_VMOVD,
4733 OpcodeStr, Dt, "$Vd, $Vm", "",
4734 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4735 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4736 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4737 (ins QPR:$Vm), IIC_VMOVQ,
4738 OpcodeStr, Dt, "$Vd, $Vm", "",
4739 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4741 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4742 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4744 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4745 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4747 // VREV16 : Vector Reverse elements within 16-bit halfwords
4749 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4750 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4751 (ins DPR:$Vm), IIC_VMOVD,
4752 OpcodeStr, Dt, "$Vd, $Vm", "",
4753 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4754 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4755 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4756 (ins QPR:$Vm), IIC_VMOVQ,
4757 OpcodeStr, Dt, "$Vd, $Vm", "",
4758 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4760 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4761 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4763 // Other Vector Shuffles.
4765 // Aligned extractions: really just dropping registers
4767 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
4768 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
4769 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
4771 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
4773 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
4775 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
4777 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
4779 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
4782 // VEXT : Vector Extract
4784 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4785 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4786 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4787 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4788 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4789 (Ty DPR:$Vm), imm:$index)))]> {
4791 let Inst{11-8} = index{3-0};
4794 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4795 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4796 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4797 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4798 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4799 (Ty QPR:$Vm), imm:$index)))]> {
4801 let Inst{11-8} = index{3-0};
4804 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4805 let Inst{11-8} = index{3-0};
4807 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4808 let Inst{11-9} = index{2-0};
4811 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4812 let Inst{11-10} = index{1-0};
4813 let Inst{9-8} = 0b00;
4815 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
4818 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
4820 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4821 let Inst{11-8} = index{3-0};
4823 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4824 let Inst{11-9} = index{2-0};
4827 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4828 let Inst{11-10} = index{1-0};
4829 let Inst{9-8} = 0b00;
4831 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
4834 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
4836 // VTRN : Vector Transpose
4838 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4839 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4840 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4842 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4843 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4844 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4846 // VUZP : Vector Unzip (Deinterleave)
4848 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4849 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4850 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4852 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4853 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4854 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4856 // VZIP : Vector Zip (Interleave)
4858 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4859 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4860 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4862 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4863 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4864 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4866 // Vector Table Lookup and Table Extension.
4868 // VTBL : Vector Table Lookup
4869 let DecoderMethod = "DecodeTBLInstruction" in {
4871 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4872 (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4873 "vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
4874 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
4875 let hasExtraSrcRegAllocReq = 1 in {
4877 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4878 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4879 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4881 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4882 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4883 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4885 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4886 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4888 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4889 } // hasExtraSrcRegAllocReq = 1
4892 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4894 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4896 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4898 // VTBX : Vector Table Extension
4900 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4901 (ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4902 "vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
4903 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4904 DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
4905 let hasExtraSrcRegAllocReq = 1 in {
4907 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4908 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4909 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4911 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4912 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4913 NVTBLFrm, IIC_VTBX3,
4914 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4917 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4918 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4919 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4921 } // hasExtraSrcRegAllocReq = 1
4924 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4925 IIC_VTBX2, "$orig = $dst", []>;
4927 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4928 IIC_VTBX3, "$orig = $dst", []>;
4930 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4931 IIC_VTBX4, "$orig = $dst", []>;
4932 } // DecoderMethod = "DecodeTBLInstruction"
4934 //===----------------------------------------------------------------------===//
4935 // NEON instructions for single-precision FP math
4936 //===----------------------------------------------------------------------===//
4938 class N2VSPat<SDNode OpNode, NeonI Inst>
4939 : NEONFPPat<(f32 (OpNode SPR:$a)),
4941 (v2f32 (COPY_TO_REGCLASS (Inst
4943 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4944 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
4946 class N3VSPat<SDNode OpNode, NeonI Inst>
4947 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
4949 (v2f32 (COPY_TO_REGCLASS (Inst
4951 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4954 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4955 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4957 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
4958 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
4960 (v2f32 (COPY_TO_REGCLASS (Inst
4962 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4965 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4968 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4969 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4971 def : N3VSPat<fadd, VADDfd>;
4972 def : N3VSPat<fsub, VSUBfd>;
4973 def : N3VSPat<fmul, VMULfd>;
4974 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
4975 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4976 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
4977 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4978 def : N2VSPat<fabs, VABSfd>;
4979 def : N2VSPat<fneg, VNEGfd>;
4980 def : N3VSPat<NEONfmax, VMAXfd>;
4981 def : N3VSPat<NEONfmin, VMINfd>;
4982 def : N2VSPat<arm_ftosi, VCVTf2sd>;
4983 def : N2VSPat<arm_ftoui, VCVTf2ud>;
4984 def : N2VSPat<arm_sitof, VCVTs2fd>;
4985 def : N2VSPat<arm_uitof, VCVTu2fd>;
4987 //===----------------------------------------------------------------------===//
4988 // Non-Instruction Patterns
4989 //===----------------------------------------------------------------------===//
4992 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
4993 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
4994 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
4995 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
4996 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
4997 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
4998 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
4999 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
5000 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
5001 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
5002 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
5003 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
5004 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
5005 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
5006 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
5007 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
5008 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
5009 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
5010 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
5011 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
5012 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
5013 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
5014 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
5015 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
5016 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
5017 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
5018 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
5019 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
5020 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
5021 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
5023 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
5024 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
5025 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
5026 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
5027 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
5028 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
5029 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5030 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
5031 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
5032 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
5033 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5034 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5035 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5036 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5037 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5038 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
5039 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
5040 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5041 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
5042 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
5043 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
5044 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
5045 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5046 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
5047 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
5048 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
5049 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
5050 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5051 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
5052 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;