1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
20 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
21 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
22 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
23 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
24 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
25 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
27 // Types for vector shift by immediates. The "SHX" version is for long and
28 // narrow operations where the source and destination vectors have different
29 // types. The "SHINS" version is for shift and insert operations.
30 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
32 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
34 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
37 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
38 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
39 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
40 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
41 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
42 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
43 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
45 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
46 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
47 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
49 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
50 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
51 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
52 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
53 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
54 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
56 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
57 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
58 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
60 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
61 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
63 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
65 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
66 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
68 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
70 // VDUPLANE can produce a quad-register result from a double-register source,
71 // so the result is not constrained to match the source.
72 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
73 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
76 def SDTARMVLD2 : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
77 def SDTARMVLD3 : SDTypeProfile<3, 1, [SDTCisSameAs<0, 1>,
78 SDTCisSameAs<0, 2>, SDTCisPtrTy<3>]>;
79 def SDTARMVLD4 : SDTypeProfile<4, 1, [SDTCisSameAs<0, 1>,
81 SDTCisSameAs<0, 3>, SDTCisPtrTy<4>]>;
82 def NEONvld2d : SDNode<"ARMISD::VLD2D", SDTARMVLD2,
83 [SDNPHasChain, SDNPMayLoad]>;
84 def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD3,
85 [SDNPHasChain, SDNPMayLoad]>;
86 def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD4,
87 [SDNPHasChain, SDNPMayLoad]>;
89 def SDTARMVST2 : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>]>;
90 def SDTARMVST3 : SDTypeProfile<0, 4, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
92 def SDTARMVST4 : SDTypeProfile<0, 5, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
96 def NEONvst2d : SDNode<"ARMISD::VST2D", SDTARMVST2,
97 [SDNPHasChain, SDNPMayStore]>;
98 def NEONvst3d : SDNode<"ARMISD::VST3D", SDTARMVST3,
99 [SDNPHasChain, SDNPMayStore]>;
100 def NEONvst4d : SDNode<"ARMISD::VST4D", SDTARMVST4,
101 [SDNPHasChain, SDNPMayStore]>;
103 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
104 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
105 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
107 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
108 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
109 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
110 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
112 //===----------------------------------------------------------------------===//
113 // NEON operand definitions
114 //===----------------------------------------------------------------------===//
116 // addrmode_neonldstm := reg
118 /* TODO: Take advantage of vldm.
119 def addrmode_neonldstm : Operand<i32>,
120 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> {
121 let PrintMethod = "printAddrNeonLdStMOperand";
122 let MIOperandInfo = (ops GPR, i32imm);
126 //===----------------------------------------------------------------------===//
127 // NEON load / store instructions
128 //===----------------------------------------------------------------------===//
130 /* TODO: Take advantage of vldm.
132 def VLDMD : NI<(outs),
133 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
135 "vldm${addr:submode} ${addr:base}, $dst1",
137 let Inst{27-25} = 0b110;
139 let Inst{11-9} = 0b101;
142 def VLDMS : NI<(outs),
143 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
145 "vldm${addr:submode} ${addr:base}, $dst1",
147 let Inst{27-25} = 0b110;
149 let Inst{11-9} = 0b101;
154 // Use vldmia to load a Q register as a D register pair.
155 def VLDRQ : NI4<(outs QPR:$dst), (ins addrmode4:$addr),
157 "vldmia $addr, ${dst:dregpair}",
158 [(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]> {
159 let Inst{27-25} = 0b110;
160 let Inst{24} = 0; // P bit
161 let Inst{23} = 1; // U bit
163 let Inst{11-9} = 0b101;
166 // Use vstmia to store a Q register as a D register pair.
167 def VSTRQ : NI4<(outs), (ins QPR:$src, addrmode4:$addr),
169 "vstmia $addr, ${src:dregpair}",
170 [(store (v2f64 QPR:$src), addrmode4:$addr)]> {
171 let Inst{27-25} = 0b110;
172 let Inst{24} = 0; // P bit
173 let Inst{23} = 1; // U bit
175 let Inst{11-9} = 0b101;
178 // VLD1 : Vector Load (multiple single elements)
179 class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
180 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr),
182 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"),
183 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
184 class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
185 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr),
187 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"),
188 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>;
190 def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1>;
191 def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1>;
192 def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1>;
193 def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1>;
194 def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1>;
196 def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1>;
197 def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1>;
198 def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1>;
199 def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1>;
200 def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1>;
204 // VLD2 : Vector Load (multiple 2-element structures)
205 class VLD2D<string OpcodeStr>
206 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr),
208 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), []>;
210 def VLD2d8 : VLD2D<"vld2.8">;
211 def VLD2d16 : VLD2D<"vld2.16">;
212 def VLD2d32 : VLD2D<"vld2.32">;
214 // VLD3 : Vector Load (multiple 3-element structures)
215 class VLD3D<string OpcodeStr>
216 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr),
218 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), []>;
220 def VLD3d8 : VLD3D<"vld3.8">;
221 def VLD3d16 : VLD3D<"vld3.16">;
222 def VLD3d32 : VLD3D<"vld3.32">;
224 // VLD4 : Vector Load (multiple 4-element structures)
225 class VLD4D<string OpcodeStr>
226 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4),
227 (ins addrmode6:$addr),
229 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), []>;
231 def VLD4d8 : VLD4D<"vld4.8">;
232 def VLD4d16 : VLD4D<"vld4.16">;
233 def VLD4d32 : VLD4D<"vld4.32">;
236 // VST1 : Vector Store (multiple single elements)
237 class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
238 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src),
240 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"),
241 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>;
242 class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
243 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src),
245 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"),
246 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
248 def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1>;
249 def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1>;
250 def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1>;
251 def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1>;
252 def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1>;
254 def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1>;
255 def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1>;
256 def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1>;
257 def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1>;
258 def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1>;
260 let mayStore = 1 in {
262 // VST2 : Vector Store (multiple 2-element structures)
263 class VST2D<string OpcodeStr>
264 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2), NoItinerary,
265 !strconcat(OpcodeStr, "\t\\{$src1,$src2\\}, $addr"), []>;
267 def VST2d8 : VST2D<"vst2.8">;
268 def VST2d16 : VST2D<"vst2.16">;
269 def VST2d32 : VST2D<"vst2.32">;
271 // VST3 : Vector Store (multiple 3-element structures)
272 class VST3D<string OpcodeStr>
273 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3),
275 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3\\}, $addr"), []>;
277 def VST3d8 : VST3D<"vst3.8">;
278 def VST3d16 : VST3D<"vst3.16">;
279 def VST3d32 : VST3D<"vst3.32">;
281 // VST4 : Vector Store (multiple 4-element structures)
282 class VST4D<string OpcodeStr>
283 : NLdSt<(outs), (ins addrmode6:$addr,
284 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), NoItinerary,
285 !strconcat(OpcodeStr, "\t\\{$src1,$src2,$src3,$src4\\}, $addr"), []>;
287 def VST4d8 : VST4D<"vst4.8">;
288 def VST4d16 : VST4D<"vst4.16">;
289 def VST4d32 : VST4D<"vst4.32">;
293 //===----------------------------------------------------------------------===//
294 // NEON pattern fragments
295 //===----------------------------------------------------------------------===//
297 // Extract D sub-registers of Q registers.
298 // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6)
299 def DSubReg_i8_reg : SDNodeXForm<imm, [{
300 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32);
302 def DSubReg_i16_reg : SDNodeXForm<imm, [{
303 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32);
305 def DSubReg_i32_reg : SDNodeXForm<imm, [{
306 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32);
308 def DSubReg_f64_reg : SDNodeXForm<imm, [{
309 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32);
312 // Extract S sub-registers of Q registers.
313 // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.)
314 def SSubReg_f32_reg : SDNodeXForm<imm, [{
315 return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32);
318 // Translate lane numbers from Q registers to D subregs.
319 def SubReg_i8_lane : SDNodeXForm<imm, [{
320 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
322 def SubReg_i16_lane : SDNodeXForm<imm, [{
323 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
325 def SubReg_i32_lane : SDNodeXForm<imm, [{
326 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
329 //===----------------------------------------------------------------------===//
330 // Instruction Classes
331 //===----------------------------------------------------------------------===//
333 // Basic 2-register operations, both double- and quad-register.
334 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
335 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
336 ValueType ResTy, ValueType OpTy, SDNode OpNode>
337 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
338 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
339 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>;
340 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
341 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
342 ValueType ResTy, ValueType OpTy, SDNode OpNode>
343 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
344 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
345 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>;
347 // Basic 2-register operations, scalar single-precision.
348 class N2VDs<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
349 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
350 ValueType ResTy, ValueType OpTy, SDNode OpNode>
351 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
352 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src),
353 NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
355 class N2VDsPat<SDNode OpNode, ValueType ResTy, ValueType OpTy, NeonI Inst>
356 : NEONFPPat<(ResTy (OpNode SPR:$a)),
358 (Inst (INSERT_SUBREG (OpTy (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
361 // Basic 2-register intrinsics, both double- and quad-register.
362 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
363 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
364 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
365 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
366 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
367 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
368 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
369 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
370 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
371 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
372 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
373 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
375 // Basic 2-register intrinsics, scalar single-precision
376 class N2VDInts<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
377 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
378 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
379 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
380 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
381 !strconcat(OpcodeStr, "\t$dst, $src"), "", []>;
383 class N2VDIntsPat<SDNode OpNode, NeonI Inst>
384 : NEONFPPat<(f32 (OpNode SPR:$a)),
386 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0)),
389 // Narrow 2-register intrinsics.
390 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
391 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
392 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp>
393 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst),
394 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
395 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>;
397 // Long 2-register intrinsics. (This is currently only used for VMOVL and is
398 // derived from N2VImm instead of N2V because of the way the size is encoded.)
399 class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
400 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD,
402 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst),
403 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
404 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>;
406 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
407 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
408 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$dst1, DPR:$dst2),
409 (ins DPR:$src1, DPR:$src2), NoItinerary,
410 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
411 "$src1 = $dst1, $src2 = $dst2", []>;
412 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr>
413 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$dst1, QPR:$dst2),
414 (ins QPR:$src1, QPR:$src2), NoItinerary,
415 !strconcat(OpcodeStr, "\t$dst1, $dst2"),
416 "$src1 = $dst1, $src2 = $dst2", []>;
418 // Basic 3-register operations, both double- and quad-register.
419 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
420 string OpcodeStr, ValueType ResTy, ValueType OpTy,
421 SDNode OpNode, bit Commutable>
422 : N3V<op24, op23, op21_20, op11_8, 0, op4,
423 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
424 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
425 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
426 let isCommutable = Commutable;
428 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
429 string OpcodeStr, ValueType ResTy, ValueType OpTy,
430 SDNode OpNode, bit Commutable>
431 : N3V<op24, op23, op21_20, op11_8, 1, op4,
432 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
433 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
434 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
435 let isCommutable = Commutable;
438 // Basic 3-register operations, scalar single-precision
439 class N3VDs<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
440 string OpcodeStr, ValueType ResTy, ValueType OpTy,
441 SDNode OpNode, bit Commutable>
442 : N3V<op24, op23, op21_20, op11_8, 0, op4,
443 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src1, DPR_VFP2:$src2), NoItinerary,
444 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", []> {
445 let isCommutable = Commutable;
447 class N3VDsPat<SDNode OpNode, NeonI Inst>
448 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
450 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
451 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
454 // Basic 3-register intrinsics, both double- and quad-register.
455 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
456 string OpcodeStr, ValueType ResTy, ValueType OpTy,
457 Intrinsic IntOp, bit Commutable>
458 : N3V<op24, op23, op21_20, op11_8, 0, op4,
459 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
460 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
461 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> {
462 let isCommutable = Commutable;
464 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
465 string OpcodeStr, ValueType ResTy, ValueType OpTy,
466 Intrinsic IntOp, bit Commutable>
467 : N3V<op24, op23, op21_20, op11_8, 1, op4,
468 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
469 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
470 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> {
471 let isCommutable = Commutable;
474 // Multiply-Add/Sub operations, both double- and quad-register.
475 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
476 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
477 : N3V<op24, op23, op21_20, op11_8, 0, op4,
478 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
479 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
480 [(set DPR:$dst, (Ty (OpNode DPR:$src1,
481 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>;
482 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
483 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
484 : N3V<op24, op23, op21_20, op11_8, 1, op4,
485 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
486 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
487 [(set QPR:$dst, (Ty (OpNode QPR:$src1,
488 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>;
490 // Multiply-Add/Sub operations, scalar single-precision
491 class N3VDMulOps<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
492 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode>
493 : N3V<op24, op23, op21_20, op11_8, 0, op4,
494 (outs DPR_VFP2:$dst),
495 (ins DPR_VFP2:$src1, DPR_VFP2:$src2, DPR_VFP2:$src3), NoItinerary,
496 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", []>;
498 class N3VDMulOpsPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
499 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
501 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$acc, arm_ssubreg_0),
502 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$a, arm_ssubreg_0),
503 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$b, arm_ssubreg_0)),
506 // Neon 3-argument intrinsics, both double- and quad-register.
507 // The destination register is also used as the first source operand register.
508 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
509 string OpcodeStr, ValueType ResTy, ValueType OpTy,
511 : N3V<op24, op23, op21_20, op11_8, 0, op4,
512 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
513 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
514 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1),
515 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>;
516 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
517 string OpcodeStr, ValueType ResTy, ValueType OpTy,
519 : N3V<op24, op23, op21_20, op11_8, 1, op4,
520 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
521 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
522 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1),
523 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>;
525 // Neon Long 3-argument intrinsic. The destination register is
526 // a quad-register and is also used as the first source operand register.
527 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
528 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp>
529 : N3V<op24, op23, op21_20, op11_8, 0, op4,
530 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
531 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst",
533 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>;
535 // Narrowing 3-register intrinsics.
536 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
537 string OpcodeStr, ValueType TyD, ValueType TyQ,
538 Intrinsic IntOp, bit Commutable>
539 : N3V<op24, op23, op21_20, op11_8, 0, op4,
540 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
541 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
542 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> {
543 let isCommutable = Commutable;
546 // Long 3-register intrinsics.
547 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
548 string OpcodeStr, ValueType TyQ, ValueType TyD,
549 Intrinsic IntOp, bit Commutable>
550 : N3V<op24, op23, op21_20, op11_8, 0, op4,
551 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
552 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
553 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> {
554 let isCommutable = Commutable;
557 // Wide 3-register intrinsics.
558 class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
559 string OpcodeStr, ValueType TyQ, ValueType TyD,
560 Intrinsic IntOp, bit Commutable>
561 : N3V<op24, op23, op21_20, op11_8, 0, op4,
562 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), NoItinerary,
563 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "",
564 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> {
565 let isCommutable = Commutable;
568 // Pairwise long 2-register intrinsics, both double- and quad-register.
569 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
570 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
571 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
572 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst),
573 (ins DPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
574 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>;
575 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
576 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
577 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
578 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst),
579 (ins QPR:$src), NoItinerary, !strconcat(OpcodeStr, "\t$dst, $src"), "",
580 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>;
582 // Pairwise long 2-register accumulate intrinsics,
583 // both double- and quad-register.
584 // The destination register is also used as the first source operand register.
585 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
586 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
587 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
588 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
589 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), NoItinerary,
590 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
591 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>;
592 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
593 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
594 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
595 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
596 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), NoItinerary,
597 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst",
598 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>;
600 // Shift by immediate,
601 // both double- and quad-register.
602 class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
603 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
604 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
605 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
606 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
607 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>;
608 class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
609 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode>
610 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
611 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
612 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
613 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>;
615 // Long shift by immediate.
616 class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
617 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
618 ValueType OpTy, SDNode OpNode>
619 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
620 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
621 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
622 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src),
623 (i32 imm:$SIMM))))]>;
625 // Narrow shift by immediate.
626 class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
627 bit op6, bit op4, string OpcodeStr, ValueType ResTy,
628 ValueType OpTy, SDNode OpNode>
629 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4,
630 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
631 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
632 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src),
633 (i32 imm:$SIMM))))]>;
635 // Shift right by immediate and accumulate,
636 // both double- and quad-register.
637 class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
638 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
639 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
640 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
642 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
643 [(set DPR:$dst, (Ty (add DPR:$src1,
644 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>;
645 class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
646 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
647 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
648 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
650 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
651 [(set QPR:$dst, (Ty (add QPR:$src1,
652 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>;
654 // Shift by immediate and insert,
655 // both double- and quad-register.
656 class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
657 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
658 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
659 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM),
661 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
662 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>;
663 class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
664 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp>
665 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
666 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM),
668 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst",
669 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>;
671 // Convert, with fractional bits immediate,
672 // both double- and quad-register.
673 class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
674 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
676 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4,
677 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), NoItinerary,
678 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
679 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>;
680 class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
681 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy,
683 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4,
684 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), NoItinerary,
685 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "",
686 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>;
688 //===----------------------------------------------------------------------===//
690 //===----------------------------------------------------------------------===//
692 // Neon 3-register vector operations.
694 // First with only element sizes of 8, 16 and 32 bits:
695 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
696 string OpcodeStr, SDNode OpNode, bit Commutable = 0> {
697 // 64-bit vector types.
698 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
699 v8i8, v8i8, OpNode, Commutable>;
700 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
701 v4i16, v4i16, OpNode, Commutable>;
702 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
703 v2i32, v2i32, OpNode, Commutable>;
705 // 128-bit vector types.
706 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
707 v16i8, v16i8, OpNode, Commutable>;
708 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"),
709 v8i16, v8i16, OpNode, Commutable>;
710 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"),
711 v4i32, v4i32, OpNode, Commutable>;
714 // ....then also with element size 64 bits:
715 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
716 string OpcodeStr, SDNode OpNode, bit Commutable = 0>
717 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> {
718 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
719 v1i64, v1i64, OpNode, Commutable>;
720 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"),
721 v2i64, v2i64, OpNode, Commutable>;
725 // Neon Narrowing 2-register vector intrinsics,
726 // source operand element sizes of 16, 32 and 64 bits:
727 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
728 bits<5> op11_7, bit op6, bit op4, string OpcodeStr,
730 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
731 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>;
732 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
733 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>;
734 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
735 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>;
739 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
740 // source operand element sizes of 16, 32 and 64 bits:
741 multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
742 bit op4, string OpcodeStr, Intrinsic IntOp> {
743 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4,
744 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
745 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4,
746 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
747 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4,
748 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
752 // Neon 3-register vector intrinsics.
754 // First with only element sizes of 16 and 32 bits:
755 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
756 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
757 // 64-bit vector types.
758 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
759 v4i16, v4i16, IntOp, Commutable>;
760 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
761 v2i32, v2i32, IntOp, Commutable>;
763 // 128-bit vector types.
764 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
765 v8i16, v8i16, IntOp, Commutable>;
766 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
767 v4i32, v4i32, IntOp, Commutable>;
770 // ....then also with element size of 8 bits:
771 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
772 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
773 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
774 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
775 v8i8, v8i8, IntOp, Commutable>;
776 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
777 v16i8, v16i8, IntOp, Commutable>;
780 // ....then also with element size of 64 bits:
781 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
782 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
783 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
784 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
785 v1i64, v1i64, IntOp, Commutable>;
786 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"),
787 v2i64, v2i64, IntOp, Commutable>;
791 // Neon Narrowing 3-register vector intrinsics,
792 // source operand element sizes of 16, 32 and 64 bits:
793 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
794 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
795 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"),
796 v8i8, v8i16, IntOp, Commutable>;
797 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"),
798 v4i16, v4i32, IntOp, Commutable>;
799 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"),
800 v2i32, v2i64, IntOp, Commutable>;
804 // Neon Long 3-register vector intrinsics.
806 // First with only element sizes of 16 and 32 bits:
807 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
808 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
809 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
810 v4i32, v4i16, IntOp, Commutable>;
811 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
812 v2i64, v2i32, IntOp, Commutable>;
815 // ....then also with element size of 8 bits:
816 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
817 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0>
818 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> {
819 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
820 v8i16, v8i8, IntOp, Commutable>;
824 // Neon Wide 3-register vector intrinsics,
825 // source operand element sizes of 8, 16 and 32 bits:
826 multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
827 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> {
828 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"),
829 v8i16, v8i8, IntOp, Commutable>;
830 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"),
831 v4i32, v4i16, IntOp, Commutable>;
832 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"),
833 v2i64, v2i32, IntOp, Commutable>;
837 // Neon Multiply-Op vector operations,
838 // element sizes of 8, 16 and 32 bits:
839 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
840 string OpcodeStr, SDNode OpNode> {
841 // 64-bit vector types.
842 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4,
843 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>;
844 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4,
845 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>;
846 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4,
847 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>;
849 // 128-bit vector types.
850 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4,
851 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>;
852 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4,
853 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>;
854 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4,
855 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>;
859 // Neon 3-argument intrinsics,
860 // element sizes of 8, 16 and 32 bits:
861 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
862 string OpcodeStr, Intrinsic IntOp> {
863 // 64-bit vector types.
864 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4,
865 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
866 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4,
867 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
868 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4,
869 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
871 // 128-bit vector types.
872 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4,
873 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
874 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4,
875 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
876 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4,
877 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
881 // Neon Long 3-argument intrinsics.
883 // First with only element sizes of 16 and 32 bits:
884 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
885 string OpcodeStr, Intrinsic IntOp> {
886 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
887 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>;
888 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4,
889 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>;
892 // ....then also with element size of 8 bits:
893 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
894 string OpcodeStr, Intrinsic IntOp>
895 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> {
896 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4,
897 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>;
901 // Neon 2-register vector intrinsics,
902 // element sizes of 8, 16 and 32 bits:
903 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
904 bits<5> op11_7, bit op4, string OpcodeStr,
906 // 64-bit vector types.
907 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
908 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>;
909 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
910 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>;
911 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
912 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>;
914 // 128-bit vector types.
915 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
916 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>;
917 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
918 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>;
919 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
920 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>;
924 // Neon Pairwise long 2-register intrinsics,
925 // element sizes of 8, 16 and 32 bits:
926 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
927 bits<5> op11_7, bit op4,
928 string OpcodeStr, Intrinsic IntOp> {
929 // 64-bit vector types.
930 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
931 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
932 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
933 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
934 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
935 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
937 // 128-bit vector types.
938 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
939 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
940 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
941 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
942 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
943 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
947 // Neon Pairwise long 2-register accumulate intrinsics,
948 // element sizes of 8, 16 and 32 bits:
949 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
950 bits<5> op11_7, bit op4,
951 string OpcodeStr, Intrinsic IntOp> {
952 // 64-bit vector types.
953 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
954 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>;
955 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
956 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>;
957 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
958 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>;
960 // 128-bit vector types.
961 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
962 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>;
963 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
964 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>;
965 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
966 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>;
970 // Neon 2-register vector shift by immediate,
971 // element sizes of 8, 16, 32 and 64 bits:
972 multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
973 string OpcodeStr, SDNode OpNode> {
974 // 64-bit vector types.
975 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4,
976 !strconcat(OpcodeStr, "8"), v8i8, OpNode>;
977 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4,
978 !strconcat(OpcodeStr, "16"), v4i16, OpNode>;
979 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4,
980 !strconcat(OpcodeStr, "32"), v2i32, OpNode>;
981 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4,
982 !strconcat(OpcodeStr, "64"), v1i64, OpNode>;
984 // 128-bit vector types.
985 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4,
986 !strconcat(OpcodeStr, "8"), v16i8, OpNode>;
987 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4,
988 !strconcat(OpcodeStr, "16"), v8i16, OpNode>;
989 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4,
990 !strconcat(OpcodeStr, "32"), v4i32, OpNode>;
991 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4,
992 !strconcat(OpcodeStr, "64"), v2i64, OpNode>;
996 // Neon Shift-Accumulate vector operations,
997 // element sizes of 8, 16, 32 and 64 bits:
998 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
999 string OpcodeStr, SDNode ShOp> {
1000 // 64-bit vector types.
1001 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4,
1002 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1003 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4,
1004 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1005 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4,
1006 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1007 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1008 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1010 // 128-bit vector types.
1011 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4,
1012 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1013 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4,
1014 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1015 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4,
1016 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1017 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4,
1018 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1022 // Neon Shift-Insert vector operations,
1023 // element sizes of 8, 16, 32 and 64 bits:
1024 multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
1025 string OpcodeStr, SDNode ShOp> {
1026 // 64-bit vector types.
1027 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4,
1028 !strconcat(OpcodeStr, "8"), v8i8, ShOp>;
1029 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4,
1030 !strconcat(OpcodeStr, "16"), v4i16, ShOp>;
1031 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4,
1032 !strconcat(OpcodeStr, "32"), v2i32, ShOp>;
1033 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4,
1034 !strconcat(OpcodeStr, "64"), v1i64, ShOp>;
1036 // 128-bit vector types.
1037 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4,
1038 !strconcat(OpcodeStr, "8"), v16i8, ShOp>;
1039 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4,
1040 !strconcat(OpcodeStr, "16"), v8i16, ShOp>;
1041 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4,
1042 !strconcat(OpcodeStr, "32"), v4i32, ShOp>;
1043 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4,
1044 !strconcat(OpcodeStr, "64"), v2i64, ShOp>;
1047 //===----------------------------------------------------------------------===//
1048 // Instruction Definitions.
1049 //===----------------------------------------------------------------------===//
1051 // Vector Add Operations.
1053 // VADD : Vector Add (integer and floating-point)
1054 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>;
1055 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>;
1056 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>;
1057 // VADDL : Vector Add Long (Q = D + D)
1058 defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>;
1059 defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>;
1060 // VADDW : Vector Add Wide (Q = Q + D)
1061 defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>;
1062 defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>;
1063 // VHADD : Vector Halving Add
1064 defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>;
1065 defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>;
1066 // VRHADD : Vector Rounding Halving Add
1067 defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>;
1068 defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>;
1069 // VQADD : Vector Saturating Add
1070 defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>;
1071 defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>;
1072 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
1073 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>;
1074 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
1075 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>;
1077 // Vector Multiply Operations.
1079 // VMUL : Vector Multiply (integer, polynomial and floating-point)
1080 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>;
1081 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8,
1082 int_arm_neon_vmulp, 1>;
1083 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8,
1084 int_arm_neon_vmulp, 1>;
1085 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>;
1086 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>;
1087 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
1088 defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>;
1089 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
1090 defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>;
1091 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
1092 defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>;
1093 defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>;
1094 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8,
1095 int_arm_neon_vmullp, 1>;
1096 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
1097 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>;
1099 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
1101 // VMLA : Vector Multiply Accumulate (integer and floating-point)
1102 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>;
1103 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>;
1104 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>;
1105 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
1106 defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>;
1107 defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>;
1108 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
1109 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>;
1110 // VMLS : Vector Multiply Subtract (integer and floating-point)
1111 defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>;
1112 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>;
1113 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>;
1114 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
1115 defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>;
1116 defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>;
1117 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
1118 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>;
1120 // Vector Subtract Operations.
1122 // VSUB : Vector Subtract (integer and floating-point)
1123 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>;
1124 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>;
1125 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>;
1126 // VSUBL : Vector Subtract Long (Q = D - D)
1127 defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>;
1128 defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>;
1129 // VSUBW : Vector Subtract Wide (Q = Q - D)
1130 defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>;
1131 defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>;
1132 // VHSUB : Vector Halving Subtract
1133 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>;
1134 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>;
1135 // VQSUB : Vector Saturing Subtract
1136 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>;
1137 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>;
1138 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
1139 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>;
1140 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
1141 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>;
1143 // Vector Comparisons.
1145 // VCEQ : Vector Compare Equal
1146 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>;
1147 def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>;
1148 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>;
1149 // VCGE : Vector Compare Greater Than or Equal
1150 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>;
1151 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>;
1152 def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>;
1153 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>;
1154 // VCGT : Vector Compare Greater Than
1155 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>;
1156 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>;
1157 def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>;
1158 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>;
1159 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
1160 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32,
1161 int_arm_neon_vacged, 0>;
1162 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32,
1163 int_arm_neon_vacgeq, 0>;
1164 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
1165 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32,
1166 int_arm_neon_vacgtd, 0>;
1167 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32,
1168 int_arm_neon_vacgtq, 0>;
1169 // VTST : Vector Test Bits
1170 defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>;
1172 // Vector Bitwise Operations.
1174 // VAND : Vector Bitwise AND
1175 def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>;
1176 def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>;
1178 // VEOR : Vector Bitwise Exclusive OR
1179 def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>;
1180 def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>;
1182 // VORR : Vector Bitwise OR
1183 def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>;
1184 def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>;
1186 // VBIC : Vector Bitwise Bit Clear (AND NOT)
1187 def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1188 (ins DPR:$src1, DPR:$src2), NoItinerary,
1189 "vbic\t$dst, $src1, $src2", "",
1190 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>;
1191 def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1192 (ins QPR:$src1, QPR:$src2), NoItinerary,
1193 "vbic\t$dst, $src1, $src2", "",
1194 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>;
1196 // VORN : Vector Bitwise OR NOT
1197 def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst),
1198 (ins DPR:$src1, DPR:$src2), NoItinerary,
1199 "vorn\t$dst, $src1, $src2", "",
1200 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>;
1201 def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst),
1202 (ins QPR:$src1, QPR:$src2), NoItinerary,
1203 "vorn\t$dst, $src1, $src2", "",
1204 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>;
1206 // VMVN : Vector Bitwise NOT
1207 def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
1208 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1209 "vmvn\t$dst, $src", "",
1210 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>;
1211 def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
1212 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1213 "vmvn\t$dst, $src", "",
1214 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>;
1215 def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>;
1216 def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>;
1218 // VBSL : Vector Bitwise Select
1219 def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst),
1220 (ins DPR:$src1, DPR:$src2, DPR:$src3), NoItinerary,
1221 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1223 (v2i32 (or (and DPR:$src2, DPR:$src1),
1224 (and DPR:$src3, (vnot DPR:$src1)))))]>;
1225 def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst),
1226 (ins QPR:$src1, QPR:$src2, QPR:$src3), NoItinerary,
1227 "vbsl\t$dst, $src2, $src3", "$src1 = $dst",
1229 (v4i32 (or (and QPR:$src2, QPR:$src1),
1230 (and QPR:$src3, (vnot QPR:$src1)))))]>;
1232 // VBIF : Vector Bitwise Insert if False
1233 // like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst",
1234 // VBIT : Vector Bitwise Insert if True
1235 // like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst",
1236 // These are not yet implemented. The TwoAddress pass will not go looking
1237 // for equivalent operations with different register constraints; it just
1240 // Vector Absolute Differences.
1242 // VABD : Vector Absolute Difference
1243 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>;
1244 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>;
1245 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32,
1246 int_arm_neon_vabds, 0>;
1247 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32,
1248 int_arm_neon_vabds, 0>;
1250 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
1251 defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>;
1252 defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>;
1254 // VABA : Vector Absolute Difference and Accumulate
1255 defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>;
1256 defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>;
1258 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
1259 defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>;
1260 defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>;
1262 // Vector Maximum and Minimum.
1264 // VMAX : Vector Maximum
1265 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>;
1266 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>;
1267 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32,
1268 int_arm_neon_vmaxs, 1>;
1269 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32,
1270 int_arm_neon_vmaxs, 1>;
1272 // VMIN : Vector Minimum
1273 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>;
1274 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>;
1275 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32,
1276 int_arm_neon_vmins, 1>;
1277 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32,
1278 int_arm_neon_vmins, 1>;
1280 // Vector Pairwise Operations.
1282 // VPADD : Vector Pairwise Add
1283 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8,
1284 int_arm_neon_vpadd, 0>;
1285 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16,
1286 int_arm_neon_vpadd, 0>;
1287 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32,
1288 int_arm_neon_vpadd, 0>;
1289 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32,
1290 int_arm_neon_vpadd, 0>;
1292 // VPADDL : Vector Pairwise Add Long
1293 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s",
1294 int_arm_neon_vpaddls>;
1295 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u",
1296 int_arm_neon_vpaddlu>;
1298 // VPADAL : Vector Pairwise Add and Accumulate Long
1299 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s",
1300 int_arm_neon_vpadals>;
1301 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u",
1302 int_arm_neon_vpadalu>;
1304 // VPMAX : Vector Pairwise Maximum
1305 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8,
1306 int_arm_neon_vpmaxs, 0>;
1307 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16,
1308 int_arm_neon_vpmaxs, 0>;
1309 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32,
1310 int_arm_neon_vpmaxs, 0>;
1311 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8,
1312 int_arm_neon_vpmaxu, 0>;
1313 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16,
1314 int_arm_neon_vpmaxu, 0>;
1315 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32,
1316 int_arm_neon_vpmaxu, 0>;
1317 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32,
1318 int_arm_neon_vpmaxs, 0>;
1320 // VPMIN : Vector Pairwise Minimum
1321 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8,
1322 int_arm_neon_vpmins, 0>;
1323 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16,
1324 int_arm_neon_vpmins, 0>;
1325 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32,
1326 int_arm_neon_vpmins, 0>;
1327 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8,
1328 int_arm_neon_vpminu, 0>;
1329 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16,
1330 int_arm_neon_vpminu, 0>;
1331 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32,
1332 int_arm_neon_vpminu, 0>;
1333 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32,
1334 int_arm_neon_vpmins, 0>;
1336 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
1338 // VRECPE : Vector Reciprocal Estimate
1339 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1340 v2i32, v2i32, int_arm_neon_vrecpe>;
1341 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32",
1342 v4i32, v4i32, int_arm_neon_vrecpe>;
1343 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1344 v2f32, v2f32, int_arm_neon_vrecpe>;
1345 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32",
1346 v4f32, v4f32, int_arm_neon_vrecpe>;
1348 // VRECPS : Vector Reciprocal Step
1349 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32,
1350 int_arm_neon_vrecps, 1>;
1351 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32,
1352 int_arm_neon_vrecps, 1>;
1354 // VRSQRTE : Vector Reciprocal Square Root Estimate
1355 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1356 v2i32, v2i32, int_arm_neon_vrsqrte>;
1357 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32",
1358 v4i32, v4i32, int_arm_neon_vrsqrte>;
1359 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1360 v2f32, v2f32, int_arm_neon_vrsqrte>;
1361 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32",
1362 v4f32, v4f32, int_arm_neon_vrsqrte>;
1364 // VRSQRTS : Vector Reciprocal Square Root Step
1365 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32,
1366 int_arm_neon_vrsqrts, 1>;
1367 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32,
1368 int_arm_neon_vrsqrts, 1>;
1372 // VSHL : Vector Shift
1373 defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>;
1374 defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>;
1375 // VSHL : Vector Shift Left (Immediate)
1376 defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>;
1377 // VSHR : Vector Shift Right (Immediate)
1378 defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>;
1379 defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>;
1381 // VSHLL : Vector Shift Left Long
1382 def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8",
1383 v8i16, v8i8, NEONvshlls>;
1384 def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16",
1385 v4i32, v4i16, NEONvshlls>;
1386 def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32",
1387 v2i64, v2i32, NEONvshlls>;
1388 def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8",
1389 v8i16, v8i8, NEONvshllu>;
1390 def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16",
1391 v4i32, v4i16, NEONvshllu>;
1392 def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32",
1393 v2i64, v2i32, NEONvshllu>;
1395 // VSHLL : Vector Shift Left Long (with maximum shift count)
1396 def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8",
1397 v8i16, v8i8, NEONvshlli>;
1398 def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16",
1399 v4i32, v4i16, NEONvshlli>;
1400 def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32",
1401 v2i64, v2i32, NEONvshlli>;
1403 // VSHRN : Vector Shift Right and Narrow
1404 def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16",
1405 v8i8, v8i16, NEONvshrn>;
1406 def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32",
1407 v4i16, v4i32, NEONvshrn>;
1408 def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64",
1409 v2i32, v2i64, NEONvshrn>;
1411 // VRSHL : Vector Rounding Shift
1412 defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>;
1413 defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>;
1414 // VRSHR : Vector Rounding Shift Right
1415 defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>;
1416 defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>;
1418 // VRSHRN : Vector Rounding Shift Right and Narrow
1419 def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16",
1420 v8i8, v8i16, NEONvrshrn>;
1421 def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32",
1422 v4i16, v4i32, NEONvrshrn>;
1423 def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64",
1424 v2i32, v2i64, NEONvrshrn>;
1426 // VQSHL : Vector Saturating Shift
1427 defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>;
1428 defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>;
1429 // VQSHL : Vector Saturating Shift Left (Immediate)
1430 defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>;
1431 defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>;
1432 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
1433 defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>;
1435 // VQSHRN : Vector Saturating Shift Right and Narrow
1436 def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16",
1437 v8i8, v8i16, NEONvqshrns>;
1438 def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32",
1439 v4i16, v4i32, NEONvqshrns>;
1440 def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64",
1441 v2i32, v2i64, NEONvqshrns>;
1442 def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16",
1443 v8i8, v8i16, NEONvqshrnu>;
1444 def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32",
1445 v4i16, v4i32, NEONvqshrnu>;
1446 def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64",
1447 v2i32, v2i64, NEONvqshrnu>;
1449 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
1450 def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16",
1451 v8i8, v8i16, NEONvqshrnsu>;
1452 def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32",
1453 v4i16, v4i32, NEONvqshrnsu>;
1454 def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64",
1455 v2i32, v2i64, NEONvqshrnsu>;
1457 // VQRSHL : Vector Saturating Rounding Shift
1458 defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s",
1459 int_arm_neon_vqrshifts, 0>;
1460 defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u",
1461 int_arm_neon_vqrshiftu, 0>;
1463 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
1464 def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16",
1465 v8i8, v8i16, NEONvqrshrns>;
1466 def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32",
1467 v4i16, v4i32, NEONvqrshrns>;
1468 def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64",
1469 v2i32, v2i64, NEONvqrshrns>;
1470 def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16",
1471 v8i8, v8i16, NEONvqrshrnu>;
1472 def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32",
1473 v4i16, v4i32, NEONvqrshrnu>;
1474 def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64",
1475 v2i32, v2i64, NEONvqrshrnu>;
1477 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
1478 def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16",
1479 v8i8, v8i16, NEONvqrshrnsu>;
1480 def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32",
1481 v4i16, v4i32, NEONvqrshrnsu>;
1482 def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64",
1483 v2i32, v2i64, NEONvqrshrnsu>;
1485 // VSRA : Vector Shift Right and Accumulate
1486 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>;
1487 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>;
1488 // VRSRA : Vector Rounding Shift Right and Accumulate
1489 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>;
1490 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>;
1492 // VSLI : Vector Shift Left and Insert
1493 defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>;
1494 // VSRI : Vector Shift Right and Insert
1495 defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>;
1497 // Vector Absolute and Saturating Absolute.
1499 // VABS : Vector Absolute Value
1500 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s",
1502 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1503 v2f32, v2f32, int_arm_neon_vabs>;
1504 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
1505 v4f32, v4f32, int_arm_neon_vabs>;
1507 // VQABS : Vector Saturating Absolute Value
1508 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s",
1509 int_arm_neon_vqabs>;
1513 def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
1514 def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>;
1516 class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty>
1517 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src),
1519 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1520 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>;
1521 class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty>
1522 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src),
1524 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1525 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>;
1527 // VNEG : Vector Negate
1528 def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>;
1529 def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>;
1530 def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>;
1531 def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>;
1532 def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>;
1533 def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>;
1535 // VNEG : Vector Negate (floating-point)
1536 def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
1537 (outs DPR:$dst), (ins DPR:$src), NoItinerary,
1538 "vneg.f32\t$dst, $src", "",
1539 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>;
1540 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
1541 (outs QPR:$dst), (ins QPR:$src), NoItinerary,
1542 "vneg.f32\t$dst, $src", "",
1543 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>;
1545 def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>;
1546 def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>;
1547 def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>;
1548 def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>;
1549 def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>;
1550 def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>;
1552 // VQNEG : Vector Saturating Negate
1553 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s",
1554 int_arm_neon_vqneg>;
1556 // Vector Bit Counting Operations.
1558 // VCLS : Vector Count Leading Sign Bits
1559 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s",
1561 // VCLZ : Vector Count Leading Zeros
1562 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i",
1564 // VCNT : Vector Count One Bits
1565 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1566 v8i8, v8i8, int_arm_neon_vcnt>;
1567 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8",
1568 v16i8, v16i8, int_arm_neon_vcnt>;
1570 // Vector Move Operations.
1572 // VMOV : Vector Move (Register)
1574 def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src),
1575 NoItinerary, "vmov\t$dst, $src", "", []>;
1576 def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src),
1577 NoItinerary, "vmov\t$dst, $src", "", []>;
1579 // VMOV : Vector Move (Immediate)
1581 // VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm.
1582 def VMOV_get_imm8 : SDNodeXForm<build_vector, [{
1583 return ARM::getVMOVImm(N, 1, *CurDAG);
1585 def vmovImm8 : PatLeaf<(build_vector), [{
1586 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0;
1589 // VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm.
1590 def VMOV_get_imm16 : SDNodeXForm<build_vector, [{
1591 return ARM::getVMOVImm(N, 2, *CurDAG);
1593 def vmovImm16 : PatLeaf<(build_vector), [{
1594 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0;
1595 }], VMOV_get_imm16>;
1597 // VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm.
1598 def VMOV_get_imm32 : SDNodeXForm<build_vector, [{
1599 return ARM::getVMOVImm(N, 4, *CurDAG);
1601 def vmovImm32 : PatLeaf<(build_vector), [{
1602 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0;
1603 }], VMOV_get_imm32>;
1605 // VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm.
1606 def VMOV_get_imm64 : SDNodeXForm<build_vector, [{
1607 return ARM::getVMOVImm(N, 8, *CurDAG);
1609 def vmovImm64 : PatLeaf<(build_vector), [{
1610 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0;
1611 }], VMOV_get_imm64>;
1613 // Note: Some of the cmode bits in the following VMOV instructions need to
1614 // be encoded based on the immed values.
1616 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst),
1617 (ins i8imm:$SIMM), NoItinerary,
1618 "vmov.i8\t$dst, $SIMM", "",
1619 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>;
1620 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst),
1621 (ins i8imm:$SIMM), NoItinerary,
1622 "vmov.i8\t$dst, $SIMM", "",
1623 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>;
1625 def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst),
1626 (ins i16imm:$SIMM), NoItinerary,
1627 "vmov.i16\t$dst, $SIMM", "",
1628 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>;
1629 def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst),
1630 (ins i16imm:$SIMM), NoItinerary,
1631 "vmov.i16\t$dst, $SIMM", "",
1632 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>;
1634 def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst),
1635 (ins i32imm:$SIMM), NoItinerary,
1636 "vmov.i32\t$dst, $SIMM", "",
1637 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>;
1638 def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst),
1639 (ins i32imm:$SIMM), NoItinerary,
1640 "vmov.i32\t$dst, $SIMM", "",
1641 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>;
1643 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst),
1644 (ins i64imm:$SIMM), NoItinerary,
1645 "vmov.i64\t$dst, $SIMM", "",
1646 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>;
1647 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst),
1648 (ins i64imm:$SIMM), NoItinerary,
1649 "vmov.i64\t$dst, $SIMM", "",
1650 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>;
1652 // VMOV : Vector Get Lane (move scalar to ARM core register)
1654 def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00,
1655 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1656 NoItinerary, "vmov", ".s8\t$dst, $src[$lane]",
1657 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src),
1659 def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01,
1660 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1661 NoItinerary, "vmov", ".s16\t$dst, $src[$lane]",
1662 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src),
1664 def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00,
1665 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1666 NoItinerary, "vmov", ".u8\t$dst, $src[$lane]",
1667 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src),
1669 def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01,
1670 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1671 NoItinerary, "vmov", ".u16\t$dst, $src[$lane]",
1672 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src),
1674 def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00,
1675 (outs GPR:$dst), (ins DPR:$src, lane_cst:$lane),
1676 NoItinerary, "vmov", ".32\t$dst, $src[$lane]",
1677 [(set GPR:$dst, (extractelt (v2i32 DPR:$src),
1679 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
1680 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
1681 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1682 (DSubReg_i8_reg imm:$lane))),
1683 (SubReg_i8_lane imm:$lane))>;
1684 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
1685 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1686 (DSubReg_i16_reg imm:$lane))),
1687 (SubReg_i16_lane imm:$lane))>;
1688 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
1689 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
1690 (DSubReg_i8_reg imm:$lane))),
1691 (SubReg_i8_lane imm:$lane))>;
1692 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
1693 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
1694 (DSubReg_i16_reg imm:$lane))),
1695 (SubReg_i16_lane imm:$lane))>;
1696 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
1697 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
1698 (DSubReg_i32_reg imm:$lane))),
1699 (SubReg_i32_lane imm:$lane))>;
1700 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
1701 (EXTRACT_SUBREG QPR:$src1, (SSubReg_f32_reg imm:$src2))>;
1702 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
1703 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
1704 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
1705 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
1708 // VMOV : Vector Set Lane (move ARM core register to scalar)
1710 let Constraints = "$src1 = $dst" in {
1711 def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst),
1712 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1713 NoItinerary, "vmov", ".8\t$dst[$lane], $src2",
1714 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1),
1715 GPR:$src2, imm:$lane))]>;
1716 def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst),
1717 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1718 NoItinerary, "vmov", ".16\t$dst[$lane], $src2",
1719 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1),
1720 GPR:$src2, imm:$lane))]>;
1721 def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst),
1722 (ins DPR:$src1, GPR:$src2, lane_cst:$lane),
1723 NoItinerary, "vmov", ".32\t$dst[$lane], $src2",
1724 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1),
1725 GPR:$src2, imm:$lane))]>;
1727 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
1728 (v16i8 (INSERT_SUBREG QPR:$src1,
1729 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
1730 (DSubReg_i8_reg imm:$lane))),
1731 GPR:$src2, (SubReg_i8_lane imm:$lane)),
1732 (DSubReg_i8_reg imm:$lane)))>;
1733 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
1734 (v8i16 (INSERT_SUBREG QPR:$src1,
1735 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
1736 (DSubReg_i16_reg imm:$lane))),
1737 GPR:$src2, (SubReg_i16_lane imm:$lane)),
1738 (DSubReg_i16_reg imm:$lane)))>;
1739 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
1740 (v4i32 (INSERT_SUBREG QPR:$src1,
1741 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
1742 (DSubReg_i32_reg imm:$lane))),
1743 GPR:$src2, (SubReg_i32_lane imm:$lane)),
1744 (DSubReg_i32_reg imm:$lane)))>;
1746 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
1747 (INSERT_SUBREG QPR:$src1, SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
1749 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1750 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
1751 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
1752 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
1754 // VDUP : Vector Duplicate (from ARM core register to all elements)
1756 class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1757 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src),
1758 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1759 [(set DPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
1760 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty>
1761 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src),
1762 NoItinerary, "vdup", !strconcat(asmSize, "\t$dst, $src"),
1763 [(set QPR:$dst, (Ty (NEONvdup (i32 GPR:$src))))]>;
1765 def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>;
1766 def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>;
1767 def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>;
1768 def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>;
1769 def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>;
1770 def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>;
1772 def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src),
1773 NoItinerary, "vdup", ".32\t$dst, $src",
1774 [(set DPR:$dst, (v2f32 (NEONvdup
1775 (f32 (bitconvert GPR:$src)))))]>;
1776 def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src),
1777 NoItinerary, "vdup", ".32\t$dst, $src",
1778 [(set QPR:$dst, (v4f32 (NEONvdup
1779 (f32 (bitconvert GPR:$src)))))]>;
1781 // VDUP : Vector Duplicate Lane (from scalar to all elements)
1783 class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty>
1784 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0,
1785 (outs DPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
1786 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1787 [(set DPR:$dst, (Ty (NEONvduplane (Ty DPR:$src), imm:$lane)))]>;
1789 class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr,
1790 ValueType ResTy, ValueType OpTy>
1791 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0,
1792 (outs QPR:$dst), (ins DPR:$src, lane_cst:$lane), NoItinerary,
1793 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "",
1794 [(set QPR:$dst, (ResTy (NEONvduplane (OpTy DPR:$src), imm:$lane)))]>;
1796 def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>;
1797 def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>;
1798 def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>;
1799 def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>;
1800 def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>;
1801 def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
1802 def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
1803 def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
1805 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
1806 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
1807 (DSubReg_i8_reg imm:$lane))),
1808 (SubReg_i8_lane imm:$lane)))>;
1809 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
1810 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
1811 (DSubReg_i16_reg imm:$lane))),
1812 (SubReg_i16_lane imm:$lane)))>;
1813 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
1814 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
1815 (DSubReg_i32_reg imm:$lane))),
1816 (SubReg_i32_lane imm:$lane)))>;
1817 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
1818 (v4f32 (VDUPLNfq (v2f32 (EXTRACT_SUBREG QPR:$src,
1819 (DSubReg_i32_reg imm:$lane))),
1820 (SubReg_i32_lane imm:$lane)))>;
1822 def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
1823 (outs DPR:$dst), (ins SPR:$src),
1824 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1825 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
1827 def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
1828 (outs QPR:$dst), (ins SPR:$src),
1829 NoItinerary, "vdup.32\t$dst, ${src:lane}", "",
1830 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
1832 // VMOVN : Vector Narrowing Move
1833 defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
1834 int_arm_neon_vmovn>;
1835 // VQMOVN : Vector Saturating Narrowing Move
1836 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s",
1837 int_arm_neon_vqmovns>;
1838 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u",
1839 int_arm_neon_vqmovnu>;
1840 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s",
1841 int_arm_neon_vqmovnsu>;
1842 // VMOVL : Vector Lengthening Move
1843 defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>;
1844 defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>;
1846 // Vector Conversions.
1848 // VCVT : Vector Convert Between Floating-Point and Integers
1849 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1850 v2i32, v2f32, fp_to_sint>;
1851 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1852 v2i32, v2f32, fp_to_uint>;
1853 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1854 v2f32, v2i32, sint_to_fp>;
1855 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1856 v2f32, v2i32, uint_to_fp>;
1858 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
1859 v4i32, v4f32, fp_to_sint>;
1860 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
1861 v4i32, v4f32, fp_to_uint>;
1862 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
1863 v4f32, v4i32, sint_to_fp>;
1864 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
1865 v4f32, v4i32, uint_to_fp>;
1867 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
1868 // Note: Some of the opcode bits in the following VCVT instructions need to
1869 // be encoded based on the immed values.
1870 def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1871 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
1872 def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1873 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
1874 def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1875 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
1876 def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1877 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
1879 def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32",
1880 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
1881 def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32",
1882 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
1883 def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32",
1884 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
1885 def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32",
1886 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
1890 // VREV64 : Vector Reverse elements within 64-bit doublewords
1892 class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1893 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst),
1894 (ins DPR:$src), NoItinerary,
1895 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1896 [(set DPR:$dst, (Ty (NEONvrev64 (Ty DPR:$src))))]>;
1897 class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1898 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst),
1899 (ins QPR:$src), NoItinerary,
1900 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1901 [(set QPR:$dst, (Ty (NEONvrev64 (Ty QPR:$src))))]>;
1903 def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>;
1904 def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>;
1905 def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>;
1906 def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>;
1908 def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>;
1909 def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>;
1910 def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>;
1911 def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>;
1913 // VREV32 : Vector Reverse elements within 32-bit words
1915 class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1916 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst),
1917 (ins DPR:$src), NoItinerary,
1918 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1919 [(set DPR:$dst, (Ty (NEONvrev32 (Ty DPR:$src))))]>;
1920 class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1921 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst),
1922 (ins QPR:$src), NoItinerary,
1923 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1924 [(set QPR:$dst, (Ty (NEONvrev32 (Ty QPR:$src))))]>;
1926 def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>;
1927 def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>;
1929 def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>;
1930 def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>;
1932 // VREV16 : Vector Reverse elements within 16-bit halfwords
1934 class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1935 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst),
1936 (ins DPR:$src), NoItinerary,
1937 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1938 [(set DPR:$dst, (Ty (NEONvrev16 (Ty DPR:$src))))]>;
1939 class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty>
1940 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst),
1941 (ins QPR:$src), NoItinerary,
1942 !strconcat(OpcodeStr, "\t$dst, $src"), "",
1943 [(set QPR:$dst, (Ty (NEONvrev16 (Ty QPR:$src))))]>;
1945 def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>;
1946 def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>;
1948 // Other Vector Shuffles.
1950 // VEXT : Vector Extract
1952 def VEXTd : N3V<0,1,0b11,0b0000,0,0, (outs DPR:$dst),
1953 (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NoItinerary,
1954 "vext.8\t$dst, $lhs, $rhs, $index", "",
1955 [(set DPR:$dst, (v8i8 (NEONvext (v8i8 DPR:$lhs),
1956 (v8i8 DPR:$rhs), imm:$index)))]>;
1957 def VEXTq : N3V<0,1,0b11,0b0000,1,0, (outs QPR:$dst),
1958 (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NoItinerary,
1959 "vext.8\t$dst, $lhs, $rhs, $index", "",
1960 [(set QPR:$dst, (v16i8 (NEONvext (v16i8 QPR:$lhs),
1961 (v16i8 QPR:$rhs), imm:$index)))]>;
1963 // VTRN : Vector Transpose
1965 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn.8">;
1966 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn.16">;
1967 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn.32">;
1969 def VTRNq8 : N2VQShuffle<0b00, 0b00001, "vtrn.8">;
1970 def VTRNq16 : N2VQShuffle<0b01, 0b00001, "vtrn.16">;
1971 def VTRNq32 : N2VQShuffle<0b10, 0b00001, "vtrn.32">;
1973 // VUZP : Vector Unzip (Deinterleave)
1975 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp.8">;
1976 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp.16">;
1977 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp.32">;
1979 def VUZPq8 : N2VQShuffle<0b00, 0b00010, "vuzp.8">;
1980 def VUZPq16 : N2VQShuffle<0b01, 0b00010, "vuzp.16">;
1981 def VUZPq32 : N2VQShuffle<0b10, 0b00010, "vuzp.32">;
1983 // VZIP : Vector Zip (Interleave)
1985 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip.8">;
1986 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip.16">;
1987 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip.32">;
1989 def VZIPq8 : N2VQShuffle<0b00, 0b00011, "vzip.8">;
1990 def VZIPq16 : N2VQShuffle<0b01, 0b00011, "vzip.16">;
1991 def VZIPq32 : N2VQShuffle<0b10, 0b00011, "vzip.32">;
1993 // Vector Table Lookup and Table Extension.
1995 // VTBL : Vector Table Lookup
1997 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$dst),
1998 (ins DPR:$tbl1, DPR:$src), NoItinerary,
1999 "vtbl.8\t$dst, \\{$tbl1\\}, $src", "",
2000 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
2002 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
2003 (ins DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
2004 "vtbl.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "",
2005 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl2
2006 DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2008 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$dst),
2009 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
2010 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "",
2011 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl3
2012 DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2014 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$dst),
2015 (ins DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
2016 "vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
2017 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
2018 DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2020 // VTBX : Vector Table Extension
2022 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$dst),
2023 (ins DPR:$orig, DPR:$tbl1, DPR:$src), NoItinerary,
2024 "vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
2025 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
2026 DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
2028 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
2029 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), NoItinerary,
2030 "vtbx.8\t$dst, \\{$tbl1,$tbl2\\}, $src", "$orig = $dst",
2031 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx2
2032 DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src)))]>;
2034 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$dst),
2035 (ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$tbl3, DPR:$src), NoItinerary,
2036 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3\\}, $src", "$orig = $dst",
2037 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx3 DPR:$orig, DPR:$tbl1,
2038 DPR:$tbl2, DPR:$tbl3, DPR:$src)))]>;
2040 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$dst), (ins DPR:$orig, DPR:$tbl1,
2041 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src), NoItinerary,
2042 "vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
2043 [(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
2044 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
2046 //===----------------------------------------------------------------------===//
2047 // NEON instructions for single-precision FP math
2048 //===----------------------------------------------------------------------===//
2050 // These need separate instructions because they must use DPR_VFP2 register
2051 // class which have SPR sub-registers.
2053 // Vector Add Operations used for single-precision FP
2054 let neverHasSideEffects = 1 in
2055 def VADDfd_sfp : N3VDs<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd,1>;
2056 def : N3VDsPat<fadd, VADDfd_sfp>;
2058 // Vector Sub Operations used for single-precision FP
2059 let neverHasSideEffects = 1 in
2060 def VSUBfd_sfp : N3VDs<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub,0>;
2061 def : N3VDsPat<fsub, VSUBfd_sfp>;
2063 // Vector Multiply Operations used for single-precision FP
2064 let neverHasSideEffects = 1 in
2065 def VMULfd_sfp : N3VDs<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul,1>;
2066 def : N3VDsPat<fmul, VMULfd_sfp>;
2068 // Vector Multiply-Accumulate/Subtract used for single-precision FP
2069 let neverHasSideEffects = 1 in
2070 def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32,fmul,fadd>;
2071 def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
2073 let neverHasSideEffects = 1 in
2074 def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32,fmul,fsub>;
2075 def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
2077 // Vector Absolute used for single-precision FP
2078 let neverHasSideEffects = 1 in
2079 def VABSfd_sfp : N2VDInts<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32",
2080 v2f32, v2f32, int_arm_neon_vabs>;
2081 def : N2VDIntsPat<fabs, VABSfd_sfp>;
2083 // Vector Negate used for single-precision FP
2084 let neverHasSideEffects = 1 in
2085 def VNEGf32d_sfp : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
2086 (outs DPR_VFP2:$dst), (ins DPR_VFP2:$src), NoItinerary,
2087 "vneg.f32\t$dst, $src", "", []>;
2088 def : N2VDIntsPat<fneg, VNEGf32d_sfp>;
2090 // Vector Convert between single-precision FP and integer
2091 let neverHasSideEffects = 1 in
2092 def VCVTf2sd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32",
2093 v2i32, v2f32, fp_to_sint>;
2094 def : N2VDsPat<arm_ftosi, f32, v2f32, VCVTf2sd_sfp>;
2096 let neverHasSideEffects = 1 in
2097 def VCVTf2ud_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32",
2098 v2i32, v2f32, fp_to_uint>;
2099 def : N2VDsPat<arm_ftoui, f32, v2f32, VCVTf2ud_sfp>;
2101 let neverHasSideEffects = 1 in
2102 def VCVTs2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32",
2103 v2f32, v2i32, sint_to_fp>;
2104 def : N2VDsPat<arm_sitof, f32, v2i32, VCVTs2fd_sfp>;
2106 let neverHasSideEffects = 1 in
2107 def VCVTu2fd_sfp : N2VDs<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32",
2108 v2f32, v2i32, uint_to_fp>;
2109 def : N2VDsPat<arm_uitof, f32, v2i32, VCVTu2fd_sfp>;
2111 //===----------------------------------------------------------------------===//
2112 // Non-Instruction Patterns
2113 //===----------------------------------------------------------------------===//
2116 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
2117 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
2118 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
2119 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
2120 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
2121 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
2122 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
2123 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
2124 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
2125 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
2126 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
2127 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
2128 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
2129 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
2130 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
2131 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
2132 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
2133 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
2134 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
2135 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
2136 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
2137 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
2138 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
2139 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
2140 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
2141 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
2142 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
2143 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
2144 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
2145 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
2147 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
2148 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
2149 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
2150 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
2151 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
2152 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
2153 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
2154 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
2155 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
2156 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
2157 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
2158 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
2159 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
2160 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
2161 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
2162 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
2163 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
2164 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
2165 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
2166 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
2167 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
2168 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
2169 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
2170 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
2171 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
2172 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
2173 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
2174 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
2175 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
2176 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;