1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
43 def nImmVMOVI16AsmOperandByteReplicate :
45 let Name = "NEONi16vmovByteReplicate";
46 let PredicateMethod = "isNEONi16ByteReplicate";
47 let RenderMethod = "addNEONvmovByteReplicateOperands";
49 def nImmVMOVI32AsmOperandByteReplicate :
51 let Name = "NEONi32vmovByteReplicate";
52 let PredicateMethod = "isNEONi32ByteReplicate";
53 let RenderMethod = "addNEONvmovByteReplicateOperands";
55 def nImmVMVNI16AsmOperandByteReplicate :
57 let Name = "NEONi16invByteReplicate";
58 let PredicateMethod = "isNEONi16ByteReplicate";
59 let RenderMethod = "addNEONinvByteReplicateOperands";
61 def nImmVMVNI32AsmOperandByteReplicate :
63 let Name = "NEONi32invByteReplicate";
64 let PredicateMethod = "isNEONi32ByteReplicate";
65 let RenderMethod = "addNEONinvByteReplicateOperands";
68 def nImmVMOVI16ByteReplicate : Operand<i32> {
69 let PrintMethod = "printNEONModImmOperand";
70 let ParserMatchClass = nImmVMOVI16AsmOperandByteReplicate;
72 def nImmVMOVI32ByteReplicate : Operand<i32> {
73 let PrintMethod = "printNEONModImmOperand";
74 let ParserMatchClass = nImmVMOVI32AsmOperandByteReplicate;
76 def nImmVMVNI16ByteReplicate : Operand<i32> {
77 let PrintMethod = "printNEONModImmOperand";
78 let ParserMatchClass = nImmVMVNI16AsmOperandByteReplicate;
80 def nImmVMVNI32ByteReplicate : Operand<i32> {
81 let PrintMethod = "printNEONModImmOperand";
82 let ParserMatchClass = nImmVMVNI32AsmOperandByteReplicate;
85 def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
86 def nImmVMOVI32Neg : Operand<i32> {
87 let PrintMethod = "printNEONModImmOperand";
88 let ParserMatchClass = nImmVMOVI32NegAsmOperand;
90 def nImmVMOVF32 : Operand<i32> {
91 let PrintMethod = "printFPImmOperand";
92 let ParserMatchClass = FPImmOperand;
94 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
95 def nImmSplatI64 : Operand<i32> {
96 let PrintMethod = "printNEONModImmOperand";
97 let ParserMatchClass = nImmSplatI64AsmOperand;
100 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
101 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
102 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
103 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
104 return ((uint64_t)Imm) < 8;
106 let ParserMatchClass = VectorIndex8Operand;
107 let PrintMethod = "printVectorIndex";
108 let MIOperandInfo = (ops i32imm);
110 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
111 return ((uint64_t)Imm) < 4;
113 let ParserMatchClass = VectorIndex16Operand;
114 let PrintMethod = "printVectorIndex";
115 let MIOperandInfo = (ops i32imm);
117 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
118 return ((uint64_t)Imm) < 2;
120 let ParserMatchClass = VectorIndex32Operand;
121 let PrintMethod = "printVectorIndex";
122 let MIOperandInfo = (ops i32imm);
125 // Register list of one D register.
126 def VecListOneDAsmOperand : AsmOperandClass {
127 let Name = "VecListOneD";
128 let ParserMethod = "parseVectorList";
129 let RenderMethod = "addVecListOperands";
131 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
132 let ParserMatchClass = VecListOneDAsmOperand;
134 // Register list of two sequential D registers.
135 def VecListDPairAsmOperand : AsmOperandClass {
136 let Name = "VecListDPair";
137 let ParserMethod = "parseVectorList";
138 let RenderMethod = "addVecListOperands";
140 def VecListDPair : RegisterOperand<DPair, "printVectorListTwo"> {
141 let ParserMatchClass = VecListDPairAsmOperand;
143 // Register list of three sequential D registers.
144 def VecListThreeDAsmOperand : AsmOperandClass {
145 let Name = "VecListThreeD";
146 let ParserMethod = "parseVectorList";
147 let RenderMethod = "addVecListOperands";
149 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
150 let ParserMatchClass = VecListThreeDAsmOperand;
152 // Register list of four sequential D registers.
153 def VecListFourDAsmOperand : AsmOperandClass {
154 let Name = "VecListFourD";
155 let ParserMethod = "parseVectorList";
156 let RenderMethod = "addVecListOperands";
158 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
159 let ParserMatchClass = VecListFourDAsmOperand;
161 // Register list of two D registers spaced by 2 (two sequential Q registers).
162 def VecListDPairSpacedAsmOperand : AsmOperandClass {
163 let Name = "VecListDPairSpaced";
164 let ParserMethod = "parseVectorList";
165 let RenderMethod = "addVecListOperands";
167 def VecListDPairSpaced : RegisterOperand<DPair, "printVectorListTwoSpaced"> {
168 let ParserMatchClass = VecListDPairSpacedAsmOperand;
170 // Register list of three D registers spaced by 2 (three Q registers).
171 def VecListThreeQAsmOperand : AsmOperandClass {
172 let Name = "VecListThreeQ";
173 let ParserMethod = "parseVectorList";
174 let RenderMethod = "addVecListOperands";
176 def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> {
177 let ParserMatchClass = VecListThreeQAsmOperand;
179 // Register list of three D registers spaced by 2 (three Q registers).
180 def VecListFourQAsmOperand : AsmOperandClass {
181 let Name = "VecListFourQ";
182 let ParserMethod = "parseVectorList";
183 let RenderMethod = "addVecListOperands";
185 def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> {
186 let ParserMatchClass = VecListFourQAsmOperand;
189 // Register list of one D register, with "all lanes" subscripting.
190 def VecListOneDAllLanesAsmOperand : AsmOperandClass {
191 let Name = "VecListOneDAllLanes";
192 let ParserMethod = "parseVectorList";
193 let RenderMethod = "addVecListOperands";
195 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
196 let ParserMatchClass = VecListOneDAllLanesAsmOperand;
198 // Register list of two D registers, with "all lanes" subscripting.
199 def VecListDPairAllLanesAsmOperand : AsmOperandClass {
200 let Name = "VecListDPairAllLanes";
201 let ParserMethod = "parseVectorList";
202 let RenderMethod = "addVecListOperands";
204 def VecListDPairAllLanes : RegisterOperand<DPair,
205 "printVectorListTwoAllLanes"> {
206 let ParserMatchClass = VecListDPairAllLanesAsmOperand;
208 // Register list of two D registers spaced by 2 (two sequential Q registers).
209 def VecListDPairSpacedAllLanesAsmOperand : AsmOperandClass {
210 let Name = "VecListDPairSpacedAllLanes";
211 let ParserMethod = "parseVectorList";
212 let RenderMethod = "addVecListOperands";
214 def VecListDPairSpacedAllLanes : RegisterOperand<DPair,
215 "printVectorListTwoSpacedAllLanes"> {
216 let ParserMatchClass = VecListDPairSpacedAllLanesAsmOperand;
218 // Register list of three D registers, with "all lanes" subscripting.
219 def VecListThreeDAllLanesAsmOperand : AsmOperandClass {
220 let Name = "VecListThreeDAllLanes";
221 let ParserMethod = "parseVectorList";
222 let RenderMethod = "addVecListOperands";
224 def VecListThreeDAllLanes : RegisterOperand<DPR,
225 "printVectorListThreeAllLanes"> {
226 let ParserMatchClass = VecListThreeDAllLanesAsmOperand;
228 // Register list of three D registers spaced by 2 (three sequential Q regs).
229 def VecListThreeQAllLanesAsmOperand : AsmOperandClass {
230 let Name = "VecListThreeQAllLanes";
231 let ParserMethod = "parseVectorList";
232 let RenderMethod = "addVecListOperands";
234 def VecListThreeQAllLanes : RegisterOperand<DPR,
235 "printVectorListThreeSpacedAllLanes"> {
236 let ParserMatchClass = VecListThreeQAllLanesAsmOperand;
238 // Register list of four D registers, with "all lanes" subscripting.
239 def VecListFourDAllLanesAsmOperand : AsmOperandClass {
240 let Name = "VecListFourDAllLanes";
241 let ParserMethod = "parseVectorList";
242 let RenderMethod = "addVecListOperands";
244 def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> {
245 let ParserMatchClass = VecListFourDAllLanesAsmOperand;
247 // Register list of four D registers spaced by 2 (four sequential Q regs).
248 def VecListFourQAllLanesAsmOperand : AsmOperandClass {
249 let Name = "VecListFourQAllLanes";
250 let ParserMethod = "parseVectorList";
251 let RenderMethod = "addVecListOperands";
253 def VecListFourQAllLanes : RegisterOperand<DPR,
254 "printVectorListFourSpacedAllLanes"> {
255 let ParserMatchClass = VecListFourQAllLanesAsmOperand;
259 // Register list of one D register, with byte lane subscripting.
260 def VecListOneDByteIndexAsmOperand : AsmOperandClass {
261 let Name = "VecListOneDByteIndexed";
262 let ParserMethod = "parseVectorList";
263 let RenderMethod = "addVecListIndexedOperands";
265 def VecListOneDByteIndexed : Operand<i32> {
266 let ParserMatchClass = VecListOneDByteIndexAsmOperand;
267 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
269 // ...with half-word lane subscripting.
270 def VecListOneDHWordIndexAsmOperand : AsmOperandClass {
271 let Name = "VecListOneDHWordIndexed";
272 let ParserMethod = "parseVectorList";
273 let RenderMethod = "addVecListIndexedOperands";
275 def VecListOneDHWordIndexed : Operand<i32> {
276 let ParserMatchClass = VecListOneDHWordIndexAsmOperand;
277 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
279 // ...with word lane subscripting.
280 def VecListOneDWordIndexAsmOperand : AsmOperandClass {
281 let Name = "VecListOneDWordIndexed";
282 let ParserMethod = "parseVectorList";
283 let RenderMethod = "addVecListIndexedOperands";
285 def VecListOneDWordIndexed : Operand<i32> {
286 let ParserMatchClass = VecListOneDWordIndexAsmOperand;
287 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
290 // Register list of two D registers with byte lane subscripting.
291 def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
292 let Name = "VecListTwoDByteIndexed";
293 let ParserMethod = "parseVectorList";
294 let RenderMethod = "addVecListIndexedOperands";
296 def VecListTwoDByteIndexed : Operand<i32> {
297 let ParserMatchClass = VecListTwoDByteIndexAsmOperand;
298 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
300 // ...with half-word lane subscripting.
301 def VecListTwoDHWordIndexAsmOperand : AsmOperandClass {
302 let Name = "VecListTwoDHWordIndexed";
303 let ParserMethod = "parseVectorList";
304 let RenderMethod = "addVecListIndexedOperands";
306 def VecListTwoDHWordIndexed : Operand<i32> {
307 let ParserMatchClass = VecListTwoDHWordIndexAsmOperand;
308 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
310 // ...with word lane subscripting.
311 def VecListTwoDWordIndexAsmOperand : AsmOperandClass {
312 let Name = "VecListTwoDWordIndexed";
313 let ParserMethod = "parseVectorList";
314 let RenderMethod = "addVecListIndexedOperands";
316 def VecListTwoDWordIndexed : Operand<i32> {
317 let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
318 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
320 // Register list of two Q registers with half-word lane subscripting.
321 def VecListTwoQHWordIndexAsmOperand : AsmOperandClass {
322 let Name = "VecListTwoQHWordIndexed";
323 let ParserMethod = "parseVectorList";
324 let RenderMethod = "addVecListIndexedOperands";
326 def VecListTwoQHWordIndexed : Operand<i32> {
327 let ParserMatchClass = VecListTwoQHWordIndexAsmOperand;
328 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
330 // ...with word lane subscripting.
331 def VecListTwoQWordIndexAsmOperand : AsmOperandClass {
332 let Name = "VecListTwoQWordIndexed";
333 let ParserMethod = "parseVectorList";
334 let RenderMethod = "addVecListIndexedOperands";
336 def VecListTwoQWordIndexed : Operand<i32> {
337 let ParserMatchClass = VecListTwoQWordIndexAsmOperand;
338 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
342 // Register list of three D registers with byte lane subscripting.
343 def VecListThreeDByteIndexAsmOperand : AsmOperandClass {
344 let Name = "VecListThreeDByteIndexed";
345 let ParserMethod = "parseVectorList";
346 let RenderMethod = "addVecListIndexedOperands";
348 def VecListThreeDByteIndexed : Operand<i32> {
349 let ParserMatchClass = VecListThreeDByteIndexAsmOperand;
350 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
352 // ...with half-word lane subscripting.
353 def VecListThreeDHWordIndexAsmOperand : AsmOperandClass {
354 let Name = "VecListThreeDHWordIndexed";
355 let ParserMethod = "parseVectorList";
356 let RenderMethod = "addVecListIndexedOperands";
358 def VecListThreeDHWordIndexed : Operand<i32> {
359 let ParserMatchClass = VecListThreeDHWordIndexAsmOperand;
360 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
362 // ...with word lane subscripting.
363 def VecListThreeDWordIndexAsmOperand : AsmOperandClass {
364 let Name = "VecListThreeDWordIndexed";
365 let ParserMethod = "parseVectorList";
366 let RenderMethod = "addVecListIndexedOperands";
368 def VecListThreeDWordIndexed : Operand<i32> {
369 let ParserMatchClass = VecListThreeDWordIndexAsmOperand;
370 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
372 // Register list of three Q registers with half-word lane subscripting.
373 def VecListThreeQHWordIndexAsmOperand : AsmOperandClass {
374 let Name = "VecListThreeQHWordIndexed";
375 let ParserMethod = "parseVectorList";
376 let RenderMethod = "addVecListIndexedOperands";
378 def VecListThreeQHWordIndexed : Operand<i32> {
379 let ParserMatchClass = VecListThreeQHWordIndexAsmOperand;
380 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
382 // ...with word lane subscripting.
383 def VecListThreeQWordIndexAsmOperand : AsmOperandClass {
384 let Name = "VecListThreeQWordIndexed";
385 let ParserMethod = "parseVectorList";
386 let RenderMethod = "addVecListIndexedOperands";
388 def VecListThreeQWordIndexed : Operand<i32> {
389 let ParserMatchClass = VecListThreeQWordIndexAsmOperand;
390 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
393 // Register list of four D registers with byte lane subscripting.
394 def VecListFourDByteIndexAsmOperand : AsmOperandClass {
395 let Name = "VecListFourDByteIndexed";
396 let ParserMethod = "parseVectorList";
397 let RenderMethod = "addVecListIndexedOperands";
399 def VecListFourDByteIndexed : Operand<i32> {
400 let ParserMatchClass = VecListFourDByteIndexAsmOperand;
401 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
403 // ...with half-word lane subscripting.
404 def VecListFourDHWordIndexAsmOperand : AsmOperandClass {
405 let Name = "VecListFourDHWordIndexed";
406 let ParserMethod = "parseVectorList";
407 let RenderMethod = "addVecListIndexedOperands";
409 def VecListFourDHWordIndexed : Operand<i32> {
410 let ParserMatchClass = VecListFourDHWordIndexAsmOperand;
411 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
413 // ...with word lane subscripting.
414 def VecListFourDWordIndexAsmOperand : AsmOperandClass {
415 let Name = "VecListFourDWordIndexed";
416 let ParserMethod = "parseVectorList";
417 let RenderMethod = "addVecListIndexedOperands";
419 def VecListFourDWordIndexed : Operand<i32> {
420 let ParserMatchClass = VecListFourDWordIndexAsmOperand;
421 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
423 // Register list of four Q registers with half-word lane subscripting.
424 def VecListFourQHWordIndexAsmOperand : AsmOperandClass {
425 let Name = "VecListFourQHWordIndexed";
426 let ParserMethod = "parseVectorList";
427 let RenderMethod = "addVecListIndexedOperands";
429 def VecListFourQHWordIndexed : Operand<i32> {
430 let ParserMatchClass = VecListFourQHWordIndexAsmOperand;
431 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
433 // ...with word lane subscripting.
434 def VecListFourQWordIndexAsmOperand : AsmOperandClass {
435 let Name = "VecListFourQWordIndexed";
436 let ParserMethod = "parseVectorList";
437 let RenderMethod = "addVecListIndexedOperands";
439 def VecListFourQWordIndexed : Operand<i32> {
440 let ParserMatchClass = VecListFourQWordIndexAsmOperand;
441 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
444 def dword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
445 return cast<LoadSDNode>(N)->getAlignment() >= 8;
447 def dword_alignedstore : PatFrag<(ops node:$val, node:$ptr),
448 (store node:$val, node:$ptr), [{
449 return cast<StoreSDNode>(N)->getAlignment() >= 8;
451 def word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
452 return cast<LoadSDNode>(N)->getAlignment() == 4;
454 def word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
455 (store node:$val, node:$ptr), [{
456 return cast<StoreSDNode>(N)->getAlignment() == 4;
458 def hword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
459 return cast<LoadSDNode>(N)->getAlignment() == 2;
461 def hword_alignedstore : PatFrag<(ops node:$val, node:$ptr),
462 (store node:$val, node:$ptr), [{
463 return cast<StoreSDNode>(N)->getAlignment() == 2;
465 def byte_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
466 return cast<LoadSDNode>(N)->getAlignment() == 1;
468 def byte_alignedstore : PatFrag<(ops node:$val, node:$ptr),
469 (store node:$val, node:$ptr), [{
470 return cast<StoreSDNode>(N)->getAlignment() == 1;
472 def non_word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
473 return cast<LoadSDNode>(N)->getAlignment() < 4;
475 def non_word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
476 (store node:$val, node:$ptr), [{
477 return cast<StoreSDNode>(N)->getAlignment() < 4;
480 //===----------------------------------------------------------------------===//
481 // NEON-specific DAG Nodes.
482 //===----------------------------------------------------------------------===//
484 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
485 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
487 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
488 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
489 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
490 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
491 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
492 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
493 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
494 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
495 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
496 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
497 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
499 // Types for vector shift by immediates. The "SHX" version is for long and
500 // narrow operations where the source and destination vectors have different
501 // types. The "SHINS" version is for shift and insert operations.
502 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
504 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
506 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
507 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
509 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
510 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
511 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
512 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
514 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
515 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
516 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
518 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
519 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
520 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
521 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
522 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
523 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
525 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
526 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
527 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
529 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
530 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
532 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
534 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
535 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
537 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
538 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
539 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
540 def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
542 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
544 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
545 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
547 def NEONvbsl : SDNode<"ARMISD::VBSL",
548 SDTypeProfile<1, 3, [SDTCisVec<0>,
551 SDTCisSameAs<0, 3>]>>;
553 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
555 // VDUPLANE can produce a quad-register result from a double-register source,
556 // so the result is not constrained to match the source.
557 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
558 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
561 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
562 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
563 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
565 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
566 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
567 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
568 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
570 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
572 SDTCisSameAs<0, 3>]>;
573 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
574 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
575 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
577 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
578 SDTCisSameAs<1, 2>]>;
579 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
580 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
582 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
583 SDTCisSameAs<0, 2>]>;
584 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
585 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
587 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
588 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
589 unsigned EltBits = 0;
590 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
591 return (EltBits == 32 && EltVal == 0);
594 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
595 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
596 unsigned EltBits = 0;
597 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
598 return (EltBits == 8 && EltVal == 0xff);
601 //===----------------------------------------------------------------------===//
602 // NEON load / store instructions
603 //===----------------------------------------------------------------------===//
605 // Use VLDM to load a Q register as a D register pair.
606 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
608 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
610 [(set DPair:$dst, (v2f64 (load GPR:$Rn)))]>;
612 // Use VSTM to store a Q register as a D register pair.
613 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
615 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
617 [(store (v2f64 DPair:$src), GPR:$Rn)]>;
619 // Classes for VLD* pseudo-instructions with multi-register operands.
620 // These are expanded to real instructions after register allocation.
621 class VLDQPseudo<InstrItinClass itin>
622 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
623 class VLDQWBPseudo<InstrItinClass itin>
624 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
625 (ins addrmode6:$addr, am6offset:$offset), itin,
627 class VLDQWBfixedPseudo<InstrItinClass itin>
628 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
629 (ins addrmode6:$addr), itin,
631 class VLDQWBregisterPseudo<InstrItinClass itin>
632 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
633 (ins addrmode6:$addr, rGPR:$offset), itin,
636 class VLDQQPseudo<InstrItinClass itin>
637 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
638 class VLDQQWBPseudo<InstrItinClass itin>
639 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
640 (ins addrmode6:$addr, am6offset:$offset), itin,
642 class VLDQQWBfixedPseudo<InstrItinClass itin>
643 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
644 (ins addrmode6:$addr), itin,
646 class VLDQQWBregisterPseudo<InstrItinClass itin>
647 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
648 (ins addrmode6:$addr, rGPR:$offset), itin,
652 class VLDQQQQPseudo<InstrItinClass itin>
653 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
655 class VLDQQQQWBPseudo<InstrItinClass itin>
656 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
657 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
658 "$addr.addr = $wb, $src = $dst">;
660 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
662 // VLD1 : Vector Load (multiple single elements)
663 class VLD1D<bits<4> op7_4, string Dt, Operand AddrMode>
664 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
665 (ins AddrMode:$Rn), IIC_VLD1,
666 "vld1", Dt, "$Vd, $Rn", "", []> {
669 let DecoderMethod = "DecodeVLDST1Instruction";
671 class VLD1Q<bits<4> op7_4, string Dt, Operand AddrMode>
672 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
673 (ins AddrMode:$Rn), IIC_VLD1x2,
674 "vld1", Dt, "$Vd, $Rn", "", []> {
676 let Inst{5-4} = Rn{5-4};
677 let DecoderMethod = "DecodeVLDST1Instruction";
680 def VLD1d8 : VLD1D<{0,0,0,?}, "8", addrmode6align64>;
681 def VLD1d16 : VLD1D<{0,1,0,?}, "16", addrmode6align64>;
682 def VLD1d32 : VLD1D<{1,0,0,?}, "32", addrmode6align64>;
683 def VLD1d64 : VLD1D<{1,1,0,?}, "64", addrmode6align64>;
685 def VLD1q8 : VLD1Q<{0,0,?,?}, "8", addrmode6align64or128>;
686 def VLD1q16 : VLD1Q<{0,1,?,?}, "16", addrmode6align64or128>;
687 def VLD1q32 : VLD1Q<{1,0,?,?}, "32", addrmode6align64or128>;
688 def VLD1q64 : VLD1Q<{1,1,?,?}, "64", addrmode6align64or128>;
690 // ...with address register writeback:
691 multiclass VLD1DWB<bits<4> op7_4, string Dt, Operand AddrMode> {
692 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
693 (ins AddrMode:$Rn), IIC_VLD1u,
694 "vld1", Dt, "$Vd, $Rn!",
695 "$Rn.addr = $wb", []> {
696 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
698 let DecoderMethod = "DecodeVLDST1Instruction";
700 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
701 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u,
702 "vld1", Dt, "$Vd, $Rn, $Rm",
703 "$Rn.addr = $wb", []> {
705 let DecoderMethod = "DecodeVLDST1Instruction";
708 multiclass VLD1QWB<bits<4> op7_4, string Dt, Operand AddrMode> {
709 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
710 (ins AddrMode:$Rn), IIC_VLD1x2u,
711 "vld1", Dt, "$Vd, $Rn!",
712 "$Rn.addr = $wb", []> {
713 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
714 let Inst{5-4} = Rn{5-4};
715 let DecoderMethod = "DecodeVLDST1Instruction";
717 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
718 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
719 "vld1", Dt, "$Vd, $Rn, $Rm",
720 "$Rn.addr = $wb", []> {
721 let Inst{5-4} = Rn{5-4};
722 let DecoderMethod = "DecodeVLDST1Instruction";
726 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8", addrmode6align64>;
727 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16", addrmode6align64>;
728 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32", addrmode6align64>;
729 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64", addrmode6align64>;
730 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8", addrmode6align64or128>;
731 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16", addrmode6align64or128>;
732 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32", addrmode6align64or128>;
733 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64", addrmode6align64or128>;
735 // ...with 3 registers
736 class VLD1D3<bits<4> op7_4, string Dt, Operand AddrMode>
737 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
738 (ins AddrMode:$Rn), IIC_VLD1x3, "vld1", Dt,
739 "$Vd, $Rn", "", []> {
742 let DecoderMethod = "DecodeVLDST1Instruction";
744 multiclass VLD1D3WB<bits<4> op7_4, string Dt, Operand AddrMode> {
745 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
746 (ins AddrMode:$Rn), IIC_VLD1x2u,
747 "vld1", Dt, "$Vd, $Rn!",
748 "$Rn.addr = $wb", []> {
749 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
751 let DecoderMethod = "DecodeVLDST1Instruction";
753 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
754 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
755 "vld1", Dt, "$Vd, $Rn, $Rm",
756 "$Rn.addr = $wb", []> {
758 let DecoderMethod = "DecodeVLDST1Instruction";
762 def VLD1d8T : VLD1D3<{0,0,0,?}, "8", addrmode6align64>;
763 def VLD1d16T : VLD1D3<{0,1,0,?}, "16", addrmode6align64>;
764 def VLD1d32T : VLD1D3<{1,0,0,?}, "32", addrmode6align64>;
765 def VLD1d64T : VLD1D3<{1,1,0,?}, "64", addrmode6align64>;
767 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8", addrmode6align64>;
768 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16", addrmode6align64>;
769 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32", addrmode6align64>;
770 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64", addrmode6align64>;
772 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
773 def VLD1d64TPseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD1x3>;
774 def VLD1d64TPseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD1x3>;
776 // ...with 4 registers
777 class VLD1D4<bits<4> op7_4, string Dt, Operand AddrMode>
778 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
779 (ins AddrMode:$Rn), IIC_VLD1x4, "vld1", Dt,
780 "$Vd, $Rn", "", []> {
782 let Inst{5-4} = Rn{5-4};
783 let DecoderMethod = "DecodeVLDST1Instruction";
785 multiclass VLD1D4WB<bits<4> op7_4, string Dt, Operand AddrMode> {
786 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
787 (ins AddrMode:$Rn), IIC_VLD1x2u,
788 "vld1", Dt, "$Vd, $Rn!",
789 "$Rn.addr = $wb", []> {
790 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
791 let Inst{5-4} = Rn{5-4};
792 let DecoderMethod = "DecodeVLDST1Instruction";
794 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
795 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
796 "vld1", Dt, "$Vd, $Rn, $Rm",
797 "$Rn.addr = $wb", []> {
798 let Inst{5-4} = Rn{5-4};
799 let DecoderMethod = "DecodeVLDST1Instruction";
803 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8", addrmode6align64or128or256>;
804 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16", addrmode6align64or128or256>;
805 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32", addrmode6align64or128or256>;
806 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64", addrmode6align64or128or256>;
808 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8", addrmode6align64or128or256>;
809 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>;
810 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>;
811 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>;
813 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
814 def VLD1d64QPseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD1x4>;
815 def VLD1d64QPseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD1x4>;
817 // VLD2 : Vector Load (multiple 2-element structures)
818 class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
819 InstrItinClass itin, Operand AddrMode>
820 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
821 (ins AddrMode:$Rn), itin,
822 "vld2", Dt, "$Vd, $Rn", "", []> {
824 let Inst{5-4} = Rn{5-4};
825 let DecoderMethod = "DecodeVLDST2Instruction";
828 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2,
829 addrmode6align64or128>;
830 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2,
831 addrmode6align64or128>;
832 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2,
833 addrmode6align64or128>;
835 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2,
836 addrmode6align64or128or256>;
837 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2,
838 addrmode6align64or128or256>;
839 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2,
840 addrmode6align64or128or256>;
842 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
843 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
844 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
846 // ...with address register writeback:
847 multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
848 RegisterOperand VdTy, InstrItinClass itin, Operand AddrMode> {
849 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
850 (ins AddrMode:$Rn), itin,
851 "vld2", Dt, "$Vd, $Rn!",
852 "$Rn.addr = $wb", []> {
853 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
854 let Inst{5-4} = Rn{5-4};
855 let DecoderMethod = "DecodeVLDST2Instruction";
857 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
858 (ins AddrMode:$Rn, rGPR:$Rm), itin,
859 "vld2", Dt, "$Vd, $Rn, $Rm",
860 "$Rn.addr = $wb", []> {
861 let Inst{5-4} = Rn{5-4};
862 let DecoderMethod = "DecodeVLDST2Instruction";
866 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u,
867 addrmode6align64or128>;
868 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u,
869 addrmode6align64or128>;
870 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u,
871 addrmode6align64or128>;
873 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u,
874 addrmode6align64or128or256>;
875 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u,
876 addrmode6align64or128or256>;
877 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u,
878 addrmode6align64or128or256>;
880 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
881 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
882 def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
883 def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
884 def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
885 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
887 // ...with double-spaced registers
888 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2,
889 addrmode6align64or128>;
890 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2,
891 addrmode6align64or128>;
892 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2,
893 addrmode6align64or128>;
894 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u,
895 addrmode6align64or128>;
896 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u,
897 addrmode6align64or128>;
898 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u,
899 addrmode6align64or128>;
901 // VLD3 : Vector Load (multiple 3-element structures)
902 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
903 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
904 (ins addrmode6:$Rn), IIC_VLD3,
905 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
908 let DecoderMethod = "DecodeVLDST3Instruction";
911 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
912 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
913 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
915 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
916 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
917 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
919 // ...with address register writeback:
920 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
921 : NLdSt<0, 0b10, op11_8, op7_4,
922 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
923 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
924 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
925 "$Rn.addr = $wb", []> {
927 let DecoderMethod = "DecodeVLDST3Instruction";
930 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
931 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
932 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
934 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
935 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
936 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
938 // ...with double-spaced registers:
939 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
940 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
941 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
942 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
943 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
944 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
946 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
947 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
948 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
950 // ...alternate versions to be allocated odd register numbers:
951 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
952 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
953 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
955 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
956 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
957 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
959 // VLD4 : Vector Load (multiple 4-element structures)
960 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
961 : NLdSt<0, 0b10, op11_8, op7_4,
962 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
963 (ins addrmode6:$Rn), IIC_VLD4,
964 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
966 let Inst{5-4} = Rn{5-4};
967 let DecoderMethod = "DecodeVLDST4Instruction";
970 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
971 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
972 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
974 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
975 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
976 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
978 // ...with address register writeback:
979 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
980 : NLdSt<0, 0b10, op11_8, op7_4,
981 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
982 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
983 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
984 "$Rn.addr = $wb", []> {
985 let Inst{5-4} = Rn{5-4};
986 let DecoderMethod = "DecodeVLDST4Instruction";
989 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
990 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
991 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
993 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
994 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
995 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
997 // ...with double-spaced registers:
998 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
999 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
1000 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
1001 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
1002 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
1003 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
1005 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1006 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1007 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1009 // ...alternate versions to be allocated odd register numbers:
1010 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
1011 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
1012 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
1014 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1015 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1016 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
1018 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1020 // Classes for VLD*LN pseudo-instructions with multi-register operands.
1021 // These are expanded to real instructions after register allocation.
1022 class VLDQLNPseudo<InstrItinClass itin>
1023 : PseudoNLdSt<(outs QPR:$dst),
1024 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1025 itin, "$src = $dst">;
1026 class VLDQLNWBPseudo<InstrItinClass itin>
1027 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1028 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1029 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1030 class VLDQQLNPseudo<InstrItinClass itin>
1031 : PseudoNLdSt<(outs QQPR:$dst),
1032 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1033 itin, "$src = $dst">;
1034 class VLDQQLNWBPseudo<InstrItinClass itin>
1035 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
1036 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1037 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1038 class VLDQQQQLNPseudo<InstrItinClass itin>
1039 : PseudoNLdSt<(outs QQQQPR:$dst),
1040 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1041 itin, "$src = $dst">;
1042 class VLDQQQQLNWBPseudo<InstrItinClass itin>
1043 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
1044 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1045 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1047 // VLD1LN : Vector Load (single element to one lane)
1048 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1050 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1051 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
1052 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1054 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1055 (i32 (LoadOp addrmode6:$Rn)),
1058 let DecoderMethod = "DecodeVLD1LN";
1060 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1062 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1063 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
1064 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1066 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1067 (i32 (LoadOp addrmode6oneL32:$Rn)),
1070 let DecoderMethod = "DecodeVLD1LN";
1072 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
1073 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1074 (i32 (LoadOp addrmode6:$addr)),
1078 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
1079 let Inst{7-5} = lane{2-0};
1081 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
1082 let Inst{7-6} = lane{1-0};
1083 let Inst{5-4} = Rn{5-4};
1085 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
1086 let Inst{7} = lane{0};
1087 let Inst{5-4} = Rn{5-4};
1090 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
1091 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
1092 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1094 def : Pat<(vector_insert (v2f32 DPR:$src),
1095 (f32 (load addrmode6:$addr)), imm:$lane),
1096 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1097 def : Pat<(vector_insert (v4f32 QPR:$src),
1098 (f32 (load addrmode6:$addr)), imm:$lane),
1099 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1101 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1103 // ...with address register writeback:
1104 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1105 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
1106 (ins addrmode6:$Rn, am6offset:$Rm,
1107 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
1108 "\\{$Vd[$lane]\\}, $Rn$Rm",
1109 "$src = $Vd, $Rn.addr = $wb", []> {
1110 let DecoderMethod = "DecodeVLD1LN";
1113 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
1114 let Inst{7-5} = lane{2-0};
1116 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
1117 let Inst{7-6} = lane{1-0};
1118 let Inst{4} = Rn{4};
1120 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
1121 let Inst{7} = lane{0};
1122 let Inst{5} = Rn{4};
1123 let Inst{4} = Rn{4};
1126 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1127 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1128 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1130 // VLD2LN : Vector Load (single 2-element structure to one lane)
1131 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1132 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
1133 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1134 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1135 "$src1 = $Vd, $src2 = $dst2", []> {
1137 let Inst{4} = Rn{4};
1138 let DecoderMethod = "DecodeVLD2LN";
1141 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1142 let Inst{7-5} = lane{2-0};
1144 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
1145 let Inst{7-6} = lane{1-0};
1147 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
1148 let Inst{7} = lane{0};
1151 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1152 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1153 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1155 // ...with double-spaced registers:
1156 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
1157 let Inst{7-6} = lane{1-0};
1159 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
1160 let Inst{7} = lane{0};
1163 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1164 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1166 // ...with address register writeback:
1167 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1168 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1169 (ins addrmode6:$Rn, am6offset:$Rm,
1170 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
1171 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1172 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1173 let Inst{4} = Rn{4};
1174 let DecoderMethod = "DecodeVLD2LN";
1177 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
1178 let Inst{7-5} = lane{2-0};
1180 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
1181 let Inst{7-6} = lane{1-0};
1183 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
1184 let Inst{7} = lane{0};
1187 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1188 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1189 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1191 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
1192 let Inst{7-6} = lane{1-0};
1194 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
1195 let Inst{7} = lane{0};
1198 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1199 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1201 // VLD3LN : Vector Load (single 3-element structure to one lane)
1202 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1203 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1204 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
1205 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
1206 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1207 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
1209 let DecoderMethod = "DecodeVLD3LN";
1212 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
1213 let Inst{7-5} = lane{2-0};
1215 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
1216 let Inst{7-6} = lane{1-0};
1218 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
1219 let Inst{7} = lane{0};
1222 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1223 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1224 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1226 // ...with double-spaced registers:
1227 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
1228 let Inst{7-6} = lane{1-0};
1230 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
1231 let Inst{7} = lane{0};
1234 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1235 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1237 // ...with address register writeback:
1238 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1239 : NLdStLn<1, 0b10, op11_8, op7_4,
1240 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1241 (ins addrmode6:$Rn, am6offset:$Rm,
1242 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1243 IIC_VLD3lnu, "vld3", Dt,
1244 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1245 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1247 let DecoderMethod = "DecodeVLD3LN";
1250 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
1251 let Inst{7-5} = lane{2-0};
1253 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
1254 let Inst{7-6} = lane{1-0};
1256 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
1257 let Inst{7} = lane{0};
1260 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1261 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1262 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1264 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
1265 let Inst{7-6} = lane{1-0};
1267 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
1268 let Inst{7} = lane{0};
1271 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1272 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1274 // VLD4LN : Vector Load (single 4-element structure to one lane)
1275 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1276 : NLdStLn<1, 0b10, op11_8, op7_4,
1277 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1278 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1279 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1280 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1281 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1283 let Inst{4} = Rn{4};
1284 let DecoderMethod = "DecodeVLD4LN";
1287 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1288 let Inst{7-5} = lane{2-0};
1290 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1291 let Inst{7-6} = lane{1-0};
1293 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1294 let Inst{7} = lane{0};
1295 let Inst{5} = Rn{5};
1298 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1299 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1300 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1302 // ...with double-spaced registers:
1303 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1304 let Inst{7-6} = lane{1-0};
1306 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1307 let Inst{7} = lane{0};
1308 let Inst{5} = Rn{5};
1311 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1312 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1314 // ...with address register writeback:
1315 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1316 : NLdStLn<1, 0b10, op11_8, op7_4,
1317 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1318 (ins addrmode6:$Rn, am6offset:$Rm,
1319 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1320 IIC_VLD4lnu, "vld4", Dt,
1321 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1322 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1324 let Inst{4} = Rn{4};
1325 let DecoderMethod = "DecodeVLD4LN" ;
1328 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1329 let Inst{7-5} = lane{2-0};
1331 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1332 let Inst{7-6} = lane{1-0};
1334 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1335 let Inst{7} = lane{0};
1336 let Inst{5} = Rn{5};
1339 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1340 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1341 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1343 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1344 let Inst{7-6} = lane{1-0};
1346 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
1347 let Inst{7} = lane{0};
1348 let Inst{5} = Rn{5};
1351 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1352 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1354 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1356 // VLD1DUP : Vector Load (single element to all lanes)
1357 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
1359 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1361 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1362 [(set VecListOneDAllLanes:$Vd,
1363 (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> {
1365 let Inst{4} = Rn{4};
1366 let DecoderMethod = "DecodeVLD1DupInstruction";
1368 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8,
1369 addrmode6dupalignNone>;
1370 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16,
1371 addrmode6dupalign16>;
1372 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load,
1373 addrmode6dupalign32>;
1375 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1376 (VLD1DUPd32 addrmode6:$addr)>;
1378 class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
1380 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1381 (ins AddrMode:$Rn), IIC_VLD1dup,
1382 "vld1", Dt, "$Vd, $Rn", "",
1383 [(set VecListDPairAllLanes:$Vd,
1384 (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> {
1386 let Inst{4} = Rn{4};
1387 let DecoderMethod = "DecodeVLD1DupInstruction";
1390 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8,
1391 addrmode6dupalignNone>;
1392 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16,
1393 addrmode6dupalign16>;
1394 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load,
1395 addrmode6dupalign32>;
1397 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1398 (VLD1DUPq32 addrmode6:$addr)>;
1400 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1401 // ...with address register writeback:
1402 multiclass VLD1DUPWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1403 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1404 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1405 (ins AddrMode:$Rn), IIC_VLD1dupu,
1406 "vld1", Dt, "$Vd, $Rn!",
1407 "$Rn.addr = $wb", []> {
1408 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1409 let Inst{4} = Rn{4};
1410 let DecoderMethod = "DecodeVLD1DupInstruction";
1412 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1413 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1414 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1415 "vld1", Dt, "$Vd, $Rn, $Rm",
1416 "$Rn.addr = $wb", []> {
1417 let Inst{4} = Rn{4};
1418 let DecoderMethod = "DecodeVLD1DupInstruction";
1421 multiclass VLD1QDUPWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1422 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1423 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1424 (ins AddrMode:$Rn), IIC_VLD1dupu,
1425 "vld1", Dt, "$Vd, $Rn!",
1426 "$Rn.addr = $wb", []> {
1427 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1428 let Inst{4} = Rn{4};
1429 let DecoderMethod = "DecodeVLD1DupInstruction";
1431 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1432 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1433 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1434 "vld1", Dt, "$Vd, $Rn, $Rm",
1435 "$Rn.addr = $wb", []> {
1436 let Inst{4} = Rn{4};
1437 let DecoderMethod = "DecodeVLD1DupInstruction";
1441 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8", addrmode6dupalignNone>;
1442 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16", addrmode6dupalign16>;
1443 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32", addrmode6dupalign32>;
1445 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8", addrmode6dupalignNone>;
1446 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16", addrmode6dupalign16>;
1447 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32", addrmode6dupalign32>;
1449 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1450 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
1451 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1452 (ins AddrMode:$Rn), IIC_VLD2dup,
1453 "vld2", Dt, "$Vd, $Rn", "", []> {
1455 let Inst{4} = Rn{4};
1456 let DecoderMethod = "DecodeVLD2DupInstruction";
1459 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1460 addrmode6dupalign16>;
1461 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1462 addrmode6dupalign32>;
1463 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1464 addrmode6dupalign64>;
1466 // HACK this one, VLD2DUPd8x2 must be changed at the same time with VLD2b8 or
1467 // "vld2.8 {d0[], d2[]}, [r4:32]" will become "vld2.8 {d0, d2}, [r4:32]".
1468 // ...with double-spaced registers
1469 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1470 addrmode6dupalign16>;
1471 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1472 addrmode6dupalign32>;
1473 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
1474 addrmode6dupalign64>;
1476 // ...with address register writeback:
1477 multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy,
1479 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
1480 (outs VdTy:$Vd, GPR:$wb),
1481 (ins AddrMode:$Rn), IIC_VLD2dupu,
1482 "vld2", Dt, "$Vd, $Rn!",
1483 "$Rn.addr = $wb", []> {
1484 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1485 let Inst{4} = Rn{4};
1486 let DecoderMethod = "DecodeVLD2DupInstruction";
1488 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
1489 (outs VdTy:$Vd, GPR:$wb),
1490 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1491 "vld2", Dt, "$Vd, $Rn, $Rm",
1492 "$Rn.addr = $wb", []> {
1493 let Inst{4} = Rn{4};
1494 let DecoderMethod = "DecodeVLD2DupInstruction";
1498 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes,
1499 addrmode6dupalign16>;
1500 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes,
1501 addrmode6dupalign32>;
1502 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes,
1503 addrmode6dupalign64>;
1505 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes,
1506 addrmode6dupalign16>;
1507 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1508 addrmode6dupalign32>;
1509 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
1510 addrmode6dupalign64>;
1512 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1513 class VLD3DUP<bits<4> op7_4, string Dt>
1514 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1515 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1516 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1519 let DecoderMethod = "DecodeVLD3DupInstruction";
1522 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1523 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1524 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1526 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1527 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1528 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1530 // ...with double-spaced registers (not used for codegen):
1531 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1532 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1533 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
1535 // ...with address register writeback:
1536 class VLD3DUPWB<bits<4> op7_4, string Dt, Operand AddrMode>
1537 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1538 (ins AddrMode:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1539 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1540 "$Rn.addr = $wb", []> {
1542 let DecoderMethod = "DecodeVLD3DupInstruction";
1545 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8", addrmode6dupalign64>;
1546 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16", addrmode6dupalign64>;
1547 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32", addrmode6dupalign64>;
1549 def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8", addrmode6dupalign64>;
1550 def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16", addrmode6dupalign64>;
1551 def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32", addrmode6dupalign64>;
1553 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1554 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1555 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1557 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1558 class VLD4DUP<bits<4> op7_4, string Dt>
1559 : NLdSt<1, 0b10, 0b1111, op7_4,
1560 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1561 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1562 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1564 let Inst{4} = Rn{4};
1565 let DecoderMethod = "DecodeVLD4DupInstruction";
1568 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1569 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1570 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1572 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1573 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1574 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1576 // ...with double-spaced registers (not used for codegen):
1577 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1578 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1579 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1581 // ...with address register writeback:
1582 class VLD4DUPWB<bits<4> op7_4, string Dt>
1583 : NLdSt<1, 0b10, 0b1111, op7_4,
1584 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1585 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1586 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1587 "$Rn.addr = $wb", []> {
1588 let Inst{4} = Rn{4};
1589 let DecoderMethod = "DecodeVLD4DupInstruction";
1592 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1593 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1594 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1596 def VLD4DUPq8_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1597 def VLD4DUPq16_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1598 def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1600 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1601 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1602 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1604 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1606 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1608 // Classes for VST* pseudo-instructions with multi-register operands.
1609 // These are expanded to real instructions after register allocation.
1610 class VSTQPseudo<InstrItinClass itin>
1611 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1612 class VSTQWBPseudo<InstrItinClass itin>
1613 : PseudoNLdSt<(outs GPR:$wb),
1614 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1615 "$addr.addr = $wb">;
1616 class VSTQWBfixedPseudo<InstrItinClass itin>
1617 : PseudoNLdSt<(outs GPR:$wb),
1618 (ins addrmode6:$addr, QPR:$src), itin,
1619 "$addr.addr = $wb">;
1620 class VSTQWBregisterPseudo<InstrItinClass itin>
1621 : PseudoNLdSt<(outs GPR:$wb),
1622 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1623 "$addr.addr = $wb">;
1624 class VSTQQPseudo<InstrItinClass itin>
1625 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1626 class VSTQQWBPseudo<InstrItinClass itin>
1627 : PseudoNLdSt<(outs GPR:$wb),
1628 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1629 "$addr.addr = $wb">;
1630 class VSTQQWBfixedPseudo<InstrItinClass itin>
1631 : PseudoNLdSt<(outs GPR:$wb),
1632 (ins addrmode6:$addr, QQPR:$src), itin,
1633 "$addr.addr = $wb">;
1634 class VSTQQWBregisterPseudo<InstrItinClass itin>
1635 : PseudoNLdSt<(outs GPR:$wb),
1636 (ins addrmode6:$addr, rGPR:$offset, QQPR:$src), itin,
1637 "$addr.addr = $wb">;
1639 class VSTQQQQPseudo<InstrItinClass itin>
1640 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1641 class VSTQQQQWBPseudo<InstrItinClass itin>
1642 : PseudoNLdSt<(outs GPR:$wb),
1643 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1644 "$addr.addr = $wb">;
1646 // VST1 : Vector Store (multiple single elements)
1647 class VST1D<bits<4> op7_4, string Dt, Operand AddrMode>
1648 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
1649 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1651 let Inst{4} = Rn{4};
1652 let DecoderMethod = "DecodeVLDST1Instruction";
1654 class VST1Q<bits<4> op7_4, string Dt, Operand AddrMode>
1655 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),
1656 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1658 let Inst{5-4} = Rn{5-4};
1659 let DecoderMethod = "DecodeVLDST1Instruction";
1662 def VST1d8 : VST1D<{0,0,0,?}, "8", addrmode6align64>;
1663 def VST1d16 : VST1D<{0,1,0,?}, "16", addrmode6align64>;
1664 def VST1d32 : VST1D<{1,0,0,?}, "32", addrmode6align64>;
1665 def VST1d64 : VST1D<{1,1,0,?}, "64", addrmode6align64>;
1667 def VST1q8 : VST1Q<{0,0,?,?}, "8", addrmode6align64or128>;
1668 def VST1q16 : VST1Q<{0,1,?,?}, "16", addrmode6align64or128>;
1669 def VST1q32 : VST1Q<{1,0,?,?}, "32", addrmode6align64or128>;
1670 def VST1q64 : VST1Q<{1,1,?,?}, "64", addrmode6align64or128>;
1672 // ...with address register writeback:
1673 multiclass VST1DWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1674 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1675 (ins AddrMode:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1676 "vst1", Dt, "$Vd, $Rn!",
1677 "$Rn.addr = $wb", []> {
1678 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1679 let Inst{4} = Rn{4};
1680 let DecoderMethod = "DecodeVLDST1Instruction";
1682 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1683 (ins AddrMode:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1685 "vst1", Dt, "$Vd, $Rn, $Rm",
1686 "$Rn.addr = $wb", []> {
1687 let Inst{4} = Rn{4};
1688 let DecoderMethod = "DecodeVLDST1Instruction";
1691 multiclass VST1QWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1692 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1693 (ins AddrMode:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1694 "vst1", Dt, "$Vd, $Rn!",
1695 "$Rn.addr = $wb", []> {
1696 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1697 let Inst{5-4} = Rn{5-4};
1698 let DecoderMethod = "DecodeVLDST1Instruction";
1700 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1701 (ins AddrMode:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1703 "vst1", Dt, "$Vd, $Rn, $Rm",
1704 "$Rn.addr = $wb", []> {
1705 let Inst{5-4} = Rn{5-4};
1706 let DecoderMethod = "DecodeVLDST1Instruction";
1710 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8", addrmode6align64>;
1711 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16", addrmode6align64>;
1712 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32", addrmode6align64>;
1713 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64", addrmode6align64>;
1715 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8", addrmode6align64or128>;
1716 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16", addrmode6align64or128>;
1717 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32", addrmode6align64or128>;
1718 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64", addrmode6align64or128>;
1720 // ...with 3 registers
1721 class VST1D3<bits<4> op7_4, string Dt, Operand AddrMode>
1722 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1723 (ins AddrMode:$Rn, VecListThreeD:$Vd),
1724 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
1726 let Inst{4} = Rn{4};
1727 let DecoderMethod = "DecodeVLDST1Instruction";
1729 multiclass VST1D3WB<bits<4> op7_4, string Dt, Operand AddrMode> {
1730 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1731 (ins AddrMode:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1732 "vst1", Dt, "$Vd, $Rn!",
1733 "$Rn.addr = $wb", []> {
1734 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1735 let Inst{5-4} = Rn{5-4};
1736 let DecoderMethod = "DecodeVLDST1Instruction";
1738 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1739 (ins AddrMode:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1741 "vst1", Dt, "$Vd, $Rn, $Rm",
1742 "$Rn.addr = $wb", []> {
1743 let Inst{5-4} = Rn{5-4};
1744 let DecoderMethod = "DecodeVLDST1Instruction";
1748 def VST1d8T : VST1D3<{0,0,0,?}, "8", addrmode6align64>;
1749 def VST1d16T : VST1D3<{0,1,0,?}, "16", addrmode6align64>;
1750 def VST1d32T : VST1D3<{1,0,0,?}, "32", addrmode6align64>;
1751 def VST1d64T : VST1D3<{1,1,0,?}, "64", addrmode6align64>;
1753 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8", addrmode6align64>;
1754 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16", addrmode6align64>;
1755 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32", addrmode6align64>;
1756 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64", addrmode6align64>;
1758 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1759 def VST1d64TPseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST1x3u>;
1760 def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
1762 // ...with 4 registers
1763 class VST1D4<bits<4> op7_4, string Dt, Operand AddrMode>
1764 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1765 (ins AddrMode:$Rn, VecListFourD:$Vd),
1766 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1769 let Inst{5-4} = Rn{5-4};
1770 let DecoderMethod = "DecodeVLDST1Instruction";
1772 multiclass VST1D4WB<bits<4> op7_4, string Dt, Operand AddrMode> {
1773 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1774 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1775 "vst1", Dt, "$Vd, $Rn!",
1776 "$Rn.addr = $wb", []> {
1777 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1778 let Inst{5-4} = Rn{5-4};
1779 let DecoderMethod = "DecodeVLDST1Instruction";
1781 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1782 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1784 "vst1", Dt, "$Vd, $Rn, $Rm",
1785 "$Rn.addr = $wb", []> {
1786 let Inst{5-4} = Rn{5-4};
1787 let DecoderMethod = "DecodeVLDST1Instruction";
1791 def VST1d8Q : VST1D4<{0,0,?,?}, "8", addrmode6align64or128or256>;
1792 def VST1d16Q : VST1D4<{0,1,?,?}, "16", addrmode6align64or128or256>;
1793 def VST1d32Q : VST1D4<{1,0,?,?}, "32", addrmode6align64or128or256>;
1794 def VST1d64Q : VST1D4<{1,1,?,?}, "64", addrmode6align64or128or256>;
1796 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8", addrmode6align64or128or256>;
1797 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>;
1798 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>;
1799 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>;
1801 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1802 def VST1d64QPseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST1x4u>;
1803 def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>;
1805 // VST2 : Vector Store (multiple 2-element structures)
1806 class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1807 InstrItinClass itin, Operand AddrMode>
1808 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins AddrMode:$Rn, VdTy:$Vd),
1809 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1811 let Inst{5-4} = Rn{5-4};
1812 let DecoderMethod = "DecodeVLDST2Instruction";
1815 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2,
1816 addrmode6align64or128>;
1817 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2,
1818 addrmode6align64or128>;
1819 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2,
1820 addrmode6align64or128>;
1822 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2,
1823 addrmode6align64or128or256>;
1824 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2,
1825 addrmode6align64or128or256>;
1826 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2,
1827 addrmode6align64or128or256>;
1829 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1830 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1831 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1833 // ...with address register writeback:
1834 multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
1835 RegisterOperand VdTy, Operand AddrMode> {
1836 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1837 (ins AddrMode:$Rn, VdTy:$Vd), IIC_VLD1u,
1838 "vst2", Dt, "$Vd, $Rn!",
1839 "$Rn.addr = $wb", []> {
1840 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1841 let Inst{5-4} = Rn{5-4};
1842 let DecoderMethod = "DecodeVLDST2Instruction";
1844 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1845 (ins AddrMode:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1846 "vst2", Dt, "$Vd, $Rn, $Rm",
1847 "$Rn.addr = $wb", []> {
1848 let Inst{5-4} = Rn{5-4};
1849 let DecoderMethod = "DecodeVLDST2Instruction";
1852 multiclass VST2QWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1853 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1854 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1855 "vst2", Dt, "$Vd, $Rn!",
1856 "$Rn.addr = $wb", []> {
1857 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1858 let Inst{5-4} = Rn{5-4};
1859 let DecoderMethod = "DecodeVLDST2Instruction";
1861 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1862 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1864 "vst2", Dt, "$Vd, $Rn, $Rm",
1865 "$Rn.addr = $wb", []> {
1866 let Inst{5-4} = Rn{5-4};
1867 let DecoderMethod = "DecodeVLDST2Instruction";
1871 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair,
1872 addrmode6align64or128>;
1873 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair,
1874 addrmode6align64or128>;
1875 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair,
1876 addrmode6align64or128>;
1878 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8", addrmode6align64or128or256>;
1879 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16", addrmode6align64or128or256>;
1880 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32", addrmode6align64or128or256>;
1882 def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1883 def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1884 def VST2q32PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1885 def VST2q8PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1886 def VST2q16PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1887 def VST2q32PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1889 // ...with double-spaced registers
1890 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2,
1891 addrmode6align64or128>;
1892 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2,
1893 addrmode6align64or128>;
1894 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2,
1895 addrmode6align64or128>;
1896 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced,
1897 addrmode6align64or128>;
1898 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced,
1899 addrmode6align64or128>;
1900 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced,
1901 addrmode6align64or128>;
1903 // VST3 : Vector Store (multiple 3-element structures)
1904 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1905 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1906 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1907 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1909 let Inst{4} = Rn{4};
1910 let DecoderMethod = "DecodeVLDST3Instruction";
1913 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1914 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1915 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1917 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1918 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1919 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1921 // ...with address register writeback:
1922 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1923 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1924 (ins addrmode6:$Rn, am6offset:$Rm,
1925 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1926 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1927 "$Rn.addr = $wb", []> {
1928 let Inst{4} = Rn{4};
1929 let DecoderMethod = "DecodeVLDST3Instruction";
1932 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1933 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1934 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1936 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1937 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1938 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1940 // ...with double-spaced registers:
1941 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1942 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1943 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1944 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1945 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1946 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1948 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1949 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1950 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1952 // ...alternate versions to be allocated odd register numbers:
1953 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1954 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1955 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1957 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1958 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1959 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1961 // VST4 : Vector Store (multiple 4-element structures)
1962 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1963 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1964 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1965 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1968 let Inst{5-4} = Rn{5-4};
1969 let DecoderMethod = "DecodeVLDST4Instruction";
1972 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1973 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1974 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1976 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1977 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1978 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1980 // ...with address register writeback:
1981 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1982 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1983 (ins addrmode6:$Rn, am6offset:$Rm,
1984 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1985 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1986 "$Rn.addr = $wb", []> {
1987 let Inst{5-4} = Rn{5-4};
1988 let DecoderMethod = "DecodeVLDST4Instruction";
1991 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1992 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1993 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1995 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1996 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1997 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1999 // ...with double-spaced registers:
2000 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
2001 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
2002 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
2003 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
2004 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
2005 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
2007 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2008 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2009 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2011 // ...alternate versions to be allocated odd register numbers:
2012 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
2013 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
2014 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
2016 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2017 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2018 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
2020 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2022 // Classes for VST*LN pseudo-instructions with multi-register operands.
2023 // These are expanded to real instructions after register allocation.
2024 class VSTQLNPseudo<InstrItinClass itin>
2025 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
2027 class VSTQLNWBPseudo<InstrItinClass itin>
2028 : PseudoNLdSt<(outs GPR:$wb),
2029 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
2030 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2031 class VSTQQLNPseudo<InstrItinClass itin>
2032 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
2034 class VSTQQLNWBPseudo<InstrItinClass itin>
2035 : PseudoNLdSt<(outs GPR:$wb),
2036 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
2037 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2038 class VSTQQQQLNPseudo<InstrItinClass itin>
2039 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
2041 class VSTQQQQLNWBPseudo<InstrItinClass itin>
2042 : PseudoNLdSt<(outs GPR:$wb),
2043 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
2044 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2046 // VST1LN : Vector Store (single element from one lane)
2047 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
2048 PatFrag StoreOp, SDNode ExtractOp, Operand AddrMode>
2049 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2050 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
2051 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
2052 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> {
2054 let DecoderMethod = "DecodeVST1LN";
2056 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
2057 : VSTQLNPseudo<IIC_VST1ln> {
2058 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2062 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
2063 NEONvgetlaneu, addrmode6> {
2064 let Inst{7-5} = lane{2-0};
2066 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
2067 NEONvgetlaneu, addrmode6> {
2068 let Inst{7-6} = lane{1-0};
2069 let Inst{4} = Rn{4};
2072 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt,
2074 let Inst{7} = lane{0};
2075 let Inst{5-4} = Rn{5-4};
2078 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
2079 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
2080 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
2082 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
2083 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
2084 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
2085 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
2087 // ...with address register writeback:
2088 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
2089 PatFrag StoreOp, SDNode ExtractOp, Operand AdrMode>
2090 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2091 (ins AdrMode:$Rn, am6offset:$Rm,
2092 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
2093 "\\{$Vd[$lane]\\}, $Rn$Rm",
2095 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
2096 AdrMode:$Rn, am6offset:$Rm))]> {
2097 let DecoderMethod = "DecodeVST1LN";
2099 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
2100 : VSTQLNWBPseudo<IIC_VST1lnu> {
2101 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2102 addrmode6:$addr, am6offset:$offset))];
2105 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
2106 NEONvgetlaneu, addrmode6> {
2107 let Inst{7-5} = lane{2-0};
2109 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
2110 NEONvgetlaneu, addrmode6> {
2111 let Inst{7-6} = lane{1-0};
2112 let Inst{4} = Rn{4};
2114 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
2115 extractelt, addrmode6oneL32> {
2116 let Inst{7} = lane{0};
2117 let Inst{5-4} = Rn{5-4};
2120 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
2121 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
2122 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
2124 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2126 // VST2LN : Vector Store (single 2-element structure from one lane)
2127 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2128 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2129 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2130 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2133 let Inst{4} = Rn{4};
2134 let DecoderMethod = "DecodeVST2LN";
2137 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
2138 let Inst{7-5} = lane{2-0};
2140 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
2141 let Inst{7-6} = lane{1-0};
2143 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
2144 let Inst{7} = lane{0};
2147 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2148 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2149 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2151 // ...with double-spaced registers:
2152 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
2153 let Inst{7-6} = lane{1-0};
2154 let Inst{4} = Rn{4};
2156 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
2157 let Inst{7} = lane{0};
2158 let Inst{4} = Rn{4};
2161 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2162 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2164 // ...with address register writeback:
2165 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2166 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2167 (ins addrmode6:$Rn, am6offset:$Rm,
2168 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2169 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2170 "$Rn.addr = $wb", []> {
2171 let Inst{4} = Rn{4};
2172 let DecoderMethod = "DecodeVST2LN";
2175 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
2176 let Inst{7-5} = lane{2-0};
2178 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
2179 let Inst{7-6} = lane{1-0};
2181 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
2182 let Inst{7} = lane{0};
2185 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2186 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2187 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2189 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
2190 let Inst{7-6} = lane{1-0};
2192 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
2193 let Inst{7} = lane{0};
2196 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2197 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2199 // VST3LN : Vector Store (single 3-element structure from one lane)
2200 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2201 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2202 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2203 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
2204 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2206 let DecoderMethod = "DecodeVST3LN";
2209 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
2210 let Inst{7-5} = lane{2-0};
2212 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
2213 let Inst{7-6} = lane{1-0};
2215 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
2216 let Inst{7} = lane{0};
2219 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2220 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2221 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2223 // ...with double-spaced registers:
2224 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
2225 let Inst{7-6} = lane{1-0};
2227 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
2228 let Inst{7} = lane{0};
2231 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2232 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2234 // ...with address register writeback:
2235 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2236 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2237 (ins addrmode6:$Rn, am6offset:$Rm,
2238 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2239 IIC_VST3lnu, "vst3", Dt,
2240 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2241 "$Rn.addr = $wb", []> {
2242 let DecoderMethod = "DecodeVST3LN";
2245 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
2246 let Inst{7-5} = lane{2-0};
2248 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
2249 let Inst{7-6} = lane{1-0};
2251 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
2252 let Inst{7} = lane{0};
2255 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2256 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2257 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2259 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
2260 let Inst{7-6} = lane{1-0};
2262 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
2263 let Inst{7} = lane{0};
2266 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2267 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2269 // VST4LN : Vector Store (single 4-element structure from one lane)
2270 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2271 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2272 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2273 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2274 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2277 let Inst{4} = Rn{4};
2278 let DecoderMethod = "DecodeVST4LN";
2281 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
2282 let Inst{7-5} = lane{2-0};
2284 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
2285 let Inst{7-6} = lane{1-0};
2287 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2288 let Inst{7} = lane{0};
2289 let Inst{5} = Rn{5};
2292 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2293 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2294 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2296 // ...with double-spaced registers:
2297 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
2298 let Inst{7-6} = lane{1-0};
2300 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2301 let Inst{7} = lane{0};
2302 let Inst{5} = Rn{5};
2305 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2306 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2308 // ...with address register writeback:
2309 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2310 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2311 (ins addrmode6:$Rn, am6offset:$Rm,
2312 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2313 IIC_VST4lnu, "vst4", Dt,
2314 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2315 "$Rn.addr = $wb", []> {
2316 let Inst{4} = Rn{4};
2317 let DecoderMethod = "DecodeVST4LN";
2320 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
2321 let Inst{7-5} = lane{2-0};
2323 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
2324 let Inst{7-6} = lane{1-0};
2326 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2327 let Inst{7} = lane{0};
2328 let Inst{5} = Rn{5};
2331 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2332 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2333 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2335 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
2336 let Inst{7-6} = lane{1-0};
2338 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
2339 let Inst{7} = lane{0};
2340 let Inst{5} = Rn{5};
2343 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2344 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2346 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2348 // Use vld1/vst1 for unaligned f64 load / store
2349 def : Pat<(f64 (hword_alignedload addrmode6:$addr)),
2350 (VLD1d16 addrmode6:$addr)>, Requires<[IsLE]>;
2351 def : Pat<(hword_alignedstore (f64 DPR:$value), addrmode6:$addr),
2352 (VST1d16 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2353 def : Pat<(f64 (byte_alignedload addrmode6:$addr)),
2354 (VLD1d8 addrmode6:$addr)>, Requires<[IsLE]>;
2355 def : Pat<(byte_alignedstore (f64 DPR:$value), addrmode6:$addr),
2356 (VST1d8 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2357 def : Pat<(f64 (non_word_alignedload addrmode6:$addr)),
2358 (VLD1d64 addrmode6:$addr)>, Requires<[IsBE]>;
2359 def : Pat<(non_word_alignedstore (f64 DPR:$value), addrmode6:$addr),
2360 (VST1d64 addrmode6:$addr, DPR:$value)>, Requires<[IsBE]>;
2362 // Use vld1/vst1 for Q and QQ. Also use them for unaligned v2f64
2363 // load / store if it's legal.
2364 def : Pat<(v2f64 (dword_alignedload addrmode6:$addr)),
2365 (VLD1q64 addrmode6:$addr)>;
2366 def : Pat<(dword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2367 (VST1q64 addrmode6:$addr, QPR:$value)>;
2368 def : Pat<(v2f64 (word_alignedload addrmode6:$addr)),
2369 (VLD1q32 addrmode6:$addr)>;
2370 def : Pat<(word_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2371 (VST1q32 addrmode6:$addr, QPR:$value)>;
2372 def : Pat<(v2f64 (hword_alignedload addrmode6:$addr)),
2373 (VLD1q16 addrmode6:$addr)>, Requires<[IsLE]>;
2374 def : Pat<(hword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2375 (VST1q16 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2376 def : Pat<(v2f64 (byte_alignedload addrmode6:$addr)),
2377 (VLD1q8 addrmode6:$addr)>, Requires<[IsLE]>;
2378 def : Pat<(byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2379 (VST1q8 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2381 //===----------------------------------------------------------------------===//
2382 // NEON pattern fragments
2383 //===----------------------------------------------------------------------===//
2385 // Extract D sub-registers of Q registers.
2386 def DSubReg_i8_reg : SDNodeXForm<imm, [{
2387 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2388 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
2390 def DSubReg_i16_reg : SDNodeXForm<imm, [{
2391 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2392 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
2394 def DSubReg_i32_reg : SDNodeXForm<imm, [{
2395 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2396 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
2398 def DSubReg_f64_reg : SDNodeXForm<imm, [{
2399 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2400 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
2403 // Extract S sub-registers of Q/D registers.
2404 def SSubReg_f32_reg : SDNodeXForm<imm, [{
2405 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
2406 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
2409 // Translate lane numbers from Q registers to D subregs.
2410 def SubReg_i8_lane : SDNodeXForm<imm, [{
2411 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
2413 def SubReg_i16_lane : SDNodeXForm<imm, [{
2414 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
2416 def SubReg_i32_lane : SDNodeXForm<imm, [{
2417 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
2420 //===----------------------------------------------------------------------===//
2421 // Instruction Classes
2422 //===----------------------------------------------------------------------===//
2424 // Basic 2-register operations: double- and quad-register.
2425 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2426 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2427 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2428 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2429 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2430 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2431 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2432 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2433 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2434 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2435 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2436 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2438 // Basic 2-register intrinsics, both double- and quad-register.
2439 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2440 bits<2> op17_16, bits<5> op11_7, bit op4,
2441 InstrItinClass itin, string OpcodeStr, string Dt,
2442 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2443 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2444 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2445 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2446 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2447 bits<2> op17_16, bits<5> op11_7, bit op4,
2448 InstrItinClass itin, string OpcodeStr, string Dt,
2449 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2450 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2451 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2452 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2454 // Same as above, but not predicated.
2455 class N2VDIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
2456 InstrItinClass itin, string OpcodeStr, string Dt,
2457 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2458 : N2Vnp<0b10, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
2459 itin, OpcodeStr, Dt, ResTy, OpTy,
2460 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2462 class N2VQIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
2463 InstrItinClass itin, string OpcodeStr, string Dt,
2464 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2465 : N2Vnp<0b10, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
2466 itin, OpcodeStr, Dt, ResTy, OpTy,
2467 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2469 // Similar to NV2VQIntnp with some more encoding bits exposed (crypto).
2470 class N2VQIntXnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
2471 bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
2472 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2473 : N2Vnp<op19_18, op17_16, op10_8, op7, op6, (outs QPR:$Vd), (ins QPR:$Vm),
2474 itin, OpcodeStr, Dt, ResTy, OpTy,
2475 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2477 // Same as N2VQIntXnp but with Vd as a src register.
2478 class N2VQIntX2np<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
2479 bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
2480 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2481 : N2Vnp<op19_18, op17_16, op10_8, op7, op6,
2482 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vm),
2483 itin, OpcodeStr, Dt, ResTy, OpTy,
2484 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vm))))]> {
2485 let Constraints = "$src = $Vd";
2488 // Narrow 2-register operations.
2489 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2490 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2491 InstrItinClass itin, string OpcodeStr, string Dt,
2492 ValueType TyD, ValueType TyQ, SDNode OpNode>
2493 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2494 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2495 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2497 // Narrow 2-register intrinsics.
2498 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2499 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2500 InstrItinClass itin, string OpcodeStr, string Dt,
2501 ValueType TyD, ValueType TyQ, SDPatternOperator IntOp>
2502 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2503 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2504 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2506 // Long 2-register operations (currently only used for VMOVL).
2507 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2508 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2509 InstrItinClass itin, string OpcodeStr, string Dt,
2510 ValueType TyQ, ValueType TyD, SDNode OpNode>
2511 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2512 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2513 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2515 // Long 2-register intrinsics.
2516 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2517 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2518 InstrItinClass itin, string OpcodeStr, string Dt,
2519 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
2520 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2521 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2522 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2524 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2525 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
2526 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2527 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2528 OpcodeStr, Dt, "$Vd, $Vm",
2529 "$src1 = $Vd, $src2 = $Vm", []>;
2530 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
2531 InstrItinClass itin, string OpcodeStr, string Dt>
2532 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2533 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2534 "$src1 = $Vd, $src2 = $Vm", []>;
2536 // Basic 3-register operations: double- and quad-register.
2537 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2538 InstrItinClass itin, string OpcodeStr, string Dt,
2539 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2540 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2541 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2542 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2543 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2544 // All of these have a two-operand InstAlias.
2545 let TwoOperandAliasConstraint = "$Vn = $Vd";
2546 let isCommutable = Commutable;
2548 // Same as N3VD but no data type.
2549 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2550 InstrItinClass itin, string OpcodeStr,
2551 ValueType ResTy, ValueType OpTy,
2552 SDNode OpNode, bit Commutable>
2553 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
2554 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2555 OpcodeStr, "$Vd, $Vn, $Vm", "",
2556 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2557 // All of these have a two-operand InstAlias.
2558 let TwoOperandAliasConstraint = "$Vn = $Vd";
2559 let isCommutable = Commutable;
2562 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2563 InstrItinClass itin, string OpcodeStr, string Dt,
2564 ValueType Ty, SDNode ShOp>
2565 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2566 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2567 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2569 (Ty (ShOp (Ty DPR:$Vn),
2570 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2571 // All of these have a two-operand InstAlias.
2572 let TwoOperandAliasConstraint = "$Vn = $Vd";
2573 let isCommutable = 0;
2575 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2576 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2577 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2578 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2579 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2581 (Ty (ShOp (Ty DPR:$Vn),
2582 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2583 // All of these have a two-operand InstAlias.
2584 let TwoOperandAliasConstraint = "$Vn = $Vd";
2585 let isCommutable = 0;
2588 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2589 InstrItinClass itin, string OpcodeStr, string Dt,
2590 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2591 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2592 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2593 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2594 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2595 // All of these have a two-operand InstAlias.
2596 let TwoOperandAliasConstraint = "$Vn = $Vd";
2597 let isCommutable = Commutable;
2599 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2600 InstrItinClass itin, string OpcodeStr,
2601 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2602 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2603 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2604 OpcodeStr, "$Vd, $Vn, $Vm", "",
2605 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2606 // All of these have a two-operand InstAlias.
2607 let TwoOperandAliasConstraint = "$Vn = $Vd";
2608 let isCommutable = Commutable;
2610 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2611 InstrItinClass itin, string OpcodeStr, string Dt,
2612 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2613 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2614 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2615 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2616 [(set (ResTy QPR:$Vd),
2617 (ResTy (ShOp (ResTy QPR:$Vn),
2618 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2620 // All of these have a two-operand InstAlias.
2621 let TwoOperandAliasConstraint = "$Vn = $Vd";
2622 let isCommutable = 0;
2624 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2625 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2626 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2627 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2628 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2629 [(set (ResTy QPR:$Vd),
2630 (ResTy (ShOp (ResTy QPR:$Vn),
2631 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2633 // All of these have a two-operand InstAlias.
2634 let TwoOperandAliasConstraint = "$Vn = $Vd";
2635 let isCommutable = 0;
2638 // Basic 3-register intrinsics, both double- and quad-register.
2639 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2640 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2641 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2642 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2643 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2644 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2645 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2646 // All of these have a two-operand InstAlias.
2647 let TwoOperandAliasConstraint = "$Vn = $Vd";
2648 let isCommutable = Commutable;
2651 class N3VDIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2652 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2653 string Dt, ValueType ResTy, ValueType OpTy,
2654 SDPatternOperator IntOp, bit Commutable>
2655 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2656 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
2657 ResTy, OpTy, IntOp, Commutable,
2658 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2660 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2661 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
2662 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2663 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2664 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2666 (Ty (IntOp (Ty DPR:$Vn),
2667 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2669 let isCommutable = 0;
2672 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2673 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
2674 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2675 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2676 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2678 (Ty (IntOp (Ty DPR:$Vn),
2679 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2680 let isCommutable = 0;
2682 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2683 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2684 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2685 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2686 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2687 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2688 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2689 let TwoOperandAliasConstraint = "$Vm = $Vd";
2690 let isCommutable = 0;
2693 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2694 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2695 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2696 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2697 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2698 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2699 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2700 // All of these have a two-operand InstAlias.
2701 let TwoOperandAliasConstraint = "$Vn = $Vd";
2702 let isCommutable = Commutable;
2705 class N3VQIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2706 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2707 string Dt, ValueType ResTy, ValueType OpTy,
2708 SDPatternOperator IntOp, bit Commutable>
2709 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2710 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
2711 ResTy, OpTy, IntOp, Commutable,
2712 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2714 // Same as N3VQIntnp but with Vd as a src register.
2715 class N3VQInt3np<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2716 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2717 string Dt, ValueType ResTy, ValueType OpTy,
2718 SDPatternOperator IntOp, bit Commutable>
2719 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2720 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr,
2721 Dt, ResTy, OpTy, IntOp, Commutable,
2722 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
2723 (OpTy QPR:$Vm))))]> {
2724 let Constraints = "$src = $Vd";
2727 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2728 string OpcodeStr, string Dt,
2729 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2730 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2731 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2732 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2733 [(set (ResTy QPR:$Vd),
2734 (ResTy (IntOp (ResTy QPR:$Vn),
2735 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2737 let isCommutable = 0;
2739 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2740 string OpcodeStr, string Dt,
2741 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2742 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2743 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2744 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2745 [(set (ResTy QPR:$Vd),
2746 (ResTy (IntOp (ResTy QPR:$Vn),
2747 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2749 let isCommutable = 0;
2751 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2752 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2753 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2754 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2755 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2756 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2757 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2758 let TwoOperandAliasConstraint = "$Vm = $Vd";
2759 let isCommutable = 0;
2762 // Multiply-Add/Sub operations: double- and quad-register.
2763 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2764 InstrItinClass itin, string OpcodeStr, string Dt,
2765 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2766 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2767 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2768 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2769 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2770 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2772 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2773 string OpcodeStr, string Dt,
2774 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2775 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2777 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2779 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2781 (Ty (ShOp (Ty DPR:$src1),
2783 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2785 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2786 string OpcodeStr, string Dt,
2787 ValueType Ty, SDNode MulOp, SDNode ShOp>
2788 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2790 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2792 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2794 (Ty (ShOp (Ty DPR:$src1),
2796 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2799 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2800 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2801 SDPatternOperator MulOp, SDPatternOperator OpNode>
2802 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2803 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2804 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2805 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2806 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2807 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2808 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2809 SDPatternOperator MulOp, SDPatternOperator ShOp>
2810 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2812 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2814 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2815 [(set (ResTy QPR:$Vd),
2816 (ResTy (ShOp (ResTy QPR:$src1),
2817 (ResTy (MulOp QPR:$Vn,
2818 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2820 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2821 string OpcodeStr, string Dt,
2822 ValueType ResTy, ValueType OpTy,
2823 SDNode MulOp, SDNode ShOp>
2824 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2826 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2828 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2829 [(set (ResTy QPR:$Vd),
2830 (ResTy (ShOp (ResTy QPR:$src1),
2831 (ResTy (MulOp QPR:$Vn,
2832 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2835 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2836 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2837 InstrItinClass itin, string OpcodeStr, string Dt,
2838 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
2839 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2840 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2841 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2842 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2843 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2844 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2845 InstrItinClass itin, string OpcodeStr, string Dt,
2846 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
2847 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2848 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2849 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2850 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2851 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2853 // Neon 3-argument intrinsics, both double- and quad-register.
2854 // The destination register is also used as the first source operand register.
2855 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2856 InstrItinClass itin, string OpcodeStr, string Dt,
2857 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2858 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2859 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2860 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2861 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2862 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2863 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2864 InstrItinClass itin, string OpcodeStr, string Dt,
2865 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2866 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2867 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2868 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2869 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2870 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2872 // Long Multiply-Add/Sub operations.
2873 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2874 InstrItinClass itin, string OpcodeStr, string Dt,
2875 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2876 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2877 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2878 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2879 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2880 (TyQ (MulOp (TyD DPR:$Vn),
2881 (TyD DPR:$Vm)))))]>;
2882 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2883 InstrItinClass itin, string OpcodeStr, string Dt,
2884 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2885 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2886 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2888 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2890 (OpNode (TyQ QPR:$src1),
2891 (TyQ (MulOp (TyD DPR:$Vn),
2892 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2894 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2895 InstrItinClass itin, string OpcodeStr, string Dt,
2896 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2897 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2898 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2900 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2902 (OpNode (TyQ QPR:$src1),
2903 (TyQ (MulOp (TyD DPR:$Vn),
2904 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2907 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2908 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2909 InstrItinClass itin, string OpcodeStr, string Dt,
2910 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
2912 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2913 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2914 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2915 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2916 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2917 (TyD DPR:$Vm)))))))]>;
2919 // Neon Long 3-argument intrinsic. The destination register is
2920 // a quad-register and is also used as the first source operand register.
2921 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2922 InstrItinClass itin, string OpcodeStr, string Dt,
2923 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
2924 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2925 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2926 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2928 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2929 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2930 string OpcodeStr, string Dt,
2931 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2932 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2934 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2936 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2937 [(set (ResTy QPR:$Vd),
2938 (ResTy (IntOp (ResTy QPR:$src1),
2940 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2942 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2943 InstrItinClass itin, string OpcodeStr, string Dt,
2944 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2945 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2947 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2949 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2950 [(set (ResTy QPR:$Vd),
2951 (ResTy (IntOp (ResTy QPR:$src1),
2953 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2956 // Narrowing 3-register intrinsics.
2957 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2958 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2959 SDPatternOperator IntOp, bit Commutable>
2960 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2961 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2962 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2963 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2964 let isCommutable = Commutable;
2967 // Long 3-register operations.
2968 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2969 InstrItinClass itin, string OpcodeStr, string Dt,
2970 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2971 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2972 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2973 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2974 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2975 let isCommutable = Commutable;
2978 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2979 InstrItinClass itin, string OpcodeStr, string Dt,
2980 ValueType TyQ, ValueType TyD, SDNode OpNode>
2981 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2982 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2983 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2985 (TyQ (OpNode (TyD DPR:$Vn),
2986 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2987 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2988 InstrItinClass itin, string OpcodeStr, string Dt,
2989 ValueType TyQ, ValueType TyD, SDNode OpNode>
2990 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2991 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2992 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2994 (TyQ (OpNode (TyD DPR:$Vn),
2995 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2997 // Long 3-register operations with explicitly extended operands.
2998 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2999 InstrItinClass itin, string OpcodeStr, string Dt,
3000 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
3002 : N3V<op24, op23, op21_20, op11_8, 0, op4,
3003 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3004 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3005 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3006 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3007 let isCommutable = Commutable;
3010 // Long 3-register intrinsics with explicit extend (VABDL).
3011 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
3012 InstrItinClass itin, string OpcodeStr, string Dt,
3013 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
3015 : N3V<op24, op23, op21_20, op11_8, 0, op4,
3016 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3017 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3018 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3019 (TyD DPR:$Vm))))))]> {
3020 let isCommutable = Commutable;
3023 // Long 3-register intrinsics.
3024 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
3025 InstrItinClass itin, string OpcodeStr, string Dt,
3026 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, bit Commutable>
3027 : N3V<op24, op23, op21_20, op11_8, 0, op4,
3028 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3029 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3030 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
3031 let isCommutable = Commutable;
3034 // Same as above, but not predicated.
3035 class N3VLIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
3036 bit op4, InstrItinClass itin, string OpcodeStr,
3037 string Dt, ValueType ResTy, ValueType OpTy,
3038 SDPatternOperator IntOp, bit Commutable>
3039 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
3040 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
3041 ResTy, OpTy, IntOp, Commutable,
3042 [(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
3044 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
3045 string OpcodeStr, string Dt,
3046 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3047 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
3048 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3049 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3050 [(set (ResTy QPR:$Vd),
3051 (ResTy (IntOp (OpTy DPR:$Vn),
3052 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
3054 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
3055 InstrItinClass itin, string OpcodeStr, string Dt,
3056 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3057 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
3058 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3059 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3060 [(set (ResTy QPR:$Vd),
3061 (ResTy (IntOp (OpTy DPR:$Vn),
3062 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
3065 // Wide 3-register operations.
3066 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
3067 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
3068 SDNode OpNode, SDNode ExtOp, bit Commutable>
3069 : N3V<op24, op23, op21_20, op11_8, 0, op4,
3070 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
3071 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3072 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
3073 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3074 // All of these have a two-operand InstAlias.
3075 let TwoOperandAliasConstraint = "$Vn = $Vd";
3076 let isCommutable = Commutable;
3079 // Pairwise long 2-register intrinsics, both double- and quad-register.
3080 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3081 bits<2> op17_16, bits<5> op11_7, bit op4,
3082 string OpcodeStr, string Dt,
3083 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3084 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
3085 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3086 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
3087 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3088 bits<2> op17_16, bits<5> op11_7, bit op4,
3089 string OpcodeStr, string Dt,
3090 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3091 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
3092 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3093 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
3095 // Pairwise long 2-register accumulate intrinsics,
3096 // both double- and quad-register.
3097 // The destination register is also used as the first source operand register.
3098 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3099 bits<2> op17_16, bits<5> op11_7, bit op4,
3100 string OpcodeStr, string Dt,
3101 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3102 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
3103 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
3104 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3105 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
3106 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3107 bits<2> op17_16, bits<5> op11_7, bit op4,
3108 string OpcodeStr, string Dt,
3109 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3110 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
3111 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
3112 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3113 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
3115 // Shift by immediate,
3116 // both double- and quad-register.
3117 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3118 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3119 Format f, InstrItinClass itin, Operand ImmTy,
3120 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
3121 : N2VImm<op24, op23, op11_8, op7, 0, op4,
3122 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
3123 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3124 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
3125 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3126 Format f, InstrItinClass itin, Operand ImmTy,
3127 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
3128 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3129 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3130 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3131 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
3134 // Long shift by immediate.
3135 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
3136 string OpcodeStr, string Dt,
3137 ValueType ResTy, ValueType OpTy, Operand ImmTy,
3138 SDPatternOperator OpNode>
3139 : N2VImm<op24, op23, op11_8, op7, op6, op4,
3140 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3141 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3142 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), ImmTy:$SIMM)))]>;
3144 // Narrow shift by immediate.
3145 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
3146 InstrItinClass itin, string OpcodeStr, string Dt,
3147 ValueType ResTy, ValueType OpTy, Operand ImmTy,
3148 SDPatternOperator OpNode>
3149 : N2VImm<op24, op23, op11_8, op7, op6, op4,
3150 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3151 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3152 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
3153 (i32 ImmTy:$SIMM))))]>;
3155 // Shift right by immediate and accumulate,
3156 // both double- and quad-register.
3157 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3158 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3159 Operand ImmTy, string OpcodeStr, string Dt,
3160 ValueType Ty, SDNode ShOp>
3161 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3162 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3163 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3164 [(set DPR:$Vd, (Ty (add DPR:$src1,
3165 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
3166 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3167 Operand ImmTy, string OpcodeStr, string Dt,
3168 ValueType Ty, SDNode ShOp>
3169 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3170 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3171 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3172 [(set QPR:$Vd, (Ty (add QPR:$src1,
3173 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
3176 // Shift by immediate and insert,
3177 // both double- and quad-register.
3178 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3179 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3180 Operand ImmTy, Format f, string OpcodeStr, string Dt,
3181 ValueType Ty,SDNode ShOp>
3182 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3183 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
3184 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3185 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
3186 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3187 Operand ImmTy, Format f, string OpcodeStr, string Dt,
3188 ValueType Ty,SDNode ShOp>
3189 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3190 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
3191 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3192 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
3195 // Convert, with fractional bits immediate,
3196 // both double- and quad-register.
3197 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3198 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
3199 SDPatternOperator IntOp>
3200 : N2VImm<op24, op23, op11_8, op7, 0, op4,
3201 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3202 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3203 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
3204 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3205 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
3206 SDPatternOperator IntOp>
3207 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3208 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3209 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3210 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
3212 //===----------------------------------------------------------------------===//
3214 //===----------------------------------------------------------------------===//
3216 // Abbreviations used in multiclass suffixes:
3217 // Q = quarter int (8 bit) elements
3218 // H = half int (16 bit) elements
3219 // S = single int (32 bit) elements
3220 // D = double int (64 bit) elements
3222 // Neon 2-register vector operations and intrinsics.
3224 // Neon 2-register comparisons.
3225 // source operand element sizes of 8, 16 and 32 bits:
3226 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3227 bits<5> op11_7, bit op4, string opc, string Dt,
3228 string asm, SDNode OpNode> {
3229 // 64-bit vector types.
3230 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
3231 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3232 opc, !strconcat(Dt, "8"), asm, "",
3233 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
3234 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3235 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3236 opc, !strconcat(Dt, "16"), asm, "",
3237 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
3238 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3239 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3240 opc, !strconcat(Dt, "32"), asm, "",
3241 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
3242 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3243 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3244 opc, "f32", asm, "",
3245 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
3246 let Inst{10} = 1; // overwrite F = 1
3249 // 128-bit vector types.
3250 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
3251 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3252 opc, !strconcat(Dt, "8"), asm, "",
3253 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
3254 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3255 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3256 opc, !strconcat(Dt, "16"), asm, "",
3257 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
3258 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3259 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3260 opc, !strconcat(Dt, "32"), asm, "",
3261 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
3262 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3263 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3264 opc, "f32", asm, "",
3265 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
3266 let Inst{10} = 1; // overwrite F = 1
3271 // Neon 2-register vector intrinsics,
3272 // element sizes of 8, 16 and 32 bits:
3273 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3274 bits<5> op11_7, bit op4,
3275 InstrItinClass itinD, InstrItinClass itinQ,
3276 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3277 // 64-bit vector types.
3278 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3279 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3280 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3281 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
3282 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3283 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
3285 // 128-bit vector types.
3286 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3287 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
3288 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3289 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
3290 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3291 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
3295 // Neon Narrowing 2-register vector operations,
3296 // source operand element sizes of 16, 32 and 64 bits:
3297 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3298 bits<5> op11_7, bit op6, bit op4,
3299 InstrItinClass itin, string OpcodeStr, string Dt,
3301 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3302 itin, OpcodeStr, !strconcat(Dt, "16"),
3303 v8i8, v8i16, OpNode>;
3304 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3305 itin, OpcodeStr, !strconcat(Dt, "32"),
3306 v4i16, v4i32, OpNode>;
3307 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3308 itin, OpcodeStr, !strconcat(Dt, "64"),
3309 v2i32, v2i64, OpNode>;
3312 // Neon Narrowing 2-register vector intrinsics,
3313 // source operand element sizes of 16, 32 and 64 bits:
3314 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3315 bits<5> op11_7, bit op6, bit op4,
3316 InstrItinClass itin, string OpcodeStr, string Dt,
3317 SDPatternOperator IntOp> {
3318 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3319 itin, OpcodeStr, !strconcat(Dt, "16"),
3320 v8i8, v8i16, IntOp>;
3321 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3322 itin, OpcodeStr, !strconcat(Dt, "32"),
3323 v4i16, v4i32, IntOp>;
3324 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3325 itin, OpcodeStr, !strconcat(Dt, "64"),
3326 v2i32, v2i64, IntOp>;
3330 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
3331 // source operand element sizes of 16, 32 and 64 bits:
3332 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
3333 string OpcodeStr, string Dt, SDNode OpNode> {
3334 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3335 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
3336 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3337 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3338 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3339 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3343 // Neon 3-register vector operations.
3345 // First with only element sizes of 8, 16 and 32 bits:
3346 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3347 InstrItinClass itinD16, InstrItinClass itinD32,
3348 InstrItinClass itinQ16, InstrItinClass itinQ32,
3349 string OpcodeStr, string Dt,
3350 SDNode OpNode, bit Commutable = 0> {
3351 // 64-bit vector types.
3352 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
3353 OpcodeStr, !strconcat(Dt, "8"),
3354 v8i8, v8i8, OpNode, Commutable>;
3355 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
3356 OpcodeStr, !strconcat(Dt, "16"),
3357 v4i16, v4i16, OpNode, Commutable>;
3358 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
3359 OpcodeStr, !strconcat(Dt, "32"),
3360 v2i32, v2i32, OpNode, Commutable>;
3362 // 128-bit vector types.
3363 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
3364 OpcodeStr, !strconcat(Dt, "8"),
3365 v16i8, v16i8, OpNode, Commutable>;
3366 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3367 OpcodeStr, !strconcat(Dt, "16"),
3368 v8i16, v8i16, OpNode, Commutable>;
3369 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
3370 OpcodeStr, !strconcat(Dt, "32"),
3371 v4i32, v4i32, OpNode, Commutable>;
3374 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
3375 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
3376 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>;
3377 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3378 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
3379 v4i32, v2i32, ShOp>;
3382 // ....then also with element size 64 bits:
3383 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3384 InstrItinClass itinD, InstrItinClass itinQ,
3385 string OpcodeStr, string Dt,
3386 SDNode OpNode, bit Commutable = 0>
3387 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
3388 OpcodeStr, Dt, OpNode, Commutable> {
3389 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
3390 OpcodeStr, !strconcat(Dt, "64"),
3391 v1i64, v1i64, OpNode, Commutable>;
3392 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
3393 OpcodeStr, !strconcat(Dt, "64"),
3394 v2i64, v2i64, OpNode, Commutable>;
3398 // Neon 3-register vector intrinsics.
3400 // First with only element sizes of 16 and 32 bits:
3401 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3402 InstrItinClass itinD16, InstrItinClass itinD32,
3403 InstrItinClass itinQ16, InstrItinClass itinQ32,
3404 string OpcodeStr, string Dt,
3405 SDPatternOperator IntOp, bit Commutable = 0> {
3406 // 64-bit vector types.
3407 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
3408 OpcodeStr, !strconcat(Dt, "16"),
3409 v4i16, v4i16, IntOp, Commutable>;
3410 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
3411 OpcodeStr, !strconcat(Dt, "32"),
3412 v2i32, v2i32, IntOp, Commutable>;
3414 // 128-bit vector types.
3415 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3416 OpcodeStr, !strconcat(Dt, "16"),
3417 v8i16, v8i16, IntOp, Commutable>;
3418 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3419 OpcodeStr, !strconcat(Dt, "32"),
3420 v4i32, v4i32, IntOp, Commutable>;
3422 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3423 InstrItinClass itinD16, InstrItinClass itinD32,
3424 InstrItinClass itinQ16, InstrItinClass itinQ32,
3425 string OpcodeStr, string Dt,
3426 SDPatternOperator IntOp> {
3427 // 64-bit vector types.
3428 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3429 OpcodeStr, !strconcat(Dt, "16"),
3430 v4i16, v4i16, IntOp>;
3431 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
3432 OpcodeStr, !strconcat(Dt, "32"),
3433 v2i32, v2i32, IntOp>;
3435 // 128-bit vector types.
3436 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3437 OpcodeStr, !strconcat(Dt, "16"),
3438 v8i16, v8i16, IntOp>;
3439 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3440 OpcodeStr, !strconcat(Dt, "32"),
3441 v4i32, v4i32, IntOp>;
3444 multiclass N3VIntSL_HS<bits<4> op11_8,
3445 InstrItinClass itinD16, InstrItinClass itinD32,
3446 InstrItinClass itinQ16, InstrItinClass itinQ32,
3447 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3448 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
3449 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
3450 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
3451 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
3452 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3453 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3454 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
3455 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
3458 // ....then also with element size of 8 bits:
3459 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3460 InstrItinClass itinD16, InstrItinClass itinD32,
3461 InstrItinClass itinQ16, InstrItinClass itinQ32,
3462 string OpcodeStr, string Dt,
3463 SDPatternOperator IntOp, bit Commutable = 0>
3464 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3465 OpcodeStr, Dt, IntOp, Commutable> {
3466 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
3467 OpcodeStr, !strconcat(Dt, "8"),
3468 v8i8, v8i8, IntOp, Commutable>;
3469 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3470 OpcodeStr, !strconcat(Dt, "8"),
3471 v16i8, v16i8, IntOp, Commutable>;
3473 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3474 InstrItinClass itinD16, InstrItinClass itinD32,
3475 InstrItinClass itinQ16, InstrItinClass itinQ32,
3476 string OpcodeStr, string Dt,
3477 SDPatternOperator IntOp>
3478 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3479 OpcodeStr, Dt, IntOp> {
3480 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
3481 OpcodeStr, !strconcat(Dt, "8"),
3483 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3484 OpcodeStr, !strconcat(Dt, "8"),
3485 v16i8, v16i8, IntOp>;
3489 // ....then also with element size of 64 bits:
3490 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3491 InstrItinClass itinD16, InstrItinClass itinD32,
3492 InstrItinClass itinQ16, InstrItinClass itinQ32,
3493 string OpcodeStr, string Dt,
3494 SDPatternOperator IntOp, bit Commutable = 0>
3495 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3496 OpcodeStr, Dt, IntOp, Commutable> {
3497 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3498 OpcodeStr, !strconcat(Dt, "64"),
3499 v1i64, v1i64, IntOp, Commutable>;
3500 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3501 OpcodeStr, !strconcat(Dt, "64"),
3502 v2i64, v2i64, IntOp, Commutable>;
3504 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3505 InstrItinClass itinD16, InstrItinClass itinD32,
3506 InstrItinClass itinQ16, InstrItinClass itinQ32,
3507 string OpcodeStr, string Dt,
3508 SDPatternOperator IntOp>
3509 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3510 OpcodeStr, Dt, IntOp> {
3511 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3512 OpcodeStr, !strconcat(Dt, "64"),
3513 v1i64, v1i64, IntOp>;
3514 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3515 OpcodeStr, !strconcat(Dt, "64"),
3516 v2i64, v2i64, IntOp>;
3519 // Neon Narrowing 3-register vector intrinsics,
3520 // source operand element sizes of 16, 32 and 64 bits:
3521 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3522 string OpcodeStr, string Dt,
3523 SDPatternOperator IntOp, bit Commutable = 0> {
3524 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
3525 OpcodeStr, !strconcat(Dt, "16"),
3526 v8i8, v8i16, IntOp, Commutable>;
3527 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3528 OpcodeStr, !strconcat(Dt, "32"),
3529 v4i16, v4i32, IntOp, Commutable>;
3530 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
3531 OpcodeStr, !strconcat(Dt, "64"),
3532 v2i32, v2i64, IntOp, Commutable>;
3536 // Neon Long 3-register vector operations.
3538 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3539 InstrItinClass itin16, InstrItinClass itin32,
3540 string OpcodeStr, string Dt,
3541 SDNode OpNode, bit Commutable = 0> {
3542 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3543 OpcodeStr, !strconcat(Dt, "8"),
3544 v8i16, v8i8, OpNode, Commutable>;
3545 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3546 OpcodeStr, !strconcat(Dt, "16"),
3547 v4i32, v4i16, OpNode, Commutable>;
3548 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
3549 OpcodeStr, !strconcat(Dt, "32"),
3550 v2i64, v2i32, OpNode, Commutable>;
3553 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
3554 InstrItinClass itin, string OpcodeStr, string Dt,
3556 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3557 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3558 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
3559 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3562 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3563 InstrItinClass itin16, InstrItinClass itin32,
3564 string OpcodeStr, string Dt,
3565 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3566 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3567 OpcodeStr, !strconcat(Dt, "8"),
3568 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3569 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3570 OpcodeStr, !strconcat(Dt, "16"),
3571 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3572 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3573 OpcodeStr, !strconcat(Dt, "32"),
3574 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3577 // Neon Long 3-register vector intrinsics.
3579 // First with only element sizes of 16 and 32 bits:
3580 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3581 InstrItinClass itin16, InstrItinClass itin32,
3582 string OpcodeStr, string Dt,
3583 SDPatternOperator IntOp, bit Commutable = 0> {
3584 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3585 OpcodeStr, !strconcat(Dt, "16"),
3586 v4i32, v4i16, IntOp, Commutable>;
3587 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
3588 OpcodeStr, !strconcat(Dt, "32"),
3589 v2i64, v2i32, IntOp, Commutable>;
3592 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
3593 InstrItinClass itin, string OpcodeStr, string Dt,
3594 SDPatternOperator IntOp> {
3595 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3596 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3597 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3598 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3601 // ....then also with element size of 8 bits:
3602 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3603 InstrItinClass itin16, InstrItinClass itin32,
3604 string OpcodeStr, string Dt,
3605 SDPatternOperator IntOp, bit Commutable = 0>
3606 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
3607 IntOp, Commutable> {
3608 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3609 OpcodeStr, !strconcat(Dt, "8"),
3610 v8i16, v8i8, IntOp, Commutable>;
3613 // ....with explicit extend (VABDL).
3614 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3615 InstrItinClass itin, string OpcodeStr, string Dt,
3616 SDPatternOperator IntOp, SDNode ExtOp, bit Commutable = 0> {
3617 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3618 OpcodeStr, !strconcat(Dt, "8"),
3619 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3620 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3621 OpcodeStr, !strconcat(Dt, "16"),
3622 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3623 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3624 OpcodeStr, !strconcat(Dt, "32"),
3625 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3629 // Neon Wide 3-register vector intrinsics,
3630 // source operand element sizes of 8, 16 and 32 bits:
3631 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3632 string OpcodeStr, string Dt,
3633 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3634 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3635 OpcodeStr, !strconcat(Dt, "8"),
3636 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3637 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3638 OpcodeStr, !strconcat(Dt, "16"),
3639 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3640 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3641 OpcodeStr, !strconcat(Dt, "32"),
3642 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3646 // Neon Multiply-Op vector operations,
3647 // element sizes of 8, 16 and 32 bits:
3648 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3649 InstrItinClass itinD16, InstrItinClass itinD32,
3650 InstrItinClass itinQ16, InstrItinClass itinQ32,
3651 string OpcodeStr, string Dt, SDNode OpNode> {
3652 // 64-bit vector types.
3653 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3654 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3655 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3656 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3657 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3658 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3660 // 128-bit vector types.
3661 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3662 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3663 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3664 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3665 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3666 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3669 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3670 InstrItinClass itinD16, InstrItinClass itinD32,
3671 InstrItinClass itinQ16, InstrItinClass itinQ32,
3672 string OpcodeStr, string Dt, SDNode ShOp> {
3673 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3674 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3675 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3676 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3677 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3678 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3680 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3681 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3685 // Neon Intrinsic-Op vector operations,
3686 // element sizes of 8, 16 and 32 bits:
3687 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3688 InstrItinClass itinD, InstrItinClass itinQ,
3689 string OpcodeStr, string Dt, SDPatternOperator IntOp,
3691 // 64-bit vector types.
3692 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3693 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3694 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3695 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3696 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3697 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3699 // 128-bit vector types.
3700 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3701 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3702 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3703 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3704 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3705 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3708 // Neon 3-argument intrinsics,
3709 // element sizes of 8, 16 and 32 bits:
3710 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3711 InstrItinClass itinD, InstrItinClass itinQ,
3712 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3713 // 64-bit vector types.
3714 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3715 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3716 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3717 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3718 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3719 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3721 // 128-bit vector types.
3722 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3723 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3724 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3725 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3726 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3727 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3731 // Neon Long Multiply-Op vector operations,
3732 // element sizes of 8, 16 and 32 bits:
3733 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3734 InstrItinClass itin16, InstrItinClass itin32,
3735 string OpcodeStr, string Dt, SDNode MulOp,
3737 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3738 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3739 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3740 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3741 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3742 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3745 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3746 string Dt, SDNode MulOp, SDNode OpNode> {
3747 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3748 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3749 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3750 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3754 // Neon Long 3-argument intrinsics.
3756 // First with only element sizes of 16 and 32 bits:
3757 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3758 InstrItinClass itin16, InstrItinClass itin32,
3759 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3760 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3761 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3762 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3763 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3766 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3767 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3768 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3769 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3770 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3771 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3774 // ....then also with element size of 8 bits:
3775 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3776 InstrItinClass itin16, InstrItinClass itin32,
3777 string OpcodeStr, string Dt, SDPatternOperator IntOp>
3778 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3779 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3780 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3783 // ....with explicit extend (VABAL).
3784 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3785 InstrItinClass itin, string OpcodeStr, string Dt,
3786 SDPatternOperator IntOp, SDNode ExtOp, SDNode OpNode> {
3787 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3788 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3789 IntOp, ExtOp, OpNode>;
3790 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3791 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3792 IntOp, ExtOp, OpNode>;
3793 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3794 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3795 IntOp, ExtOp, OpNode>;
3799 // Neon Pairwise long 2-register intrinsics,
3800 // element sizes of 8, 16 and 32 bits:
3801 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3802 bits<5> op11_7, bit op4,
3803 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3804 // 64-bit vector types.
3805 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3806 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3807 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3808 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3809 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3810 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3812 // 128-bit vector types.
3813 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3814 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3815 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3816 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3817 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3818 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3822 // Neon Pairwise long 2-register accumulate intrinsics,
3823 // element sizes of 8, 16 and 32 bits:
3824 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3825 bits<5> op11_7, bit op4,
3826 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3827 // 64-bit vector types.
3828 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3829 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3830 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3831 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3832 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3833 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3835 // 128-bit vector types.
3836 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3837 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3838 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3839 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3840 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3841 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3845 // Neon 2-register vector shift by immediate,
3846 // with f of either N2RegVShLFrm or N2RegVShRFrm
3847 // element sizes of 8, 16, 32 and 64 bits:
3848 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3849 InstrItinClass itin, string OpcodeStr, string Dt,
3851 // 64-bit vector types.
3852 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3853 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3854 let Inst{21-19} = 0b001; // imm6 = 001xxx
3856 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3857 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3858 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3860 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3861 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3862 let Inst{21} = 0b1; // imm6 = 1xxxxx
3864 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3865 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3868 // 128-bit vector types.
3869 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3870 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3871 let Inst{21-19} = 0b001; // imm6 = 001xxx
3873 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3874 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3875 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3877 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3878 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3879 let Inst{21} = 0b1; // imm6 = 1xxxxx
3881 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3882 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3885 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3886 InstrItinClass itin, string OpcodeStr, string Dt,
3887 string baseOpc, SDNode OpNode> {
3888 // 64-bit vector types.
3889 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3890 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3891 let Inst{21-19} = 0b001; // imm6 = 001xxx
3893 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3894 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3895 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3897 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3898 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3899 let Inst{21} = 0b1; // imm6 = 1xxxxx
3901 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3902 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3905 // 128-bit vector types.
3906 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3907 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3908 let Inst{21-19} = 0b001; // imm6 = 001xxx
3910 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3911 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3912 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3914 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3915 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3916 let Inst{21} = 0b1; // imm6 = 1xxxxx
3918 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3919 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3923 // Neon Shift-Accumulate vector operations,
3924 // element sizes of 8, 16, 32 and 64 bits:
3925 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3926 string OpcodeStr, string Dt, SDNode ShOp> {
3927 // 64-bit vector types.
3928 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3929 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3930 let Inst{21-19} = 0b001; // imm6 = 001xxx
3932 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3933 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3934 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3936 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3937 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3938 let Inst{21} = 0b1; // imm6 = 1xxxxx
3940 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3941 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3944 // 128-bit vector types.
3945 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3946 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3947 let Inst{21-19} = 0b001; // imm6 = 001xxx
3949 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3950 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3951 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3953 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3954 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3955 let Inst{21} = 0b1; // imm6 = 1xxxxx
3957 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3958 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3962 // Neon Shift-Insert vector operations,
3963 // with f of either N2RegVShLFrm or N2RegVShRFrm
3964 // element sizes of 8, 16, 32 and 64 bits:
3965 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3967 // 64-bit vector types.
3968 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3969 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3970 let Inst{21-19} = 0b001; // imm6 = 001xxx
3972 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3973 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3974 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3976 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3977 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3978 let Inst{21} = 0b1; // imm6 = 1xxxxx
3980 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3981 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3984 // 128-bit vector types.
3985 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3986 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3987 let Inst{21-19} = 0b001; // imm6 = 001xxx
3989 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3990 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3991 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3993 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3994 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3995 let Inst{21} = 0b1; // imm6 = 1xxxxx
3997 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3998 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
4001 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
4003 // 64-bit vector types.
4004 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
4005 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
4006 let Inst{21-19} = 0b001; // imm6 = 001xxx
4008 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
4009 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
4010 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4012 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
4013 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
4014 let Inst{21} = 0b1; // imm6 = 1xxxxx
4016 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
4017 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
4020 // 128-bit vector types.
4021 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
4022 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
4023 let Inst{21-19} = 0b001; // imm6 = 001xxx
4025 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
4026 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
4027 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4029 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
4030 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
4031 let Inst{21} = 0b1; // imm6 = 1xxxxx
4033 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
4034 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
4038 // Neon Shift Long operations,
4039 // element sizes of 8, 16, 32 bits:
4040 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
4041 bit op4, string OpcodeStr, string Dt,
4042 SDPatternOperator OpNode> {
4043 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
4044 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
4045 let Inst{21-19} = 0b001; // imm6 = 001xxx
4047 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
4048 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
4049 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4051 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
4052 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> {
4053 let Inst{21} = 0b1; // imm6 = 1xxxxx
4057 // Neon Shift Narrow operations,
4058 // element sizes of 16, 32, 64 bits:
4059 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
4060 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
4061 SDPatternOperator OpNode> {
4062 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
4063 OpcodeStr, !strconcat(Dt, "16"),
4064 v8i8, v8i16, shr_imm8, OpNode> {
4065 let Inst{21-19} = 0b001; // imm6 = 001xxx
4067 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
4068 OpcodeStr, !strconcat(Dt, "32"),
4069 v4i16, v4i32, shr_imm16, OpNode> {
4070 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4072 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
4073 OpcodeStr, !strconcat(Dt, "64"),
4074 v2i32, v2i64, shr_imm32, OpNode> {
4075 let Inst{21} = 0b1; // imm6 = 1xxxxx
4079 //===----------------------------------------------------------------------===//
4080 // Instruction Definitions.
4081 //===----------------------------------------------------------------------===//
4083 // Vector Add Operations.
4085 // VADD : Vector Add (integer and floating-point)
4086 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
4088 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
4089 v2f32, v2f32, fadd, 1>;
4090 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
4091 v4f32, v4f32, fadd, 1>;
4092 // VADDL : Vector Add Long (Q = D + D)
4093 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
4094 "vaddl", "s", add, sext, 1>;
4095 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
4096 "vaddl", "u", add, zext, 1>;
4097 // VADDW : Vector Add Wide (Q = Q + D)
4098 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
4099 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
4100 // VHADD : Vector Halving Add
4101 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
4102 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4103 "vhadd", "s", int_arm_neon_vhadds, 1>;
4104 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
4105 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4106 "vhadd", "u", int_arm_neon_vhaddu, 1>;
4107 // VRHADD : Vector Rounding Halving Add
4108 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
4109 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4110 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
4111 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
4112 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4113 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
4114 // VQADD : Vector Saturating Add
4115 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
4116 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4117 "vqadd", "s", int_arm_neon_vqadds, 1>;
4118 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
4119 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4120 "vqadd", "u", int_arm_neon_vqaddu, 1>;
4121 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
4122 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i", null_frag, 1>;
4123 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
4124 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
4125 int_arm_neon_vraddhn, 1>;
4127 def : Pat<(v8i8 (trunc (NEONvshru (add (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4128 (VADDHNv8i8 QPR:$Vn, QPR:$Vm)>;
4129 def : Pat<(v4i16 (trunc (NEONvshru (add (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4130 (VADDHNv4i16 QPR:$Vn, QPR:$Vm)>;
4131 def : Pat<(v2i32 (trunc (NEONvshru (add (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4132 (VADDHNv2i32 QPR:$Vn, QPR:$Vm)>;
4134 // Vector Multiply Operations.
4136 // VMUL : Vector Multiply (integer, polynomial and floating-point)
4137 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
4138 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
4139 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
4140 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
4141 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
4142 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
4143 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
4144 v2f32, v2f32, fmul, 1>;
4145 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
4146 v4f32, v4f32, fmul, 1>;
4147 defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>;
4148 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
4149 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
4152 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
4153 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
4154 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
4155 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4156 (DSubReg_i16_reg imm:$lane))),
4157 (SubReg_i16_lane imm:$lane)))>;
4158 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
4159 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
4160 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
4161 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4162 (DSubReg_i32_reg imm:$lane))),
4163 (SubReg_i32_lane imm:$lane)))>;
4164 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
4165 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
4166 (v4f32 (VMULslfq (v4f32 QPR:$src1),
4167 (v2f32 (EXTRACT_SUBREG QPR:$src2,
4168 (DSubReg_i32_reg imm:$lane))),
4169 (SubReg_i32_lane imm:$lane)))>;
4172 def : Pat<(v2f32 (fmul DPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4174 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4176 def : Pat<(v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4178 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4182 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
4183 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
4184 IIC_VMULi16Q, IIC_VMULi32Q,
4185 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
4186 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
4187 IIC_VMULi16Q, IIC_VMULi32Q,
4188 "vqdmulh", "s", int_arm_neon_vqdmulh>;
4189 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
4190 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4192 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
4193 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4194 (DSubReg_i16_reg imm:$lane))),
4195 (SubReg_i16_lane imm:$lane)))>;
4196 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
4197 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4199 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
4200 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4201 (DSubReg_i32_reg imm:$lane))),
4202 (SubReg_i32_lane imm:$lane)))>;
4204 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
4205 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
4206 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
4207 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
4208 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
4209 IIC_VMULi16Q, IIC_VMULi32Q,
4210 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
4211 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
4212 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4214 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
4215 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4216 (DSubReg_i16_reg imm:$lane))),
4217 (SubReg_i16_lane imm:$lane)))>;
4218 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
4219 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4221 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
4222 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4223 (DSubReg_i32_reg imm:$lane))),
4224 (SubReg_i32_lane imm:$lane)))>;
4226 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
4227 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
4228 DecoderNamespace = "NEONData" in {
4229 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4230 "vmull", "s", NEONvmulls, 1>;
4231 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4232 "vmull", "u", NEONvmullu, 1>;
4233 def VMULLp8 : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
4234 v8i16, v8i8, int_arm_neon_vmullp, 1>;
4235 def VMULLp64 : N3VLIntnp<0b00101, 0b10, 0b1110, 0, 0, NoItinerary,
4236 "vmull", "p64", v2i64, v1i64, int_arm_neon_vmullp, 1>,
4237 Requires<[HasV8, HasCrypto]>;
4239 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
4240 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
4242 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
4243 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
4244 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
4245 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
4246 "vqdmull", "s", int_arm_neon_vqdmull>;
4248 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
4250 // VMLA : Vector Multiply Accumulate (integer and floating-point)
4251 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4252 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4253 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
4254 v2f32, fmul_su, fadd_mlx>,
4255 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4256 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
4257 v4f32, fmul_su, fadd_mlx>,
4258 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4259 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
4260 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4261 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
4262 v2f32, fmul_su, fadd_mlx>,
4263 Requires<[HasNEON, UseFPVMLx]>;
4264 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
4265 v4f32, v2f32, fmul_su, fadd_mlx>,
4266 Requires<[HasNEON, UseFPVMLx]>;
4268 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
4269 (mul (v8i16 QPR:$src2),
4270 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4271 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4272 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4273 (DSubReg_i16_reg imm:$lane))),
4274 (SubReg_i16_lane imm:$lane)))>;
4276 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
4277 (mul (v4i32 QPR:$src2),
4278 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4279 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4280 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4281 (DSubReg_i32_reg imm:$lane))),
4282 (SubReg_i32_lane imm:$lane)))>;
4284 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
4285 (fmul_su (v4f32 QPR:$src2),
4286 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4287 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
4289 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4290 (DSubReg_i32_reg imm:$lane))),
4291 (SubReg_i32_lane imm:$lane)))>,
4292 Requires<[HasNEON, UseFPVMLx]>;
4294 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
4295 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4296 "vmlal", "s", NEONvmulls, add>;
4297 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4298 "vmlal", "u", NEONvmullu, add>;
4300 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
4301 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
4303 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
4304 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4305 "vqdmlal", "s", null_frag>;
4306 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", null_frag>;
4308 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4309 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4310 (v4i16 DPR:$Vm))))),
4311 (VQDMLALv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4312 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4313 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4314 (v2i32 DPR:$Vm))))),
4315 (VQDMLALv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4316 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4317 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4318 (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm),
4320 (VQDMLALslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4321 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4322 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4323 (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm),
4325 (VQDMLALslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4327 // VMLS : Vector Multiply Subtract (integer and floating-point)
4328 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4329 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4330 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
4331 v2f32, fmul_su, fsub_mlx>,
4332 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4333 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
4334 v4f32, fmul_su, fsub_mlx>,
4335 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4336 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
4337 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4338 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
4339 v2f32, fmul_su, fsub_mlx>,
4340 Requires<[HasNEON, UseFPVMLx]>;
4341 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
4342 v4f32, v2f32, fmul_su, fsub_mlx>,
4343 Requires<[HasNEON, UseFPVMLx]>;
4345 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
4346 (mul (v8i16 QPR:$src2),
4347 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4348 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4349 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4350 (DSubReg_i16_reg imm:$lane))),
4351 (SubReg_i16_lane imm:$lane)))>;
4353 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
4354 (mul (v4i32 QPR:$src2),
4355 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4356 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4357 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4358 (DSubReg_i32_reg imm:$lane))),
4359 (SubReg_i32_lane imm:$lane)))>;
4361 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
4362 (fmul_su (v4f32 QPR:$src2),
4363 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4364 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
4365 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4366 (DSubReg_i32_reg imm:$lane))),
4367 (SubReg_i32_lane imm:$lane)))>,
4368 Requires<[HasNEON, UseFPVMLx]>;
4370 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
4371 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4372 "vmlsl", "s", NEONvmulls, sub>;
4373 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4374 "vmlsl", "u", NEONvmullu, sub>;
4376 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
4377 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
4379 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
4380 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
4381 "vqdmlsl", "s", null_frag>;
4382 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", null_frag>;
4384 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4385 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4386 (v4i16 DPR:$Vm))))),
4387 (VQDMLSLv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4388 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4389 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4390 (v2i32 DPR:$Vm))))),
4391 (VQDMLSLv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4392 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4393 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4394 (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm),
4396 (VQDMLSLslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4397 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4398 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4399 (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm),
4401 (VQDMLSLslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4403 // Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations.
4404 def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32",
4405 v2f32, fmul_su, fadd_mlx>,
4406 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4408 def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32",
4409 v4f32, fmul_su, fadd_mlx>,
4410 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4412 // Fused Vector Multiply Subtract (floating-point)
4413 def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32",
4414 v2f32, fmul_su, fsub_mlx>,
4415 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4416 def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
4417 v4f32, fmul_su, fsub_mlx>,
4418 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4420 // Match @llvm.fma.* intrinsics
4421 def : Pat<(v2f32 (fma DPR:$Vn, DPR:$Vm, DPR:$src1)),
4422 (VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4423 Requires<[HasVFP4]>;
4424 def : Pat<(v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)),
4425 (VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4426 Requires<[HasVFP4]>;
4427 def : Pat<(v2f32 (fma (fneg DPR:$Vn), DPR:$Vm, DPR:$src1)),
4428 (VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4429 Requires<[HasVFP4]>;
4430 def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)),
4431 (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4432 Requires<[HasVFP4]>;
4434 // Vector Subtract Operations.
4436 // VSUB : Vector Subtract (integer and floating-point)
4437 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
4438 "vsub", "i", sub, 0>;
4439 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
4440 v2f32, v2f32, fsub, 0>;
4441 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
4442 v4f32, v4f32, fsub, 0>;
4443 // VSUBL : Vector Subtract Long (Q = D - D)
4444 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4445 "vsubl", "s", sub, sext, 0>;
4446 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4447 "vsubl", "u", sub, zext, 0>;
4448 // VSUBW : Vector Subtract Wide (Q = Q - D)
4449 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
4450 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
4451 // VHSUB : Vector Halving Subtract
4452 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
4453 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4454 "vhsub", "s", int_arm_neon_vhsubs, 0>;
4455 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
4456 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4457 "vhsub", "u", int_arm_neon_vhsubu, 0>;
4458 // VQSUB : Vector Saturing Subtract
4459 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
4460 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4461 "vqsub", "s", int_arm_neon_vqsubs, 0>;
4462 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
4463 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4464 "vqsub", "u", int_arm_neon_vqsubu, 0>;
4465 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
4466 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i", null_frag, 0>;
4467 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
4468 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
4469 int_arm_neon_vrsubhn, 0>;
4471 def : Pat<(v8i8 (trunc (NEONvshru (sub (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4472 (VSUBHNv8i8 QPR:$Vn, QPR:$Vm)>;
4473 def : Pat<(v4i16 (trunc (NEONvshru (sub (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4474 (VSUBHNv4i16 QPR:$Vn, QPR:$Vm)>;
4475 def : Pat<(v2i32 (trunc (NEONvshru (sub (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4476 (VSUBHNv2i32 QPR:$Vn, QPR:$Vm)>;
4478 // Vector Comparisons.
4480 // VCEQ : Vector Compare Equal
4481 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4482 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
4483 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
4485 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
4488 let TwoOperandAliasConstraint = "$Vm = $Vd" in
4489 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
4490 "$Vd, $Vm, #0", NEONvceqz>;
4492 // VCGE : Vector Compare Greater Than or Equal
4493 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4494 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
4495 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4496 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
4497 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
4499 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
4502 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
4503 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
4504 "$Vd, $Vm, #0", NEONvcgez>;
4505 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
4506 "$Vd, $Vm, #0", NEONvclez>;
4509 // VCGT : Vector Compare Greater Than
4510 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4511 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
4512 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4513 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
4514 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
4516 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
4519 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
4520 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
4521 "$Vd, $Vm, #0", NEONvcgtz>;
4522 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
4523 "$Vd, $Vm, #0", NEONvcltz>;
4526 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
4527 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
4528 "f32", v2i32, v2f32, int_arm_neon_vacge, 0>;
4529 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
4530 "f32", v4i32, v4f32, int_arm_neon_vacge, 0>;
4531 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
4532 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
4533 "f32", v2i32, v2f32, int_arm_neon_vacgt, 0>;
4534 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
4535 "f32", v4i32, v4f32, int_arm_neon_vacgt, 0>;
4536 // VTST : Vector Test Bits
4537 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
4538 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
4540 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
4541 (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4542 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
4543 (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4544 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
4545 (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4546 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
4547 (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4549 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
4550 (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4551 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
4552 (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4553 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
4554 (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4555 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
4556 (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4558 // Vector Bitwise Operations.
4560 def vnotd : PatFrag<(ops node:$in),
4561 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
4562 def vnotq : PatFrag<(ops node:$in),
4563 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
4566 // VAND : Vector Bitwise AND
4567 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
4568 v2i32, v2i32, and, 1>;
4569 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
4570 v4i32, v4i32, and, 1>;
4572 // VEOR : Vector Bitwise Exclusive OR
4573 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
4574 v2i32, v2i32, xor, 1>;
4575 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
4576 v4i32, v4i32, xor, 1>;
4578 // VORR : Vector Bitwise OR
4579 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
4580 v2i32, v2i32, or, 1>;
4581 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
4582 v4i32, v4i32, or, 1>;
4584 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
4585 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4587 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4589 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4590 let Inst{9} = SIMM{9};
4593 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
4594 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4596 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4598 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4599 let Inst{10-9} = SIMM{10-9};
4602 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
4603 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4605 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4607 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4608 let Inst{9} = SIMM{9};
4611 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
4612 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4614 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4616 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4617 let Inst{10-9} = SIMM{10-9};
4621 // VBIC : Vector Bitwise Bit Clear (AND NOT)
4622 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
4623 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4624 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4625 "vbic", "$Vd, $Vn, $Vm", "",
4626 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4627 (vnotd DPR:$Vm))))]>;
4628 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4629 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4630 "vbic", "$Vd, $Vn, $Vm", "",
4631 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4632 (vnotq QPR:$Vm))))]>;
4635 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
4636 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4638 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4640 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4641 let Inst{9} = SIMM{9};
4644 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
4645 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4647 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4649 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4650 let Inst{10-9} = SIMM{10-9};
4653 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
4654 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4656 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4658 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4659 let Inst{9} = SIMM{9};
4662 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
4663 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4665 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4667 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4668 let Inst{10-9} = SIMM{10-9};
4671 // VORN : Vector Bitwise OR NOT
4672 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4673 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4674 "vorn", "$Vd, $Vn, $Vm", "",
4675 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4676 (vnotd DPR:$Vm))))]>;
4677 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4678 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4679 "vorn", "$Vd, $Vn, $Vm", "",
4680 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4681 (vnotq QPR:$Vm))))]>;
4683 // VMVN : Vector Bitwise NOT (Immediate)
4685 let isReMaterializable = 1 in {
4687 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4688 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4689 "vmvn", "i16", "$Vd, $SIMM", "",
4690 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4691 let Inst{9} = SIMM{9};
4694 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4695 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4696 "vmvn", "i16", "$Vd, $SIMM", "",
4697 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4698 let Inst{9} = SIMM{9};
4701 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4702 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4703 "vmvn", "i32", "$Vd, $SIMM", "",
4704 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4705 let Inst{11-8} = SIMM{11-8};
4708 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4709 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4710 "vmvn", "i32", "$Vd, $SIMM", "",
4711 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4712 let Inst{11-8} = SIMM{11-8};
4716 // VMVN : Vector Bitwise NOT
4717 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
4718 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4719 "vmvn", "$Vd, $Vm", "",
4720 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
4721 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
4722 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4723 "vmvn", "$Vd, $Vm", "",
4724 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4725 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4726 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4728 // VBSL : Vector Bitwise Select
4729 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4730 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4731 N3RegFrm, IIC_VCNTiD,
4732 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4734 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
4735 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 DPR:$src1),
4736 (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))),
4737 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4738 Requires<[HasNEON]>;
4739 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 DPR:$src1),
4740 (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))),
4741 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4742 Requires<[HasNEON]>;
4743 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 DPR:$src1),
4744 (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))),
4745 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4746 Requires<[HasNEON]>;
4747 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 DPR:$src1),
4748 (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))),
4749 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4750 Requires<[HasNEON]>;
4751 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 DPR:$src1),
4752 (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))),
4753 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4754 Requires<[HasNEON]>;
4756 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4757 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4758 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
4759 Requires<[HasNEON]>;
4761 def : Pat<(v1i64 (or (and DPR:$Vn, DPR:$Vd),
4762 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4763 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
4764 Requires<[HasNEON]>;
4766 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4767 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4768 N3RegFrm, IIC_VCNTiQ,
4769 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4771 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4773 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 QPR:$src1),
4774 (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))),
4775 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4776 Requires<[HasNEON]>;
4777 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 QPR:$src1),
4778 (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))),
4779 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4780 Requires<[HasNEON]>;
4781 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 QPR:$src1),
4782 (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))),
4783 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4784 Requires<[HasNEON]>;
4785 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 QPR:$src1),
4786 (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))),
4787 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4788 Requires<[HasNEON]>;
4789 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 QPR:$src1),
4790 (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))),
4791 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4792 Requires<[HasNEON]>;
4794 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4795 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4796 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
4797 Requires<[HasNEON]>;
4798 def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
4799 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4800 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
4801 Requires<[HasNEON]>;
4803 // VBIF : Vector Bitwise Insert if False
4804 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4805 // FIXME: This instruction's encoding MAY NOT BE correct.
4806 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4807 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4808 N3RegFrm, IIC_VBINiD,
4809 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4811 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4812 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4813 N3RegFrm, IIC_VBINiQ,
4814 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4817 // VBIT : Vector Bitwise Insert if True
4818 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4819 // FIXME: This instruction's encoding MAY NOT BE correct.
4820 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4821 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4822 N3RegFrm, IIC_VBINiD,
4823 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4825 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4826 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4827 N3RegFrm, IIC_VBINiQ,
4828 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4831 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4832 // for equivalent operations with different register constraints; it just
4835 // Vector Absolute Differences.
4837 // VABD : Vector Absolute Difference
4838 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
4839 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4840 "vabd", "s", int_arm_neon_vabds, 1>;
4841 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
4842 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4843 "vabd", "u", int_arm_neon_vabdu, 1>;
4844 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
4845 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
4846 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
4847 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
4849 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
4850 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4851 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4852 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4853 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
4855 // VABA : Vector Absolute Difference and Accumulate
4856 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4857 "vaba", "s", int_arm_neon_vabds, add>;
4858 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4859 "vaba", "u", int_arm_neon_vabdu, add>;
4861 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
4862 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4863 "vabal", "s", int_arm_neon_vabds, zext, add>;
4864 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4865 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4867 // Vector Maximum and Minimum.
4869 // VMAX : Vector Maximum
4870 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4871 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4872 "vmax", "s", int_arm_neon_vmaxs, 1>;
4873 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4874 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4875 "vmax", "u", int_arm_neon_vmaxu, 1>;
4876 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4878 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4879 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4881 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4884 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
4885 def VMAXNMND : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1,
4886 N3RegFrm, NoItinerary, "vmaxnm", "f32",
4887 v2f32, v2f32, int_arm_neon_vmaxnm, 1>,
4888 Requires<[HasV8, HasNEON]>;
4889 def VMAXNMNQ : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1,
4890 N3RegFrm, NoItinerary, "vmaxnm", "f32",
4891 v4f32, v4f32, int_arm_neon_vmaxnm, 1>,
4892 Requires<[HasV8, HasNEON]>;
4895 // VMIN : Vector Minimum
4896 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4897 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4898 "vmin", "s", int_arm_neon_vmins, 1>;
4899 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4900 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4901 "vmin", "u", int_arm_neon_vminu, 1>;
4902 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4904 v2f32, v2f32, int_arm_neon_vmins, 1>;
4905 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4907 v4f32, v4f32, int_arm_neon_vmins, 1>;
4910 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
4911 def VMINNMND : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1,
4912 N3RegFrm, NoItinerary, "vminnm", "f32",
4913 v2f32, v2f32, int_arm_neon_vminnm, 1>,
4914 Requires<[HasV8, HasNEON]>;
4915 def VMINNMNQ : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1,
4916 N3RegFrm, NoItinerary, "vminnm", "f32",
4917 v4f32, v4f32, int_arm_neon_vminnm, 1>,
4918 Requires<[HasV8, HasNEON]>;
4921 // Vector Pairwise Operations.
4923 // VPADD : Vector Pairwise Add
4924 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4926 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4927 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4929 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4930 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4932 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4933 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4934 IIC_VPBIND, "vpadd", "f32",
4935 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4937 // VPADDL : Vector Pairwise Add Long
4938 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4939 int_arm_neon_vpaddls>;
4940 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4941 int_arm_neon_vpaddlu>;
4943 // VPADAL : Vector Pairwise Add and Accumulate Long
4944 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4945 int_arm_neon_vpadals>;
4946 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4947 int_arm_neon_vpadalu>;
4949 // VPMAX : Vector Pairwise Maximum
4950 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4951 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4952 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4953 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4954 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4955 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4956 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4957 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4958 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4959 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4960 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4961 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4962 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4963 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4965 // VPMIN : Vector Pairwise Minimum
4966 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4967 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4968 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4969 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4970 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4971 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4972 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4973 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4974 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4975 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4976 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4977 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4978 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4979 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4981 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4983 // VRECPE : Vector Reciprocal Estimate
4984 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4985 IIC_VUNAD, "vrecpe", "u32",
4986 v2i32, v2i32, int_arm_neon_vrecpe>;
4987 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4988 IIC_VUNAQ, "vrecpe", "u32",
4989 v4i32, v4i32, int_arm_neon_vrecpe>;
4990 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4991 IIC_VUNAD, "vrecpe", "f32",
4992 v2f32, v2f32, int_arm_neon_vrecpe>;
4993 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4994 IIC_VUNAQ, "vrecpe", "f32",
4995 v4f32, v4f32, int_arm_neon_vrecpe>;
4997 // VRECPS : Vector Reciprocal Step
4998 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4999 IIC_VRECSD, "vrecps", "f32",
5000 v2f32, v2f32, int_arm_neon_vrecps, 1>;
5001 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
5002 IIC_VRECSQ, "vrecps", "f32",
5003 v4f32, v4f32, int_arm_neon_vrecps, 1>;
5005 // VRSQRTE : Vector Reciprocal Square Root Estimate
5006 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
5007 IIC_VUNAD, "vrsqrte", "u32",
5008 v2i32, v2i32, int_arm_neon_vrsqrte>;
5009 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
5010 IIC_VUNAQ, "vrsqrte", "u32",
5011 v4i32, v4i32, int_arm_neon_vrsqrte>;
5012 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
5013 IIC_VUNAD, "vrsqrte", "f32",
5014 v2f32, v2f32, int_arm_neon_vrsqrte>;
5015 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
5016 IIC_VUNAQ, "vrsqrte", "f32",
5017 v4f32, v4f32, int_arm_neon_vrsqrte>;
5019 // VRSQRTS : Vector Reciprocal Square Root Step
5020 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
5021 IIC_VRECSD, "vrsqrts", "f32",
5022 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
5023 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
5024 IIC_VRECSQ, "vrsqrts", "f32",
5025 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
5029 // VSHL : Vector Shift
5030 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
5031 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
5032 "vshl", "s", int_arm_neon_vshifts>;
5033 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
5034 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
5035 "vshl", "u", int_arm_neon_vshiftu>;
5037 // VSHL : Vector Shift Left (Immediate)
5038 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
5040 // VSHR : Vector Shift Right (Immediate)
5041 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", "VSHRs",
5043 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", "VSHRu",
5046 // VSHLL : Vector Shift Left Long
5047 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s",
5048 PatFrag<(ops node:$LHS, node:$RHS), (NEONvshl (sext node:$LHS), node:$RHS)>>;
5049 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u",
5050 PatFrag<(ops node:$LHS, node:$RHS), (NEONvshl (zext node:$LHS), node:$RHS)>>;
5052 // VSHLL : Vector Shift Left Long (with maximum shift count)
5053 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
5054 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
5055 ValueType OpTy, Operand ImmTy>
5056 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
5057 ResTy, OpTy, ImmTy, null_frag> {
5058 let Inst{21-16} = op21_16;
5059 let DecoderMethod = "DecodeVSHLMaxInstruction";
5061 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
5063 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
5064 v4i32, v4i16, imm16>;
5065 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
5066 v2i64, v2i32, imm32>;
5068 def : Pat<(v8i16 (NEONvshl (zext (v8i8 DPR:$Rn)), (i32 8))),
5069 (VSHLLi8 DPR:$Rn, 8)>;
5070 def : Pat<(v4i32 (NEONvshl (zext (v4i16 DPR:$Rn)), (i32 16))),
5071 (VSHLLi16 DPR:$Rn, 16)>;
5072 def : Pat<(v2i64 (NEONvshl (zext (v2i32 DPR:$Rn)), (i32 32))),
5073 (VSHLLi32 DPR:$Rn, 32)>;
5074 def : Pat<(v8i16 (NEONvshl (sext (v8i8 DPR:$Rn)), (i32 8))),
5075 (VSHLLi8 DPR:$Rn, 8)>;
5076 def : Pat<(v4i32 (NEONvshl (sext (v4i16 DPR:$Rn)), (i32 16))),
5077 (VSHLLi16 DPR:$Rn, 16)>;
5078 def : Pat<(v2i64 (NEONvshl (sext (v2i32 DPR:$Rn)), (i32 32))),
5079 (VSHLLi32 DPR:$Rn, 32)>;
5081 // VSHRN : Vector Shift Right and Narrow
5082 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
5083 PatFrag<(ops node:$Rn, node:$amt),
5084 (trunc (NEONvshrs node:$Rn, node:$amt))>>;
5086 def : Pat<(v8i8 (trunc (NEONvshru (v8i16 QPR:$Vn), shr_imm8:$amt))),
5087 (VSHRNv8i8 QPR:$Vn, shr_imm8:$amt)>;
5088 def : Pat<(v4i16 (trunc (NEONvshru (v4i32 QPR:$Vn), shr_imm16:$amt))),
5089 (VSHRNv4i16 QPR:$Vn, shr_imm16:$amt)>;
5090 def : Pat<(v2i32 (trunc (NEONvshru (v2i64 QPR:$Vn), shr_imm32:$amt))),
5091 (VSHRNv2i32 QPR:$Vn, shr_imm32:$amt)>;
5093 // VRSHL : Vector Rounding Shift
5094 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
5095 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5096 "vrshl", "s", int_arm_neon_vrshifts>;
5097 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
5098 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5099 "vrshl", "u", int_arm_neon_vrshiftu>;
5100 // VRSHR : Vector Rounding Shift Right
5101 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", "VRSHRs",
5103 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", "VRSHRu",
5106 // VRSHRN : Vector Rounding Shift Right and Narrow
5107 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
5110 // VQSHL : Vector Saturating Shift
5111 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
5112 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5113 "vqshl", "s", int_arm_neon_vqshifts>;
5114 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
5115 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5116 "vqshl", "u", int_arm_neon_vqshiftu>;
5117 // VQSHL : Vector Saturating Shift Left (Immediate)
5118 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
5119 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
5121 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
5122 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
5124 // VQSHRN : Vector Saturating Shift Right and Narrow
5125 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
5127 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
5130 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
5131 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
5134 // VQRSHL : Vector Saturating Rounding Shift
5135 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
5136 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5137 "vqrshl", "s", int_arm_neon_vqrshifts>;
5138 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
5139 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5140 "vqrshl", "u", int_arm_neon_vqrshiftu>;
5142 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
5143 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
5145 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
5148 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
5149 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
5152 // VSRA : Vector Shift Right and Accumulate
5153 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
5154 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
5155 // VRSRA : Vector Rounding Shift Right and Accumulate
5156 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
5157 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
5159 // VSLI : Vector Shift Left and Insert
5160 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
5162 // VSRI : Vector Shift Right and Insert
5163 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
5165 // Vector Absolute and Saturating Absolute.
5167 // VABS : Vector Absolute Value
5168 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
5169 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
5171 def VABSfd : N2VD<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
5173 v2f32, v2f32, fabs>;
5174 def VABSfq : N2VQ<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
5176 v4f32, v4f32, fabs>;
5178 def : Pat<(xor (v2i32 (bitconvert (v8i8 (NEONvshrs DPR:$src, (i32 7))))),
5179 (v2i32 (bitconvert (v8i8 (add DPR:$src,
5180 (NEONvshrs DPR:$src, (i32 7))))))),
5181 (VABSv8i8 DPR:$src)>;
5182 def : Pat<(xor (v2i32 (bitconvert (v4i16 (NEONvshrs DPR:$src, (i32 15))))),
5183 (v2i32 (bitconvert (v4i16 (add DPR:$src,
5184 (NEONvshrs DPR:$src, (i32 15))))))),
5185 (VABSv4i16 DPR:$src)>;
5186 def : Pat<(xor (v2i32 (NEONvshrs DPR:$src, (i32 31))),
5187 (v2i32 (add DPR:$src, (NEONvshrs DPR:$src, (i32 31))))),
5188 (VABSv2i32 DPR:$src)>;
5189 def : Pat<(xor (v4i32 (bitconvert (v16i8 (NEONvshrs QPR:$src, (i32 7))))),
5190 (v4i32 (bitconvert (v16i8 (add QPR:$src,
5191 (NEONvshrs QPR:$src, (i32 7))))))),
5192 (VABSv16i8 QPR:$src)>;
5193 def : Pat<(xor (v4i32 (bitconvert (v8i16 (NEONvshrs QPR:$src, (i32 15))))),
5194 (v4i32 (bitconvert (v8i16 (add QPR:$src,
5195 (NEONvshrs QPR:$src, (i32 15))))))),
5196 (VABSv8i16 QPR:$src)>;
5197 def : Pat<(xor (v4i32 (NEONvshrs QPR:$src, (i32 31))),
5198 (v4i32 (add QPR:$src, (NEONvshrs QPR:$src, (i32 31))))),
5199 (VABSv4i32 QPR:$src)>;
5201 // VQABS : Vector Saturating Absolute Value
5202 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
5203 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
5204 int_arm_neon_vqabs>;
5208 def vnegd : PatFrag<(ops node:$in),
5209 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
5210 def vnegq : PatFrag<(ops node:$in),
5211 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
5213 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
5214 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
5215 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
5216 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
5217 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
5218 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
5219 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
5220 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
5222 // VNEG : Vector Negate (integer)
5223 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
5224 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
5225 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
5226 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
5227 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
5228 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
5230 // VNEG : Vector Negate (floating-point)
5231 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
5232 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
5233 "vneg", "f32", "$Vd, $Vm", "",
5234 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
5235 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
5236 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
5237 "vneg", "f32", "$Vd, $Vm", "",
5238 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
5240 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
5241 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
5242 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
5243 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
5244 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
5245 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
5247 // VQNEG : Vector Saturating Negate
5248 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
5249 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
5250 int_arm_neon_vqneg>;
5252 // Vector Bit Counting Operations.
5254 // VCLS : Vector Count Leading Sign Bits
5255 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
5256 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
5258 // VCLZ : Vector Count Leading Zeros
5259 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
5260 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
5262 // VCNT : Vector Count One Bits
5263 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
5264 IIC_VCNTiD, "vcnt", "8",
5266 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
5267 IIC_VCNTiQ, "vcnt", "8",
5268 v16i8, v16i8, ctpop>;
5271 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
5272 (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
5273 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5275 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
5276 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
5277 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5280 // Vector Move Operations.
5282 // VMOV : Vector Move (Register)
5283 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
5284 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
5285 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
5286 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
5288 // VMOV : Vector Move (Immediate)
5290 let isReMaterializable = 1 in {
5291 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
5292 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
5293 "vmov", "i8", "$Vd, $SIMM", "",
5294 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
5295 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
5296 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
5297 "vmov", "i8", "$Vd, $SIMM", "",
5298 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
5300 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
5301 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
5302 "vmov", "i16", "$Vd, $SIMM", "",
5303 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
5304 let Inst{9} = SIMM{9};
5307 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
5308 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
5309 "vmov", "i16", "$Vd, $SIMM", "",
5310 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
5311 let Inst{9} = SIMM{9};
5314 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
5315 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
5316 "vmov", "i32", "$Vd, $SIMM", "",
5317 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
5318 let Inst{11-8} = SIMM{11-8};
5321 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
5322 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
5323 "vmov", "i32", "$Vd, $SIMM", "",
5324 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
5325 let Inst{11-8} = SIMM{11-8};
5328 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
5329 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
5330 "vmov", "i64", "$Vd, $SIMM", "",
5331 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
5332 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
5333 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
5334 "vmov", "i64", "$Vd, $SIMM", "",
5335 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
5337 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
5338 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
5339 "vmov", "f32", "$Vd, $SIMM", "",
5340 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
5341 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
5342 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
5343 "vmov", "f32", "$Vd, $SIMM", "",
5344 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
5345 } // isReMaterializable
5347 // Add support for bytes replication feature, so it could be GAS compatible.
5348 // E.g. instructions below:
5349 // "vmov.i32 d0, 0xffffffff"
5350 // "vmov.i32 d0, 0xabababab"
5351 // "vmov.i16 d0, 0xabab"
5352 // are incorrect, but we could deal with such cases.
5353 // For last two instructions, for example, it should emit:
5354 // "vmov.i8 d0, 0xab"
5355 def : NEONInstAlias<"vmov${p}.i16 $Vd, $Vm",
5356 (VMOVv8i8 DPR:$Vd, nImmVMOVI16ByteReplicate:$Vm, pred:$p)>;
5357 def : NEONInstAlias<"vmov${p}.i32 $Vd, $Vm",
5358 (VMOVv8i8 DPR:$Vd, nImmVMOVI32ByteReplicate:$Vm, pred:$p)>;
5359 def : NEONInstAlias<"vmov${p}.i16 $Vd, $Vm",
5360 (VMOVv16i8 QPR:$Vd, nImmVMOVI16ByteReplicate:$Vm, pred:$p)>;
5361 def : NEONInstAlias<"vmov${p}.i32 $Vd, $Vm",
5362 (VMOVv16i8 QPR:$Vd, nImmVMOVI32ByteReplicate:$Vm, pred:$p)>;
5364 // Also add same support for VMVN instructions. So instruction:
5365 // "vmvn.i32 d0, 0xabababab"
5367 // "vmov.i8 d0, 0x54"
5368 def : NEONInstAlias<"vmvn${p}.i16 $Vd, $Vm",
5369 (VMOVv8i8 DPR:$Vd, nImmVMVNI16ByteReplicate:$Vm, pred:$p)>;
5370 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $Vm",
5371 (VMOVv8i8 DPR:$Vd, nImmVMVNI32ByteReplicate:$Vm, pred:$p)>;
5372 def : NEONInstAlias<"vmvn${p}.i16 $Vd, $Vm",
5373 (VMOVv16i8 QPR:$Vd, nImmVMVNI16ByteReplicate:$Vm, pred:$p)>;
5374 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $Vm",
5375 (VMOVv16i8 QPR:$Vd, nImmVMVNI32ByteReplicate:$Vm, pred:$p)>;
5377 // On some CPUs the two instructions "vmov.i32 dD, #0" and "vmov.i32 qD, #0"
5378 // require zero cycles to execute so they should be used wherever possible for
5379 // setting a register to zero.
5381 // Even without these pseudo-insts we would probably end up with the correct
5382 // instruction, but we could not mark the general ones with "isAsCheapAsAMove"
5383 // since they are sometimes rather expensive (in general).
5385 let AddedComplexity = 50, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
5386 def VMOVD0 : ARMPseudoExpand<(outs DPR:$Vd), (ins), 4, IIC_VMOVImm,
5387 [(set DPR:$Vd, (v2i32 NEONimmAllZerosV))],
5388 (VMOVv2i32 DPR:$Vd, 0, (ops 14, zero_reg))>,
5390 def VMOVQ0 : ARMPseudoExpand<(outs QPR:$Vd), (ins), 4, IIC_VMOVImm,
5391 [(set QPR:$Vd, (v4i32 NEONimmAllZerosV))],
5392 (VMOVv4i32 QPR:$Vd, 0, (ops 14, zero_reg))>,
5396 // VMOV : Vector Get Lane (move scalar to ARM core register)
5398 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
5399 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5400 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
5401 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
5403 let Inst{21} = lane{2};
5404 let Inst{6-5} = lane{1-0};
5406 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
5407 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5408 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
5409 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
5411 let Inst{21} = lane{1};
5412 let Inst{6} = lane{0};
5414 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
5415 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5416 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
5417 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
5419 let Inst{21} = lane{2};
5420 let Inst{6-5} = lane{1-0};
5422 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
5423 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5424 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
5425 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
5427 let Inst{21} = lane{1};
5428 let Inst{6} = lane{0};
5430 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
5431 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
5432 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
5433 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
5435 Requires<[HasNEON, HasFastVGETLNi32]> {
5436 let Inst{21} = lane{0};
5438 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
5439 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
5440 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5441 (DSubReg_i8_reg imm:$lane))),
5442 (SubReg_i8_lane imm:$lane))>;
5443 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
5444 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5445 (DSubReg_i16_reg imm:$lane))),
5446 (SubReg_i16_lane imm:$lane))>;
5447 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
5448 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5449 (DSubReg_i8_reg imm:$lane))),
5450 (SubReg_i8_lane imm:$lane))>;
5451 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
5452 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5453 (DSubReg_i16_reg imm:$lane))),
5454 (SubReg_i16_lane imm:$lane))>;
5455 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5456 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
5457 (DSubReg_i32_reg imm:$lane))),
5458 (SubReg_i32_lane imm:$lane))>,
5459 Requires<[HasNEON, HasFastVGETLNi32]>;
5460 def : Pat<(extractelt (v2i32 DPR:$src), imm:$lane),
5462 (i32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5463 Requires<[HasNEON, HasSlowVGETLNi32]>;
5464 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5466 (i32 (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5467 Requires<[HasNEON, HasSlowVGETLNi32]>;
5468 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
5469 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
5470 (SSubReg_f32_reg imm:$src2))>;
5471 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
5472 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
5473 (SSubReg_f32_reg imm:$src2))>;
5474 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
5475 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5476 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
5477 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5480 // VMOV : Vector Set Lane (move ARM core register to scalar)
5482 let Constraints = "$src1 = $V" in {
5483 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
5484 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
5485 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
5486 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
5487 GPR:$R, imm:$lane))]> {
5488 let Inst{21} = lane{2};
5489 let Inst{6-5} = lane{1-0};
5491 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
5492 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
5493 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
5494 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
5495 GPR:$R, imm:$lane))]> {
5496 let Inst{21} = lane{1};
5497 let Inst{6} = lane{0};
5499 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
5500 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
5501 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
5502 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
5503 GPR:$R, imm:$lane))]> {
5504 let Inst{21} = lane{0};
5507 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
5508 (v16i8 (INSERT_SUBREG QPR:$src1,
5509 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
5510 (DSubReg_i8_reg imm:$lane))),
5511 GPR:$src2, (SubReg_i8_lane imm:$lane))),
5512 (DSubReg_i8_reg imm:$lane)))>;
5513 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
5514 (v8i16 (INSERT_SUBREG QPR:$src1,
5515 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
5516 (DSubReg_i16_reg imm:$lane))),
5517 GPR:$src2, (SubReg_i16_lane imm:$lane))),
5518 (DSubReg_i16_reg imm:$lane)))>;
5519 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
5520 (v4i32 (INSERT_SUBREG QPR:$src1,
5521 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
5522 (DSubReg_i32_reg imm:$lane))),
5523 GPR:$src2, (SubReg_i32_lane imm:$lane))),
5524 (DSubReg_i32_reg imm:$lane)))>;
5526 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
5527 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
5528 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5529 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
5530 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
5531 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5533 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5534 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5535 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5536 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5538 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
5539 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5540 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
5541 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
5542 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
5543 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5545 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
5546 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5547 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
5548 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5549 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
5550 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5552 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
5553 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
5554 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5556 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
5557 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
5558 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5560 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
5561 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
5562 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5565 // VDUP : Vector Duplicate (from ARM core register to all elements)
5567 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5568 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
5569 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5570 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5571 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5572 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
5573 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5574 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5576 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
5577 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
5578 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>,
5579 Requires<[HasNEON, HasFastVDUP32]>;
5580 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
5581 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
5582 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
5584 // NEONvdup patterns for uarchs with fast VDUP.32.
5585 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>,
5586 Requires<[HasNEON,HasFastVDUP32]>;
5587 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
5589 // NEONvdup patterns for uarchs with slow VDUP.32 - use VMOVDRR instead.
5590 def : Pat<(v2i32 (NEONvdup (i32 GPR:$R))), (VMOVDRR GPR:$R, GPR:$R)>,
5591 Requires<[HasNEON,HasSlowVDUP32]>;
5592 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VMOVDRR GPR:$R, GPR:$R)>,
5593 Requires<[HasNEON,HasSlowVDUP32]>;
5595 // VDUP : Vector Duplicate Lane (from scalar to all elements)
5597 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
5598 ValueType Ty, Operand IdxTy>
5599 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5600 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
5601 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
5603 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
5604 ValueType ResTy, ValueType OpTy, Operand IdxTy>
5605 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5606 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
5607 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
5608 VectorIndex32:$lane)))]>;
5610 // Inst{19-16} is partially specified depending on the element size.
5612 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
5614 let Inst{19-17} = lane{2-0};
5616 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
5618 let Inst{19-18} = lane{1-0};
5620 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
5622 let Inst{19} = lane{0};
5624 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
5626 let Inst{19-17} = lane{2-0};
5628 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
5630 let Inst{19-18} = lane{1-0};
5632 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
5634 let Inst{19} = lane{0};
5637 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5638 (VDUPLN32d DPR:$Vm, imm:$lane)>;
5640 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5641 (VDUPLN32q DPR:$Vm, imm:$lane)>;
5643 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
5644 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
5645 (DSubReg_i8_reg imm:$lane))),
5646 (SubReg_i8_lane imm:$lane)))>;
5647 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
5648 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
5649 (DSubReg_i16_reg imm:$lane))),
5650 (SubReg_i16_lane imm:$lane)))>;
5651 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
5652 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
5653 (DSubReg_i32_reg imm:$lane))),
5654 (SubReg_i32_lane imm:$lane)))>;
5655 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
5656 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
5657 (DSubReg_i32_reg imm:$lane))),
5658 (SubReg_i32_lane imm:$lane)))>;
5660 def : Pat<(v2f32 (NEONvdup (f32 SPR:$src))),
5661 (v2f32 (VDUPLN32d (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
5662 SPR:$src, ssub_0), (i32 0)))>;
5663 def : Pat<(v4f32 (NEONvdup (f32 SPR:$src))),
5664 (v4f32 (VDUPLN32q (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
5665 SPR:$src, ssub_0), (i32 0)))>;
5667 // VMOVN : Vector Narrowing Move
5668 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
5669 "vmovn", "i", trunc>;
5670 // VQMOVN : Vector Saturating Narrowing Move
5671 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
5672 "vqmovn", "s", int_arm_neon_vqmovns>;
5673 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
5674 "vqmovn", "u", int_arm_neon_vqmovnu>;
5675 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
5676 "vqmovun", "s", int_arm_neon_vqmovnsu>;
5677 // VMOVL : Vector Lengthening Move
5678 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
5679 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
5680 def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
5681 def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>;
5682 def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>;
5684 // Vector Conversions.
5686 // VCVT : Vector Convert Between Floating-Point and Integers
5687 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5688 v2i32, v2f32, fp_to_sint>;
5689 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5690 v2i32, v2f32, fp_to_uint>;
5691 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5692 v2f32, v2i32, sint_to_fp>;
5693 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5694 v2f32, v2i32, uint_to_fp>;
5696 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5697 v4i32, v4f32, fp_to_sint>;
5698 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5699 v4i32, v4f32, fp_to_uint>;
5700 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5701 v4f32, v4i32, sint_to_fp>;
5702 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5703 v4f32, v4i32, uint_to_fp>;
5706 multiclass VCVT_FPI<string op, bits<3> op10_8, SDPatternOperator IntS,
5707 SDPatternOperator IntU> {
5708 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
5709 def SD : N2VDIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
5710 "s32.f32", v2i32, v2f32, IntS>, Requires<[HasV8, HasNEON]>;
5711 def SQ : N2VQIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
5712 "s32.f32", v4i32, v4f32, IntS>, Requires<[HasV8, HasNEON]>;
5713 def UD : N2VDIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
5714 "u32.f32", v2i32, v2f32, IntU>, Requires<[HasV8, HasNEON]>;
5715 def UQ : N2VQIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
5716 "u32.f32", v4i32, v4f32, IntU>, Requires<[HasV8, HasNEON]>;
5720 defm VCVTAN : VCVT_FPI<"a", 0b000, int_arm_neon_vcvtas, int_arm_neon_vcvtau>;
5721 defm VCVTNN : VCVT_FPI<"n", 0b001, int_arm_neon_vcvtns, int_arm_neon_vcvtnu>;
5722 defm VCVTPN : VCVT_FPI<"p", 0b010, int_arm_neon_vcvtps, int_arm_neon_vcvtpu>;
5723 defm VCVTMN : VCVT_FPI<"m", 0b011, int_arm_neon_vcvtms, int_arm_neon_vcvtmu>;
5725 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
5726 let DecoderMethod = "DecodeVCVTD" in {
5727 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5728 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
5729 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5730 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
5731 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5732 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
5733 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5734 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
5737 let DecoderMethod = "DecodeVCVTQ" in {
5738 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5739 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
5740 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5741 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
5742 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5743 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
5744 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5745 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
5748 def : NEONInstAlias<"vcvt${p}.s32.f32 $Dd, $Dm, #0",
5749 (VCVTf2sd DPR:$Dd, DPR:$Dm, pred:$p)>;
5750 def : NEONInstAlias<"vcvt${p}.u32.f32 $Dd, $Dm, #0",
5751 (VCVTf2ud DPR:$Dd, DPR:$Dm, pred:$p)>;
5752 def : NEONInstAlias<"vcvt${p}.f32.s32 $Dd, $Dm, #0",
5753 (VCVTs2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
5754 def : NEONInstAlias<"vcvt${p}.f32.u32 $Dd, $Dm, #0",
5755 (VCVTu2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
5757 def : NEONInstAlias<"vcvt${p}.s32.f32 $Qd, $Qm, #0",
5758 (VCVTf2sq QPR:$Qd, QPR:$Qm, pred:$p)>;
5759 def : NEONInstAlias<"vcvt${p}.u32.f32 $Qd, $Qm, #0",
5760 (VCVTf2uq QPR:$Qd, QPR:$Qm, pred:$p)>;
5761 def : NEONInstAlias<"vcvt${p}.f32.s32 $Qd, $Qm, #0",
5762 (VCVTs2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5763 def : NEONInstAlias<"vcvt${p}.f32.u32 $Qd, $Qm, #0",
5764 (VCVTu2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5767 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
5768 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
5769 IIC_VUNAQ, "vcvt", "f16.f32",
5770 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
5771 Requires<[HasNEON, HasFP16]>;
5772 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
5773 IIC_VUNAQ, "vcvt", "f32.f16",
5774 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
5775 Requires<[HasNEON, HasFP16]>;
5779 // VREV64 : Vector Reverse elements within 64-bit doublewords
5781 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5782 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
5783 (ins DPR:$Vm), IIC_VMOVD,
5784 OpcodeStr, Dt, "$Vd, $Vm", "",
5785 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
5786 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5787 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
5788 (ins QPR:$Vm), IIC_VMOVQ,
5789 OpcodeStr, Dt, "$Vd, $Vm", "",
5790 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
5792 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
5793 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
5794 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
5795 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
5797 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
5798 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5799 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
5800 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
5802 // VREV32 : Vector Reverse elements within 32-bit words
5804 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5805 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
5806 (ins DPR:$Vm), IIC_VMOVD,
5807 OpcodeStr, Dt, "$Vd, $Vm", "",
5808 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
5809 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5810 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
5811 (ins QPR:$Vm), IIC_VMOVQ,
5812 OpcodeStr, Dt, "$Vd, $Vm", "",
5813 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
5815 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
5816 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
5818 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
5819 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
5821 // VREV16 : Vector Reverse elements within 16-bit halfwords
5823 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5824 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
5825 (ins DPR:$Vm), IIC_VMOVD,
5826 OpcodeStr, Dt, "$Vd, $Vm", "",
5827 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
5828 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5829 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
5830 (ins QPR:$Vm), IIC_VMOVQ,
5831 OpcodeStr, Dt, "$Vd, $Vm", "",
5832 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
5834 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
5835 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
5837 // Other Vector Shuffles.
5839 // Aligned extractions: really just dropping registers
5841 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
5842 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
5843 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
5845 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
5847 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
5849 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
5851 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
5853 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
5856 // VEXT : Vector Extract
5859 // All of these have a two-operand InstAlias.
5860 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
5861 class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5862 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
5863 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
5864 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5865 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
5866 (Ty DPR:$Vm), imm:$index)))]> {
5869 let Inst{10-8} = index{2-0};
5872 class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5873 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
5874 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
5875 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5876 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
5877 (Ty QPR:$Vm), imm:$index)))]> {
5879 let Inst{11-8} = index{3-0};
5883 def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> {
5884 let Inst{10-8} = index{2-0};
5886 def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> {
5887 let Inst{10-9} = index{1-0};
5890 def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> {
5891 let Inst{10} = index{0};
5892 let Inst{9-8} = 0b00;
5894 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
5897 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
5899 def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> {
5900 let Inst{11-8} = index{3-0};
5902 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
5903 let Inst{11-9} = index{2-0};
5906 def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
5907 let Inst{11-10} = index{1-0};
5908 let Inst{9-8} = 0b00;
5910 def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> {
5911 let Inst{11} = index{0};
5912 let Inst{10-8} = 0b000;
5914 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
5917 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
5919 // VTRN : Vector Transpose
5921 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
5922 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
5923 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
5925 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
5926 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
5927 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
5929 // VUZP : Vector Unzip (Deinterleave)
5931 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
5932 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
5933 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5934 def : NEONInstAlias<"vuzp${p}.32 $Dd, $Dm",
5935 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
5937 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
5938 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
5939 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
5941 // VZIP : Vector Zip (Interleave)
5943 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
5944 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
5945 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5946 def : NEONInstAlias<"vzip${p}.32 $Dd, $Dm",
5947 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
5949 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
5950 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
5951 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
5953 // Vector Table Lookup and Table Extension.
5955 // VTBL : Vector Table Lookup
5956 let DecoderMethod = "DecodeTBLInstruction" in {
5958 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
5959 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
5960 "vtbl", "8", "$Vd, $Vn, $Vm", "",
5961 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
5962 let hasExtraSrcRegAllocReq = 1 in {
5964 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
5965 (ins VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
5966 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5968 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
5969 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
5970 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5972 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
5973 (ins VecListFourD:$Vn, DPR:$Vm),
5975 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5976 } // hasExtraSrcRegAllocReq = 1
5979 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
5981 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
5983 // VTBX : Vector Table Extension
5985 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
5986 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
5987 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
5988 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
5989 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
5990 let hasExtraSrcRegAllocReq = 1 in {
5992 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
5993 (ins DPR:$orig, VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
5994 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
5996 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
5997 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
5998 NVTBLFrm, IIC_VTBX3,
5999 "vtbx", "8", "$Vd, $Vn, $Vm",
6002 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
6003 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
6004 "vtbx", "8", "$Vd, $Vn, $Vm",
6006 } // hasExtraSrcRegAllocReq = 1
6009 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
6010 IIC_VTBX3, "$orig = $dst", []>;
6012 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
6013 IIC_VTBX4, "$orig = $dst", []>;
6014 } // DecoderMethod = "DecodeTBLInstruction"
6016 // VRINT : Vector Rounding
6017 multiclass VRINT_FPI<string op, bits<3> op9_7, SDPatternOperator Int> {
6018 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
6019 def D : N2VDIntnp<0b10, 0b100, 0, NoItinerary,
6020 !strconcat("vrint", op), "f32",
6021 v2f32, v2f32, Int>, Requires<[HasV8, HasNEON]> {
6022 let Inst{9-7} = op9_7;
6024 def Q : N2VQIntnp<0b10, 0b100, 0, NoItinerary,
6025 !strconcat("vrint", op), "f32",
6026 v4f32, v4f32, Int>, Requires<[HasV8, HasNEON]> {
6027 let Inst{9-7} = op9_7;
6031 def : NEONInstAlias<!strconcat("vrint", op, ".f32.f32\t$Dd, $Dm"),
6032 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>;
6033 def : NEONInstAlias<!strconcat("vrint", op, ".f32.f32\t$Qd, $Qm"),
6034 (!cast<Instruction>(NAME#"Q") QPR:$Qd, QPR:$Qm)>;
6037 defm VRINTNN : VRINT_FPI<"n", 0b000, int_arm_neon_vrintn>;
6038 defm VRINTXN : VRINT_FPI<"x", 0b001, int_arm_neon_vrintx>;
6039 defm VRINTAN : VRINT_FPI<"a", 0b010, int_arm_neon_vrinta>;
6040 defm VRINTZN : VRINT_FPI<"z", 0b011, int_arm_neon_vrintz>;
6041 defm VRINTMN : VRINT_FPI<"m", 0b101, int_arm_neon_vrintm>;
6042 defm VRINTPN : VRINT_FPI<"p", 0b111, int_arm_neon_vrintp>;
6044 // Cryptography instructions
6045 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
6046 DecoderNamespace = "v8Crypto", hasSideEffects = 0 in {
6047 class AES<string op, bit op7, bit op6, SDPatternOperator Int>
6048 : N2VQIntXnp<0b00, 0b00, 0b011, op6, op7, NoItinerary,
6049 !strconcat("aes", op), "8", v16i8, v16i8, Int>,
6050 Requires<[HasV8, HasCrypto]>;
6051 class AES2Op<string op, bit op7, bit op6, SDPatternOperator Int>
6052 : N2VQIntX2np<0b00, 0b00, 0b011, op6, op7, NoItinerary,
6053 !strconcat("aes", op), "8", v16i8, v16i8, Int>,
6054 Requires<[HasV8, HasCrypto]>;
6055 class N2SHA<string op, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
6056 SDPatternOperator Int>
6057 : N2VQIntXnp<0b10, op17_16, op10_8, op6, op7, NoItinerary,
6058 !strconcat("sha", op), "32", v4i32, v4i32, Int>,
6059 Requires<[HasV8, HasCrypto]>;
6060 class N2SHA2Op<string op, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
6061 SDPatternOperator Int>
6062 : N2VQIntX2np<0b10, op17_16, op10_8, op6, op7, NoItinerary,
6063 !strconcat("sha", op), "32", v4i32, v4i32, Int>,
6064 Requires<[HasV8, HasCrypto]>;
6065 class N3SHA3Op<string op, bits<5> op27_23, bits<2> op21_20, SDPatternOperator Int>
6066 : N3VQInt3np<op27_23, op21_20, 0b1100, 1, 0, N3RegFrm, NoItinerary,
6067 !strconcat("sha", op), "32", v4i32, v4i32, Int, 0>,
6068 Requires<[HasV8, HasCrypto]>;
6071 def AESD : AES2Op<"d", 0, 1, int_arm_neon_aesd>;
6072 def AESE : AES2Op<"e", 0, 0, int_arm_neon_aese>;
6073 def AESIMC : AES<"imc", 1, 1, int_arm_neon_aesimc>;
6074 def AESMC : AES<"mc", 1, 0, int_arm_neon_aesmc>;
6076 def SHA1H : N2SHA<"1h", 0b01, 0b010, 1, 1, null_frag>;
6077 def SHA1SU1 : N2SHA2Op<"1su1", 0b10, 0b011, 1, 0, int_arm_neon_sha1su1>;
6078 def SHA256SU0 : N2SHA2Op<"256su0", 0b10, 0b011, 1, 1, int_arm_neon_sha256su0>;
6079 def SHA1C : N3SHA3Op<"1c", 0b00100, 0b00, null_frag>;
6080 def SHA1M : N3SHA3Op<"1m", 0b00100, 0b10, null_frag>;
6081 def SHA1P : N3SHA3Op<"1p", 0b00100, 0b01, null_frag>;
6082 def SHA1SU0 : N3SHA3Op<"1su0", 0b00100, 0b11, int_arm_neon_sha1su0>;
6083 def SHA256H : N3SHA3Op<"256h", 0b00110, 0b00, int_arm_neon_sha256h>;
6084 def SHA256H2 : N3SHA3Op<"256h2", 0b00110, 0b01, int_arm_neon_sha256h2>;
6085 def SHA256SU1 : N3SHA3Op<"256su1", 0b00110, 0b10, int_arm_neon_sha256su1>;
6087 def : Pat<(i32 (int_arm_neon_sha1h i32:$Rn)),
6088 (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG
6089 (SHA1H (SUBREG_TO_REG (i64 0),
6090 (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)),
6094 def : Pat<(v4i32 (int_arm_neon_sha1c v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
6095 (SHA1C v4i32:$hash_abcd,
6096 (SUBREG_TO_REG (i64 0),
6097 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
6101 def : Pat<(v4i32 (int_arm_neon_sha1m v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
6102 (SHA1M v4i32:$hash_abcd,
6103 (SUBREG_TO_REG (i64 0),
6104 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
6108 def : Pat<(v4i32 (int_arm_neon_sha1p v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
6109 (SHA1P v4i32:$hash_abcd,
6110 (SUBREG_TO_REG (i64 0),
6111 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
6115 //===----------------------------------------------------------------------===//
6116 // NEON instructions for single-precision FP math
6117 //===----------------------------------------------------------------------===//
6119 class N2VSPat<SDNode OpNode, NeonI Inst>
6120 : NEONFPPat<(f32 (OpNode SPR:$a)),
6122 (v2f32 (COPY_TO_REGCLASS (Inst
6124 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6125 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
6127 class N3VSPat<SDNode OpNode, NeonI Inst>
6128 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
6130 (v2f32 (COPY_TO_REGCLASS (Inst
6132 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6135 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6136 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
6138 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
6139 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
6141 (v2f32 (COPY_TO_REGCLASS (Inst
6143 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6146 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6149 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6150 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
6152 def : N3VSPat<fadd, VADDfd>;
6153 def : N3VSPat<fsub, VSUBfd>;
6154 def : N3VSPat<fmul, VMULfd>;
6155 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
6156 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
6157 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
6158 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
6159 def : N3VSMulOpPat<fmul, fadd, VFMAfd>,
6160 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
6161 def : N3VSMulOpPat<fmul, fsub, VFMSfd>,
6162 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
6163 def : N2VSPat<fabs, VABSfd>;
6164 def : N2VSPat<fneg, VNEGfd>;
6165 def : N3VSPat<NEONfmax, VMAXfd>;
6166 def : N3VSPat<NEONfmin, VMINfd>;
6167 def : N2VSPat<arm_ftosi, VCVTf2sd>;
6168 def : N2VSPat<arm_ftoui, VCVTf2ud>;
6169 def : N2VSPat<arm_sitof, VCVTs2fd>;
6170 def : N2VSPat<arm_uitof, VCVTu2fd>;
6172 // Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers.
6173 def : Pat<(f32 (bitconvert GPR:$a)),
6174 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
6175 Requires<[HasNEON, DontUseVMOVSR]>;
6177 //===----------------------------------------------------------------------===//
6178 // Non-Instruction Patterns
6179 //===----------------------------------------------------------------------===//
6182 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
6183 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
6184 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
6185 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
6186 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
6187 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
6188 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
6189 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
6190 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
6191 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
6192 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
6193 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
6194 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
6195 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
6196 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
6197 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
6198 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
6199 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
6200 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
6201 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
6202 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
6203 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
6204 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
6205 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
6206 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
6207 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
6208 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
6209 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
6210 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
6211 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
6213 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
6214 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
6215 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
6216 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
6217 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
6218 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
6219 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
6220 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
6221 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
6222 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
6223 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
6224 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
6225 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
6226 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
6227 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
6228 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
6229 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
6230 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
6231 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
6232 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
6233 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
6234 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
6235 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
6236 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
6237 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
6238 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
6239 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
6240 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
6241 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
6242 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
6244 // Fold extracting an element out of a v2i32 into a vfp register.
6245 def : Pat<(f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane)))),
6246 (f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6248 // Vector lengthening move with load, matching extending loads.
6250 // extload, zextload and sextload for a standard lengthening load. Example:
6251 // Lengthen_Single<"8", "i16", "8"> =
6252 // Pat<(v8i16 (extloadvi8 addrmode6:$addr))
6253 // (VMOVLuv8i16 (VLD1d8 addrmode6:$addr,
6254 // (f64 (IMPLICIT_DEF)), (i32 0)))>;
6255 multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> {
6256 let AddedComplexity = 10 in {
6257 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6258 (!cast<PatFrag>("extloadvi" # SrcTy) addrmode6:$addr)),
6259 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
6260 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6262 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6263 (!cast<PatFrag>("zextloadvi" # SrcTy) addrmode6:$addr)),
6264 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
6265 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6267 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6268 (!cast<PatFrag>("sextloadvi" # SrcTy) addrmode6:$addr)),
6269 (!cast<Instruction>("VMOVLsv" # DestLanes # DestTy)
6270 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6274 // extload, zextload and sextload for a lengthening load which only uses
6275 // half the lanes available. Example:
6276 // Lengthen_HalfSingle<"4", "i16", "8", "i16", "i8"> =
6277 // Pat<(v4i16 (extloadvi8 addrmode6oneL32:$addr)),
6278 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
6279 // (f64 (IMPLICIT_DEF)), (i32 0))),
6281 multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
6282 string InsnLanes, string InsnTy> {
6283 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6284 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6285 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6286 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6288 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6289 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6290 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6291 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6293 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6294 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6295 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
6296 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6300 // extload, zextload and sextload for a lengthening load followed by another
6301 // lengthening load, to quadruple the initial length.
6303 // Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32"> =
6304 // Pat<(v4i32 (extloadvi8 addrmode6oneL32:$addr))
6305 // (EXTRACT_SUBREG (VMOVLuv4i32
6306 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
6307 // (f64 (IMPLICIT_DEF)),
6311 multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
6312 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6314 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6315 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6316 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6317 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6318 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6320 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6321 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6322 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6323 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6324 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6326 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6327 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6328 (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6329 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6330 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6334 // extload, zextload and sextload for a lengthening load followed by another
6335 // lengthening load, to quadruple the initial length, but which ends up only
6336 // requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
6338 // Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> =
6339 // Pat<(v2i32 (extloadvi8 addrmode6:$addr))
6340 // (EXTRACT_SUBREG (VMOVLuv4i32
6341 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr,
6342 // (f64 (IMPLICIT_DEF)), (i32 0))),
6345 multiclass Lengthen_HalfDouble<string DestLanes, string DestTy, string SrcTy,
6346 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6348 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6349 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6:$addr)),
6350 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6351 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6352 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6355 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6356 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6:$addr)),
6357 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6358 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6359 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6362 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6363 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6:$addr)),
6364 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6365 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6366 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6371 defm : Lengthen_Single<"8", "i16", "8">; // v8i8 -> v8i16
6372 defm : Lengthen_Single<"4", "i32", "16">; // v4i16 -> v4i32
6373 defm : Lengthen_Single<"2", "i64", "32">; // v2i32 -> v2i64
6375 defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16
6376 defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
6378 // Double lengthening - v4i8 -> v4i16 -> v4i32
6379 defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32">;
6380 // v2i8 -> v2i16 -> v2i32
6381 defm : Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32">;
6382 // v2i16 -> v2i32 -> v2i64
6383 defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64">;
6385 // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
6386 def : Pat<(v2i64 (extloadvi8 addrmode6:$addr)),
6387 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6388 (VLD1LNd16 addrmode6:$addr,
6389 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6390 def : Pat<(v2i64 (zextloadvi8 addrmode6:$addr)),
6391 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6392 (VLD1LNd16 addrmode6:$addr,
6393 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6394 def : Pat<(v2i64 (sextloadvi8 addrmode6:$addr)),
6395 (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
6396 (VLD1LNd16 addrmode6:$addr,
6397 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6399 //===----------------------------------------------------------------------===//
6400 // Assembler aliases
6403 def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
6404 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
6405 def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
6406 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;
6408 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
6409 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
6410 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6411 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
6412 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6413 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
6414 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6415 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
6416 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6417 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
6418 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6419 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
6420 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6421 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
6422 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6423 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
6424 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6425 // ... two-operand aliases
6426 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
6427 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6428 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
6429 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6430 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
6431 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6432 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
6433 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6434 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
6435 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6436 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
6437 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6439 // VLD1 single-lane pseudo-instructions. These need special handling for
6440 // the lane index that an InstAlias can't handle, so we use these instead.
6441 def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
6442 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6444 def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr",
6445 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6447 def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr",
6448 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6451 def VLD1LNdWB_fixed_Asm_8 :
6452 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!",
6453 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6455 def VLD1LNdWB_fixed_Asm_16 :
6456 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!",
6457 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6459 def VLD1LNdWB_fixed_Asm_32 :
6460 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!",
6461 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6463 def VLD1LNdWB_register_Asm_8 :
6464 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm",
6465 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6466 rGPR:$Rm, pred:$p)>;
6467 def VLD1LNdWB_register_Asm_16 :
6468 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm",
6469 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6470 rGPR:$Rm, pred:$p)>;
6471 def VLD1LNdWB_register_Asm_32 :
6472 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm",
6473 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6474 rGPR:$Rm, pred:$p)>;
6477 // VST1 single-lane pseudo-instructions. These need special handling for
6478 // the lane index that an InstAlias can't handle, so we use these instead.
6479 def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr",
6480 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6482 def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr",
6483 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6485 def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr",
6486 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6489 def VST1LNdWB_fixed_Asm_8 :
6490 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!",
6491 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6493 def VST1LNdWB_fixed_Asm_16 :
6494 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!",
6495 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6497 def VST1LNdWB_fixed_Asm_32 :
6498 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!",
6499 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6501 def VST1LNdWB_register_Asm_8 :
6502 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm",
6503 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6504 rGPR:$Rm, pred:$p)>;
6505 def VST1LNdWB_register_Asm_16 :
6506 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm",
6507 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6508 rGPR:$Rm, pred:$p)>;
6509 def VST1LNdWB_register_Asm_32 :
6510 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm",
6511 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6512 rGPR:$Rm, pred:$p)>;
6514 // VLD2 single-lane pseudo-instructions. These need special handling for
6515 // the lane index that an InstAlias can't handle, so we use these instead.
6516 def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr",
6517 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6519 def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6520 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6522 def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6523 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, pred:$p)>;
6524 def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6525 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6527 def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6528 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6531 def VLD2LNdWB_fixed_Asm_8 :
6532 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!",
6533 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6535 def VLD2LNdWB_fixed_Asm_16 :
6536 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6537 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6539 def VLD2LNdWB_fixed_Asm_32 :
6540 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6541 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6543 def VLD2LNqWB_fixed_Asm_16 :
6544 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6545 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6547 def VLD2LNqWB_fixed_Asm_32 :
6548 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6549 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6551 def VLD2LNdWB_register_Asm_8 :
6552 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm",
6553 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6554 rGPR:$Rm, pred:$p)>;
6555 def VLD2LNdWB_register_Asm_16 :
6556 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6557 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6558 rGPR:$Rm, pred:$p)>;
6559 def VLD2LNdWB_register_Asm_32 :
6560 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6561 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6562 rGPR:$Rm, pred:$p)>;
6563 def VLD2LNqWB_register_Asm_16 :
6564 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6565 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6566 rGPR:$Rm, pred:$p)>;
6567 def VLD2LNqWB_register_Asm_32 :
6568 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6569 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6570 rGPR:$Rm, pred:$p)>;
6573 // VST2 single-lane pseudo-instructions. These need special handling for
6574 // the lane index that an InstAlias can't handle, so we use these instead.
6575 def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr",
6576 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6578 def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6579 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6581 def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6582 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6584 def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6585 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6587 def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6588 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6591 def VST2LNdWB_fixed_Asm_8 :
6592 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!",
6593 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6595 def VST2LNdWB_fixed_Asm_16 :
6596 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6597 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6599 def VST2LNdWB_fixed_Asm_32 :
6600 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6601 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6603 def VST2LNqWB_fixed_Asm_16 :
6604 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6605 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6607 def VST2LNqWB_fixed_Asm_32 :
6608 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6609 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6611 def VST2LNdWB_register_Asm_8 :
6612 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm",
6613 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6614 rGPR:$Rm, pred:$p)>;
6615 def VST2LNdWB_register_Asm_16 :
6616 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6617 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6618 rGPR:$Rm, pred:$p)>;
6619 def VST2LNdWB_register_Asm_32 :
6620 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6621 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6622 rGPR:$Rm, pred:$p)>;
6623 def VST2LNqWB_register_Asm_16 :
6624 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6625 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6626 rGPR:$Rm, pred:$p)>;
6627 def VST2LNqWB_register_Asm_32 :
6628 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6629 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6630 rGPR:$Rm, pred:$p)>;
6632 // VLD3 all-lanes pseudo-instructions. These need special handling for
6633 // the lane index that an InstAlias can't handle, so we use these instead.
6634 def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6635 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6637 def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6638 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6640 def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6641 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6643 def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6644 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6646 def VLD3DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6647 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6649 def VLD3DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6650 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6653 def VLD3DUPdWB_fixed_Asm_8 :
6654 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6655 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6657 def VLD3DUPdWB_fixed_Asm_16 :
6658 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6659 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6661 def VLD3DUPdWB_fixed_Asm_32 :
6662 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6663 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6665 def VLD3DUPqWB_fixed_Asm_8 :
6666 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6667 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6669 def VLD3DUPqWB_fixed_Asm_16 :
6670 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6671 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6673 def VLD3DUPqWB_fixed_Asm_32 :
6674 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6675 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6677 def VLD3DUPdWB_register_Asm_8 :
6678 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6679 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6680 rGPR:$Rm, pred:$p)>;
6681 def VLD3DUPdWB_register_Asm_16 :
6682 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6683 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6684 rGPR:$Rm, pred:$p)>;
6685 def VLD3DUPdWB_register_Asm_32 :
6686 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6687 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6688 rGPR:$Rm, pred:$p)>;
6689 def VLD3DUPqWB_register_Asm_8 :
6690 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6691 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6692 rGPR:$Rm, pred:$p)>;
6693 def VLD3DUPqWB_register_Asm_16 :
6694 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6695 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6696 rGPR:$Rm, pred:$p)>;
6697 def VLD3DUPqWB_register_Asm_32 :
6698 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6699 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6700 rGPR:$Rm, pred:$p)>;
6703 // VLD3 single-lane pseudo-instructions. These need special handling for
6704 // the lane index that an InstAlias can't handle, so we use these instead.
6705 def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6706 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6708 def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6709 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6711 def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6712 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6714 def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6715 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6717 def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6718 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6721 def VLD3LNdWB_fixed_Asm_8 :
6722 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6723 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6725 def VLD3LNdWB_fixed_Asm_16 :
6726 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6727 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6729 def VLD3LNdWB_fixed_Asm_32 :
6730 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6731 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6733 def VLD3LNqWB_fixed_Asm_16 :
6734 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6735 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6737 def VLD3LNqWB_fixed_Asm_32 :
6738 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6739 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6741 def VLD3LNdWB_register_Asm_8 :
6742 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6743 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6744 rGPR:$Rm, pred:$p)>;
6745 def VLD3LNdWB_register_Asm_16 :
6746 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6747 (ins VecListThreeDHWordIndexed:$list,
6748 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
6749 def VLD3LNdWB_register_Asm_32 :
6750 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6751 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6752 rGPR:$Rm, pred:$p)>;
6753 def VLD3LNqWB_register_Asm_16 :
6754 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6755 (ins VecListThreeQHWordIndexed:$list,
6756 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
6757 def VLD3LNqWB_register_Asm_32 :
6758 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6759 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6760 rGPR:$Rm, pred:$p)>;
6762 // VLD3 multiple structure pseudo-instructions. These need special handling for
6763 // the vector operands that the normal instructions don't yet model.
6764 // FIXME: Remove these when the register classes and instructions are updated.
6765 def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6766 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6767 def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6768 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6769 def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6770 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6771 def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6772 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6773 def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6774 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6775 def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6776 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6778 def VLD3dWB_fixed_Asm_8 :
6779 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6780 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6781 def VLD3dWB_fixed_Asm_16 :
6782 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6783 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6784 def VLD3dWB_fixed_Asm_32 :
6785 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6786 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6787 def VLD3qWB_fixed_Asm_8 :
6788 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6789 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6790 def VLD3qWB_fixed_Asm_16 :
6791 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6792 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6793 def VLD3qWB_fixed_Asm_32 :
6794 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6795 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6796 def VLD3dWB_register_Asm_8 :
6797 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6798 (ins VecListThreeD:$list, addrmode6align64:$addr,
6799 rGPR:$Rm, pred:$p)>;
6800 def VLD3dWB_register_Asm_16 :
6801 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6802 (ins VecListThreeD:$list, addrmode6align64:$addr,
6803 rGPR:$Rm, pred:$p)>;
6804 def VLD3dWB_register_Asm_32 :
6805 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6806 (ins VecListThreeD:$list, addrmode6align64:$addr,
6807 rGPR:$Rm, pred:$p)>;
6808 def VLD3qWB_register_Asm_8 :
6809 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6810 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6811 rGPR:$Rm, pred:$p)>;
6812 def VLD3qWB_register_Asm_16 :
6813 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6814 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6815 rGPR:$Rm, pred:$p)>;
6816 def VLD3qWB_register_Asm_32 :
6817 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6818 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6819 rGPR:$Rm, pred:$p)>;
6821 // VST3 single-lane pseudo-instructions. These need special handling for
6822 // the lane index that an InstAlias can't handle, so we use these instead.
6823 def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6824 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6826 def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6827 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6829 def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6830 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6832 def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6833 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6835 def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6836 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6839 def VST3LNdWB_fixed_Asm_8 :
6840 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6841 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6843 def VST3LNdWB_fixed_Asm_16 :
6844 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6845 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6847 def VST3LNdWB_fixed_Asm_32 :
6848 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6849 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6851 def VST3LNqWB_fixed_Asm_16 :
6852 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6853 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6855 def VST3LNqWB_fixed_Asm_32 :
6856 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6857 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6859 def VST3LNdWB_register_Asm_8 :
6860 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6861 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6862 rGPR:$Rm, pred:$p)>;
6863 def VST3LNdWB_register_Asm_16 :
6864 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6865 (ins VecListThreeDHWordIndexed:$list,
6866 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
6867 def VST3LNdWB_register_Asm_32 :
6868 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6869 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6870 rGPR:$Rm, pred:$p)>;
6871 def VST3LNqWB_register_Asm_16 :
6872 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6873 (ins VecListThreeQHWordIndexed:$list,
6874 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
6875 def VST3LNqWB_register_Asm_32 :
6876 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6877 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6878 rGPR:$Rm, pred:$p)>;
6881 // VST3 multiple structure pseudo-instructions. These need special handling for
6882 // the vector operands that the normal instructions don't yet model.
6883 // FIXME: Remove these when the register classes and instructions are updated.
6884 def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6885 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6886 def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6887 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6888 def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6889 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6890 def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6891 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6892 def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6893 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6894 def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6895 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6897 def VST3dWB_fixed_Asm_8 :
6898 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6899 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6900 def VST3dWB_fixed_Asm_16 :
6901 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6902 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6903 def VST3dWB_fixed_Asm_32 :
6904 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6905 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6906 def VST3qWB_fixed_Asm_8 :
6907 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6908 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6909 def VST3qWB_fixed_Asm_16 :
6910 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6911 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6912 def VST3qWB_fixed_Asm_32 :
6913 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6914 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6915 def VST3dWB_register_Asm_8 :
6916 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6917 (ins VecListThreeD:$list, addrmode6align64:$addr,
6918 rGPR:$Rm, pred:$p)>;
6919 def VST3dWB_register_Asm_16 :
6920 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6921 (ins VecListThreeD:$list, addrmode6align64:$addr,
6922 rGPR:$Rm, pred:$p)>;
6923 def VST3dWB_register_Asm_32 :
6924 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6925 (ins VecListThreeD:$list, addrmode6align64:$addr,
6926 rGPR:$Rm, pred:$p)>;
6927 def VST3qWB_register_Asm_8 :
6928 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6929 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6930 rGPR:$Rm, pred:$p)>;
6931 def VST3qWB_register_Asm_16 :
6932 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6933 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6934 rGPR:$Rm, pred:$p)>;
6935 def VST3qWB_register_Asm_32 :
6936 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6937 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6938 rGPR:$Rm, pred:$p)>;
6940 // VLD4 all-lanes pseudo-instructions. These need special handling for
6941 // the lane index that an InstAlias can't handle, so we use these instead.
6942 def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6943 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
6945 def VLD4DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6946 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
6948 def VLD4DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6949 (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr,
6951 def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6952 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
6954 def VLD4DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6955 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
6957 def VLD4DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6958 (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr,
6961 def VLD4DUPdWB_fixed_Asm_8 :
6962 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6963 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
6965 def VLD4DUPdWB_fixed_Asm_16 :
6966 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6967 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
6969 def VLD4DUPdWB_fixed_Asm_32 :
6970 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6971 (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr,
6973 def VLD4DUPqWB_fixed_Asm_8 :
6974 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6975 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
6977 def VLD4DUPqWB_fixed_Asm_16 :
6978 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6979 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
6981 def VLD4DUPqWB_fixed_Asm_32 :
6982 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6983 (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr,
6985 def VLD4DUPdWB_register_Asm_8 :
6986 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6987 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
6988 rGPR:$Rm, pred:$p)>;
6989 def VLD4DUPdWB_register_Asm_16 :
6990 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6991 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
6992 rGPR:$Rm, pred:$p)>;
6993 def VLD4DUPdWB_register_Asm_32 :
6994 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6995 (ins VecListFourDAllLanes:$list,
6996 addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p)>;
6997 def VLD4DUPqWB_register_Asm_8 :
6998 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6999 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
7000 rGPR:$Rm, pred:$p)>;
7001 def VLD4DUPqWB_register_Asm_16 :
7002 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7003 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
7004 rGPR:$Rm, pred:$p)>;
7005 def VLD4DUPqWB_register_Asm_32 :
7006 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7007 (ins VecListFourQAllLanes:$list,
7008 addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p)>;
7011 // VLD4 single-lane pseudo-instructions. These need special handling for
7012 // the lane index that an InstAlias can't handle, so we use these instead.
7013 def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7014 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7016 def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7017 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7019 def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7020 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7022 def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7023 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7025 def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7026 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7029 def VLD4LNdWB_fixed_Asm_8 :
7030 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7031 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7033 def VLD4LNdWB_fixed_Asm_16 :
7034 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7035 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7037 def VLD4LNdWB_fixed_Asm_32 :
7038 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7039 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7041 def VLD4LNqWB_fixed_Asm_16 :
7042 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7043 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7045 def VLD4LNqWB_fixed_Asm_32 :
7046 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7047 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7049 def VLD4LNdWB_register_Asm_8 :
7050 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7051 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7052 rGPR:$Rm, pred:$p)>;
7053 def VLD4LNdWB_register_Asm_16 :
7054 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7055 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7056 rGPR:$Rm, pred:$p)>;
7057 def VLD4LNdWB_register_Asm_32 :
7058 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7059 (ins VecListFourDWordIndexed:$list,
7060 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
7061 def VLD4LNqWB_register_Asm_16 :
7062 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7063 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7064 rGPR:$Rm, pred:$p)>;
7065 def VLD4LNqWB_register_Asm_32 :
7066 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7067 (ins VecListFourQWordIndexed:$list,
7068 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
7072 // VLD4 multiple structure pseudo-instructions. These need special handling for
7073 // the vector operands that the normal instructions don't yet model.
7074 // FIXME: Remove these when the register classes and instructions are updated.
7075 def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7076 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7078 def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7079 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7081 def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7082 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7084 def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7085 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7087 def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7088 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7090 def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7091 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7094 def VLD4dWB_fixed_Asm_8 :
7095 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7096 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7098 def VLD4dWB_fixed_Asm_16 :
7099 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7100 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7102 def VLD4dWB_fixed_Asm_32 :
7103 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7104 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7106 def VLD4qWB_fixed_Asm_8 :
7107 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7108 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7110 def VLD4qWB_fixed_Asm_16 :
7111 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7112 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7114 def VLD4qWB_fixed_Asm_32 :
7115 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7116 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7118 def VLD4dWB_register_Asm_8 :
7119 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7120 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7121 rGPR:$Rm, pred:$p)>;
7122 def VLD4dWB_register_Asm_16 :
7123 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7124 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7125 rGPR:$Rm, pred:$p)>;
7126 def VLD4dWB_register_Asm_32 :
7127 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7128 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7129 rGPR:$Rm, pred:$p)>;
7130 def VLD4qWB_register_Asm_8 :
7131 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7132 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7133 rGPR:$Rm, pred:$p)>;
7134 def VLD4qWB_register_Asm_16 :
7135 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7136 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7137 rGPR:$Rm, pred:$p)>;
7138 def VLD4qWB_register_Asm_32 :
7139 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7140 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7141 rGPR:$Rm, pred:$p)>;
7143 // VST4 single-lane pseudo-instructions. These need special handling for
7144 // the lane index that an InstAlias can't handle, so we use these instead.
7145 def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
7146 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7148 def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7149 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7151 def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7152 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7154 def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7155 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7157 def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7158 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7161 def VST4LNdWB_fixed_Asm_8 :
7162 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
7163 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7165 def VST4LNdWB_fixed_Asm_16 :
7166 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7167 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7169 def VST4LNdWB_fixed_Asm_32 :
7170 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7171 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7173 def VST4LNqWB_fixed_Asm_16 :
7174 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7175 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7177 def VST4LNqWB_fixed_Asm_32 :
7178 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7179 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7181 def VST4LNdWB_register_Asm_8 :
7182 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7183 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7184 rGPR:$Rm, pred:$p)>;
7185 def VST4LNdWB_register_Asm_16 :
7186 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7187 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7188 rGPR:$Rm, pred:$p)>;
7189 def VST4LNdWB_register_Asm_32 :
7190 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7191 (ins VecListFourDWordIndexed:$list,
7192 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
7193 def VST4LNqWB_register_Asm_16 :
7194 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7195 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7196 rGPR:$Rm, pred:$p)>;
7197 def VST4LNqWB_register_Asm_32 :
7198 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7199 (ins VecListFourQWordIndexed:$list,
7200 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
7203 // VST4 multiple structure pseudo-instructions. These need special handling for
7204 // the vector operands that the normal instructions don't yet model.
7205 // FIXME: Remove these when the register classes and instructions are updated.
7206 def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
7207 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7209 def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7210 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7212 def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7213 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7215 def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
7216 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7218 def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7219 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7221 def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7222 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7225 def VST4dWB_fixed_Asm_8 :
7226 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
7227 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7229 def VST4dWB_fixed_Asm_16 :
7230 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7231 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7233 def VST4dWB_fixed_Asm_32 :
7234 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7235 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7237 def VST4qWB_fixed_Asm_8 :
7238 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
7239 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7241 def VST4qWB_fixed_Asm_16 :
7242 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7243 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7245 def VST4qWB_fixed_Asm_32 :
7246 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7247 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7249 def VST4dWB_register_Asm_8 :
7250 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7251 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7252 rGPR:$Rm, pred:$p)>;
7253 def VST4dWB_register_Asm_16 :
7254 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7255 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7256 rGPR:$Rm, pred:$p)>;
7257 def VST4dWB_register_Asm_32 :
7258 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7259 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7260 rGPR:$Rm, pred:$p)>;
7261 def VST4qWB_register_Asm_8 :
7262 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7263 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7264 rGPR:$Rm, pred:$p)>;
7265 def VST4qWB_register_Asm_16 :
7266 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7267 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7268 rGPR:$Rm, pred:$p)>;
7269 def VST4qWB_register_Asm_32 :
7270 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7271 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7272 rGPR:$Rm, pred:$p)>;
7274 // VMOV/VMVN takes an optional datatype suffix
7275 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
7276 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
7277 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
7278 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
7280 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
7281 (VMVNd DPR:$Vd, DPR:$Vm, pred:$p)>;
7282 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
7283 (VMVNq QPR:$Vd, QPR:$Vm, pred:$p)>;
7285 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
7286 // D-register versions.
7287 def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm",
7288 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7289 def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm",
7290 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7291 def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm",
7292 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7293 def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm",
7294 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7295 def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm",
7296 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7297 def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm",
7298 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7299 def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm",
7300 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7301 // Q-register versions.
7302 def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
7303 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7304 def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
7305 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7306 def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
7307 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7308 def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
7309 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7310 def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
7311 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7312 def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
7313 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7314 def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
7315 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7317 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
7318 // D-register versions.
7319 def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
7320 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7321 def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
7322 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7323 def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
7324 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7325 def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
7326 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7327 def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
7328 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7329 def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
7330 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7331 def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
7332 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7333 // Q-register versions.
7334 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
7335 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7336 def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
7337 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7338 def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm",
7339 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7340 def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm",
7341 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7342 def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm",
7343 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7344 def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
7345 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7346 def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
7347 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7349 // VSWP allows, but does not require, a type suffix.
7350 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
7351 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
7352 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
7353 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
7355 // VBIF, VBIT, and VBSL allow, but do not require, a type suffix.
7356 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
7357 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7358 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
7359 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7360 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
7361 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7362 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
7363 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7364 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
7365 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7366 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
7367 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7369 // "vmov Rd, #-imm" can be handled via "vmvn".
7370 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
7371 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7372 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
7373 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7374 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
7375 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7376 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
7377 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7379 // 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
7380 // these should restrict to just the Q register variants, but the register
7381 // classes are enough to match correctly regardless, so we keep it simple
7382 // and just use MnemonicAlias.
7383 def : NEONMnemonicAlias<"vbicq", "vbic">;
7384 def : NEONMnemonicAlias<"vandq", "vand">;
7385 def : NEONMnemonicAlias<"veorq", "veor">;
7386 def : NEONMnemonicAlias<"vorrq", "vorr">;
7388 def : NEONMnemonicAlias<"vmovq", "vmov">;
7389 def : NEONMnemonicAlias<"vmvnq", "vmvn">;
7390 // Explicit versions for floating point so that the FPImm variants get
7391 // handled early. The parser gets confused otherwise.
7392 def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">;
7393 def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">;
7395 def : NEONMnemonicAlias<"vaddq", "vadd">;
7396 def : NEONMnemonicAlias<"vsubq", "vsub">;
7398 def : NEONMnemonicAlias<"vminq", "vmin">;
7399 def : NEONMnemonicAlias<"vmaxq", "vmax">;
7401 def : NEONMnemonicAlias<"vmulq", "vmul">;
7403 def : NEONMnemonicAlias<"vabsq", "vabs">;
7405 def : NEONMnemonicAlias<"vshlq", "vshl">;
7406 def : NEONMnemonicAlias<"vshrq", "vshr">;
7408 def : NEONMnemonicAlias<"vcvtq", "vcvt">;
7410 def : NEONMnemonicAlias<"vcleq", "vcle">;
7411 def : NEONMnemonicAlias<"vceqq", "vceq">;
7413 def : NEONMnemonicAlias<"vzipq", "vzip">;
7414 def : NEONMnemonicAlias<"vswpq", "vswp">;
7416 def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">;
7417 def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">;
7420 // Alias for loading floating point immediates that aren't representable
7421 // using the vmov.f32 encoding but the bitpattern is representable using
7422 // the .i32 encoding.
7423 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
7424 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
7425 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
7426 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;