1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
19 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
21 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
22 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
23 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
24 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
25 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
26 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
27 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
28 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
29 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
30 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
31 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
33 // Types for vector shift by immediates. The "SHX" version is for long and
34 // narrow operations where the source and destination vectors have different
35 // types. The "SHINS" version is for shift and insert operations.
36 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
38 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
40 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
43 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
44 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
45 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
46 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
47 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
48 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
49 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
51 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
52 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
53 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
55 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
56 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
57 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
58 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
59 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
60 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
62 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
63 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
64 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
66 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
67 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
69 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
71 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
72 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
74 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
75 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
76 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
78 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
80 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
81 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
83 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
85 // VDUPLANE can produce a quad-register result from a double-register source,
86 // so the result is not constrained to match the source.
87 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
88 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
91 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
92 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
93 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
95 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
96 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
97 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
98 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
100 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
102 SDTCisSameAs<0, 3>]>;
103 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
104 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
105 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
107 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
108 SDTCisSameAs<1, 2>]>;
109 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
110 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
112 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
113 SDTCisSameAs<0, 2>]>;
114 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
115 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
117 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
118 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
119 unsigned EltBits = 0;
120 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
121 return (EltBits == 32 && EltVal == 0);
124 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
125 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
126 unsigned EltBits = 0;
127 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
128 return (EltBits == 8 && EltVal == 0xff);
131 //===----------------------------------------------------------------------===//
132 // NEON operand definitions
133 //===----------------------------------------------------------------------===//
135 def nModImm : Operand<i32> {
136 let PrintMethod = "printNEONModImmOperand";
139 //===----------------------------------------------------------------------===//
140 // NEON load / store instructions
141 //===----------------------------------------------------------------------===//
143 // Use VLDM to load a Q register as a D register pair.
144 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
146 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
148 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
150 // Use VSTM to store a Q register as a D register pair.
151 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
153 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
155 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
157 // Classes for VLD* pseudo-instructions with multi-register operands.
158 // These are expanded to real instructions after register allocation.
159 class VLDQPseudo<InstrItinClass itin>
160 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
161 class VLDQWBPseudo<InstrItinClass itin>
162 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
163 (ins addrmode6:$addr, am6offset:$offset), itin,
165 class VLDQQPseudo<InstrItinClass itin>
166 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
167 class VLDQQWBPseudo<InstrItinClass itin>
168 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
169 (ins addrmode6:$addr, am6offset:$offset), itin,
171 class VLDQQQQPseudo<InstrItinClass itin>
172 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src), itin,"">;
173 class VLDQQQQWBPseudo<InstrItinClass itin>
174 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
175 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
176 "$addr.addr = $wb, $src = $dst">;
178 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
180 // VLD1 : Vector Load (multiple single elements)
181 class VLD1D<bits<4> op7_4, string Dt>
182 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd),
183 (ins addrmode6:$Rn), IIC_VLD1,
184 "vld1", Dt, "\\{$Vd\\}, $Rn", "", []> {
188 class VLD1Q<bits<4> op7_4, string Dt>
189 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2),
190 (ins addrmode6:$Rn), IIC_VLD1x2,
191 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
193 let Inst{5-4} = Rn{5-4};
196 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
197 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
198 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
199 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
201 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
202 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
203 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
204 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
206 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
207 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
208 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
209 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
211 // ...with address register writeback:
212 class VLD1DWB<bits<4> op7_4, string Dt>
213 : NLdSt<0,0b10,0b0111,op7_4, (outs DPR:$Vd, GPR:$wb),
214 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1u,
215 "vld1", Dt, "\\{$Vd\\}, $Rn$Rm",
216 "$Rn.addr = $wb", []> {
219 class VLD1QWB<bits<4> op7_4, string Dt>
220 : NLdSt<0,0b10,0b1010,op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
221 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x2u,
222 "vld1", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
223 "$Rn.addr = $wb", []> {
224 let Inst{5-4} = Rn{5-4};
227 def VLD1d8_UPD : VLD1DWB<{0,0,0,?}, "8">;
228 def VLD1d16_UPD : VLD1DWB<{0,1,0,?}, "16">;
229 def VLD1d32_UPD : VLD1DWB<{1,0,0,?}, "32">;
230 def VLD1d64_UPD : VLD1DWB<{1,1,0,?}, "64">;
232 def VLD1q8_UPD : VLD1QWB<{0,0,?,?}, "8">;
233 def VLD1q16_UPD : VLD1QWB<{0,1,?,?}, "16">;
234 def VLD1q32_UPD : VLD1QWB<{1,0,?,?}, "32">;
235 def VLD1q64_UPD : VLD1QWB<{1,1,?,?}, "64">;
237 def VLD1q8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
238 def VLD1q16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
239 def VLD1q32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
240 def VLD1q64Pseudo_UPD : VLDQWBPseudo<IIC_VLD1x2u>;
242 // ...with 3 registers (some of these are only for the disassembler):
243 class VLD1D3<bits<4> op7_4, string Dt>
244 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
245 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
246 "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
250 class VLD1D3WB<bits<4> op7_4, string Dt>
251 : NLdSt<0,0b10,0b0110,op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
252 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x3u, "vld1", Dt,
253 "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
257 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
258 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
259 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
260 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
262 def VLD1d8T_UPD : VLD1D3WB<{0,0,0,?}, "8">;
263 def VLD1d16T_UPD : VLD1D3WB<{0,1,0,?}, "16">;
264 def VLD1d32T_UPD : VLD1D3WB<{1,0,0,?}, "32">;
265 def VLD1d64T_UPD : VLD1D3WB<{1,1,0,?}, "64">;
267 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
268 def VLD1d64TPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x3u>;
270 // ...with 4 registers (some of these are only for the disassembler):
271 class VLD1D4<bits<4> op7_4, string Dt>
272 : NLdSt<0,0b10,0b0010,op7_4,(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
273 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
274 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
276 let Inst{5-4} = Rn{5-4};
278 class VLD1D4WB<bits<4> op7_4, string Dt>
279 : NLdSt<0,0b10,0b0010,op7_4,
280 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
281 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD1x4u, "vld1", Dt,
282 "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", "$Rn.addr = $wb",
284 let Inst{5-4} = Rn{5-4};
287 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
288 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
289 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
290 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
292 def VLD1d8Q_UPD : VLD1D4WB<{0,0,?,?}, "8">;
293 def VLD1d16Q_UPD : VLD1D4WB<{0,1,?,?}, "16">;
294 def VLD1d32Q_UPD : VLD1D4WB<{1,0,?,?}, "32">;
295 def VLD1d64Q_UPD : VLD1D4WB<{1,1,?,?}, "64">;
297 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
298 def VLD1d64QPseudo_UPD : VLDQQWBPseudo<IIC_VLD1x4u>;
300 // VLD2 : Vector Load (multiple 2-element structures)
301 class VLD2D<bits<4> op11_8, bits<4> op7_4, string Dt>
302 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
303 (ins addrmode6:$Rn), IIC_VLD2,
304 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn", "", []> {
306 let Inst{5-4} = Rn{5-4};
308 class VLD2Q<bits<4> op7_4, string Dt>
309 : NLdSt<0, 0b10, 0b0011, op7_4,
310 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
311 (ins addrmode6:$Rn), IIC_VLD2x2,
312 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
314 let Inst{5-4} = Rn{5-4};
317 def VLD2d8 : VLD2D<0b1000, {0,0,?,?}, "8">;
318 def VLD2d16 : VLD2D<0b1000, {0,1,?,?}, "16">;
319 def VLD2d32 : VLD2D<0b1000, {1,0,?,?}, "32">;
321 def VLD2q8 : VLD2Q<{0,0,?,?}, "8">;
322 def VLD2q16 : VLD2Q<{0,1,?,?}, "16">;
323 def VLD2q32 : VLD2Q<{1,0,?,?}, "32">;
325 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
326 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
327 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
329 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
330 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
331 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
333 // ...with address register writeback:
334 class VLD2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
335 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
336 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2u,
337 "vld2", Dt, "\\{$Vd, $dst2\\}, $Rn$Rm",
338 "$Rn.addr = $wb", []> {
339 let Inst{5-4} = Rn{5-4};
341 class VLD2QWB<bits<4> op7_4, string Dt>
342 : NLdSt<0, 0b10, 0b0011, op7_4,
343 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
344 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD2x2u,
345 "vld2", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
346 "$Rn.addr = $wb", []> {
347 let Inst{5-4} = Rn{5-4};
350 def VLD2d8_UPD : VLD2DWB<0b1000, {0,0,?,?}, "8">;
351 def VLD2d16_UPD : VLD2DWB<0b1000, {0,1,?,?}, "16">;
352 def VLD2d32_UPD : VLD2DWB<0b1000, {1,0,?,?}, "32">;
354 def VLD2q8_UPD : VLD2QWB<{0,0,?,?}, "8">;
355 def VLD2q16_UPD : VLD2QWB<{0,1,?,?}, "16">;
356 def VLD2q32_UPD : VLD2QWB<{1,0,?,?}, "32">;
358 def VLD2d8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
359 def VLD2d16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
360 def VLD2d32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2u>;
362 def VLD2q8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
363 def VLD2q16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
364 def VLD2q32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD2x2u>;
366 // ...with double-spaced registers (for disassembly only):
367 def VLD2b8 : VLD2D<0b1001, {0,0,?,?}, "8">;
368 def VLD2b16 : VLD2D<0b1001, {0,1,?,?}, "16">;
369 def VLD2b32 : VLD2D<0b1001, {1,0,?,?}, "32">;
370 def VLD2b8_UPD : VLD2DWB<0b1001, {0,0,?,?}, "8">;
371 def VLD2b16_UPD : VLD2DWB<0b1001, {0,1,?,?}, "16">;
372 def VLD2b32_UPD : VLD2DWB<0b1001, {1,0,?,?}, "32">;
374 // VLD3 : Vector Load (multiple 3-element structures)
375 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
376 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
377 (ins addrmode6:$Rn), IIC_VLD3,
378 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
383 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
384 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
385 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
387 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
388 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
389 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
391 // ...with address register writeback:
392 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
393 : NLdSt<0, 0b10, op11_8, op7_4,
394 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
395 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
396 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
397 "$Rn.addr = $wb", []> {
401 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
402 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
403 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
405 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
406 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
407 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
409 // ...with double-spaced registers:
410 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
411 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
412 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
413 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
414 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
415 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
417 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
418 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
419 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
421 // ...alternate versions to be allocated odd register numbers:
422 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
423 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
424 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
426 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
427 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
428 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
430 // VLD4 : Vector Load (multiple 4-element structures)
431 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
432 : NLdSt<0, 0b10, op11_8, op7_4,
433 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
434 (ins addrmode6:$Rn), IIC_VLD4,
435 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
437 let Inst{5-4} = Rn{5-4};
440 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
441 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
442 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
444 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
445 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
446 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
448 // ...with address register writeback:
449 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
450 : NLdSt<0, 0b10, op11_8, op7_4,
451 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
452 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
453 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
454 "$Rn.addr = $wb", []> {
455 let Inst{5-4} = Rn{5-4};
458 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
459 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
460 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
462 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
463 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
464 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
466 // ...with double-spaced registers:
467 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
468 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
469 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
470 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
471 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
472 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
474 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
475 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
476 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
478 // ...alternate versions to be allocated odd register numbers:
479 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
480 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
481 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
483 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
484 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
485 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
487 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
489 // Classes for VLD*LN pseudo-instructions with multi-register operands.
490 // These are expanded to real instructions after register allocation.
491 class VLDQLNPseudo<InstrItinClass itin>
492 : PseudoNLdSt<(outs QPR:$dst),
493 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
494 itin, "$src = $dst">;
495 class VLDQLNWBPseudo<InstrItinClass itin>
496 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
497 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
498 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
499 class VLDQQLNPseudo<InstrItinClass itin>
500 : PseudoNLdSt<(outs QQPR:$dst),
501 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
502 itin, "$src = $dst">;
503 class VLDQQLNWBPseudo<InstrItinClass itin>
504 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
505 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
506 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
507 class VLDQQQQLNPseudo<InstrItinClass itin>
508 : PseudoNLdSt<(outs QQQQPR:$dst),
509 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
510 itin, "$src = $dst">;
511 class VLDQQQQLNWBPseudo<InstrItinClass itin>
512 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
513 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
514 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
516 // VLD1LN : Vector Load (single element to one lane)
517 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
519 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
520 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
521 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
523 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
524 (i32 (LoadOp addrmode6:$Rn)),
528 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
529 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
530 (i32 (LoadOp addrmode6:$addr)),
534 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
535 let Inst{7-5} = lane{2-0};
537 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
538 let Inst{7-6} = lane{1-0};
541 def VLD1LNd32 : VLD1LN<0b1000, {?,0,?,?}, "32", v2i32, load> {
542 let Inst{7} = lane{0};
547 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
548 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
549 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
551 def : Pat<(vector_insert (v2f32 DPR:$src),
552 (f32 (load addrmode6:$addr)), imm:$lane),
553 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
554 def : Pat<(vector_insert (v4f32 QPR:$src),
555 (f32 (load addrmode6:$addr)), imm:$lane),
556 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
558 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
560 // ...with address register writeback:
561 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
562 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
563 (ins addrmode6:$Rn, am6offset:$Rm,
564 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
565 "\\{$Vd[$lane]\\}, $Rn$Rm",
566 "$src = $Vd, $Rn.addr = $wb", []>;
568 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
569 let Inst{7-5} = lane{2-0};
571 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
572 let Inst{7-6} = lane{1-0};
575 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
576 let Inst{7} = lane{0};
581 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
582 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
583 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
585 // VLD2LN : Vector Load (single 2-element structure to one lane)
586 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
587 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
588 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
589 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
590 "$src1 = $Vd, $src2 = $dst2", []> {
595 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
596 let Inst{7-5} = lane{2-0};
598 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
599 let Inst{7-6} = lane{1-0};
601 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
602 let Inst{7} = lane{0};
605 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
606 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
607 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
609 // ...with double-spaced registers:
610 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
611 let Inst{7-6} = lane{1-0};
613 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
614 let Inst{7} = lane{0};
617 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
618 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
620 // ...with address register writeback:
621 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
622 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
623 (ins addrmode6:$Rn, am6offset:$Rm,
624 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
625 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
626 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
630 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
631 let Inst{7-5} = lane{2-0};
633 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
634 let Inst{7-6} = lane{1-0};
636 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
637 let Inst{7} = lane{0};
640 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
641 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
642 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
644 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
645 let Inst{7-6} = lane{1-0};
647 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
648 let Inst{7} = lane{0};
651 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
652 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
654 // VLD3LN : Vector Load (single 3-element structure to one lane)
655 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
656 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
657 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
658 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
659 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
660 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
664 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
665 let Inst{7-5} = lane{2-0};
667 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
668 let Inst{7-6} = lane{1-0};
670 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
671 let Inst{7} = lane{0};
674 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
675 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
676 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
678 // ...with double-spaced registers:
679 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
680 let Inst{7-6} = lane{1-0};
682 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
683 let Inst{7} = lane{0};
686 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
687 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
689 // ...with address register writeback:
690 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
691 : NLdStLn<1, 0b10, op11_8, op7_4,
692 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
693 (ins addrmode6:$Rn, am6offset:$Rm,
694 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
695 IIC_VLD3lnu, "vld3", Dt,
696 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
697 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
700 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
701 let Inst{7-5} = lane{2-0};
703 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
704 let Inst{7-6} = lane{1-0};
706 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
707 let Inst{7} = lane{0};
710 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
711 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
712 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
714 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
715 let Inst{7-6} = lane{1-0};
717 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
718 let Inst{7} = lane{0};
721 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
722 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
724 // VLD4LN : Vector Load (single 4-element structure to one lane)
725 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
726 : NLdStLn<1, 0b10, op11_8, op7_4,
727 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
728 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
729 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
730 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
731 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
736 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
737 let Inst{7-5} = lane{2-0};
739 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
740 let Inst{7-6} = lane{1-0};
742 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
743 let Inst{7} = lane{0};
747 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
748 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
749 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
751 // ...with double-spaced registers:
752 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
753 let Inst{7-6} = lane{1-0};
755 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
756 let Inst{7} = lane{0};
760 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
761 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
763 // ...with address register writeback:
764 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
765 : NLdStLn<1, 0b10, op11_8, op7_4,
766 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
767 (ins addrmode6:$Rn, am6offset:$Rm,
768 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
769 IIC_VLD4lnu, "vld4", Dt,
770 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
771 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
776 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
777 let Inst{7-5} = lane{2-0};
779 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
780 let Inst{7-6} = lane{1-0};
782 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
783 let Inst{7} = lane{0};
787 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
788 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
789 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
791 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
792 let Inst{7-6} = lane{1-0};
794 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
795 let Inst{7} = lane{0};
799 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
800 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
802 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
804 // VLD1DUP : Vector Load (single element to all lanes)
805 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
806 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd), (ins addrmode6dup:$Rn),
807 IIC_VLD1dup, "vld1", Dt, "\\{$Vd[]\\}, $Rn", "",
808 [(set DPR:$Vd, (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
812 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
813 let Pattern = [(set QPR:$dst,
814 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
817 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
818 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
819 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
821 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
822 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
823 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
825 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
826 (VLD1DUPd32 addrmode6:$addr)>;
827 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
828 (VLD1DUPq32Pseudo addrmode6:$addr)>;
830 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
832 class VLD1QDUP<bits<4> op7_4, string Dt>
833 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2),
834 (ins addrmode6dup:$Rn), IIC_VLD1dup,
835 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
840 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
841 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
842 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
844 // ...with address register writeback:
845 class VLD1DUPWB<bits<4> op7_4, string Dt>
846 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, GPR:$wb),
847 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
848 "vld1", Dt, "\\{$Vd[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
851 class VLD1QDUPWB<bits<4> op7_4, string Dt>
852 : NLdSt<1, 0b10, 0b1100, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
853 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD1dupu,
854 "vld1", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
858 def VLD1DUPd8_UPD : VLD1DUPWB<{0,0,0,0}, "8">;
859 def VLD1DUPd16_UPD : VLD1DUPWB<{0,1,0,?}, "16">;
860 def VLD1DUPd32_UPD : VLD1DUPWB<{1,0,0,?}, "32">;
862 def VLD1DUPq8_UPD : VLD1QDUPWB<{0,0,1,0}, "8">;
863 def VLD1DUPq16_UPD : VLD1QDUPWB<{0,1,1,?}, "16">;
864 def VLD1DUPq32_UPD : VLD1QDUPWB<{1,0,1,?}, "32">;
866 def VLD1DUPq8Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
867 def VLD1DUPq16Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
868 def VLD1DUPq32Pseudo_UPD : VLDQWBPseudo<IIC_VLD1dupu>;
870 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
871 class VLD2DUP<bits<4> op7_4, string Dt>
872 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
873 (ins addrmode6dup:$Rn), IIC_VLD2dup,
874 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
879 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
880 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
881 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
883 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
884 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
885 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
887 // ...with double-spaced registers (not used for codegen):
888 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
889 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
890 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
892 // ...with address register writeback:
893 class VLD2DUPWB<bits<4> op7_4, string Dt>
894 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
895 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
896 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
900 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
901 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
902 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
904 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
905 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
906 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
908 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
909 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
910 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
912 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
913 class VLD3DUP<bits<4> op7_4, string Dt>
914 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
915 (ins addrmode6dup:$Rn), IIC_VLD3dup,
916 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
921 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
922 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
923 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
925 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
926 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
927 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
929 // ...with double-spaced registers (not used for codegen):
930 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
931 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
932 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
934 // ...with address register writeback:
935 class VLD3DUPWB<bits<4> op7_4, string Dt>
936 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
937 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
938 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
939 "$Rn.addr = $wb", []> {
943 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
944 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
945 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
947 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
948 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
949 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
951 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
952 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
953 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
955 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
956 class VLD4DUP<bits<4> op7_4, string Dt>
957 : NLdSt<1, 0b10, 0b1111, op7_4,
958 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
959 (ins addrmode6dup:$Rn), IIC_VLD4dup,
960 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
965 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
966 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
967 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
969 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
970 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
971 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
973 // ...with double-spaced registers (not used for codegen):
974 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
975 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
976 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
978 // ...with address register writeback:
979 class VLD4DUPWB<bits<4> op7_4, string Dt>
980 : NLdSt<1, 0b10, 0b1111, op7_4,
981 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
982 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
983 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
984 "$Rn.addr = $wb", []> {
988 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
989 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
990 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
992 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
993 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
994 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
996 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
997 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
998 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1000 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1002 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1004 // Classes for VST* pseudo-instructions with multi-register operands.
1005 // These are expanded to real instructions after register allocation.
1006 class VSTQPseudo<InstrItinClass itin>
1007 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1008 class VSTQWBPseudo<InstrItinClass itin>
1009 : PseudoNLdSt<(outs GPR:$wb),
1010 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1011 "$addr.addr = $wb">;
1012 class VSTQQPseudo<InstrItinClass itin>
1013 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1014 class VSTQQWBPseudo<InstrItinClass itin>
1015 : PseudoNLdSt<(outs GPR:$wb),
1016 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1017 "$addr.addr = $wb">;
1018 class VSTQQQQPseudo<InstrItinClass itin>
1019 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1020 class VSTQQQQWBPseudo<InstrItinClass itin>
1021 : PseudoNLdSt<(outs GPR:$wb),
1022 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1023 "$addr.addr = $wb">;
1025 // VST1 : Vector Store (multiple single elements)
1026 class VST1D<bits<4> op7_4, string Dt>
1027 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, DPR:$Vd),
1028 IIC_VST1, "vst1", Dt, "\\{$Vd\\}, $Rn", "", []> {
1030 let Inst{4} = Rn{4};
1032 class VST1Q<bits<4> op7_4, string Dt>
1033 : NLdSt<0,0b00,0b1010,op7_4, (outs),
1034 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2), IIC_VST1x2,
1035 "vst1", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1037 let Inst{5-4} = Rn{5-4};
1040 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1041 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1042 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1043 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1045 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1046 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1047 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1048 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1050 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1051 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1052 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1053 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1055 // ...with address register writeback:
1056 class VST1DWB<bits<4> op7_4, string Dt>
1057 : NLdSt<0, 0b00, 0b0111, op7_4, (outs GPR:$wb),
1058 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd), IIC_VST1u,
1059 "vst1", Dt, "\\{$Vd\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1060 let Inst{4} = Rn{4};
1062 class VST1QWB<bits<4> op7_4, string Dt>
1063 : NLdSt<0, 0b00, 0b1010, op7_4, (outs GPR:$wb),
1064 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1065 IIC_VST1x2u, "vst1", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1066 "$Rn.addr = $wb", []> {
1067 let Inst{5-4} = Rn{5-4};
1070 def VST1d8_UPD : VST1DWB<{0,0,0,?}, "8">;
1071 def VST1d16_UPD : VST1DWB<{0,1,0,?}, "16">;
1072 def VST1d32_UPD : VST1DWB<{1,0,0,?}, "32">;
1073 def VST1d64_UPD : VST1DWB<{1,1,0,?}, "64">;
1075 def VST1q8_UPD : VST1QWB<{0,0,?,?}, "8">;
1076 def VST1q16_UPD : VST1QWB<{0,1,?,?}, "16">;
1077 def VST1q32_UPD : VST1QWB<{1,0,?,?}, "32">;
1078 def VST1q64_UPD : VST1QWB<{1,1,?,?}, "64">;
1080 def VST1q8Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1081 def VST1q16Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1082 def VST1q32Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1083 def VST1q64Pseudo_UPD : VSTQWBPseudo<IIC_VST1x2u>;
1085 // ...with 3 registers (some of these are only for the disassembler):
1086 class VST1D3<bits<4> op7_4, string Dt>
1087 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1088 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3),
1089 IIC_VST1x3, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1091 let Inst{4} = Rn{4};
1093 class VST1D3WB<bits<4> op7_4, string Dt>
1094 : NLdSt<0, 0b00, 0b0110, op7_4, (outs GPR:$wb),
1095 (ins addrmode6:$Rn, am6offset:$Rm,
1096 DPR:$Vd, DPR:$src2, DPR:$src3),
1097 IIC_VST1x3u, "vst1", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1098 "$Rn.addr = $wb", []> {
1099 let Inst{4} = Rn{4};
1102 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1103 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1104 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1105 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1107 def VST1d8T_UPD : VST1D3WB<{0,0,0,?}, "8">;
1108 def VST1d16T_UPD : VST1D3WB<{0,1,0,?}, "16">;
1109 def VST1d32T_UPD : VST1D3WB<{1,0,0,?}, "32">;
1110 def VST1d64T_UPD : VST1D3WB<{1,1,0,?}, "64">;
1112 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1113 def VST1d64TPseudo_UPD : VSTQQWBPseudo<IIC_VST1x3u>;
1115 // ...with 4 registers (some of these are only for the disassembler):
1116 class VST1D4<bits<4> op7_4, string Dt>
1117 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1118 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1119 IIC_VST1x4, "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", "",
1122 let Inst{5-4} = Rn{5-4};
1124 class VST1D4WB<bits<4> op7_4, string Dt>
1125 : NLdSt<0, 0b00, 0b0010, op7_4, (outs GPR:$wb),
1126 (ins addrmode6:$Rn, am6offset:$Rm,
1127 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST1x4u,
1128 "vst1", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1129 "$Rn.addr = $wb", []> {
1130 let Inst{5-4} = Rn{5-4};
1133 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1134 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1135 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1136 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1138 def VST1d8Q_UPD : VST1D4WB<{0,0,?,?}, "8">;
1139 def VST1d16Q_UPD : VST1D4WB<{0,1,?,?}, "16">;
1140 def VST1d32Q_UPD : VST1D4WB<{1,0,?,?}, "32">;
1141 def VST1d64Q_UPD : VST1D4WB<{1,1,?,?}, "64">;
1143 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1144 def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
1146 // VST2 : Vector Store (multiple 2-element structures)
1147 class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
1148 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1149 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
1150 IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
1152 let Inst{5-4} = Rn{5-4};
1154 class VST2Q<bits<4> op7_4, string Dt>
1155 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1156 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1157 IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1160 let Inst{5-4} = Rn{5-4};
1163 def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
1164 def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
1165 def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
1167 def VST2q8 : VST2Q<{0,0,?,?}, "8">;
1168 def VST2q16 : VST2Q<{0,1,?,?}, "16">;
1169 def VST2q32 : VST2Q<{1,0,?,?}, "32">;
1171 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1172 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1173 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1175 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1176 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1177 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1179 // ...with address register writeback:
1180 class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1181 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1182 (ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
1183 IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
1184 "$Rn.addr = $wb", []> {
1185 let Inst{5-4} = Rn{5-4};
1187 class VST2QWB<bits<4> op7_4, string Dt>
1188 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1189 (ins addrmode6:$Rn, am6offset:$Rm,
1190 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
1191 "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1192 "$Rn.addr = $wb", []> {
1193 let Inst{5-4} = Rn{5-4};
1196 def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
1197 def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
1198 def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
1200 def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
1201 def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
1202 def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
1204 def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1205 def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1206 def VST2d32Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
1208 def VST2q8Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1209 def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1210 def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
1212 // ...with double-spaced registers (for disassembly only):
1213 def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
1214 def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
1215 def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
1216 def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
1217 def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
1218 def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
1220 // VST3 : Vector Store (multiple 3-element structures)
1221 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1222 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1223 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1224 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1226 let Inst{4} = Rn{4};
1229 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1230 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1231 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1233 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1234 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1235 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1237 // ...with address register writeback:
1238 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1239 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1240 (ins addrmode6:$Rn, am6offset:$Rm,
1241 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1242 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1243 "$Rn.addr = $wb", []> {
1244 let Inst{4} = Rn{4};
1247 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1248 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1249 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1251 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1252 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1253 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1255 // ...with double-spaced registers:
1256 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1257 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1258 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1259 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1260 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1261 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1263 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1264 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1265 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1267 // ...alternate versions to be allocated odd register numbers:
1268 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1269 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1270 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1272 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1273 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1274 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1276 // VST4 : Vector Store (multiple 4-element structures)
1277 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1278 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1279 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1280 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1283 let Inst{5-4} = Rn{5-4};
1286 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1287 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1288 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1290 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1291 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1292 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1294 // ...with address register writeback:
1295 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1296 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1297 (ins addrmode6:$Rn, am6offset:$Rm,
1298 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1299 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1300 "$Rn.addr = $wb", []> {
1301 let Inst{5-4} = Rn{5-4};
1304 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1305 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1306 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1308 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1309 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1310 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1312 // ...with double-spaced registers:
1313 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1314 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1315 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1316 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1317 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1318 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1320 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1321 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1322 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1324 // ...alternate versions to be allocated odd register numbers:
1325 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1326 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1327 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1329 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1330 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1331 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1333 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1335 // Classes for VST*LN pseudo-instructions with multi-register operands.
1336 // These are expanded to real instructions after register allocation.
1337 class VSTQLNPseudo<InstrItinClass itin>
1338 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1340 class VSTQLNWBPseudo<InstrItinClass itin>
1341 : PseudoNLdSt<(outs GPR:$wb),
1342 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1343 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1344 class VSTQQLNPseudo<InstrItinClass itin>
1345 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1347 class VSTQQLNWBPseudo<InstrItinClass itin>
1348 : PseudoNLdSt<(outs GPR:$wb),
1349 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1350 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1351 class VSTQQQQLNPseudo<InstrItinClass itin>
1352 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1354 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1355 : PseudoNLdSt<(outs GPR:$wb),
1356 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1357 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1359 // VST1LN : Vector Store (single element from one lane)
1360 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1361 PatFrag StoreOp, SDNode ExtractOp>
1362 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1363 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1364 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1365 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1368 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1369 : VSTQLNPseudo<IIC_VST1ln> {
1370 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1374 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1376 let Inst{7-5} = lane{2-0};
1378 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1380 let Inst{7-6} = lane{1-0};
1381 let Inst{4} = Rn{5};
1383 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1384 let Inst{7} = lane{0};
1385 let Inst{5-4} = Rn{5-4};
1388 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1389 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1390 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1392 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1393 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1394 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1395 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1397 // ...with address register writeback:
1398 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1399 PatFrag StoreOp, SDNode ExtractOp>
1400 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1401 (ins addrmode6:$Rn, am6offset:$Rm,
1402 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1403 "\\{$Vd[$lane]\\}, $Rn$Rm",
1405 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1406 addrmode6:$Rn, am6offset:$Rm))]>;
1407 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1408 : VSTQLNWBPseudo<IIC_VST1lnu> {
1409 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1410 addrmode6:$addr, am6offset:$offset))];
1413 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
1415 let Inst{7-5} = lane{2-0};
1417 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
1419 let Inst{7-6} = lane{1-0};
1420 let Inst{4} = Rn{5};
1422 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
1424 let Inst{7} = lane{0};
1425 let Inst{5-4} = Rn{5-4};
1428 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
1429 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
1430 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
1432 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1434 // VST2LN : Vector Store (single 2-element structure from one lane)
1435 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1436 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1437 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1438 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1441 let Inst{4} = Rn{4};
1444 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1445 let Inst{7-5} = lane{2-0};
1447 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1448 let Inst{7-6} = lane{1-0};
1450 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1451 let Inst{7} = lane{0};
1454 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1455 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1456 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1458 // ...with double-spaced registers:
1459 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1460 let Inst{7-6} = lane{1-0};
1461 let Inst{4} = Rn{4};
1463 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1464 let Inst{7} = lane{0};
1465 let Inst{4} = Rn{4};
1468 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1469 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1471 // ...with address register writeback:
1472 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1473 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1474 (ins addrmode6:$addr, am6offset:$offset,
1475 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1476 "\\{$src1[$lane], $src2[$lane]\\}, $addr$offset",
1477 "$addr.addr = $wb", []> {
1478 let Inst{4} = Rn{4};
1481 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1482 let Inst{7-5} = lane{2-0};
1484 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1485 let Inst{7-6} = lane{1-0};
1487 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1488 let Inst{7} = lane{0};
1491 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1492 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1493 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1495 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1496 let Inst{7-6} = lane{1-0};
1498 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1499 let Inst{7} = lane{0};
1502 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1503 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1505 // VST3LN : Vector Store (single 3-element structure from one lane)
1506 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1507 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1508 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1509 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1510 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1514 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1515 let Inst{7-5} = lane{2-0};
1517 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1518 let Inst{7-6} = lane{1-0};
1520 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1521 let Inst{7} = lane{0};
1524 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1525 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1526 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1528 // ...with double-spaced registers:
1529 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1530 let Inst{7-6} = lane{1-0};
1532 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1533 let Inst{7} = lane{0};
1536 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1537 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1539 // ...with address register writeback:
1540 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1541 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1542 (ins addrmode6:$Rn, am6offset:$Rm,
1543 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1544 IIC_VST3lnu, "vst3", Dt,
1545 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1546 "$Rn.addr = $wb", []>;
1548 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1549 let Inst{7-5} = lane{2-0};
1551 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
1552 let Inst{7-6} = lane{1-0};
1554 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
1555 let Inst{7} = lane{0};
1558 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1559 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1560 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
1562 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
1563 let Inst{7-6} = lane{1-0};
1565 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
1566 let Inst{7} = lane{0};
1569 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1570 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
1572 // VST4LN : Vector Store (single 4-element structure from one lane)
1573 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1574 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1575 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
1576 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
1577 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
1580 let Inst{4} = Rn{4};
1583 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1584 let Inst{7-5} = lane{2-0};
1586 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
1587 let Inst{7-6} = lane{1-0};
1589 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
1590 let Inst{7} = lane{0};
1591 let Inst{5} = Rn{5};
1594 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1595 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1596 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
1598 // ...with double-spaced registers:
1599 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
1600 let Inst{7-6} = lane{1-0};
1602 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
1603 let Inst{7} = lane{0};
1604 let Inst{5} = Rn{5};
1607 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1608 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
1610 // ...with address register writeback:
1611 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1612 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1613 (ins addrmode6:$Rn, am6offset:$Rm,
1614 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1615 IIC_VST4lnu, "vst4", Dt,
1616 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
1617 "$Rn.addr = $wb", []> {
1618 let Inst{4} = Rn{4};
1621 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
1622 let Inst{7-5} = lane{2-0};
1624 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
1625 let Inst{7-6} = lane{1-0};
1627 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
1628 let Inst{7} = lane{0};
1629 let Inst{5} = Rn{5};
1632 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1633 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1634 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
1636 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
1637 let Inst{7-6} = lane{1-0};
1639 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
1640 let Inst{7} = lane{0};
1641 let Inst{5} = Rn{5};
1644 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1645 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
1647 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1650 //===----------------------------------------------------------------------===//
1651 // NEON pattern fragments
1652 //===----------------------------------------------------------------------===//
1654 // Extract D sub-registers of Q registers.
1655 def DSubReg_i8_reg : SDNodeXForm<imm, [{
1656 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1657 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
1659 def DSubReg_i16_reg : SDNodeXForm<imm, [{
1660 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1661 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
1663 def DSubReg_i32_reg : SDNodeXForm<imm, [{
1664 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1665 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
1667 def DSubReg_f64_reg : SDNodeXForm<imm, [{
1668 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1669 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
1672 // Extract S sub-registers of Q/D registers.
1673 def SSubReg_f32_reg : SDNodeXForm<imm, [{
1674 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
1675 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
1678 // Translate lane numbers from Q registers to D subregs.
1679 def SubReg_i8_lane : SDNodeXForm<imm, [{
1680 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
1682 def SubReg_i16_lane : SDNodeXForm<imm, [{
1683 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
1685 def SubReg_i32_lane : SDNodeXForm<imm, [{
1686 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
1689 //===----------------------------------------------------------------------===//
1690 // Instruction Classes
1691 //===----------------------------------------------------------------------===//
1693 // Basic 2-register operations: double- and quad-register.
1694 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1695 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1696 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1697 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1698 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
1699 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1700 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1701 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
1702 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
1703 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1704 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
1705 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1707 // Basic 2-register intrinsics, both double- and quad-register.
1708 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1709 bits<2> op17_16, bits<5> op11_7, bit op4,
1710 InstrItinClass itin, string OpcodeStr, string Dt,
1711 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1712 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
1713 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1714 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1715 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1716 bits<2> op17_16, bits<5> op11_7, bit op4,
1717 InstrItinClass itin, string OpcodeStr, string Dt,
1718 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1719 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
1720 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1721 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1723 // Narrow 2-register operations.
1724 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1725 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1726 InstrItinClass itin, string OpcodeStr, string Dt,
1727 ValueType TyD, ValueType TyQ, SDNode OpNode>
1728 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1729 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1730 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
1732 // Narrow 2-register intrinsics.
1733 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1734 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1735 InstrItinClass itin, string OpcodeStr, string Dt,
1736 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
1737 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
1738 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1739 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
1741 // Long 2-register operations (currently only used for VMOVL).
1742 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1743 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1744 InstrItinClass itin, string OpcodeStr, string Dt,
1745 ValueType TyQ, ValueType TyD, SDNode OpNode>
1746 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1747 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1748 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
1750 // Long 2-register intrinsics.
1751 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
1752 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
1753 InstrItinClass itin, string OpcodeStr, string Dt,
1754 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
1755 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
1756 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1757 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
1759 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
1760 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
1761 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
1762 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
1763 OpcodeStr, Dt, "$Vd, $Vm",
1764 "$src1 = $Vd, $src2 = $Vm", []>;
1765 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
1766 InstrItinClass itin, string OpcodeStr, string Dt>
1767 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
1768 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
1769 "$src1 = $Vd, $src2 = $Vm", []>;
1771 // Basic 3-register operations: double- and quad-register.
1772 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1773 InstrItinClass itin, string OpcodeStr, string Dt,
1774 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1775 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1776 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1777 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1778 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1779 let isCommutable = Commutable;
1781 // Same as N3VD but no data type.
1782 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1783 InstrItinClass itin, string OpcodeStr,
1784 ValueType ResTy, ValueType OpTy,
1785 SDNode OpNode, bit Commutable>
1786 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
1787 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1788 OpcodeStr, "$Vd, $Vn, $Vm", "",
1789 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
1790 let isCommutable = Commutable;
1793 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
1794 InstrItinClass itin, string OpcodeStr, string Dt,
1795 ValueType Ty, SDNode ShOp>
1796 : N3V<0, 1, op21_20, op11_8, 1, 0,
1797 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1798 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1800 (Ty (ShOp (Ty DPR:$Vn),
1801 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
1802 let isCommutable = 0;
1804 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
1805 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
1806 : N3V<0, 1, op21_20, op11_8, 1, 0,
1807 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1808 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1810 (Ty (ShOp (Ty DPR:$Vn),
1811 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1812 let isCommutable = 0;
1815 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1816 InstrItinClass itin, string OpcodeStr, string Dt,
1817 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1818 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1819 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1820 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1821 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1822 let isCommutable = Commutable;
1824 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1825 InstrItinClass itin, string OpcodeStr,
1826 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
1827 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
1828 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1829 OpcodeStr, "$Vd, $Vn, $Vm", "",
1830 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
1831 let isCommutable = Commutable;
1833 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
1834 InstrItinClass itin, string OpcodeStr, string Dt,
1835 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1836 : N3V<1, 1, op21_20, op11_8, 1, 0,
1837 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1838 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1839 [(set (ResTy QPR:$Vd),
1840 (ResTy (ShOp (ResTy QPR:$Vn),
1841 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1843 let isCommutable = 0;
1845 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
1846 ValueType ResTy, ValueType OpTy, SDNode ShOp>
1847 : N3V<1, 1, op21_20, op11_8, 1, 0,
1848 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1849 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm[$lane]","",
1850 [(set (ResTy QPR:$Vd),
1851 (ResTy (ShOp (ResTy QPR:$Vn),
1852 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1854 let isCommutable = 0;
1857 // Basic 3-register intrinsics, both double- and quad-register.
1858 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1859 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1860 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1861 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1862 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
1863 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1864 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
1865 let isCommutable = Commutable;
1867 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1868 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1869 : N3V<0, 1, op21_20, op11_8, 1, 0,
1870 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1871 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1873 (Ty (IntOp (Ty DPR:$Vn),
1874 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
1876 let isCommutable = 0;
1878 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1879 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
1880 : N3V<0, 1, op21_20, op11_8, 1, 0,
1881 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1882 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1884 (Ty (IntOp (Ty DPR:$Vn),
1885 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
1886 let isCommutable = 0;
1888 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1889 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1890 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1891 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1892 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
1893 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1894 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
1895 let isCommutable = 0;
1898 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1899 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1900 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
1901 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1902 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
1903 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
1904 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
1905 let isCommutable = Commutable;
1907 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1908 string OpcodeStr, string Dt,
1909 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1910 : N3V<1, 1, op21_20, op11_8, 1, 0,
1911 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1912 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1913 [(set (ResTy QPR:$Vd),
1914 (ResTy (IntOp (ResTy QPR:$Vn),
1915 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1917 let isCommutable = 0;
1919 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1920 string OpcodeStr, string Dt,
1921 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1922 : N3V<1, 1, op21_20, op11_8, 1, 0,
1923 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1924 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
1925 [(set (ResTy QPR:$Vd),
1926 (ResTy (IntOp (ResTy QPR:$Vn),
1927 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
1929 let isCommutable = 0;
1931 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1932 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
1933 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
1934 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1935 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
1936 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
1937 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
1938 let isCommutable = 0;
1941 // Multiply-Add/Sub operations: double- and quad-register.
1942 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1943 InstrItinClass itin, string OpcodeStr, string Dt,
1944 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
1945 : N3V<op24, op23, op21_20, op11_8, 0, op4,
1946 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
1947 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1948 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
1949 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
1951 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1952 string OpcodeStr, string Dt,
1953 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
1954 : N3V<0, 1, op21_20, op11_8, 1, 0,
1956 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1958 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1960 (Ty (ShOp (Ty DPR:$src1),
1962 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
1964 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1965 string OpcodeStr, string Dt,
1966 ValueType Ty, SDNode MulOp, SDNode ShOp>
1967 : N3V<0, 1, op21_20, op11_8, 1, 0,
1969 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
1971 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1973 (Ty (ShOp (Ty DPR:$src1),
1975 (Ty (NEONvduplane (Ty DPR_8:$Vm),
1978 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
1979 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
1980 SDPatternOperator MulOp, SDPatternOperator OpNode>
1981 : N3V<op24, op23, op21_20, op11_8, 1, op4,
1982 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
1983 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
1984 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
1985 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
1986 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
1987 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
1988 SDPatternOperator MulOp, SDPatternOperator ShOp>
1989 : N3V<1, 1, op21_20, op11_8, 1, 0,
1991 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
1993 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
1994 [(set (ResTy QPR:$Vd),
1995 (ResTy (ShOp (ResTy QPR:$src1),
1996 (ResTy (MulOp QPR:$Vn,
1997 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
1999 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2000 string OpcodeStr, string Dt,
2001 ValueType ResTy, ValueType OpTy,
2002 SDNode MulOp, SDNode ShOp>
2003 : N3V<1, 1, op21_20, op11_8, 1, 0,
2005 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2007 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2008 [(set (ResTy QPR:$Vd),
2009 (ResTy (ShOp (ResTy QPR:$src1),
2010 (ResTy (MulOp QPR:$Vn,
2011 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2014 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2015 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2016 InstrItinClass itin, string OpcodeStr, string Dt,
2017 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2018 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2019 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2020 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2021 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2022 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2023 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2024 InstrItinClass itin, string OpcodeStr, string Dt,
2025 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2026 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2027 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2028 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2029 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2030 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2032 // Neon 3-argument intrinsics, both double- and quad-register.
2033 // The destination register is also used as the first source operand register.
2034 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2035 InstrItinClass itin, string OpcodeStr, string Dt,
2036 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2037 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2038 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2039 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2040 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2041 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2042 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2043 InstrItinClass itin, string OpcodeStr, string Dt,
2044 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2045 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2046 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2047 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2048 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2049 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2051 // Long Multiply-Add/Sub operations.
2052 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2053 InstrItinClass itin, string OpcodeStr, string Dt,
2054 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2055 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2056 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2057 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2058 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2059 (TyQ (MulOp (TyD DPR:$Vn),
2060 (TyD DPR:$Vm)))))]>;
2061 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2062 InstrItinClass itin, string OpcodeStr, string Dt,
2063 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2064 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2065 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2067 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2069 (OpNode (TyQ QPR:$src1),
2070 (TyQ (MulOp (TyD DPR:$Vn),
2071 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2073 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2074 InstrItinClass itin, string OpcodeStr, string Dt,
2075 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2076 : N3V<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2077 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2079 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2081 (OpNode (TyQ QPR:$src1),
2082 (TyQ (MulOp (TyD DPR:$Vn),
2083 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2086 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2087 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2088 InstrItinClass itin, string OpcodeStr, string Dt,
2089 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2091 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2092 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2093 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2094 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2095 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2096 (TyD DPR:$Vm)))))))]>;
2098 // Neon Long 3-argument intrinsic. The destination register is
2099 // a quad-register and is also used as the first source operand register.
2100 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2101 InstrItinClass itin, string OpcodeStr, string Dt,
2102 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2103 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2104 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2105 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2107 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2108 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2109 string OpcodeStr, string Dt,
2110 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2111 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2113 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2115 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2116 [(set (ResTy QPR:$Vd),
2117 (ResTy (IntOp (ResTy QPR:$src1),
2119 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2121 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2122 InstrItinClass itin, string OpcodeStr, string Dt,
2123 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2124 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2126 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2128 OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
2129 [(set (ResTy QPR:$Vd),
2130 (ResTy (IntOp (ResTy QPR:$src1),
2132 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2135 // Narrowing 3-register intrinsics.
2136 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2137 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2138 Intrinsic IntOp, bit Commutable>
2139 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2140 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2141 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2142 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2143 let isCommutable = Commutable;
2146 // Long 3-register operations.
2147 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2148 InstrItinClass itin, string OpcodeStr, string Dt,
2149 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2150 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2151 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2152 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2153 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2154 let isCommutable = Commutable;
2156 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2157 InstrItinClass itin, string OpcodeStr, string Dt,
2158 ValueType TyQ, ValueType TyD, SDNode OpNode>
2159 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2160 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2161 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2163 (TyQ (OpNode (TyD DPR:$Vn),
2164 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2165 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2166 InstrItinClass itin, string OpcodeStr, string Dt,
2167 ValueType TyQ, ValueType TyD, SDNode OpNode>
2168 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2169 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2170 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2172 (TyQ (OpNode (TyD DPR:$Vn),
2173 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2175 // Long 3-register operations with explicitly extended operands.
2176 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2177 InstrItinClass itin, string OpcodeStr, string Dt,
2178 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2180 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2181 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2182 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2183 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2184 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2185 let isCommutable = Commutable;
2188 // Long 3-register intrinsics with explicit extend (VABDL).
2189 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2190 InstrItinClass itin, string OpcodeStr, string Dt,
2191 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2193 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2194 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2195 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2196 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2197 (TyD DPR:$Vm))))))]> {
2198 let isCommutable = Commutable;
2201 // Long 3-register intrinsics.
2202 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2203 InstrItinClass itin, string OpcodeStr, string Dt,
2204 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2205 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2206 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2207 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2208 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2209 let isCommutable = Commutable;
2211 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2212 string OpcodeStr, string Dt,
2213 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2214 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2215 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
2216 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2217 [(set (ResTy QPR:$Vd),
2218 (ResTy (IntOp (OpTy DPR:$Vn),
2219 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2221 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2222 InstrItinClass itin, string OpcodeStr, string Dt,
2223 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2224 : N3V<op24, 1, op21_20, op11_8, 1, 0,
2225 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
2226 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "",
2227 [(set (ResTy QPR:$Vd),
2228 (ResTy (IntOp (OpTy DPR:$Vn),
2229 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2232 // Wide 3-register operations.
2233 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2234 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2235 SDNode OpNode, SDNode ExtOp, bit Commutable>
2236 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2237 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2238 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2239 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2240 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2241 let isCommutable = Commutable;
2244 // Pairwise long 2-register intrinsics, both double- and quad-register.
2245 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2246 bits<2> op17_16, bits<5> op11_7, bit op4,
2247 string OpcodeStr, string Dt,
2248 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2249 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2250 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2251 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2252 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2253 bits<2> op17_16, bits<5> op11_7, bit op4,
2254 string OpcodeStr, string Dt,
2255 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2256 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2257 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2258 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2260 // Pairwise long 2-register accumulate intrinsics,
2261 // both double- and quad-register.
2262 // The destination register is also used as the first source operand register.
2263 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2264 bits<2> op17_16, bits<5> op11_7, bit op4,
2265 string OpcodeStr, string Dt,
2266 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2267 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2268 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2269 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2270 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2271 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2272 bits<2> op17_16, bits<5> op11_7, bit op4,
2273 string OpcodeStr, string Dt,
2274 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2275 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2276 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2277 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2278 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2280 // Shift by immediate,
2281 // both double- and quad-register.
2282 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2283 Format f, InstrItinClass itin, Operand ImmTy,
2284 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2285 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2286 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2287 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2288 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2289 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2290 Format f, InstrItinClass itin, Operand ImmTy,
2291 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2292 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2293 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2294 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2295 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2297 // Long shift by immediate.
2298 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2299 string OpcodeStr, string Dt,
2300 ValueType ResTy, ValueType OpTy, SDNode OpNode>
2301 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2302 (outs QPR:$Vd), (ins DPR:$Vm, i32imm:$SIMM), N2RegVShLFrm,
2303 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2304 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2305 (i32 imm:$SIMM))))]>;
2307 // Narrow shift by immediate.
2308 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2309 InstrItinClass itin, string OpcodeStr, string Dt,
2310 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2311 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2312 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2313 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2314 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2315 (i32 imm:$SIMM))))]>;
2317 // Shift right by immediate and accumulate,
2318 // both double- and quad-register.
2319 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2320 Operand ImmTy, string OpcodeStr, string Dt,
2321 ValueType Ty, SDNode ShOp>
2322 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2323 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2324 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2325 [(set DPR:$Vd, (Ty (add DPR:$src1,
2326 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2327 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2328 Operand ImmTy, string OpcodeStr, string Dt,
2329 ValueType Ty, SDNode ShOp>
2330 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2331 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2332 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2333 [(set QPR:$Vd, (Ty (add QPR:$src1,
2334 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2336 // Shift by immediate and insert,
2337 // both double- and quad-register.
2338 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2339 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2340 ValueType Ty,SDNode ShOp>
2341 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2342 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2343 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2344 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2345 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2346 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2347 ValueType Ty,SDNode ShOp>
2348 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2349 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2350 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2351 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2353 // Convert, with fractional bits immediate,
2354 // both double- and quad-register.
2355 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2356 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2358 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2359 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2360 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2361 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2362 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2363 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2365 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2366 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2367 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2368 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2370 //===----------------------------------------------------------------------===//
2372 //===----------------------------------------------------------------------===//
2374 // Abbreviations used in multiclass suffixes:
2375 // Q = quarter int (8 bit) elements
2376 // H = half int (16 bit) elements
2377 // S = single int (32 bit) elements
2378 // D = double int (64 bit) elements
2380 // Neon 2-register vector operations and intrinsics.
2382 // Neon 2-register comparisons.
2383 // source operand element sizes of 8, 16 and 32 bits:
2384 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2385 bits<5> op11_7, bit op4, string opc, string Dt,
2386 string asm, SDNode OpNode> {
2387 // 64-bit vector types.
2388 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2389 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2390 opc, !strconcat(Dt, "8"), asm, "",
2391 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2392 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2393 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2394 opc, !strconcat(Dt, "16"), asm, "",
2395 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2396 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2397 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2398 opc, !strconcat(Dt, "32"), asm, "",
2399 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2400 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2401 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2402 opc, "f32", asm, "",
2403 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2404 let Inst{10} = 1; // overwrite F = 1
2407 // 128-bit vector types.
2408 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2409 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2410 opc, !strconcat(Dt, "8"), asm, "",
2411 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2412 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2413 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2414 opc, !strconcat(Dt, "16"), asm, "",
2415 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2416 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2417 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2418 opc, !strconcat(Dt, "32"), asm, "",
2419 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2420 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2421 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2422 opc, "f32", asm, "",
2423 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2424 let Inst{10} = 1; // overwrite F = 1
2429 // Neon 2-register vector intrinsics,
2430 // element sizes of 8, 16 and 32 bits:
2431 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2432 bits<5> op11_7, bit op4,
2433 InstrItinClass itinD, InstrItinClass itinQ,
2434 string OpcodeStr, string Dt, Intrinsic IntOp> {
2435 // 64-bit vector types.
2436 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2437 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2438 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2439 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2440 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2441 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2443 // 128-bit vector types.
2444 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2445 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2446 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2447 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2448 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2449 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2453 // Neon Narrowing 2-register vector operations,
2454 // source operand element sizes of 16, 32 and 64 bits:
2455 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2456 bits<5> op11_7, bit op6, bit op4,
2457 InstrItinClass itin, string OpcodeStr, string Dt,
2459 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2460 itin, OpcodeStr, !strconcat(Dt, "16"),
2461 v8i8, v8i16, OpNode>;
2462 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2463 itin, OpcodeStr, !strconcat(Dt, "32"),
2464 v4i16, v4i32, OpNode>;
2465 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2466 itin, OpcodeStr, !strconcat(Dt, "64"),
2467 v2i32, v2i64, OpNode>;
2470 // Neon Narrowing 2-register vector intrinsics,
2471 // source operand element sizes of 16, 32 and 64 bits:
2472 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2473 bits<5> op11_7, bit op6, bit op4,
2474 InstrItinClass itin, string OpcodeStr, string Dt,
2476 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2477 itin, OpcodeStr, !strconcat(Dt, "16"),
2478 v8i8, v8i16, IntOp>;
2479 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2480 itin, OpcodeStr, !strconcat(Dt, "32"),
2481 v4i16, v4i32, IntOp>;
2482 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2483 itin, OpcodeStr, !strconcat(Dt, "64"),
2484 v2i32, v2i64, IntOp>;
2488 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2489 // source operand element sizes of 16, 32 and 64 bits:
2490 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2491 string OpcodeStr, string Dt, SDNode OpNode> {
2492 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2493 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2494 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2495 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2496 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2497 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2501 // Neon 3-register vector operations.
2503 // First with only element sizes of 8, 16 and 32 bits:
2504 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2505 InstrItinClass itinD16, InstrItinClass itinD32,
2506 InstrItinClass itinQ16, InstrItinClass itinQ32,
2507 string OpcodeStr, string Dt,
2508 SDNode OpNode, bit Commutable = 0> {
2509 // 64-bit vector types.
2510 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2511 OpcodeStr, !strconcat(Dt, "8"),
2512 v8i8, v8i8, OpNode, Commutable>;
2513 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2514 OpcodeStr, !strconcat(Dt, "16"),
2515 v4i16, v4i16, OpNode, Commutable>;
2516 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2517 OpcodeStr, !strconcat(Dt, "32"),
2518 v2i32, v2i32, OpNode, Commutable>;
2520 // 128-bit vector types.
2521 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2522 OpcodeStr, !strconcat(Dt, "8"),
2523 v16i8, v16i8, OpNode, Commutable>;
2524 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2525 OpcodeStr, !strconcat(Dt, "16"),
2526 v8i16, v8i16, OpNode, Commutable>;
2527 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2528 OpcodeStr, !strconcat(Dt, "32"),
2529 v4i32, v4i32, OpNode, Commutable>;
2532 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, string Dt, SDNode ShOp> {
2533 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2535 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, !strconcat(Dt,"32"),
2537 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, !strconcat(Dt, "16"),
2538 v8i16, v4i16, ShOp>;
2539 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, !strconcat(Dt,"32"),
2540 v4i32, v2i32, ShOp>;
2543 // ....then also with element size 64 bits:
2544 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2545 InstrItinClass itinD, InstrItinClass itinQ,
2546 string OpcodeStr, string Dt,
2547 SDNode OpNode, bit Commutable = 0>
2548 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2549 OpcodeStr, Dt, OpNode, Commutable> {
2550 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2551 OpcodeStr, !strconcat(Dt, "64"),
2552 v1i64, v1i64, OpNode, Commutable>;
2553 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
2554 OpcodeStr, !strconcat(Dt, "64"),
2555 v2i64, v2i64, OpNode, Commutable>;
2559 // Neon 3-register vector intrinsics.
2561 // First with only element sizes of 16 and 32 bits:
2562 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2563 InstrItinClass itinD16, InstrItinClass itinD32,
2564 InstrItinClass itinQ16, InstrItinClass itinQ32,
2565 string OpcodeStr, string Dt,
2566 Intrinsic IntOp, bit Commutable = 0> {
2567 // 64-bit vector types.
2568 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
2569 OpcodeStr, !strconcat(Dt, "16"),
2570 v4i16, v4i16, IntOp, Commutable>;
2571 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
2572 OpcodeStr, !strconcat(Dt, "32"),
2573 v2i32, v2i32, IntOp, Commutable>;
2575 // 128-bit vector types.
2576 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2577 OpcodeStr, !strconcat(Dt, "16"),
2578 v8i16, v8i16, IntOp, Commutable>;
2579 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2580 OpcodeStr, !strconcat(Dt, "32"),
2581 v4i32, v4i32, IntOp, Commutable>;
2583 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2584 InstrItinClass itinD16, InstrItinClass itinD32,
2585 InstrItinClass itinQ16, InstrItinClass itinQ32,
2586 string OpcodeStr, string Dt,
2588 // 64-bit vector types.
2589 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
2590 OpcodeStr, !strconcat(Dt, "16"),
2591 v4i16, v4i16, IntOp>;
2592 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
2593 OpcodeStr, !strconcat(Dt, "32"),
2594 v2i32, v2i32, IntOp>;
2596 // 128-bit vector types.
2597 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
2598 OpcodeStr, !strconcat(Dt, "16"),
2599 v8i16, v8i16, IntOp>;
2600 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
2601 OpcodeStr, !strconcat(Dt, "32"),
2602 v4i32, v4i32, IntOp>;
2605 multiclass N3VIntSL_HS<bits<4> op11_8,
2606 InstrItinClass itinD16, InstrItinClass itinD32,
2607 InstrItinClass itinQ16, InstrItinClass itinQ32,
2608 string OpcodeStr, string Dt, Intrinsic IntOp> {
2609 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
2610 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
2611 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
2612 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
2613 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
2614 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
2615 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
2616 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
2619 // ....then also with element size of 8 bits:
2620 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2621 InstrItinClass itinD16, InstrItinClass itinD32,
2622 InstrItinClass itinQ16, InstrItinClass itinQ32,
2623 string OpcodeStr, string Dt,
2624 Intrinsic IntOp, bit Commutable = 0>
2625 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2626 OpcodeStr, Dt, IntOp, Commutable> {
2627 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
2628 OpcodeStr, !strconcat(Dt, "8"),
2629 v8i8, v8i8, IntOp, Commutable>;
2630 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2631 OpcodeStr, !strconcat(Dt, "8"),
2632 v16i8, v16i8, IntOp, Commutable>;
2634 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2635 InstrItinClass itinD16, InstrItinClass itinD32,
2636 InstrItinClass itinQ16, InstrItinClass itinQ32,
2637 string OpcodeStr, string Dt,
2639 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2640 OpcodeStr, Dt, IntOp> {
2641 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
2642 OpcodeStr, !strconcat(Dt, "8"),
2644 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
2645 OpcodeStr, !strconcat(Dt, "8"),
2646 v16i8, v16i8, IntOp>;
2650 // ....then also with element size of 64 bits:
2651 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2652 InstrItinClass itinD16, InstrItinClass itinD32,
2653 InstrItinClass itinQ16, InstrItinClass itinQ32,
2654 string OpcodeStr, string Dt,
2655 Intrinsic IntOp, bit Commutable = 0>
2656 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2657 OpcodeStr, Dt, IntOp, Commutable> {
2658 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
2659 OpcodeStr, !strconcat(Dt, "64"),
2660 v1i64, v1i64, IntOp, Commutable>;
2661 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2662 OpcodeStr, !strconcat(Dt, "64"),
2663 v2i64, v2i64, IntOp, Commutable>;
2665 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
2666 InstrItinClass itinD16, InstrItinClass itinD32,
2667 InstrItinClass itinQ16, InstrItinClass itinQ32,
2668 string OpcodeStr, string Dt,
2670 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
2671 OpcodeStr, Dt, IntOp> {
2672 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
2673 OpcodeStr, !strconcat(Dt, "64"),
2674 v1i64, v1i64, IntOp>;
2675 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
2676 OpcodeStr, !strconcat(Dt, "64"),
2677 v2i64, v2i64, IntOp>;
2680 // Neon Narrowing 3-register vector intrinsics,
2681 // source operand element sizes of 16, 32 and 64 bits:
2682 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2683 string OpcodeStr, string Dt,
2684 Intrinsic IntOp, bit Commutable = 0> {
2685 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
2686 OpcodeStr, !strconcat(Dt, "16"),
2687 v8i8, v8i16, IntOp, Commutable>;
2688 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
2689 OpcodeStr, !strconcat(Dt, "32"),
2690 v4i16, v4i32, IntOp, Commutable>;
2691 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
2692 OpcodeStr, !strconcat(Dt, "64"),
2693 v2i32, v2i64, IntOp, Commutable>;
2697 // Neon Long 3-register vector operations.
2699 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2700 InstrItinClass itin16, InstrItinClass itin32,
2701 string OpcodeStr, string Dt,
2702 SDNode OpNode, bit Commutable = 0> {
2703 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
2704 OpcodeStr, !strconcat(Dt, "8"),
2705 v8i16, v8i8, OpNode, Commutable>;
2706 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
2707 OpcodeStr, !strconcat(Dt, "16"),
2708 v4i32, v4i16, OpNode, Commutable>;
2709 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
2710 OpcodeStr, !strconcat(Dt, "32"),
2711 v2i64, v2i32, OpNode, Commutable>;
2714 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
2715 InstrItinClass itin, string OpcodeStr, string Dt,
2717 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
2718 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2719 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
2720 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2723 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2724 InstrItinClass itin16, InstrItinClass itin32,
2725 string OpcodeStr, string Dt,
2726 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2727 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
2728 OpcodeStr, !strconcat(Dt, "8"),
2729 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2730 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
2731 OpcodeStr, !strconcat(Dt, "16"),
2732 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2733 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
2734 OpcodeStr, !strconcat(Dt, "32"),
2735 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2738 // Neon Long 3-register vector intrinsics.
2740 // First with only element sizes of 16 and 32 bits:
2741 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2742 InstrItinClass itin16, InstrItinClass itin32,
2743 string OpcodeStr, string Dt,
2744 Intrinsic IntOp, bit Commutable = 0> {
2745 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
2746 OpcodeStr, !strconcat(Dt, "16"),
2747 v4i32, v4i16, IntOp, Commutable>;
2748 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
2749 OpcodeStr, !strconcat(Dt, "32"),
2750 v2i64, v2i32, IntOp, Commutable>;
2753 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
2754 InstrItinClass itin, string OpcodeStr, string Dt,
2756 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
2757 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2758 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
2759 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2762 // ....then also with element size of 8 bits:
2763 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2764 InstrItinClass itin16, InstrItinClass itin32,
2765 string OpcodeStr, string Dt,
2766 Intrinsic IntOp, bit Commutable = 0>
2767 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
2768 IntOp, Commutable> {
2769 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
2770 OpcodeStr, !strconcat(Dt, "8"),
2771 v8i16, v8i8, IntOp, Commutable>;
2774 // ....with explicit extend (VABDL).
2775 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2776 InstrItinClass itin, string OpcodeStr, string Dt,
2777 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
2778 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
2779 OpcodeStr, !strconcat(Dt, "8"),
2780 v8i16, v8i8, IntOp, ExtOp, Commutable>;
2781 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
2782 OpcodeStr, !strconcat(Dt, "16"),
2783 v4i32, v4i16, IntOp, ExtOp, Commutable>;
2784 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
2785 OpcodeStr, !strconcat(Dt, "32"),
2786 v2i64, v2i32, IntOp, ExtOp, Commutable>;
2790 // Neon Wide 3-register vector intrinsics,
2791 // source operand element sizes of 8, 16 and 32 bits:
2792 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2793 string OpcodeStr, string Dt,
2794 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
2795 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
2796 OpcodeStr, !strconcat(Dt, "8"),
2797 v8i16, v8i8, OpNode, ExtOp, Commutable>;
2798 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
2799 OpcodeStr, !strconcat(Dt, "16"),
2800 v4i32, v4i16, OpNode, ExtOp, Commutable>;
2801 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
2802 OpcodeStr, !strconcat(Dt, "32"),
2803 v2i64, v2i32, OpNode, ExtOp, Commutable>;
2807 // Neon Multiply-Op vector operations,
2808 // element sizes of 8, 16 and 32 bits:
2809 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2810 InstrItinClass itinD16, InstrItinClass itinD32,
2811 InstrItinClass itinQ16, InstrItinClass itinQ32,
2812 string OpcodeStr, string Dt, SDNode OpNode> {
2813 // 64-bit vector types.
2814 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
2815 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
2816 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
2817 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
2818 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
2819 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
2821 // 128-bit vector types.
2822 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
2823 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
2824 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
2825 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
2826 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
2827 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
2830 multiclass N3VMulOpSL_HS<bits<4> op11_8,
2831 InstrItinClass itinD16, InstrItinClass itinD32,
2832 InstrItinClass itinQ16, InstrItinClass itinQ32,
2833 string OpcodeStr, string Dt, SDNode ShOp> {
2834 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
2835 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
2836 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
2837 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
2838 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
2839 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
2841 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
2842 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
2846 // Neon Intrinsic-Op vector operations,
2847 // element sizes of 8, 16 and 32 bits:
2848 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2849 InstrItinClass itinD, InstrItinClass itinQ,
2850 string OpcodeStr, string Dt, Intrinsic IntOp,
2852 // 64-bit vector types.
2853 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
2854 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
2855 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
2856 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
2857 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
2858 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
2860 // 128-bit vector types.
2861 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
2862 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
2863 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
2864 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
2865 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
2866 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
2869 // Neon 3-argument intrinsics,
2870 // element sizes of 8, 16 and 32 bits:
2871 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2872 InstrItinClass itinD, InstrItinClass itinQ,
2873 string OpcodeStr, string Dt, Intrinsic IntOp> {
2874 // 64-bit vector types.
2875 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
2876 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2877 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
2878 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
2879 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
2880 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
2882 // 128-bit vector types.
2883 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
2884 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
2885 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
2886 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
2887 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
2888 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
2892 // Neon Long Multiply-Op vector operations,
2893 // element sizes of 8, 16 and 32 bits:
2894 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2895 InstrItinClass itin16, InstrItinClass itin32,
2896 string OpcodeStr, string Dt, SDNode MulOp,
2898 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
2899 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
2900 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
2901 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
2902 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
2903 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2906 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
2907 string Dt, SDNode MulOp, SDNode OpNode> {
2908 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
2909 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
2910 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
2911 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
2915 // Neon Long 3-argument intrinsics.
2917 // First with only element sizes of 16 and 32 bits:
2918 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
2919 InstrItinClass itin16, InstrItinClass itin32,
2920 string OpcodeStr, string Dt, Intrinsic IntOp> {
2921 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
2922 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
2923 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
2924 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2927 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
2928 string OpcodeStr, string Dt, Intrinsic IntOp> {
2929 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
2930 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
2931 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
2932 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
2935 // ....then also with element size of 8 bits:
2936 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2937 InstrItinClass itin16, InstrItinClass itin32,
2938 string OpcodeStr, string Dt, Intrinsic IntOp>
2939 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
2940 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
2941 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
2944 // ....with explicit extend (VABAL).
2945 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2946 InstrItinClass itin, string OpcodeStr, string Dt,
2947 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
2948 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
2949 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
2950 IntOp, ExtOp, OpNode>;
2951 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
2952 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
2953 IntOp, ExtOp, OpNode>;
2954 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
2955 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
2956 IntOp, ExtOp, OpNode>;
2960 // Neon Pairwise long 2-register intrinsics,
2961 // element sizes of 8, 16 and 32 bits:
2962 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2963 bits<5> op11_7, bit op4,
2964 string OpcodeStr, string Dt, Intrinsic IntOp> {
2965 // 64-bit vector types.
2966 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2967 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2968 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2969 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2970 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2971 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2973 // 128-bit vector types.
2974 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2975 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2976 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2977 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
2978 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2979 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
2983 // Neon Pairwise long 2-register accumulate intrinsics,
2984 // element sizes of 8, 16 and 32 bits:
2985 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2986 bits<5> op11_7, bit op4,
2987 string OpcodeStr, string Dt, Intrinsic IntOp> {
2988 // 64-bit vector types.
2989 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2990 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
2991 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2992 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
2993 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2994 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
2996 // 128-bit vector types.
2997 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2998 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
2999 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3000 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3001 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3002 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3006 // Neon 2-register vector shift by immediate,
3007 // with f of either N2RegVShLFrm or N2RegVShRFrm
3008 // element sizes of 8, 16, 32 and 64 bits:
3009 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3010 InstrItinClass itin, string OpcodeStr, string Dt,
3012 // 64-bit vector types.
3013 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3014 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3015 let Inst{21-19} = 0b001; // imm6 = 001xxx
3017 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3018 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3019 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3021 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3022 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3023 let Inst{21} = 0b1; // imm6 = 1xxxxx
3025 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3026 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3029 // 128-bit vector types.
3030 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3031 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3032 let Inst{21-19} = 0b001; // imm6 = 001xxx
3034 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3035 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3036 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3038 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3039 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3040 let Inst{21} = 0b1; // imm6 = 1xxxxx
3042 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3043 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3046 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3047 InstrItinClass itin, string OpcodeStr, string Dt,
3049 // 64-bit vector types.
3050 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3051 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3052 let Inst{21-19} = 0b001; // imm6 = 001xxx
3054 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3055 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3056 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3058 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3059 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3060 let Inst{21} = 0b1; // imm6 = 1xxxxx
3062 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3063 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3066 // 128-bit vector types.
3067 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3068 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3069 let Inst{21-19} = 0b001; // imm6 = 001xxx
3071 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3072 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3073 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3075 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3076 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3077 let Inst{21} = 0b1; // imm6 = 1xxxxx
3079 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3080 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3084 // Neon Shift-Accumulate vector operations,
3085 // element sizes of 8, 16, 32 and 64 bits:
3086 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3087 string OpcodeStr, string Dt, SDNode ShOp> {
3088 // 64-bit vector types.
3089 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3090 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3091 let Inst{21-19} = 0b001; // imm6 = 001xxx
3093 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3094 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3095 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3097 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3098 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3099 let Inst{21} = 0b1; // imm6 = 1xxxxx
3101 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3102 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3105 // 128-bit vector types.
3106 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3107 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3108 let Inst{21-19} = 0b001; // imm6 = 001xxx
3110 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3111 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3112 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3114 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3115 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3116 let Inst{21} = 0b1; // imm6 = 1xxxxx
3118 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3119 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3123 // Neon Shift-Insert vector operations,
3124 // with f of either N2RegVShLFrm or N2RegVShRFrm
3125 // element sizes of 8, 16, 32 and 64 bits:
3126 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3128 // 64-bit vector types.
3129 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3130 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3131 let Inst{21-19} = 0b001; // imm6 = 001xxx
3133 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3134 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3135 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3137 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3138 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3139 let Inst{21} = 0b1; // imm6 = 1xxxxx
3141 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3142 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3145 // 128-bit vector types.
3146 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3147 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3148 let Inst{21-19} = 0b001; // imm6 = 001xxx
3150 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3151 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3152 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3154 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3155 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3156 let Inst{21} = 0b1; // imm6 = 1xxxxx
3158 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3159 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3162 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3164 // 64-bit vector types.
3165 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3166 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3167 let Inst{21-19} = 0b001; // imm6 = 001xxx
3169 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3170 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3171 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3173 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3174 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3175 let Inst{21} = 0b1; // imm6 = 1xxxxx
3177 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3178 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3181 // 128-bit vector types.
3182 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3183 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3184 let Inst{21-19} = 0b001; // imm6 = 001xxx
3186 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3187 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3188 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3190 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3191 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3192 let Inst{21} = 0b1; // imm6 = 1xxxxx
3194 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3195 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3199 // Neon Shift Long operations,
3200 // element sizes of 8, 16, 32 bits:
3201 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3202 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3203 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3204 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode> {
3205 let Inst{21-19} = 0b001; // imm6 = 001xxx
3207 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3208 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode> {
3209 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3211 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3212 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode> {
3213 let Inst{21} = 0b1; // imm6 = 1xxxxx
3217 // Neon Shift Narrow operations,
3218 // element sizes of 16, 32, 64 bits:
3219 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3220 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3222 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3223 OpcodeStr, !strconcat(Dt, "16"),
3224 v8i8, v8i16, shr_imm8, OpNode> {
3225 let Inst{21-19} = 0b001; // imm6 = 001xxx
3227 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3228 OpcodeStr, !strconcat(Dt, "32"),
3229 v4i16, v4i32, shr_imm16, OpNode> {
3230 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3232 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3233 OpcodeStr, !strconcat(Dt, "64"),
3234 v2i32, v2i64, shr_imm32, OpNode> {
3235 let Inst{21} = 0b1; // imm6 = 1xxxxx
3239 //===----------------------------------------------------------------------===//
3240 // Instruction Definitions.
3241 //===----------------------------------------------------------------------===//
3243 // Vector Add Operations.
3245 // VADD : Vector Add (integer and floating-point)
3246 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3248 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3249 v2f32, v2f32, fadd, 1>;
3250 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3251 v4f32, v4f32, fadd, 1>;
3252 // VADDL : Vector Add Long (Q = D + D)
3253 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3254 "vaddl", "s", add, sext, 1>;
3255 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3256 "vaddl", "u", add, zext, 1>;
3257 // VADDW : Vector Add Wide (Q = Q + D)
3258 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3259 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3260 // VHADD : Vector Halving Add
3261 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3262 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3263 "vhadd", "s", int_arm_neon_vhadds, 1>;
3264 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3265 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3266 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3267 // VRHADD : Vector Rounding Halving Add
3268 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3269 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3270 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3271 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3272 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3273 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3274 // VQADD : Vector Saturating Add
3275 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3276 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3277 "vqadd", "s", int_arm_neon_vqadds, 1>;
3278 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3279 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3280 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3281 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3282 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3283 int_arm_neon_vaddhn, 1>;
3284 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3285 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3286 int_arm_neon_vraddhn, 1>;
3288 // Vector Multiply Operations.
3290 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3291 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3292 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3293 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3294 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3295 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3296 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3297 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3298 v2f32, v2f32, fmul, 1>;
3299 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3300 v4f32, v4f32, fmul, 1>;
3301 defm VMULsl : N3VSL_HS<0b1000, "vmul", "i", mul>;
3302 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3303 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3306 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3307 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3308 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3309 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3310 (DSubReg_i16_reg imm:$lane))),
3311 (SubReg_i16_lane imm:$lane)))>;
3312 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3313 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3314 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3315 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3316 (DSubReg_i32_reg imm:$lane))),
3317 (SubReg_i32_lane imm:$lane)))>;
3318 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3319 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3320 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3321 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3322 (DSubReg_i32_reg imm:$lane))),
3323 (SubReg_i32_lane imm:$lane)))>;
3325 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3326 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3327 IIC_VMULi16Q, IIC_VMULi32Q,
3328 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3329 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3330 IIC_VMULi16Q, IIC_VMULi32Q,
3331 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3332 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3333 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3335 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3336 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3337 (DSubReg_i16_reg imm:$lane))),
3338 (SubReg_i16_lane imm:$lane)))>;
3339 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3340 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3342 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3343 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3344 (DSubReg_i32_reg imm:$lane))),
3345 (SubReg_i32_lane imm:$lane)))>;
3347 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3348 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3349 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3350 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3351 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3352 IIC_VMULi16Q, IIC_VMULi32Q,
3353 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3354 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3355 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3357 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3358 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3359 (DSubReg_i16_reg imm:$lane))),
3360 (SubReg_i16_lane imm:$lane)))>;
3361 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3362 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3364 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3365 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3366 (DSubReg_i32_reg imm:$lane))),
3367 (SubReg_i32_lane imm:$lane)))>;
3369 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3370 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3371 "vmull", "s", NEONvmulls, 1>;
3372 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3373 "vmull", "u", NEONvmullu, 1>;
3374 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3375 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3376 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3377 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3379 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3380 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3381 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3382 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3383 "vqdmull", "s", int_arm_neon_vqdmull>;
3385 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3387 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3388 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3389 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3390 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3391 v2f32, fmul_su, fadd_mlx>,
3392 Requires<[HasNEON, UseFPVMLx]>;
3393 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3394 v4f32, fmul_su, fadd_mlx>,
3395 Requires<[HasNEON, UseFPVMLx]>;
3396 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3397 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3398 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3399 v2f32, fmul_su, fadd_mlx>,
3400 Requires<[HasNEON, UseFPVMLx]>;
3401 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3402 v4f32, v2f32, fmul_su, fadd_mlx>,
3403 Requires<[HasNEON, UseFPVMLx]>;
3405 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3406 (mul (v8i16 QPR:$src2),
3407 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3408 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3409 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3410 (DSubReg_i16_reg imm:$lane))),
3411 (SubReg_i16_lane imm:$lane)))>;
3413 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3414 (mul (v4i32 QPR:$src2),
3415 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3416 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3417 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3418 (DSubReg_i32_reg imm:$lane))),
3419 (SubReg_i32_lane imm:$lane)))>;
3421 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3422 (fmul_su (v4f32 QPR:$src2),
3423 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3424 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3426 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3427 (DSubReg_i32_reg imm:$lane))),
3428 (SubReg_i32_lane imm:$lane)))>,
3429 Requires<[HasNEON, UseFPVMLx]>;
3431 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3432 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3433 "vmlal", "s", NEONvmulls, add>;
3434 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3435 "vmlal", "u", NEONvmullu, add>;
3437 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3438 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3440 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3441 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3442 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3443 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3445 // VMLS : Vector Multiply Subtract (integer and floating-point)
3446 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3447 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3448 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3449 v2f32, fmul_su, fsub_mlx>,
3450 Requires<[HasNEON, UseFPVMLx]>;
3451 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3452 v4f32, fmul_su, fsub_mlx>,
3453 Requires<[HasNEON, UseFPVMLx]>;
3454 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3455 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3456 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3457 v2f32, fmul_su, fsub_mlx>,
3458 Requires<[HasNEON, UseFPVMLx]>;
3459 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3460 v4f32, v2f32, fmul_su, fsub_mlx>,
3461 Requires<[HasNEON, UseFPVMLx]>;
3463 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3464 (mul (v8i16 QPR:$src2),
3465 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3466 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3467 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3468 (DSubReg_i16_reg imm:$lane))),
3469 (SubReg_i16_lane imm:$lane)))>;
3471 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3472 (mul (v4i32 QPR:$src2),
3473 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3474 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3475 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3476 (DSubReg_i32_reg imm:$lane))),
3477 (SubReg_i32_lane imm:$lane)))>;
3479 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3480 (fmul_su (v4f32 QPR:$src2),
3481 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3482 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3483 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3484 (DSubReg_i32_reg imm:$lane))),
3485 (SubReg_i32_lane imm:$lane)))>,
3486 Requires<[HasNEON, UseFPVMLx]>;
3488 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3489 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3490 "vmlsl", "s", NEONvmulls, sub>;
3491 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3492 "vmlsl", "u", NEONvmullu, sub>;
3494 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3495 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3497 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3498 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3499 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3500 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3502 // Vector Subtract Operations.
3504 // VSUB : Vector Subtract (integer and floating-point)
3505 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3506 "vsub", "i", sub, 0>;
3507 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3508 v2f32, v2f32, fsub, 0>;
3509 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3510 v4f32, v4f32, fsub, 0>;
3511 // VSUBL : Vector Subtract Long (Q = D - D)
3512 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3513 "vsubl", "s", sub, sext, 0>;
3514 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3515 "vsubl", "u", sub, zext, 0>;
3516 // VSUBW : Vector Subtract Wide (Q = Q - D)
3517 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3518 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3519 // VHSUB : Vector Halving Subtract
3520 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3521 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3522 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3523 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3524 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3525 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3526 // VQSUB : Vector Saturing Subtract
3527 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3528 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3529 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3530 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3531 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3532 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3533 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3534 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3535 int_arm_neon_vsubhn, 0>;
3536 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3537 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3538 int_arm_neon_vrsubhn, 0>;
3540 // Vector Comparisons.
3542 // VCEQ : Vector Compare Equal
3543 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3544 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3545 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3547 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3550 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3551 "$Vd, $Vm, #0", NEONvceqz>;
3553 // VCGE : Vector Compare Greater Than or Equal
3554 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3555 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
3556 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3557 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
3558 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
3560 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
3563 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
3564 "$Vd, $Vm, #0", NEONvcgez>;
3565 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
3566 "$Vd, $Vm, #0", NEONvclez>;
3568 // VCGT : Vector Compare Greater Than
3569 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3570 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
3571 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3572 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
3573 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
3575 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
3578 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
3579 "$Vd, $Vm, #0", NEONvcgtz>;
3580 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
3581 "$Vd, $Vm, #0", NEONvcltz>;
3583 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
3584 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
3585 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
3586 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
3587 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
3588 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
3589 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
3590 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
3591 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
3592 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
3593 // VTST : Vector Test Bits
3594 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
3595 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
3597 // Vector Bitwise Operations.
3599 def vnotd : PatFrag<(ops node:$in),
3600 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
3601 def vnotq : PatFrag<(ops node:$in),
3602 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
3605 // VAND : Vector Bitwise AND
3606 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
3607 v2i32, v2i32, and, 1>;
3608 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
3609 v4i32, v4i32, and, 1>;
3611 // VEOR : Vector Bitwise Exclusive OR
3612 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
3613 v2i32, v2i32, xor, 1>;
3614 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
3615 v4i32, v4i32, xor, 1>;
3617 // VORR : Vector Bitwise OR
3618 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
3619 v2i32, v2i32, or, 1>;
3620 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
3621 v4i32, v4i32, or, 1>;
3623 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
3624 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3626 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3628 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3629 let Inst{9} = SIMM{9};
3632 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
3633 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3635 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3637 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
3638 let Inst{10-9} = SIMM{10-9};
3641 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
3642 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3644 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
3646 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3647 let Inst{9} = SIMM{9};
3650 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
3651 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3653 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
3655 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
3656 let Inst{10-9} = SIMM{10-9};
3660 // VBIC : Vector Bitwise Bit Clear (AND NOT)
3661 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3662 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3663 "vbic", "$Vd, $Vn, $Vm", "",
3664 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
3665 (vnotd DPR:$Vm))))]>;
3666 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3667 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3668 "vbic", "$Vd, $Vn, $Vm", "",
3669 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
3670 (vnotq QPR:$Vm))))]>;
3672 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
3673 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3675 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3677 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3678 let Inst{9} = SIMM{9};
3681 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
3682 (outs DPR:$Vd), (ins nModImm:$SIMM, DPR:$src),
3684 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3686 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
3687 let Inst{10-9} = SIMM{10-9};
3690 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
3691 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3693 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
3695 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3696 let Inst{9} = SIMM{9};
3699 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
3700 (outs QPR:$Vd), (ins nModImm:$SIMM, QPR:$src),
3702 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
3704 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
3705 let Inst{10-9} = SIMM{10-9};
3708 // VORN : Vector Bitwise OR NOT
3709 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
3710 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
3711 "vorn", "$Vd, $Vn, $Vm", "",
3712 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
3713 (vnotd DPR:$Vm))))]>;
3714 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
3715 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
3716 "vorn", "$Vd, $Vn, $Vm", "",
3717 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
3718 (vnotq QPR:$Vm))))]>;
3720 // VMVN : Vector Bitwise NOT (Immediate)
3722 let isReMaterializable = 1 in {
3724 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
3725 (ins nModImm:$SIMM), IIC_VMOVImm,
3726 "vmvn", "i16", "$Vd, $SIMM", "",
3727 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
3728 let Inst{9} = SIMM{9};
3731 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
3732 (ins nModImm:$SIMM), IIC_VMOVImm,
3733 "vmvn", "i16", "$Vd, $SIMM", "",
3734 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
3735 let Inst{9} = SIMM{9};
3738 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
3739 (ins nModImm:$SIMM), IIC_VMOVImm,
3740 "vmvn", "i32", "$Vd, $SIMM", "",
3741 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
3742 let Inst{11-8} = SIMM{11-8};
3745 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
3746 (ins nModImm:$SIMM), IIC_VMOVImm,
3747 "vmvn", "i32", "$Vd, $SIMM", "",
3748 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
3749 let Inst{11-8} = SIMM{11-8};
3753 // VMVN : Vector Bitwise NOT
3754 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
3755 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
3756 "vmvn", "$Vd, $Vm", "",
3757 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
3758 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
3759 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
3760 "vmvn", "$Vd, $Vm", "",
3761 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
3762 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
3763 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
3765 // VBSL : Vector Bitwise Select
3766 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
3767 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3768 N3RegFrm, IIC_VCNTiD,
3769 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3771 (v2i32 (or (and DPR:$Vn, DPR:$src1),
3772 (and DPR:$Vm, (vnotd DPR:$src1)))))]>;
3773 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
3774 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3775 N3RegFrm, IIC_VCNTiQ,
3776 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3778 (v4i32 (or (and QPR:$Vn, QPR:$src1),
3779 (and QPR:$Vm, (vnotq QPR:$src1)))))]>;
3781 // VBIF : Vector Bitwise Insert if False
3782 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
3783 // FIXME: This instruction's encoding MAY NOT BE correct.
3784 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
3785 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3786 N3RegFrm, IIC_VBINiD,
3787 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3788 [/* For disassembly only; pattern left blank */]>;
3789 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
3790 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3791 N3RegFrm, IIC_VBINiQ,
3792 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3793 [/* For disassembly only; pattern left blank */]>;
3795 // VBIT : Vector Bitwise Insert if True
3796 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
3797 // FIXME: This instruction's encoding MAY NOT BE correct.
3798 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
3799 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
3800 N3RegFrm, IIC_VBINiD,
3801 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3802 [/* For disassembly only; pattern left blank */]>;
3803 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
3804 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
3805 N3RegFrm, IIC_VBINiQ,
3806 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
3807 [/* For disassembly only; pattern left blank */]>;
3809 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
3810 // for equivalent operations with different register constraints; it just
3813 // Vector Absolute Differences.
3815 // VABD : Vector Absolute Difference
3816 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
3817 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3818 "vabd", "s", int_arm_neon_vabds, 1>;
3819 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
3820 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3821 "vabd", "u", int_arm_neon_vabdu, 1>;
3822 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
3823 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
3824 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
3825 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
3827 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
3828 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
3829 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
3830 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
3831 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
3833 // VABA : Vector Absolute Difference and Accumulate
3834 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3835 "vaba", "s", int_arm_neon_vabds, add>;
3836 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
3837 "vaba", "u", int_arm_neon_vabdu, add>;
3839 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
3840 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
3841 "vabal", "s", int_arm_neon_vabds, zext, add>;
3842 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
3843 "vabal", "u", int_arm_neon_vabdu, zext, add>;
3845 // Vector Maximum and Minimum.
3847 // VMAX : Vector Maximum
3848 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
3849 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3850 "vmax", "s", int_arm_neon_vmaxs, 1>;
3851 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
3852 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3853 "vmax", "u", int_arm_neon_vmaxu, 1>;
3854 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
3856 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
3857 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3859 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
3861 // VMIN : Vector Minimum
3862 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
3863 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3864 "vmin", "s", int_arm_neon_vmins, 1>;
3865 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
3866 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3867 "vmin", "u", int_arm_neon_vminu, 1>;
3868 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
3870 v2f32, v2f32, int_arm_neon_vmins, 1>;
3871 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
3873 v4f32, v4f32, int_arm_neon_vmins, 1>;
3875 // Vector Pairwise Operations.
3877 // VPADD : Vector Pairwise Add
3878 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3880 v8i8, v8i8, int_arm_neon_vpadd, 0>;
3881 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3883 v4i16, v4i16, int_arm_neon_vpadd, 0>;
3884 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
3886 v2i32, v2i32, int_arm_neon_vpadd, 0>;
3887 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
3888 IIC_VPBIND, "vpadd", "f32",
3889 v2f32, v2f32, int_arm_neon_vpadd, 0>;
3891 // VPADDL : Vector Pairwise Add Long
3892 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
3893 int_arm_neon_vpaddls>;
3894 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
3895 int_arm_neon_vpaddlu>;
3897 // VPADAL : Vector Pairwise Add and Accumulate Long
3898 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
3899 int_arm_neon_vpadals>;
3900 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
3901 int_arm_neon_vpadalu>;
3903 // VPMAX : Vector Pairwise Maximum
3904 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3905 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
3906 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3907 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
3908 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3909 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
3910 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3911 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
3912 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3913 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
3914 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
3915 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
3916 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
3917 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
3919 // VPMIN : Vector Pairwise Minimum
3920 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3921 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
3922 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3923 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
3924 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3925 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
3926 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3927 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
3928 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3929 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
3930 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
3931 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
3932 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
3933 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
3935 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
3937 // VRECPE : Vector Reciprocal Estimate
3938 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3939 IIC_VUNAD, "vrecpe", "u32",
3940 v2i32, v2i32, int_arm_neon_vrecpe>;
3941 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
3942 IIC_VUNAQ, "vrecpe", "u32",
3943 v4i32, v4i32, int_arm_neon_vrecpe>;
3944 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3945 IIC_VUNAD, "vrecpe", "f32",
3946 v2f32, v2f32, int_arm_neon_vrecpe>;
3947 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
3948 IIC_VUNAQ, "vrecpe", "f32",
3949 v4f32, v4f32, int_arm_neon_vrecpe>;
3951 // VRECPS : Vector Reciprocal Step
3952 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3953 IIC_VRECSD, "vrecps", "f32",
3954 v2f32, v2f32, int_arm_neon_vrecps, 1>;
3955 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
3956 IIC_VRECSQ, "vrecps", "f32",
3957 v4f32, v4f32, int_arm_neon_vrecps, 1>;
3959 // VRSQRTE : Vector Reciprocal Square Root Estimate
3960 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3961 IIC_VUNAD, "vrsqrte", "u32",
3962 v2i32, v2i32, int_arm_neon_vrsqrte>;
3963 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
3964 IIC_VUNAQ, "vrsqrte", "u32",
3965 v4i32, v4i32, int_arm_neon_vrsqrte>;
3966 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3967 IIC_VUNAD, "vrsqrte", "f32",
3968 v2f32, v2f32, int_arm_neon_vrsqrte>;
3969 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
3970 IIC_VUNAQ, "vrsqrte", "f32",
3971 v4f32, v4f32, int_arm_neon_vrsqrte>;
3973 // VRSQRTS : Vector Reciprocal Square Root Step
3974 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3975 IIC_VRECSD, "vrsqrts", "f32",
3976 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
3977 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
3978 IIC_VRECSQ, "vrsqrts", "f32",
3979 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
3983 // VSHL : Vector Shift
3984 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
3985 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3986 "vshl", "s", int_arm_neon_vshifts>;
3987 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
3988 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
3989 "vshl", "u", int_arm_neon_vshiftu>;
3991 // VSHL : Vector Shift Left (Immediate)
3992 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
3994 // VSHR : Vector Shift Right (Immediate)
3995 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
3996 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
3998 // VSHLL : Vector Shift Left Long
3999 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4000 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4002 // VSHLL : Vector Shift Left Long (with maximum shift count)
4003 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4004 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4005 ValueType OpTy, SDNode OpNode>
4006 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4007 ResTy, OpTy, OpNode> {
4008 let Inst{21-16} = op21_16;
4010 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4011 v8i16, v8i8, NEONvshlli>;
4012 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4013 v4i32, v4i16, NEONvshlli>;
4014 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4015 v2i64, v2i32, NEONvshlli>;
4017 // VSHRN : Vector Shift Right and Narrow
4018 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4021 // VRSHL : Vector Rounding Shift
4022 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4023 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4024 "vrshl", "s", int_arm_neon_vrshifts>;
4025 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4026 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4027 "vrshl", "u", int_arm_neon_vrshiftu>;
4028 // VRSHR : Vector Rounding Shift Right
4029 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
4030 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
4032 // VRSHRN : Vector Rounding Shift Right and Narrow
4033 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4036 // VQSHL : Vector Saturating Shift
4037 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4038 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4039 "vqshl", "s", int_arm_neon_vqshifts>;
4040 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4041 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4042 "vqshl", "u", int_arm_neon_vqshiftu>;
4043 // VQSHL : Vector Saturating Shift Left (Immediate)
4044 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4045 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4047 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4048 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4050 // VQSHRN : Vector Saturating Shift Right and Narrow
4051 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4053 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4056 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4057 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4060 // VQRSHL : Vector Saturating Rounding Shift
4061 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4062 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4063 "vqrshl", "s", int_arm_neon_vqrshifts>;
4064 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4065 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4066 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4068 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4069 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4071 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4074 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4075 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4078 // VSRA : Vector Shift Right and Accumulate
4079 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4080 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4081 // VRSRA : Vector Rounding Shift Right and Accumulate
4082 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4083 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4085 // VSLI : Vector Shift Left and Insert
4086 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4088 // VSRI : Vector Shift Right and Insert
4089 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4091 // Vector Absolute and Saturating Absolute.
4093 // VABS : Vector Absolute Value
4094 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4095 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4097 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4098 IIC_VUNAD, "vabs", "f32",
4099 v2f32, v2f32, int_arm_neon_vabs>;
4100 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4101 IIC_VUNAQ, "vabs", "f32",
4102 v4f32, v4f32, int_arm_neon_vabs>;
4104 // VQABS : Vector Saturating Absolute Value
4105 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4106 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4107 int_arm_neon_vqabs>;
4111 def vnegd : PatFrag<(ops node:$in),
4112 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4113 def vnegq : PatFrag<(ops node:$in),
4114 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4116 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4117 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4118 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4119 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4120 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4121 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4122 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4123 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4125 // VNEG : Vector Negate (integer)
4126 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4127 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4128 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4129 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4130 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4131 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4133 // VNEG : Vector Negate (floating-point)
4134 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4135 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4136 "vneg", "f32", "$Vd, $Vm", "",
4137 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4138 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4139 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4140 "vneg", "f32", "$Vd, $Vm", "",
4141 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4143 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4144 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4145 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4146 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4147 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4148 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4150 // VQNEG : Vector Saturating Negate
4151 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4152 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4153 int_arm_neon_vqneg>;
4155 // Vector Bit Counting Operations.
4157 // VCLS : Vector Count Leading Sign Bits
4158 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4159 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4161 // VCLZ : Vector Count Leading Zeros
4162 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4163 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4165 // VCNT : Vector Count One Bits
4166 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4167 IIC_VCNTiD, "vcnt", "8",
4168 v8i8, v8i8, int_arm_neon_vcnt>;
4169 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4170 IIC_VCNTiQ, "vcnt", "8",
4171 v16i8, v16i8, int_arm_neon_vcnt>;
4173 // Vector Swap -- for disassembly only.
4174 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4175 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4176 "vswp", "$Vd, $Vm", "", []>;
4177 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4178 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4179 "vswp", "$Vd, $Vm", "", []>;
4181 // Vector Move Operations.
4183 // VMOV : Vector Move (Register)
4185 let neverHasSideEffects = 1 in {
4186 def VMOVDneon: N3VX<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$Vd), (ins DPR:$Vm),
4187 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
4188 let Vn{4-0} = Vm{4-0};
4190 def VMOVQ : N3VX<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$Vd), (ins QPR:$Vm),
4191 N3RegFrm, IIC_VMOV, "vmov", "$Vd, $Vm", "", []> {
4192 let Vn{4-0} = Vm{4-0};
4195 // Pseudo vector move instructions for QQ and QQQQ registers. This should
4196 // be expanded after register allocation is completed.
4197 def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
4200 def VMOVQQQQ : PseudoInst<(outs QQQQPR:$dst), (ins QQQQPR:$src),
4202 } // neverHasSideEffects
4204 // VMOV : Vector Move (Immediate)
4206 let isReMaterializable = 1 in {
4207 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4208 (ins nModImm:$SIMM), IIC_VMOVImm,
4209 "vmov", "i8", "$Vd, $SIMM", "",
4210 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4211 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4212 (ins nModImm:$SIMM), IIC_VMOVImm,
4213 "vmov", "i8", "$Vd, $SIMM", "",
4214 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4216 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4217 (ins nModImm:$SIMM), IIC_VMOVImm,
4218 "vmov", "i16", "$Vd, $SIMM", "",
4219 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4220 let Inst{9} = SIMM{9};
4223 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4224 (ins nModImm:$SIMM), IIC_VMOVImm,
4225 "vmov", "i16", "$Vd, $SIMM", "",
4226 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4227 let Inst{9} = SIMM{9};
4230 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4231 (ins nModImm:$SIMM), IIC_VMOVImm,
4232 "vmov", "i32", "$Vd, $SIMM", "",
4233 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4234 let Inst{11-8} = SIMM{11-8};
4237 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4238 (ins nModImm:$SIMM), IIC_VMOVImm,
4239 "vmov", "i32", "$Vd, $SIMM", "",
4240 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4241 let Inst{11-8} = SIMM{11-8};
4244 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4245 (ins nModImm:$SIMM), IIC_VMOVImm,
4246 "vmov", "i64", "$Vd, $SIMM", "",
4247 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4248 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4249 (ins nModImm:$SIMM), IIC_VMOVImm,
4250 "vmov", "i64", "$Vd, $SIMM", "",
4251 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4252 } // isReMaterializable
4254 // VMOV : Vector Get Lane (move scalar to ARM core register)
4256 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4257 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4258 IIC_VMOVSI, "vmov", "s8", "$R, $V[$lane]",
4259 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4261 let Inst{21} = lane{2};
4262 let Inst{6-5} = lane{1-0};
4264 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4265 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4266 IIC_VMOVSI, "vmov", "s16", "$R, $V[$lane]",
4267 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4269 let Inst{21} = lane{1};
4270 let Inst{6} = lane{0};
4272 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4273 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4274 IIC_VMOVSI, "vmov", "u8", "$R, $V[$lane]",
4275 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4277 let Inst{21} = lane{2};
4278 let Inst{6-5} = lane{1-0};
4280 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4281 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4282 IIC_VMOVSI, "vmov", "u16", "$R, $V[$lane]",
4283 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4285 let Inst{21} = lane{1};
4286 let Inst{6} = lane{0};
4288 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4289 (outs GPR:$R), (ins DPR:$V, nohash_imm:$lane),
4290 IIC_VMOVSI, "vmov", "32", "$R, $V[$lane]",
4291 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4293 let Inst{21} = lane{0};
4295 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4296 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4297 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4298 (DSubReg_i8_reg imm:$lane))),
4299 (SubReg_i8_lane imm:$lane))>;
4300 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4301 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4302 (DSubReg_i16_reg imm:$lane))),
4303 (SubReg_i16_lane imm:$lane))>;
4304 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4305 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4306 (DSubReg_i8_reg imm:$lane))),
4307 (SubReg_i8_lane imm:$lane))>;
4308 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4309 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4310 (DSubReg_i16_reg imm:$lane))),
4311 (SubReg_i16_lane imm:$lane))>;
4312 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4313 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4314 (DSubReg_i32_reg imm:$lane))),
4315 (SubReg_i32_lane imm:$lane))>;
4316 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4317 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4318 (SSubReg_f32_reg imm:$src2))>;
4319 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4320 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4321 (SSubReg_f32_reg imm:$src2))>;
4322 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4323 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4324 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4325 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4328 // VMOV : Vector Set Lane (move ARM core register to scalar)
4330 let Constraints = "$src1 = $V" in {
4331 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4332 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4333 IIC_VMOVISL, "vmov", "8", "$V[$lane], $R",
4334 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4335 GPR:$R, imm:$lane))]> {
4336 let Inst{21} = lane{2};
4337 let Inst{6-5} = lane{1-0};
4339 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4340 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4341 IIC_VMOVISL, "vmov", "16", "$V[$lane], $R",
4342 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4343 GPR:$R, imm:$lane))]> {
4344 let Inst{21} = lane{1};
4345 let Inst{6} = lane{0};
4347 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4348 (ins DPR:$src1, GPR:$R, nohash_imm:$lane),
4349 IIC_VMOVISL, "vmov", "32", "$V[$lane], $R",
4350 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4351 GPR:$R, imm:$lane))]> {
4352 let Inst{21} = lane{0};
4355 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4356 (v16i8 (INSERT_SUBREG QPR:$src1,
4357 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4358 (DSubReg_i8_reg imm:$lane))),
4359 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4360 (DSubReg_i8_reg imm:$lane)))>;
4361 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4362 (v8i16 (INSERT_SUBREG QPR:$src1,
4363 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4364 (DSubReg_i16_reg imm:$lane))),
4365 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4366 (DSubReg_i16_reg imm:$lane)))>;
4367 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4368 (v4i32 (INSERT_SUBREG QPR:$src1,
4369 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4370 (DSubReg_i32_reg imm:$lane))),
4371 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4372 (DSubReg_i32_reg imm:$lane)))>;
4374 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4375 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4376 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4377 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4378 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4379 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4381 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4382 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4383 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4384 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4386 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4387 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4388 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4389 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4390 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4391 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4393 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4394 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4395 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4396 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4397 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4398 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4400 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4401 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4402 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4404 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4405 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4406 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4408 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4409 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4410 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4413 // VDUP : Vector Duplicate (from ARM core register to all elements)
4415 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4416 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4417 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4418 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4419 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4420 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4421 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4422 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4424 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4425 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4426 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4427 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4428 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4429 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4431 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
4432 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
4434 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4436 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4438 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, nohash_imm:$lane),
4439 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm[$lane]",
4440 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4442 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4443 ValueType ResTy, ValueType OpTy>
4444 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, nohash_imm:$lane),
4445 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm[$lane]",
4446 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4449 // Inst{19-16} is partially specified depending on the element size.
4451 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8> {
4452 let Inst{19-17} = lane{2-0};
4454 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16> {
4455 let Inst{19-18} = lane{1-0};
4457 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32> {
4458 let Inst{19} = lane{0};
4460 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8> {
4461 let Inst{19-17} = lane{2-0};
4463 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16> {
4464 let Inst{19-18} = lane{1-0};
4466 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32> {
4467 let Inst{19} = lane{0};
4470 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4471 (VDUPLN32d DPR:$Vm, imm:$lane)>;
4473 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4474 (VDUPLN32q DPR:$Vm, imm:$lane)>;
4476 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4477 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4478 (DSubReg_i8_reg imm:$lane))),
4479 (SubReg_i8_lane imm:$lane)))>;
4480 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4481 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4482 (DSubReg_i16_reg imm:$lane))),
4483 (SubReg_i16_lane imm:$lane)))>;
4484 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4485 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4486 (DSubReg_i32_reg imm:$lane))),
4487 (SubReg_i32_lane imm:$lane)))>;
4488 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4489 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
4490 (DSubReg_i32_reg imm:$lane))),
4491 (SubReg_i32_lane imm:$lane)))>;
4493 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4494 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4495 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4496 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4498 // VMOVN : Vector Narrowing Move
4499 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4500 "vmovn", "i", trunc>;
4501 // VQMOVN : Vector Saturating Narrowing Move
4502 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4503 "vqmovn", "s", int_arm_neon_vqmovns>;
4504 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4505 "vqmovn", "u", int_arm_neon_vqmovnu>;
4506 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4507 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4508 // VMOVL : Vector Lengthening Move
4509 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4510 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4512 // Vector Conversions.
4514 // VCVT : Vector Convert Between Floating-Point and Integers
4515 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4516 v2i32, v2f32, fp_to_sint>;
4517 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4518 v2i32, v2f32, fp_to_uint>;
4519 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4520 v2f32, v2i32, sint_to_fp>;
4521 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4522 v2f32, v2i32, uint_to_fp>;
4524 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4525 v4i32, v4f32, fp_to_sint>;
4526 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4527 v4i32, v4f32, fp_to_uint>;
4528 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4529 v4f32, v4i32, sint_to_fp>;
4530 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4531 v4f32, v4i32, uint_to_fp>;
4533 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4534 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4535 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4536 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4537 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4538 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4539 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4540 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4541 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
4543 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4544 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
4545 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4546 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
4547 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4548 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
4549 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4550 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
4552 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
4553 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
4554 IIC_VUNAQ, "vcvt", "f16.f32",
4555 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
4556 Requires<[HasNEON, HasFP16]>;
4557 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
4558 IIC_VUNAQ, "vcvt", "f32.f16",
4559 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
4560 Requires<[HasNEON, HasFP16]>;
4564 // VREV64 : Vector Reverse elements within 64-bit doublewords
4566 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4567 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
4568 (ins DPR:$Vm), IIC_VMOVD,
4569 OpcodeStr, Dt, "$Vd, $Vm", "",
4570 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
4571 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4572 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
4573 (ins QPR:$Vm), IIC_VMOVQ,
4574 OpcodeStr, Dt, "$Vd, $Vm", "",
4575 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
4577 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
4578 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
4579 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
4580 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
4582 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
4583 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
4584 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
4585 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
4587 // VREV32 : Vector Reverse elements within 32-bit words
4589 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4590 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
4591 (ins DPR:$Vm), IIC_VMOVD,
4592 OpcodeStr, Dt, "$Vd, $Vm", "",
4593 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
4594 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4595 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
4596 (ins QPR:$Vm), IIC_VMOVQ,
4597 OpcodeStr, Dt, "$Vd, $Vm", "",
4598 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
4600 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
4601 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
4603 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
4604 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
4606 // VREV16 : Vector Reverse elements within 16-bit halfwords
4608 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4609 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
4610 (ins DPR:$Vm), IIC_VMOVD,
4611 OpcodeStr, Dt, "$Vd, $Vm", "",
4612 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
4613 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
4614 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
4615 (ins QPR:$Vm), IIC_VMOVQ,
4616 OpcodeStr, Dt, "$Vd, $Vm", "",
4617 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
4619 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
4620 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
4622 // Other Vector Shuffles.
4624 // Aligned extractions: really just dropping registers
4626 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
4627 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
4628 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
4630 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
4632 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
4634 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
4636 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
4638 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
4641 // VEXT : Vector Extract
4643 class VEXTd<string OpcodeStr, string Dt, ValueType Ty>
4644 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
4645 (ins DPR:$Vn, DPR:$Vm, i32imm:$index), NVExtFrm,
4646 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4647 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
4648 (Ty DPR:$Vm), imm:$index)))]> {
4650 let Inst{11-8} = index{3-0};
4653 class VEXTq<string OpcodeStr, string Dt, ValueType Ty>
4654 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
4655 (ins QPR:$Vn, QPR:$Vm, i32imm:$index), NVExtFrm,
4656 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
4657 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
4658 (Ty QPR:$Vm), imm:$index)))]> {
4660 let Inst{11-8} = index{3-0};
4663 def VEXTd8 : VEXTd<"vext", "8", v8i8> {
4664 let Inst{11-8} = index{3-0};
4666 def VEXTd16 : VEXTd<"vext", "16", v4i16> {
4667 let Inst{11-9} = index{2-0};
4670 def VEXTd32 : VEXTd<"vext", "32", v2i32> {
4671 let Inst{11-10} = index{1-0};
4672 let Inst{9-8} = 0b00;
4674 def VEXTdf : VEXTd<"vext", "32", v2f32> {
4675 let Inst{11} = index{0};
4676 let Inst{10-8} = 0b000;
4679 def VEXTq8 : VEXTq<"vext", "8", v16i8> {
4680 let Inst{11-8} = index{3-0};
4682 def VEXTq16 : VEXTq<"vext", "16", v8i16> {
4683 let Inst{11-9} = index{2-0};
4686 def VEXTq32 : VEXTq<"vext", "32", v4i32> {
4687 let Inst{11-10} = index{1-0};
4688 let Inst{9-8} = 0b00;
4690 def VEXTqf : VEXTq<"vext", "32", v4f32> {
4691 let Inst{11} = index{0};
4692 let Inst{10-8} = 0b000;
4695 // VTRN : Vector Transpose
4697 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
4698 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
4699 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
4701 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
4702 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
4703 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
4705 // VUZP : Vector Unzip (Deinterleave)
4707 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
4708 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
4709 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
4711 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
4712 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
4713 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
4715 // VZIP : Vector Zip (Interleave)
4717 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
4718 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
4719 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
4721 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
4722 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
4723 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
4725 // Vector Table Lookup and Table Extension.
4727 // VTBL : Vector Table Lookup
4729 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
4730 (ins DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
4731 "vtbl", "8", "$Vd, \\{$Vn\\}, $Vm", "",
4732 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 DPR:$Vn, DPR:$Vm)))]>;
4733 let hasExtraSrcRegAllocReq = 1 in {
4735 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
4736 (ins DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTB2,
4737 "vtbl", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "", []>;
4739 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
4740 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm), NVTBLFrm, IIC_VTB3,
4741 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm", "", []>;
4743 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
4744 (ins DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm),
4746 "vtbl", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm", "", []>;
4747 } // hasExtraSrcRegAllocReq = 1
4750 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
4752 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
4754 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
4756 // VTBX : Vector Table Extension
4758 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
4759 (ins DPR:$orig, DPR:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
4760 "vtbx", "8", "$Vd, \\{$Vn\\}, $Vm", "$orig = $Vd",
4761 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
4762 DPR:$orig, DPR:$Vn, DPR:$Vm)))]>;
4763 let hasExtraSrcRegAllocReq = 1 in {
4765 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
4766 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
4767 "vtbx", "8", "$Vd, \\{$Vn, $tbl2\\}, $Vm", "$orig = $Vd", []>;
4769 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
4770 (ins DPR:$orig, DPR:$Vn, DPR:$tbl2, DPR:$tbl3, DPR:$Vm),
4771 NVTBLFrm, IIC_VTBX3,
4772 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3\\}, $Vm",
4775 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), (ins DPR:$orig, DPR:$Vn,
4776 DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
4777 "vtbx", "8", "$Vd, \\{$Vn, $tbl2, $tbl3, $tbl4\\}, $Vm",
4779 } // hasExtraSrcRegAllocReq = 1
4782 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
4783 IIC_VTBX2, "$orig = $dst", []>;
4785 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4786 IIC_VTBX3, "$orig = $dst", []>;
4788 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
4789 IIC_VTBX4, "$orig = $dst", []>;
4791 //===----------------------------------------------------------------------===//
4792 // NEON instructions for single-precision FP math
4793 //===----------------------------------------------------------------------===//
4795 class N2VSPat<SDNode OpNode, NeonI Inst>
4796 : NEONFPPat<(f32 (OpNode SPR:$a)),
4798 (v2f32 (COPY_TO_REGCLASS (Inst
4800 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4801 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
4803 class N3VSPat<SDNode OpNode, NeonI Inst>
4804 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
4806 (v2f32 (COPY_TO_REGCLASS (Inst
4808 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4811 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4812 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4814 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
4815 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
4817 (v2f32 (COPY_TO_REGCLASS (Inst
4819 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4822 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4825 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
4826 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
4828 def : N3VSPat<fadd, VADDfd>;
4829 def : N3VSPat<fsub, VSUBfd>;
4830 def : N3VSPat<fmul, VMULfd>;
4831 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
4832 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4833 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
4834 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
4835 def : N2VSPat<fabs, VABSfd>;
4836 def : N2VSPat<fneg, VNEGfd>;
4837 def : N3VSPat<NEONfmax, VMAXfd>;
4838 def : N3VSPat<NEONfmin, VMINfd>;
4839 def : N2VSPat<arm_ftosi, VCVTf2sd>;
4840 def : N2VSPat<arm_ftoui, VCVTf2ud>;
4841 def : N2VSPat<arm_sitof, VCVTs2fd>;
4842 def : N2VSPat<arm_uitof, VCVTu2fd>;
4844 //===----------------------------------------------------------------------===//
4845 // Non-Instruction Patterns
4846 //===----------------------------------------------------------------------===//
4849 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
4850 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
4851 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
4852 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
4853 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
4854 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
4855 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
4856 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
4857 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
4858 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
4859 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
4860 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
4861 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
4862 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
4863 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
4864 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
4865 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
4866 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
4867 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
4868 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
4869 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
4870 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
4871 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
4872 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
4873 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
4874 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
4875 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
4876 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
4877 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
4878 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
4880 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
4881 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
4882 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
4883 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
4884 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
4885 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
4886 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
4887 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
4888 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
4889 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
4890 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
4891 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
4892 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
4893 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
4894 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
4895 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
4896 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
4897 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
4898 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
4899 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
4900 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
4901 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
4902 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
4903 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
4904 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
4905 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
4906 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
4907 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
4908 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
4909 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;