1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
42 def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
43 def nImmVMOVI32Neg : Operand<i32> {
44 let PrintMethod = "printNEONModImmOperand";
45 let ParserMatchClass = nImmVMOVI32NegAsmOperand;
47 def nImmVMOVF32 : Operand<i32> {
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
51 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
52 def nImmSplatI64 : Operand<i32> {
53 let PrintMethod = "printNEONModImmOperand";
54 let ParserMatchClass = nImmSplatI64AsmOperand;
57 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
58 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
59 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
60 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
61 return ((uint64_t)Imm) < 8;
63 let ParserMatchClass = VectorIndex8Operand;
64 let PrintMethod = "printVectorIndex";
65 let MIOperandInfo = (ops i32imm);
67 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
68 return ((uint64_t)Imm) < 4;
70 let ParserMatchClass = VectorIndex16Operand;
71 let PrintMethod = "printVectorIndex";
72 let MIOperandInfo = (ops i32imm);
74 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
75 return ((uint64_t)Imm) < 2;
77 let ParserMatchClass = VectorIndex32Operand;
78 let PrintMethod = "printVectorIndex";
79 let MIOperandInfo = (ops i32imm);
82 // Register list of one D register.
83 def VecListOneDAsmOperand : AsmOperandClass {
84 let Name = "VecListOneD";
85 let ParserMethod = "parseVectorList";
86 let RenderMethod = "addVecListOperands";
88 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
89 let ParserMatchClass = VecListOneDAsmOperand;
91 // Register list of two sequential D registers.
92 def VecListDPairAsmOperand : AsmOperandClass {
93 let Name = "VecListDPair";
94 let ParserMethod = "parseVectorList";
95 let RenderMethod = "addVecListOperands";
97 def VecListDPair : RegisterOperand<DPair, "printVectorListTwo"> {
98 let ParserMatchClass = VecListDPairAsmOperand;
100 // Register list of three sequential D registers.
101 def VecListThreeDAsmOperand : AsmOperandClass {
102 let Name = "VecListThreeD";
103 let ParserMethod = "parseVectorList";
104 let RenderMethod = "addVecListOperands";
106 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
107 let ParserMatchClass = VecListThreeDAsmOperand;
109 // Register list of four sequential D registers.
110 def VecListFourDAsmOperand : AsmOperandClass {
111 let Name = "VecListFourD";
112 let ParserMethod = "parseVectorList";
113 let RenderMethod = "addVecListOperands";
115 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
116 let ParserMatchClass = VecListFourDAsmOperand;
118 // Register list of two D registers spaced by 2 (two sequential Q registers).
119 def VecListDPairSpacedAsmOperand : AsmOperandClass {
120 let Name = "VecListDPairSpaced";
121 let ParserMethod = "parseVectorList";
122 let RenderMethod = "addVecListOperands";
124 def VecListDPairSpaced : RegisterOperand<DPair, "printVectorListTwoSpaced"> {
125 let ParserMatchClass = VecListDPairSpacedAsmOperand;
127 // Register list of three D registers spaced by 2 (three Q registers).
128 def VecListThreeQAsmOperand : AsmOperandClass {
129 let Name = "VecListThreeQ";
130 let ParserMethod = "parseVectorList";
131 let RenderMethod = "addVecListOperands";
133 def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> {
134 let ParserMatchClass = VecListThreeQAsmOperand;
136 // Register list of three D registers spaced by 2 (three Q registers).
137 def VecListFourQAsmOperand : AsmOperandClass {
138 let Name = "VecListFourQ";
139 let ParserMethod = "parseVectorList";
140 let RenderMethod = "addVecListOperands";
142 def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> {
143 let ParserMatchClass = VecListFourQAsmOperand;
146 // Register list of one D register, with "all lanes" subscripting.
147 def VecListOneDAllLanesAsmOperand : AsmOperandClass {
148 let Name = "VecListOneDAllLanes";
149 let ParserMethod = "parseVectorList";
150 let RenderMethod = "addVecListOperands";
152 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
153 let ParserMatchClass = VecListOneDAllLanesAsmOperand;
155 // Register list of two D registers, with "all lanes" subscripting.
156 def VecListDPairAllLanesAsmOperand : AsmOperandClass {
157 let Name = "VecListDPairAllLanes";
158 let ParserMethod = "parseVectorList";
159 let RenderMethod = "addVecListOperands";
161 def VecListDPairAllLanes : RegisterOperand<DPair,
162 "printVectorListTwoAllLanes"> {
163 let ParserMatchClass = VecListDPairAllLanesAsmOperand;
165 // Register list of two D registers spaced by 2 (two sequential Q registers).
166 def VecListDPairSpacedAllLanesAsmOperand : AsmOperandClass {
167 let Name = "VecListDPairSpacedAllLanes";
168 let ParserMethod = "parseVectorList";
169 let RenderMethod = "addVecListOperands";
171 def VecListDPairSpacedAllLanes : RegisterOperand<DPair,
172 "printVectorListTwoSpacedAllLanes"> {
173 let ParserMatchClass = VecListDPairSpacedAllLanesAsmOperand;
175 // Register list of three D registers, with "all lanes" subscripting.
176 def VecListThreeDAllLanesAsmOperand : AsmOperandClass {
177 let Name = "VecListThreeDAllLanes";
178 let ParserMethod = "parseVectorList";
179 let RenderMethod = "addVecListOperands";
181 def VecListThreeDAllLanes : RegisterOperand<DPR,
182 "printVectorListThreeAllLanes"> {
183 let ParserMatchClass = VecListThreeDAllLanesAsmOperand;
185 // Register list of three D registers spaced by 2 (three sequential Q regs).
186 def VecListThreeQAllLanesAsmOperand : AsmOperandClass {
187 let Name = "VecListThreeQAllLanes";
188 let ParserMethod = "parseVectorList";
189 let RenderMethod = "addVecListOperands";
191 def VecListThreeQAllLanes : RegisterOperand<DPR,
192 "printVectorListThreeSpacedAllLanes"> {
193 let ParserMatchClass = VecListThreeQAllLanesAsmOperand;
195 // Register list of four D registers, with "all lanes" subscripting.
196 def VecListFourDAllLanesAsmOperand : AsmOperandClass {
197 let Name = "VecListFourDAllLanes";
198 let ParserMethod = "parseVectorList";
199 let RenderMethod = "addVecListOperands";
201 def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> {
202 let ParserMatchClass = VecListFourDAllLanesAsmOperand;
204 // Register list of four D registers spaced by 2 (four sequential Q regs).
205 def VecListFourQAllLanesAsmOperand : AsmOperandClass {
206 let Name = "VecListFourQAllLanes";
207 let ParserMethod = "parseVectorList";
208 let RenderMethod = "addVecListOperands";
210 def VecListFourQAllLanes : RegisterOperand<DPR,
211 "printVectorListFourSpacedAllLanes"> {
212 let ParserMatchClass = VecListFourQAllLanesAsmOperand;
216 // Register list of one D register, with byte lane subscripting.
217 def VecListOneDByteIndexAsmOperand : AsmOperandClass {
218 let Name = "VecListOneDByteIndexed";
219 let ParserMethod = "parseVectorList";
220 let RenderMethod = "addVecListIndexedOperands";
222 def VecListOneDByteIndexed : Operand<i32> {
223 let ParserMatchClass = VecListOneDByteIndexAsmOperand;
224 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
226 // ...with half-word lane subscripting.
227 def VecListOneDHWordIndexAsmOperand : AsmOperandClass {
228 let Name = "VecListOneDHWordIndexed";
229 let ParserMethod = "parseVectorList";
230 let RenderMethod = "addVecListIndexedOperands";
232 def VecListOneDHWordIndexed : Operand<i32> {
233 let ParserMatchClass = VecListOneDHWordIndexAsmOperand;
234 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
236 // ...with word lane subscripting.
237 def VecListOneDWordIndexAsmOperand : AsmOperandClass {
238 let Name = "VecListOneDWordIndexed";
239 let ParserMethod = "parseVectorList";
240 let RenderMethod = "addVecListIndexedOperands";
242 def VecListOneDWordIndexed : Operand<i32> {
243 let ParserMatchClass = VecListOneDWordIndexAsmOperand;
244 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
247 // Register list of two D registers with byte lane subscripting.
248 def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
249 let Name = "VecListTwoDByteIndexed";
250 let ParserMethod = "parseVectorList";
251 let RenderMethod = "addVecListIndexedOperands";
253 def VecListTwoDByteIndexed : Operand<i32> {
254 let ParserMatchClass = VecListTwoDByteIndexAsmOperand;
255 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
257 // ...with half-word lane subscripting.
258 def VecListTwoDHWordIndexAsmOperand : AsmOperandClass {
259 let Name = "VecListTwoDHWordIndexed";
260 let ParserMethod = "parseVectorList";
261 let RenderMethod = "addVecListIndexedOperands";
263 def VecListTwoDHWordIndexed : Operand<i32> {
264 let ParserMatchClass = VecListTwoDHWordIndexAsmOperand;
265 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
267 // ...with word lane subscripting.
268 def VecListTwoDWordIndexAsmOperand : AsmOperandClass {
269 let Name = "VecListTwoDWordIndexed";
270 let ParserMethod = "parseVectorList";
271 let RenderMethod = "addVecListIndexedOperands";
273 def VecListTwoDWordIndexed : Operand<i32> {
274 let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
277 // Register list of two Q registers with half-word lane subscripting.
278 def VecListTwoQHWordIndexAsmOperand : AsmOperandClass {
279 let Name = "VecListTwoQHWordIndexed";
280 let ParserMethod = "parseVectorList";
281 let RenderMethod = "addVecListIndexedOperands";
283 def VecListTwoQHWordIndexed : Operand<i32> {
284 let ParserMatchClass = VecListTwoQHWordIndexAsmOperand;
285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
287 // ...with word lane subscripting.
288 def VecListTwoQWordIndexAsmOperand : AsmOperandClass {
289 let Name = "VecListTwoQWordIndexed";
290 let ParserMethod = "parseVectorList";
291 let RenderMethod = "addVecListIndexedOperands";
293 def VecListTwoQWordIndexed : Operand<i32> {
294 let ParserMatchClass = VecListTwoQWordIndexAsmOperand;
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
299 // Register list of three D registers with byte lane subscripting.
300 def VecListThreeDByteIndexAsmOperand : AsmOperandClass {
301 let Name = "VecListThreeDByteIndexed";
302 let ParserMethod = "parseVectorList";
303 let RenderMethod = "addVecListIndexedOperands";
305 def VecListThreeDByteIndexed : Operand<i32> {
306 let ParserMatchClass = VecListThreeDByteIndexAsmOperand;
307 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
309 // ...with half-word lane subscripting.
310 def VecListThreeDHWordIndexAsmOperand : AsmOperandClass {
311 let Name = "VecListThreeDHWordIndexed";
312 let ParserMethod = "parseVectorList";
313 let RenderMethod = "addVecListIndexedOperands";
315 def VecListThreeDHWordIndexed : Operand<i32> {
316 let ParserMatchClass = VecListThreeDHWordIndexAsmOperand;
317 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
319 // ...with word lane subscripting.
320 def VecListThreeDWordIndexAsmOperand : AsmOperandClass {
321 let Name = "VecListThreeDWordIndexed";
322 let ParserMethod = "parseVectorList";
323 let RenderMethod = "addVecListIndexedOperands";
325 def VecListThreeDWordIndexed : Operand<i32> {
326 let ParserMatchClass = VecListThreeDWordIndexAsmOperand;
327 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
329 // Register list of three Q registers with half-word lane subscripting.
330 def VecListThreeQHWordIndexAsmOperand : AsmOperandClass {
331 let Name = "VecListThreeQHWordIndexed";
332 let ParserMethod = "parseVectorList";
333 let RenderMethod = "addVecListIndexedOperands";
335 def VecListThreeQHWordIndexed : Operand<i32> {
336 let ParserMatchClass = VecListThreeQHWordIndexAsmOperand;
337 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
339 // ...with word lane subscripting.
340 def VecListThreeQWordIndexAsmOperand : AsmOperandClass {
341 let Name = "VecListThreeQWordIndexed";
342 let ParserMethod = "parseVectorList";
343 let RenderMethod = "addVecListIndexedOperands";
345 def VecListThreeQWordIndexed : Operand<i32> {
346 let ParserMatchClass = VecListThreeQWordIndexAsmOperand;
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
350 // Register list of four D registers with byte lane subscripting.
351 def VecListFourDByteIndexAsmOperand : AsmOperandClass {
352 let Name = "VecListFourDByteIndexed";
353 let ParserMethod = "parseVectorList";
354 let RenderMethod = "addVecListIndexedOperands";
356 def VecListFourDByteIndexed : Operand<i32> {
357 let ParserMatchClass = VecListFourDByteIndexAsmOperand;
358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
360 // ...with half-word lane subscripting.
361 def VecListFourDHWordIndexAsmOperand : AsmOperandClass {
362 let Name = "VecListFourDHWordIndexed";
363 let ParserMethod = "parseVectorList";
364 let RenderMethod = "addVecListIndexedOperands";
366 def VecListFourDHWordIndexed : Operand<i32> {
367 let ParserMatchClass = VecListFourDHWordIndexAsmOperand;
368 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
370 // ...with word lane subscripting.
371 def VecListFourDWordIndexAsmOperand : AsmOperandClass {
372 let Name = "VecListFourDWordIndexed";
373 let ParserMethod = "parseVectorList";
374 let RenderMethod = "addVecListIndexedOperands";
376 def VecListFourDWordIndexed : Operand<i32> {
377 let ParserMatchClass = VecListFourDWordIndexAsmOperand;
378 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
380 // Register list of four Q registers with half-word lane subscripting.
381 def VecListFourQHWordIndexAsmOperand : AsmOperandClass {
382 let Name = "VecListFourQHWordIndexed";
383 let ParserMethod = "parseVectorList";
384 let RenderMethod = "addVecListIndexedOperands";
386 def VecListFourQHWordIndexed : Operand<i32> {
387 let ParserMatchClass = VecListFourQHWordIndexAsmOperand;
388 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
390 // ...with word lane subscripting.
391 def VecListFourQWordIndexAsmOperand : AsmOperandClass {
392 let Name = "VecListFourQWordIndexed";
393 let ParserMethod = "parseVectorList";
394 let RenderMethod = "addVecListIndexedOperands";
396 def VecListFourQWordIndexed : Operand<i32> {
397 let ParserMatchClass = VecListFourQWordIndexAsmOperand;
398 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
401 def dword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
402 return cast<LoadSDNode>(N)->getAlignment() >= 8;
404 def dword_alignedstore : PatFrag<(ops node:$val, node:$ptr),
405 (store node:$val, node:$ptr), [{
406 return cast<StoreSDNode>(N)->getAlignment() >= 8;
408 def word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
409 return cast<LoadSDNode>(N)->getAlignment() == 4;
411 def word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
412 (store node:$val, node:$ptr), [{
413 return cast<StoreSDNode>(N)->getAlignment() == 4;
415 def hword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
416 return cast<LoadSDNode>(N)->getAlignment() == 2;
418 def hword_alignedstore : PatFrag<(ops node:$val, node:$ptr),
419 (store node:$val, node:$ptr), [{
420 return cast<StoreSDNode>(N)->getAlignment() == 2;
422 def byte_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
423 return cast<LoadSDNode>(N)->getAlignment() == 1;
425 def byte_alignedstore : PatFrag<(ops node:$val, node:$ptr),
426 (store node:$val, node:$ptr), [{
427 return cast<StoreSDNode>(N)->getAlignment() == 1;
429 def non_word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
430 return cast<LoadSDNode>(N)->getAlignment() < 4;
432 def non_word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
433 (store node:$val, node:$ptr), [{
434 return cast<StoreSDNode>(N)->getAlignment() < 4;
437 //===----------------------------------------------------------------------===//
438 // NEON-specific DAG Nodes.
439 //===----------------------------------------------------------------------===//
441 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
442 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
444 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
445 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
446 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
447 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
448 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
449 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
450 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
451 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
452 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
453 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
454 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
456 // Types for vector shift by immediates. The "SHX" version is for long and
457 // narrow operations where the source and destination vectors have different
458 // types. The "SHINS" version is for shift and insert operations.
459 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
461 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
463 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
464 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
466 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
467 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
468 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
469 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
470 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
471 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
472 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
474 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
475 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
476 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
478 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
479 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
480 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
481 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
482 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
483 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
485 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
486 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
487 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
489 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
490 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
492 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
494 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
495 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
497 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
498 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
499 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
500 def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
502 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
504 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
505 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
507 def NEONvbsl : SDNode<"ARMISD::VBSL",
508 SDTypeProfile<1, 3, [SDTCisVec<0>,
511 SDTCisSameAs<0, 3>]>>;
513 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
515 // VDUPLANE can produce a quad-register result from a double-register source,
516 // so the result is not constrained to match the source.
517 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
518 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
521 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
522 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
523 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
525 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
526 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
527 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
528 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
530 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
532 SDTCisSameAs<0, 3>]>;
533 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
534 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
535 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
537 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
538 SDTCisSameAs<1, 2>]>;
539 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
540 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
542 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
543 SDTCisSameAs<0, 2>]>;
544 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
545 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
547 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
548 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
549 unsigned EltBits = 0;
550 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
551 return (EltBits == 32 && EltVal == 0);
554 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
555 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
556 unsigned EltBits = 0;
557 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
558 return (EltBits == 8 && EltVal == 0xff);
561 //===----------------------------------------------------------------------===//
562 // NEON load / store instructions
563 //===----------------------------------------------------------------------===//
565 // Use VLDM to load a Q register as a D register pair.
566 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
568 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
570 [(set DPair:$dst, (v2f64 (load GPR:$Rn)))]>;
572 // Use VSTM to store a Q register as a D register pair.
573 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
575 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
577 [(store (v2f64 DPair:$src), GPR:$Rn)]>;
579 // Classes for VLD* pseudo-instructions with multi-register operands.
580 // These are expanded to real instructions after register allocation.
581 class VLDQPseudo<InstrItinClass itin>
582 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
583 class VLDQWBPseudo<InstrItinClass itin>
584 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
585 (ins addrmode6:$addr, am6offset:$offset), itin,
587 class VLDQWBfixedPseudo<InstrItinClass itin>
588 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
589 (ins addrmode6:$addr), itin,
591 class VLDQWBregisterPseudo<InstrItinClass itin>
592 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
593 (ins addrmode6:$addr, rGPR:$offset), itin,
596 class VLDQQPseudo<InstrItinClass itin>
597 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
598 class VLDQQWBPseudo<InstrItinClass itin>
599 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
600 (ins addrmode6:$addr, am6offset:$offset), itin,
602 class VLDQQWBfixedPseudo<InstrItinClass itin>
603 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
604 (ins addrmode6:$addr), itin,
606 class VLDQQWBregisterPseudo<InstrItinClass itin>
607 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
608 (ins addrmode6:$addr, rGPR:$offset), itin,
612 class VLDQQQQPseudo<InstrItinClass itin>
613 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
615 class VLDQQQQWBPseudo<InstrItinClass itin>
616 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
617 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
618 "$addr.addr = $wb, $src = $dst">;
620 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
622 // VLD1 : Vector Load (multiple single elements)
623 class VLD1D<bits<4> op7_4, string Dt>
624 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
625 (ins addrmode6:$Rn), IIC_VLD1,
626 "vld1", Dt, "$Vd, $Rn", "", []> {
629 let DecoderMethod = "DecodeVLDST1Instruction";
631 class VLD1Q<bits<4> op7_4, string Dt>
632 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
633 (ins addrmode6:$Rn), IIC_VLD1x2,
634 "vld1", Dt, "$Vd, $Rn", "", []> {
636 let Inst{5-4} = Rn{5-4};
637 let DecoderMethod = "DecodeVLDST1Instruction";
640 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
641 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
642 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
643 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
645 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
646 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
647 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
648 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
650 // ...with address register writeback:
651 multiclass VLD1DWB<bits<4> op7_4, string Dt> {
652 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
653 (ins addrmode6:$Rn), IIC_VLD1u,
654 "vld1", Dt, "$Vd, $Rn!",
655 "$Rn.addr = $wb", []> {
656 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
658 let DecoderMethod = "DecodeVLDST1Instruction";
660 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
661 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
662 "vld1", Dt, "$Vd, $Rn, $Rm",
663 "$Rn.addr = $wb", []> {
665 let DecoderMethod = "DecodeVLDST1Instruction";
668 multiclass VLD1QWB<bits<4> op7_4, string Dt> {
669 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
670 (ins addrmode6:$Rn), IIC_VLD1x2u,
671 "vld1", Dt, "$Vd, $Rn!",
672 "$Rn.addr = $wb", []> {
673 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
674 let Inst{5-4} = Rn{5-4};
675 let DecoderMethod = "DecodeVLDST1Instruction";
677 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
678 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
679 "vld1", Dt, "$Vd, $Rn, $Rm",
680 "$Rn.addr = $wb", []> {
681 let Inst{5-4} = Rn{5-4};
682 let DecoderMethod = "DecodeVLDST1Instruction";
686 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
687 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
688 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
689 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
690 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
691 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
692 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
693 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
695 // ...with 3 registers
696 class VLD1D3<bits<4> op7_4, string Dt>
697 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
698 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
699 "$Vd, $Rn", "", []> {
702 let DecoderMethod = "DecodeVLDST1Instruction";
704 multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
705 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
706 (ins addrmode6:$Rn), IIC_VLD1x2u,
707 "vld1", Dt, "$Vd, $Rn!",
708 "$Rn.addr = $wb", []> {
709 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
711 let DecoderMethod = "DecodeVLDST1Instruction";
713 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
714 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
715 "vld1", Dt, "$Vd, $Rn, $Rm",
716 "$Rn.addr = $wb", []> {
718 let DecoderMethod = "DecodeVLDST1Instruction";
722 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
723 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
724 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
725 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
727 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">;
728 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;
729 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;
730 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;
732 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
734 // ...with 4 registers
735 class VLD1D4<bits<4> op7_4, string Dt>
736 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
737 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
738 "$Vd, $Rn", "", []> {
740 let Inst{5-4} = Rn{5-4};
741 let DecoderMethod = "DecodeVLDST1Instruction";
743 multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
744 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
745 (ins addrmode6:$Rn), IIC_VLD1x2u,
746 "vld1", Dt, "$Vd, $Rn!",
747 "$Rn.addr = $wb", []> {
748 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
749 let Inst{5-4} = Rn{5-4};
750 let DecoderMethod = "DecodeVLDST1Instruction";
752 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
753 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
754 "vld1", Dt, "$Vd, $Rn, $Rm",
755 "$Rn.addr = $wb", []> {
756 let Inst{5-4} = Rn{5-4};
757 let DecoderMethod = "DecodeVLDST1Instruction";
761 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
762 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
763 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
764 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
766 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">;
767 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">;
768 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">;
769 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;
771 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
773 // VLD2 : Vector Load (multiple 2-element structures)
774 class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
776 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
777 (ins addrmode6:$Rn), itin,
778 "vld2", Dt, "$Vd, $Rn", "", []> {
780 let Inst{5-4} = Rn{5-4};
781 let DecoderMethod = "DecodeVLDST2Instruction";
784 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2>;
785 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2>;
786 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2>;
788 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>;
789 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>;
790 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>;
792 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
793 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
794 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
796 // ...with address register writeback:
797 multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
798 RegisterOperand VdTy, InstrItinClass itin> {
799 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
800 (ins addrmode6:$Rn), itin,
801 "vld2", Dt, "$Vd, $Rn!",
802 "$Rn.addr = $wb", []> {
803 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
804 let Inst{5-4} = Rn{5-4};
805 let DecoderMethod = "DecodeVLDST2Instruction";
807 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
808 (ins addrmode6:$Rn, rGPR:$Rm), itin,
809 "vld2", Dt, "$Vd, $Rn, $Rm",
810 "$Rn.addr = $wb", []> {
811 let Inst{5-4} = Rn{5-4};
812 let DecoderMethod = "DecodeVLDST2Instruction";
816 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u>;
817 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u>;
818 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u>;
820 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>;
821 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>;
822 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>;
824 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
825 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
826 def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
827 def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
828 def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
829 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
831 // ...with double-spaced registers
832 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2>;
833 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2>;
834 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2>;
835 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u>;
836 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u>;
837 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u>;
839 // VLD3 : Vector Load (multiple 3-element structures)
840 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
841 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
842 (ins addrmode6:$Rn), IIC_VLD3,
843 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
846 let DecoderMethod = "DecodeVLDST3Instruction";
849 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
850 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
851 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
853 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
854 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
855 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
857 // ...with address register writeback:
858 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
859 : NLdSt<0, 0b10, op11_8, op7_4,
860 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
861 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
862 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
863 "$Rn.addr = $wb", []> {
865 let DecoderMethod = "DecodeVLDST3Instruction";
868 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
869 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
870 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
872 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
873 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
874 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
876 // ...with double-spaced registers:
877 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
878 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
879 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
880 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
881 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
882 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
884 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
885 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
886 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
888 // ...alternate versions to be allocated odd register numbers:
889 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
890 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
891 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
893 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
894 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
895 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
897 // VLD4 : Vector Load (multiple 4-element structures)
898 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
899 : NLdSt<0, 0b10, op11_8, op7_4,
900 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
901 (ins addrmode6:$Rn), IIC_VLD4,
902 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
904 let Inst{5-4} = Rn{5-4};
905 let DecoderMethod = "DecodeVLDST4Instruction";
908 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
909 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
910 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
912 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
913 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
914 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
916 // ...with address register writeback:
917 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
918 : NLdSt<0, 0b10, op11_8, op7_4,
919 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
920 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
921 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
922 "$Rn.addr = $wb", []> {
923 let Inst{5-4} = Rn{5-4};
924 let DecoderMethod = "DecodeVLDST4Instruction";
927 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
928 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
929 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
931 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
932 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
933 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
935 // ...with double-spaced registers:
936 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
937 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
938 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
939 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
940 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
941 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
943 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
944 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
945 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
947 // ...alternate versions to be allocated odd register numbers:
948 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
949 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
950 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
952 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
953 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
954 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
956 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
958 // Classes for VLD*LN pseudo-instructions with multi-register operands.
959 // These are expanded to real instructions after register allocation.
960 class VLDQLNPseudo<InstrItinClass itin>
961 : PseudoNLdSt<(outs QPR:$dst),
962 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
963 itin, "$src = $dst">;
964 class VLDQLNWBPseudo<InstrItinClass itin>
965 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
966 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
967 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
968 class VLDQQLNPseudo<InstrItinClass itin>
969 : PseudoNLdSt<(outs QQPR:$dst),
970 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
971 itin, "$src = $dst">;
972 class VLDQQLNWBPseudo<InstrItinClass itin>
973 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
974 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
975 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
976 class VLDQQQQLNPseudo<InstrItinClass itin>
977 : PseudoNLdSt<(outs QQQQPR:$dst),
978 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
979 itin, "$src = $dst">;
980 class VLDQQQQLNWBPseudo<InstrItinClass itin>
981 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
982 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
983 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
985 // VLD1LN : Vector Load (single element to one lane)
986 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
988 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
989 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
990 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
992 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
993 (i32 (LoadOp addrmode6:$Rn)),
996 let DecoderMethod = "DecodeVLD1LN";
998 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1000 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1001 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
1002 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1004 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1005 (i32 (LoadOp addrmode6oneL32:$Rn)),
1008 let DecoderMethod = "DecodeVLD1LN";
1010 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
1011 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1012 (i32 (LoadOp addrmode6:$addr)),
1016 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
1017 let Inst{7-5} = lane{2-0};
1019 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
1020 let Inst{7-6} = lane{1-0};
1021 let Inst{5-4} = Rn{5-4};
1023 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
1024 let Inst{7} = lane{0};
1025 let Inst{5-4} = Rn{5-4};
1028 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
1029 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
1030 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1032 def : Pat<(vector_insert (v2f32 DPR:$src),
1033 (f32 (load addrmode6:$addr)), imm:$lane),
1034 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1035 def : Pat<(vector_insert (v4f32 QPR:$src),
1036 (f32 (load addrmode6:$addr)), imm:$lane),
1037 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1039 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1041 // ...with address register writeback:
1042 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1043 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
1044 (ins addrmode6:$Rn, am6offset:$Rm,
1045 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
1046 "\\{$Vd[$lane]\\}, $Rn$Rm",
1047 "$src = $Vd, $Rn.addr = $wb", []> {
1048 let DecoderMethod = "DecodeVLD1LN";
1051 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
1052 let Inst{7-5} = lane{2-0};
1054 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
1055 let Inst{7-6} = lane{1-0};
1056 let Inst{4} = Rn{4};
1058 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
1059 let Inst{7} = lane{0};
1060 let Inst{5} = Rn{4};
1061 let Inst{4} = Rn{4};
1064 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1065 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1066 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1068 // VLD2LN : Vector Load (single 2-element structure to one lane)
1069 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1070 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
1071 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1072 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1073 "$src1 = $Vd, $src2 = $dst2", []> {
1075 let Inst{4} = Rn{4};
1076 let DecoderMethod = "DecodeVLD2LN";
1079 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1080 let Inst{7-5} = lane{2-0};
1082 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
1083 let Inst{7-6} = lane{1-0};
1085 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
1086 let Inst{7} = lane{0};
1089 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1090 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1091 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1093 // ...with double-spaced registers:
1094 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
1095 let Inst{7-6} = lane{1-0};
1097 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
1098 let Inst{7} = lane{0};
1101 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1102 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1104 // ...with address register writeback:
1105 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1106 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1107 (ins addrmode6:$Rn, am6offset:$Rm,
1108 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
1109 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1110 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1111 let Inst{4} = Rn{4};
1112 let DecoderMethod = "DecodeVLD2LN";
1115 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
1116 let Inst{7-5} = lane{2-0};
1118 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
1119 let Inst{7-6} = lane{1-0};
1121 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
1122 let Inst{7} = lane{0};
1125 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1126 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1127 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1129 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
1130 let Inst{7-6} = lane{1-0};
1132 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
1133 let Inst{7} = lane{0};
1136 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1137 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1139 // VLD3LN : Vector Load (single 3-element structure to one lane)
1140 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1141 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1142 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
1143 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
1144 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1145 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
1147 let DecoderMethod = "DecodeVLD3LN";
1150 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
1151 let Inst{7-5} = lane{2-0};
1153 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
1154 let Inst{7-6} = lane{1-0};
1156 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
1157 let Inst{7} = lane{0};
1160 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1161 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1162 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1164 // ...with double-spaced registers:
1165 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
1166 let Inst{7-6} = lane{1-0};
1168 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
1169 let Inst{7} = lane{0};
1172 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1173 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1175 // ...with address register writeback:
1176 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1177 : NLdStLn<1, 0b10, op11_8, op7_4,
1178 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1179 (ins addrmode6:$Rn, am6offset:$Rm,
1180 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1181 IIC_VLD3lnu, "vld3", Dt,
1182 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1183 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1185 let DecoderMethod = "DecodeVLD3LN";
1188 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
1189 let Inst{7-5} = lane{2-0};
1191 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
1192 let Inst{7-6} = lane{1-0};
1194 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
1195 let Inst{7} = lane{0};
1198 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1199 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1200 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1202 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
1203 let Inst{7-6} = lane{1-0};
1205 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
1206 let Inst{7} = lane{0};
1209 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1210 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1212 // VLD4LN : Vector Load (single 4-element structure to one lane)
1213 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1214 : NLdStLn<1, 0b10, op11_8, op7_4,
1215 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1216 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1217 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1218 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1219 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1221 let Inst{4} = Rn{4};
1222 let DecoderMethod = "DecodeVLD4LN";
1225 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1226 let Inst{7-5} = lane{2-0};
1228 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1229 let Inst{7-6} = lane{1-0};
1231 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1232 let Inst{7} = lane{0};
1233 let Inst{5} = Rn{5};
1236 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1237 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1238 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1240 // ...with double-spaced registers:
1241 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1242 let Inst{7-6} = lane{1-0};
1244 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1245 let Inst{7} = lane{0};
1246 let Inst{5} = Rn{5};
1249 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1250 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1252 // ...with address register writeback:
1253 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1254 : NLdStLn<1, 0b10, op11_8, op7_4,
1255 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1256 (ins addrmode6:$Rn, am6offset:$Rm,
1257 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1258 IIC_VLD4lnu, "vld4", Dt,
1259 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1260 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1262 let Inst{4} = Rn{4};
1263 let DecoderMethod = "DecodeVLD4LN" ;
1266 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1267 let Inst{7-5} = lane{2-0};
1269 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1270 let Inst{7-6} = lane{1-0};
1272 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1273 let Inst{7} = lane{0};
1274 let Inst{5} = Rn{5};
1277 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1278 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1279 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1281 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1282 let Inst{7-6} = lane{1-0};
1284 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
1285 let Inst{7} = lane{0};
1286 let Inst{5} = Rn{5};
1289 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1290 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1292 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1294 // VLD1DUP : Vector Load (single element to all lanes)
1295 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1296 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1297 (ins addrmode6dup:$Rn),
1298 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1299 [(set VecListOneDAllLanes:$Vd,
1300 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1302 let Inst{4} = Rn{4};
1303 let DecoderMethod = "DecodeVLD1DupInstruction";
1305 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
1306 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
1307 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
1309 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1310 (VLD1DUPd32 addrmode6:$addr)>;
1312 class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1313 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1314 (ins addrmode6dup:$Rn), IIC_VLD1dup,
1315 "vld1", Dt, "$Vd, $Rn", "",
1316 [(set VecListDPairAllLanes:$Vd,
1317 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1319 let Inst{4} = Rn{4};
1320 let DecoderMethod = "DecodeVLD1DupInstruction";
1323 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8>;
1324 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16>;
1325 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load>;
1327 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1328 (VLD1DUPq32 addrmode6:$addr)>;
1330 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1331 // ...with address register writeback:
1332 multiclass VLD1DUPWB<bits<4> op7_4, string Dt> {
1333 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1334 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1335 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1336 "vld1", Dt, "$Vd, $Rn!",
1337 "$Rn.addr = $wb", []> {
1338 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1339 let Inst{4} = Rn{4};
1340 let DecoderMethod = "DecodeVLD1DupInstruction";
1342 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1343 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1344 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1345 "vld1", Dt, "$Vd, $Rn, $Rm",
1346 "$Rn.addr = $wb", []> {
1347 let Inst{4} = Rn{4};
1348 let DecoderMethod = "DecodeVLD1DupInstruction";
1351 multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
1352 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1353 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1354 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1355 "vld1", Dt, "$Vd, $Rn!",
1356 "$Rn.addr = $wb", []> {
1357 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1358 let Inst{4} = Rn{4};
1359 let DecoderMethod = "DecodeVLD1DupInstruction";
1361 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1362 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1363 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1364 "vld1", Dt, "$Vd, $Rn, $Rm",
1365 "$Rn.addr = $wb", []> {
1366 let Inst{4} = Rn{4};
1367 let DecoderMethod = "DecodeVLD1DupInstruction";
1371 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8">;
1372 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16">;
1373 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32">;
1375 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">;
1376 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">;
1377 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">;
1379 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1380 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy>
1381 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1382 (ins addrmode6dup:$Rn), IIC_VLD2dup,
1383 "vld2", Dt, "$Vd, $Rn", "", []> {
1385 let Inst{4} = Rn{4};
1386 let DecoderMethod = "DecodeVLD2DupInstruction";
1389 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes>;
1390 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes>;
1391 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes>;
1393 // ...with double-spaced registers
1394 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes>;
1395 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1396 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
1398 // ...with address register writeback:
1399 multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy> {
1400 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
1401 (outs VdTy:$Vd, GPR:$wb),
1402 (ins addrmode6dup:$Rn), IIC_VLD2dupu,
1403 "vld2", Dt, "$Vd, $Rn!",
1404 "$Rn.addr = $wb", []> {
1405 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1406 let Inst{4} = Rn{4};
1407 let DecoderMethod = "DecodeVLD2DupInstruction";
1409 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
1410 (outs VdTy:$Vd, GPR:$wb),
1411 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1412 "vld2", Dt, "$Vd, $Rn, $Rm",
1413 "$Rn.addr = $wb", []> {
1414 let Inst{4} = Rn{4};
1415 let DecoderMethod = "DecodeVLD2DupInstruction";
1419 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes>;
1420 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes>;
1421 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes>;
1423 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes>;
1424 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes>;
1425 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes>;
1427 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1428 class VLD3DUP<bits<4> op7_4, string Dt>
1429 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1430 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1431 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1434 let DecoderMethod = "DecodeVLD3DupInstruction";
1437 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1438 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1439 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1441 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1442 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1443 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1445 // ...with double-spaced registers (not used for codegen):
1446 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1447 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1448 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
1450 // ...with address register writeback:
1451 class VLD3DUPWB<bits<4> op7_4, string Dt>
1452 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1453 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1454 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1455 "$Rn.addr = $wb", []> {
1457 let DecoderMethod = "DecodeVLD3DupInstruction";
1460 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1461 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1462 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1464 def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1465 def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1466 def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1468 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1469 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1470 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1472 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1473 class VLD4DUP<bits<4> op7_4, string Dt>
1474 : NLdSt<1, 0b10, 0b1111, op7_4,
1475 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1476 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1477 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1479 let Inst{4} = Rn{4};
1480 let DecoderMethod = "DecodeVLD4DupInstruction";
1483 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1484 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1485 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1487 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1488 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1489 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1491 // ...with double-spaced registers (not used for codegen):
1492 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1493 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1494 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1496 // ...with address register writeback:
1497 class VLD4DUPWB<bits<4> op7_4, string Dt>
1498 : NLdSt<1, 0b10, 0b1111, op7_4,
1499 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1500 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1501 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1502 "$Rn.addr = $wb", []> {
1503 let Inst{4} = Rn{4};
1504 let DecoderMethod = "DecodeVLD4DupInstruction";
1507 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1508 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1509 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1511 def VLD4DUPq8_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1512 def VLD4DUPq16_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1513 def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1515 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1516 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1517 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1519 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1521 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1523 // Classes for VST* pseudo-instructions with multi-register operands.
1524 // These are expanded to real instructions after register allocation.
1525 class VSTQPseudo<InstrItinClass itin>
1526 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1527 class VSTQWBPseudo<InstrItinClass itin>
1528 : PseudoNLdSt<(outs GPR:$wb),
1529 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1530 "$addr.addr = $wb">;
1531 class VSTQWBfixedPseudo<InstrItinClass itin>
1532 : PseudoNLdSt<(outs GPR:$wb),
1533 (ins addrmode6:$addr, QPR:$src), itin,
1534 "$addr.addr = $wb">;
1535 class VSTQWBregisterPseudo<InstrItinClass itin>
1536 : PseudoNLdSt<(outs GPR:$wb),
1537 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1538 "$addr.addr = $wb">;
1539 class VSTQQPseudo<InstrItinClass itin>
1540 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1541 class VSTQQWBPseudo<InstrItinClass itin>
1542 : PseudoNLdSt<(outs GPR:$wb),
1543 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1544 "$addr.addr = $wb">;
1545 class VSTQQWBfixedPseudo<InstrItinClass itin>
1546 : PseudoNLdSt<(outs GPR:$wb),
1547 (ins addrmode6:$addr, QQPR:$src), itin,
1548 "$addr.addr = $wb">;
1549 class VSTQQWBregisterPseudo<InstrItinClass itin>
1550 : PseudoNLdSt<(outs GPR:$wb),
1551 (ins addrmode6:$addr, rGPR:$offset, QQPR:$src), itin,
1552 "$addr.addr = $wb">;
1554 class VSTQQQQPseudo<InstrItinClass itin>
1555 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1556 class VSTQQQQWBPseudo<InstrItinClass itin>
1557 : PseudoNLdSt<(outs GPR:$wb),
1558 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1559 "$addr.addr = $wb">;
1561 // VST1 : Vector Store (multiple single elements)
1562 class VST1D<bits<4> op7_4, string Dt>
1563 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
1564 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1566 let Inst{4} = Rn{4};
1567 let DecoderMethod = "DecodeVLDST1Instruction";
1569 class VST1Q<bits<4> op7_4, string Dt>
1570 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListDPair:$Vd),
1571 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1573 let Inst{5-4} = Rn{5-4};
1574 let DecoderMethod = "DecodeVLDST1Instruction";
1577 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1578 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1579 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1580 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1582 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1583 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1584 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1585 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1587 // ...with address register writeback:
1588 multiclass VST1DWB<bits<4> op7_4, string Dt> {
1589 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1590 (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1591 "vst1", Dt, "$Vd, $Rn!",
1592 "$Rn.addr = $wb", []> {
1593 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1594 let Inst{4} = Rn{4};
1595 let DecoderMethod = "DecodeVLDST1Instruction";
1597 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1598 (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1600 "vst1", Dt, "$Vd, $Rn, $Rm",
1601 "$Rn.addr = $wb", []> {
1602 let Inst{4} = Rn{4};
1603 let DecoderMethod = "DecodeVLDST1Instruction";
1606 multiclass VST1QWB<bits<4> op7_4, string Dt> {
1607 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1608 (ins addrmode6:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1609 "vst1", Dt, "$Vd, $Rn!",
1610 "$Rn.addr = $wb", []> {
1611 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1612 let Inst{5-4} = Rn{5-4};
1613 let DecoderMethod = "DecodeVLDST1Instruction";
1615 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1616 (ins addrmode6:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1618 "vst1", Dt, "$Vd, $Rn, $Rm",
1619 "$Rn.addr = $wb", []> {
1620 let Inst{5-4} = Rn{5-4};
1621 let DecoderMethod = "DecodeVLDST1Instruction";
1625 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;
1626 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;
1627 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;
1628 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;
1630 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;
1631 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
1632 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
1633 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
1635 // ...with 3 registers
1636 class VST1D3<bits<4> op7_4, string Dt>
1637 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1638 (ins addrmode6:$Rn, VecListThreeD:$Vd),
1639 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
1641 let Inst{4} = Rn{4};
1642 let DecoderMethod = "DecodeVLDST1Instruction";
1644 multiclass VST1D3WB<bits<4> op7_4, string Dt> {
1645 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1646 (ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1647 "vst1", Dt, "$Vd, $Rn!",
1648 "$Rn.addr = $wb", []> {
1649 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1650 let Inst{5-4} = Rn{5-4};
1651 let DecoderMethod = "DecodeVLDST1Instruction";
1653 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1654 (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1656 "vst1", Dt, "$Vd, $Rn, $Rm",
1657 "$Rn.addr = $wb", []> {
1658 let Inst{5-4} = Rn{5-4};
1659 let DecoderMethod = "DecodeVLDST1Instruction";
1663 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1664 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1665 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1666 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1668 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">;
1669 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">;
1670 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">;
1671 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">;
1673 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1674 def VST1d64TPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x3u>;
1675 def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
1677 // ...with 4 registers
1678 class VST1D4<bits<4> op7_4, string Dt>
1679 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1680 (ins addrmode6:$Rn, VecListFourD:$Vd),
1681 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1684 let Inst{5-4} = Rn{5-4};
1685 let DecoderMethod = "DecodeVLDST1Instruction";
1687 multiclass VST1D4WB<bits<4> op7_4, string Dt> {
1688 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1689 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1690 "vst1", Dt, "$Vd, $Rn!",
1691 "$Rn.addr = $wb", []> {
1692 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1693 let Inst{5-4} = Rn{5-4};
1694 let DecoderMethod = "DecodeVLDST1Instruction";
1696 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1697 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1699 "vst1", Dt, "$Vd, $Rn, $Rm",
1700 "$Rn.addr = $wb", []> {
1701 let Inst{5-4} = Rn{5-4};
1702 let DecoderMethod = "DecodeVLDST1Instruction";
1706 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1707 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1708 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1709 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1711 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">;
1712 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">;
1713 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">;
1714 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">;
1716 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1717 def VST1d64QPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x4u>;
1718 def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>;
1720 // VST2 : Vector Store (multiple 2-element structures)
1721 class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1722 InstrItinClass itin>
1723 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, VdTy:$Vd),
1724 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1726 let Inst{5-4} = Rn{5-4};
1727 let DecoderMethod = "DecodeVLDST2Instruction";
1730 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2>;
1731 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2>;
1732 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2>;
1734 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>;
1735 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>;
1736 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>;
1738 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1739 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1740 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1742 // ...with address register writeback:
1743 multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
1744 RegisterOperand VdTy> {
1745 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1746 (ins addrmode6:$Rn, VdTy:$Vd), IIC_VLD1u,
1747 "vst2", Dt, "$Vd, $Rn!",
1748 "$Rn.addr = $wb", []> {
1749 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1750 let Inst{5-4} = Rn{5-4};
1751 let DecoderMethod = "DecodeVLDST2Instruction";
1753 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1754 (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1755 "vst2", Dt, "$Vd, $Rn, $Rm",
1756 "$Rn.addr = $wb", []> {
1757 let Inst{5-4} = Rn{5-4};
1758 let DecoderMethod = "DecodeVLDST2Instruction";
1761 multiclass VST2QWB<bits<4> op7_4, string Dt> {
1762 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1763 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1764 "vst2", Dt, "$Vd, $Rn!",
1765 "$Rn.addr = $wb", []> {
1766 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1767 let Inst{5-4} = Rn{5-4};
1768 let DecoderMethod = "DecodeVLDST2Instruction";
1770 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1771 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1773 "vst2", Dt, "$Vd, $Rn, $Rm",
1774 "$Rn.addr = $wb", []> {
1775 let Inst{5-4} = Rn{5-4};
1776 let DecoderMethod = "DecodeVLDST2Instruction";
1780 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair>;
1781 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair>;
1782 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair>;
1784 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">;
1785 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">;
1786 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">;
1788 def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1789 def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1790 def VST2q32PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1791 def VST2q8PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1792 def VST2q16PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1793 def VST2q32PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1795 // ...with double-spaced registers
1796 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2>;
1797 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2>;
1798 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2>;
1799 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced>;
1800 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced>;
1801 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced>;
1803 // VST3 : Vector Store (multiple 3-element structures)
1804 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1805 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1806 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1807 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1809 let Inst{4} = Rn{4};
1810 let DecoderMethod = "DecodeVLDST3Instruction";
1813 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1814 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1815 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1817 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1818 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1819 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1821 // ...with address register writeback:
1822 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1823 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1824 (ins addrmode6:$Rn, am6offset:$Rm,
1825 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1826 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1827 "$Rn.addr = $wb", []> {
1828 let Inst{4} = Rn{4};
1829 let DecoderMethod = "DecodeVLDST3Instruction";
1832 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1833 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1834 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1836 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1837 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1838 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1840 // ...with double-spaced registers:
1841 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1842 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1843 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1844 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1845 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1846 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1848 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1849 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1850 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1852 // ...alternate versions to be allocated odd register numbers:
1853 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1854 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1855 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1857 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1858 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1859 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1861 // VST4 : Vector Store (multiple 4-element structures)
1862 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1863 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1864 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1865 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1868 let Inst{5-4} = Rn{5-4};
1869 let DecoderMethod = "DecodeVLDST4Instruction";
1872 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1873 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1874 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1876 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1877 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1878 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1880 // ...with address register writeback:
1881 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1882 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1883 (ins addrmode6:$Rn, am6offset:$Rm,
1884 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1885 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1886 "$Rn.addr = $wb", []> {
1887 let Inst{5-4} = Rn{5-4};
1888 let DecoderMethod = "DecodeVLDST4Instruction";
1891 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1892 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1893 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1895 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1896 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1897 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1899 // ...with double-spaced registers:
1900 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1901 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1902 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1903 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1904 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1905 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1907 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1908 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1909 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1911 // ...alternate versions to be allocated odd register numbers:
1912 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1913 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1914 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1916 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1917 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1918 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1920 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1922 // Classes for VST*LN pseudo-instructions with multi-register operands.
1923 // These are expanded to real instructions after register allocation.
1924 class VSTQLNPseudo<InstrItinClass itin>
1925 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1927 class VSTQLNWBPseudo<InstrItinClass itin>
1928 : PseudoNLdSt<(outs GPR:$wb),
1929 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1930 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1931 class VSTQQLNPseudo<InstrItinClass itin>
1932 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1934 class VSTQQLNWBPseudo<InstrItinClass itin>
1935 : PseudoNLdSt<(outs GPR:$wb),
1936 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1937 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1938 class VSTQQQQLNPseudo<InstrItinClass itin>
1939 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1941 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1942 : PseudoNLdSt<(outs GPR:$wb),
1943 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1944 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1946 // VST1LN : Vector Store (single element from one lane)
1947 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1948 PatFrag StoreOp, SDNode ExtractOp, Operand AddrMode>
1949 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1950 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
1951 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1952 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> {
1954 let DecoderMethod = "DecodeVST1LN";
1956 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1957 : VSTQLNPseudo<IIC_VST1ln> {
1958 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1962 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1963 NEONvgetlaneu, addrmode6> {
1964 let Inst{7-5} = lane{2-0};
1966 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1967 NEONvgetlaneu, addrmode6> {
1968 let Inst{7-6} = lane{1-0};
1969 let Inst{4} = Rn{4};
1972 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt,
1974 let Inst{7} = lane{0};
1975 let Inst{5-4} = Rn{5-4};
1978 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1979 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1980 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1982 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1983 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1984 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1985 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1987 // ...with address register writeback:
1988 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1989 PatFrag StoreOp, SDNode ExtractOp, Operand AdrMode>
1990 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1991 (ins AdrMode:$Rn, am6offset:$Rm,
1992 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1993 "\\{$Vd[$lane]\\}, $Rn$Rm",
1995 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1996 AdrMode:$Rn, am6offset:$Rm))]> {
1997 let DecoderMethod = "DecodeVST1LN";
1999 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
2000 : VSTQLNWBPseudo<IIC_VST1lnu> {
2001 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2002 addrmode6:$addr, am6offset:$offset))];
2005 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
2006 NEONvgetlaneu, addrmode6> {
2007 let Inst{7-5} = lane{2-0};
2009 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
2010 NEONvgetlaneu, addrmode6> {
2011 let Inst{7-6} = lane{1-0};
2012 let Inst{4} = Rn{4};
2014 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
2015 extractelt, addrmode6oneL32> {
2016 let Inst{7} = lane{0};
2017 let Inst{5-4} = Rn{5-4};
2020 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
2021 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
2022 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
2024 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2026 // VST2LN : Vector Store (single 2-element structure from one lane)
2027 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2028 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2029 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2030 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2033 let Inst{4} = Rn{4};
2034 let DecoderMethod = "DecodeVST2LN";
2037 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
2038 let Inst{7-5} = lane{2-0};
2040 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
2041 let Inst{7-6} = lane{1-0};
2043 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
2044 let Inst{7} = lane{0};
2047 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2048 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2049 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2051 // ...with double-spaced registers:
2052 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
2053 let Inst{7-6} = lane{1-0};
2054 let Inst{4} = Rn{4};
2056 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
2057 let Inst{7} = lane{0};
2058 let Inst{4} = Rn{4};
2061 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2062 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2064 // ...with address register writeback:
2065 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2066 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2067 (ins addrmode6:$Rn, am6offset:$Rm,
2068 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2069 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2070 "$Rn.addr = $wb", []> {
2071 let Inst{4} = Rn{4};
2072 let DecoderMethod = "DecodeVST2LN";
2075 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
2076 let Inst{7-5} = lane{2-0};
2078 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
2079 let Inst{7-6} = lane{1-0};
2081 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
2082 let Inst{7} = lane{0};
2085 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2086 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2087 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2089 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
2090 let Inst{7-6} = lane{1-0};
2092 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
2093 let Inst{7} = lane{0};
2096 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2097 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2099 // VST3LN : Vector Store (single 3-element structure from one lane)
2100 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2101 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2102 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2103 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
2104 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2106 let DecoderMethod = "DecodeVST3LN";
2109 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
2110 let Inst{7-5} = lane{2-0};
2112 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
2113 let Inst{7-6} = lane{1-0};
2115 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
2116 let Inst{7} = lane{0};
2119 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2120 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2121 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2123 // ...with double-spaced registers:
2124 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
2125 let Inst{7-6} = lane{1-0};
2127 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
2128 let Inst{7} = lane{0};
2131 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2132 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2134 // ...with address register writeback:
2135 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2136 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2137 (ins addrmode6:$Rn, am6offset:$Rm,
2138 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2139 IIC_VST3lnu, "vst3", Dt,
2140 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2141 "$Rn.addr = $wb", []> {
2142 let DecoderMethod = "DecodeVST3LN";
2145 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
2146 let Inst{7-5} = lane{2-0};
2148 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
2149 let Inst{7-6} = lane{1-0};
2151 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
2152 let Inst{7} = lane{0};
2155 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2156 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2157 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2159 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
2160 let Inst{7-6} = lane{1-0};
2162 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
2163 let Inst{7} = lane{0};
2166 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2167 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2169 // VST4LN : Vector Store (single 4-element structure from one lane)
2170 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2171 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2172 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2173 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2174 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2177 let Inst{4} = Rn{4};
2178 let DecoderMethod = "DecodeVST4LN";
2181 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
2182 let Inst{7-5} = lane{2-0};
2184 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
2185 let Inst{7-6} = lane{1-0};
2187 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2188 let Inst{7} = lane{0};
2189 let Inst{5} = Rn{5};
2192 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2193 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2194 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2196 // ...with double-spaced registers:
2197 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
2198 let Inst{7-6} = lane{1-0};
2200 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2201 let Inst{7} = lane{0};
2202 let Inst{5} = Rn{5};
2205 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2206 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2208 // ...with address register writeback:
2209 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2210 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2211 (ins addrmode6:$Rn, am6offset:$Rm,
2212 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2213 IIC_VST4lnu, "vst4", Dt,
2214 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2215 "$Rn.addr = $wb", []> {
2216 let Inst{4} = Rn{4};
2217 let DecoderMethod = "DecodeVST4LN";
2220 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
2221 let Inst{7-5} = lane{2-0};
2223 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
2224 let Inst{7-6} = lane{1-0};
2226 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2227 let Inst{7} = lane{0};
2228 let Inst{5} = Rn{5};
2231 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2232 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2233 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2235 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
2236 let Inst{7-6} = lane{1-0};
2238 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
2239 let Inst{7} = lane{0};
2240 let Inst{5} = Rn{5};
2243 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2244 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2246 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2248 // Use vld1/vst1 for unaligned f64 load / store
2249 def : Pat<(f64 (hword_alignedload addrmode6:$addr)),
2250 (VLD1d16 addrmode6:$addr)>, Requires<[IsLE]>;
2251 def : Pat<(hword_alignedstore (f64 DPR:$value), addrmode6:$addr),
2252 (VST1d16 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2253 def : Pat<(f64 (byte_alignedload addrmode6:$addr)),
2254 (VLD1d8 addrmode6:$addr)>, Requires<[IsLE]>;
2255 def : Pat<(byte_alignedstore (f64 DPR:$value), addrmode6:$addr),
2256 (VST1d8 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2257 def : Pat<(f64 (non_word_alignedload addrmode6:$addr)),
2258 (VLD1d64 addrmode6:$addr)>, Requires<[IsBE]>;
2259 def : Pat<(non_word_alignedstore (f64 DPR:$value), addrmode6:$addr),
2260 (VST1d64 addrmode6:$addr, DPR:$value)>, Requires<[IsBE]>;
2262 // Use vld1/vst1 for Q and QQ. Also use them for unaligned v2f64
2263 // load / store if it's legal.
2264 def : Pat<(v2f64 (dword_alignedload addrmode6:$addr)),
2265 (VLD1q64 addrmode6:$addr)>;
2266 def : Pat<(dword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2267 (VST1q64 addrmode6:$addr, QPR:$value)>;
2268 def : Pat<(v2f64 (word_alignedload addrmode6:$addr)),
2269 (VLD1q32 addrmode6:$addr)>;
2270 def : Pat<(word_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2271 (VST1q32 addrmode6:$addr, QPR:$value)>;
2272 def : Pat<(v2f64 (hword_alignedload addrmode6:$addr)),
2273 (VLD1q16 addrmode6:$addr)>, Requires<[IsLE]>;
2274 def : Pat<(hword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2275 (VST1q16 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2276 def : Pat<(v2f64 (byte_alignedload addrmode6:$addr)),
2277 (VLD1q8 addrmode6:$addr)>, Requires<[IsLE]>;
2278 def : Pat<(byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2279 (VST1q8 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2281 //===----------------------------------------------------------------------===//
2282 // NEON pattern fragments
2283 //===----------------------------------------------------------------------===//
2285 // Extract D sub-registers of Q registers.
2286 def DSubReg_i8_reg : SDNodeXForm<imm, [{
2287 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2288 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
2290 def DSubReg_i16_reg : SDNodeXForm<imm, [{
2291 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2292 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
2294 def DSubReg_i32_reg : SDNodeXForm<imm, [{
2295 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2296 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
2298 def DSubReg_f64_reg : SDNodeXForm<imm, [{
2299 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2300 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
2303 // Extract S sub-registers of Q/D registers.
2304 def SSubReg_f32_reg : SDNodeXForm<imm, [{
2305 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
2306 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
2309 // Translate lane numbers from Q registers to D subregs.
2310 def SubReg_i8_lane : SDNodeXForm<imm, [{
2311 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
2313 def SubReg_i16_lane : SDNodeXForm<imm, [{
2314 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
2316 def SubReg_i32_lane : SDNodeXForm<imm, [{
2317 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
2320 //===----------------------------------------------------------------------===//
2321 // Instruction Classes
2322 //===----------------------------------------------------------------------===//
2324 // Basic 2-register operations: double- and quad-register.
2325 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2326 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2327 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2328 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2329 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2330 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2331 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2332 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2333 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2334 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2335 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2336 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2338 // Basic 2-register intrinsics, both double- and quad-register.
2339 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2340 bits<2> op17_16, bits<5> op11_7, bit op4,
2341 InstrItinClass itin, string OpcodeStr, string Dt,
2342 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2343 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2344 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2345 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2346 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2347 bits<2> op17_16, bits<5> op11_7, bit op4,
2348 InstrItinClass itin, string OpcodeStr, string Dt,
2349 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2350 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2351 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2352 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2354 // Same as above, but not predicated.
2355 class N2VDIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
2356 InstrItinClass itin, string OpcodeStr, string Dt,
2357 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2358 : N2Vnp<0b10, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
2359 itin, OpcodeStr, Dt, ResTy, OpTy,
2360 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2362 class N2VQIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
2363 InstrItinClass itin, string OpcodeStr, string Dt,
2364 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2365 : N2Vnp<0b10, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
2366 itin, OpcodeStr, Dt, ResTy, OpTy,
2367 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2369 // Similar to NV2VQIntnp with some more encoding bits exposed (crypto).
2370 class N2VQIntXnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
2371 bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
2372 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2373 : N2Vnp<op19_18, op17_16, op10_8, op7, op6, (outs QPR:$Vd), (ins QPR:$Vm),
2374 itin, OpcodeStr, Dt, ResTy, OpTy,
2375 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2377 // Same as N2VQIntXnp but with Vd as a src register.
2378 class N2VQIntX2np<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
2379 bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
2380 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2381 : N2Vnp<op19_18, op17_16, op10_8, op7, op6,
2382 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vm),
2383 itin, OpcodeStr, Dt, ResTy, OpTy,
2384 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vm))))]> {
2385 let Constraints = "$src = $Vd";
2388 // Narrow 2-register operations.
2389 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2390 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2391 InstrItinClass itin, string OpcodeStr, string Dt,
2392 ValueType TyD, ValueType TyQ, SDNode OpNode>
2393 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2394 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2395 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2397 // Narrow 2-register intrinsics.
2398 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2399 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2400 InstrItinClass itin, string OpcodeStr, string Dt,
2401 ValueType TyD, ValueType TyQ, SDPatternOperator IntOp>
2402 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2403 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2404 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2406 // Long 2-register operations (currently only used for VMOVL).
2407 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2408 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2409 InstrItinClass itin, string OpcodeStr, string Dt,
2410 ValueType TyQ, ValueType TyD, SDNode OpNode>
2411 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2412 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2413 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2415 // Long 2-register intrinsics.
2416 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2417 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2418 InstrItinClass itin, string OpcodeStr, string Dt,
2419 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
2420 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2421 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2422 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2424 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2425 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
2426 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2427 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2428 OpcodeStr, Dt, "$Vd, $Vm",
2429 "$src1 = $Vd, $src2 = $Vm", []>;
2430 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
2431 InstrItinClass itin, string OpcodeStr, string Dt>
2432 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2433 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2434 "$src1 = $Vd, $src2 = $Vm", []>;
2436 // Basic 3-register operations: double- and quad-register.
2437 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2438 InstrItinClass itin, string OpcodeStr, string Dt,
2439 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2440 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2441 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2442 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2443 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2444 // All of these have a two-operand InstAlias.
2445 let TwoOperandAliasConstraint = "$Vn = $Vd";
2446 let isCommutable = Commutable;
2448 // Same as N3VD but no data type.
2449 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2450 InstrItinClass itin, string OpcodeStr,
2451 ValueType ResTy, ValueType OpTy,
2452 SDNode OpNode, bit Commutable>
2453 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
2454 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2455 OpcodeStr, "$Vd, $Vn, $Vm", "",
2456 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2457 // All of these have a two-operand InstAlias.
2458 let TwoOperandAliasConstraint = "$Vn = $Vd";
2459 let isCommutable = Commutable;
2462 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2463 InstrItinClass itin, string OpcodeStr, string Dt,
2464 ValueType Ty, SDNode ShOp>
2465 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2466 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2467 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2469 (Ty (ShOp (Ty DPR:$Vn),
2470 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2471 // All of these have a two-operand InstAlias.
2472 let TwoOperandAliasConstraint = "$Vn = $Vd";
2473 let isCommutable = 0;
2475 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2476 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2477 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2478 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2479 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2481 (Ty (ShOp (Ty DPR:$Vn),
2482 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2483 // All of these have a two-operand InstAlias.
2484 let TwoOperandAliasConstraint = "$Vn = $Vd";
2485 let isCommutable = 0;
2488 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2489 InstrItinClass itin, string OpcodeStr, string Dt,
2490 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2491 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2492 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2493 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2494 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2495 // All of these have a two-operand InstAlias.
2496 let TwoOperandAliasConstraint = "$Vn = $Vd";
2497 let isCommutable = Commutable;
2499 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2500 InstrItinClass itin, string OpcodeStr,
2501 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2502 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2503 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2504 OpcodeStr, "$Vd, $Vn, $Vm", "",
2505 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2506 // All of these have a two-operand InstAlias.
2507 let TwoOperandAliasConstraint = "$Vn = $Vd";
2508 let isCommutable = Commutable;
2510 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2511 InstrItinClass itin, string OpcodeStr, string Dt,
2512 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2513 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2514 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2515 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2516 [(set (ResTy QPR:$Vd),
2517 (ResTy (ShOp (ResTy QPR:$Vn),
2518 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2520 // All of these have a two-operand InstAlias.
2521 let TwoOperandAliasConstraint = "$Vn = $Vd";
2522 let isCommutable = 0;
2524 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2525 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2526 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2527 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2528 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2529 [(set (ResTy QPR:$Vd),
2530 (ResTy (ShOp (ResTy QPR:$Vn),
2531 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2533 // All of these have a two-operand InstAlias.
2534 let TwoOperandAliasConstraint = "$Vn = $Vd";
2535 let isCommutable = 0;
2538 // Basic 3-register intrinsics, both double- and quad-register.
2539 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2540 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2541 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2542 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2543 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2544 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2545 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2546 // All of these have a two-operand InstAlias.
2547 let TwoOperandAliasConstraint = "$Vn = $Vd";
2548 let isCommutable = Commutable;
2551 class N3VDIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2552 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2553 string Dt, ValueType ResTy, ValueType OpTy,
2554 SDPatternOperator IntOp, bit Commutable>
2555 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2556 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
2557 ResTy, OpTy, IntOp, Commutable,
2558 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2560 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2561 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
2562 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2563 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2564 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2566 (Ty (IntOp (Ty DPR:$Vn),
2567 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2569 let isCommutable = 0;
2572 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2573 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
2574 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2575 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2576 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2578 (Ty (IntOp (Ty DPR:$Vn),
2579 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2580 let isCommutable = 0;
2582 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2583 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2584 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2585 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2586 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2587 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2588 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2589 let TwoOperandAliasConstraint = "$Vm = $Vd";
2590 let isCommutable = 0;
2593 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2594 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2595 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2596 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2597 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2598 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2599 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2600 // All of these have a two-operand InstAlias.
2601 let TwoOperandAliasConstraint = "$Vn = $Vd";
2602 let isCommutable = Commutable;
2605 class N3VQIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2606 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2607 string Dt, ValueType ResTy, ValueType OpTy,
2608 SDPatternOperator IntOp, bit Commutable>
2609 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2610 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
2611 ResTy, OpTy, IntOp, Commutable,
2612 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2614 // Same as N3VQIntnp but with Vd as a src register.
2615 class N3VQInt3np<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2616 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2617 string Dt, ValueType ResTy, ValueType OpTy,
2618 SDPatternOperator IntOp, bit Commutable>
2619 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2620 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr,
2621 Dt, ResTy, OpTy, IntOp, Commutable,
2622 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
2623 (OpTy QPR:$Vm))))]> {
2624 let Constraints = "$src = $Vd";
2627 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2628 string OpcodeStr, string Dt,
2629 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2630 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2631 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2632 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2633 [(set (ResTy QPR:$Vd),
2634 (ResTy (IntOp (ResTy QPR:$Vn),
2635 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2637 let isCommutable = 0;
2639 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2640 string OpcodeStr, string Dt,
2641 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2642 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2643 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2644 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2645 [(set (ResTy QPR:$Vd),
2646 (ResTy (IntOp (ResTy QPR:$Vn),
2647 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2649 let isCommutable = 0;
2651 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2652 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2653 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2654 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2655 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2656 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2657 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2658 let TwoOperandAliasConstraint = "$Vm = $Vd";
2659 let isCommutable = 0;
2662 // Multiply-Add/Sub operations: double- and quad-register.
2663 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2664 InstrItinClass itin, string OpcodeStr, string Dt,
2665 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2666 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2667 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2668 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2669 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2670 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2672 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2673 string OpcodeStr, string Dt,
2674 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2675 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2677 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2679 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2681 (Ty (ShOp (Ty DPR:$src1),
2683 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2685 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2686 string OpcodeStr, string Dt,
2687 ValueType Ty, SDNode MulOp, SDNode ShOp>
2688 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2690 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2692 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2694 (Ty (ShOp (Ty DPR:$src1),
2696 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2699 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2700 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2701 SDPatternOperator MulOp, SDPatternOperator OpNode>
2702 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2703 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2704 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2705 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2706 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2707 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2708 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2709 SDPatternOperator MulOp, SDPatternOperator ShOp>
2710 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2712 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2714 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2715 [(set (ResTy QPR:$Vd),
2716 (ResTy (ShOp (ResTy QPR:$src1),
2717 (ResTy (MulOp QPR:$Vn,
2718 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2720 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2721 string OpcodeStr, string Dt,
2722 ValueType ResTy, ValueType OpTy,
2723 SDNode MulOp, SDNode ShOp>
2724 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2726 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2728 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2729 [(set (ResTy QPR:$Vd),
2730 (ResTy (ShOp (ResTy QPR:$src1),
2731 (ResTy (MulOp QPR:$Vn,
2732 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2735 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2736 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2737 InstrItinClass itin, string OpcodeStr, string Dt,
2738 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
2739 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2740 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2741 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2742 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2743 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2744 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2745 InstrItinClass itin, string OpcodeStr, string Dt,
2746 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
2747 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2748 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2749 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2750 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2751 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2753 // Neon 3-argument intrinsics, both double- and quad-register.
2754 // The destination register is also used as the first source operand register.
2755 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2756 InstrItinClass itin, string OpcodeStr, string Dt,
2757 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2758 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2759 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2760 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2761 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2762 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2763 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2764 InstrItinClass itin, string OpcodeStr, string Dt,
2765 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2766 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2767 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2768 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2769 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2770 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2772 // Long Multiply-Add/Sub operations.
2773 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2774 InstrItinClass itin, string OpcodeStr, string Dt,
2775 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2776 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2777 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2778 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2779 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2780 (TyQ (MulOp (TyD DPR:$Vn),
2781 (TyD DPR:$Vm)))))]>;
2782 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2783 InstrItinClass itin, string OpcodeStr, string Dt,
2784 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2785 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2786 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2788 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2790 (OpNode (TyQ QPR:$src1),
2791 (TyQ (MulOp (TyD DPR:$Vn),
2792 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2794 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2795 InstrItinClass itin, string OpcodeStr, string Dt,
2796 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2797 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2798 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2800 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2802 (OpNode (TyQ QPR:$src1),
2803 (TyQ (MulOp (TyD DPR:$Vn),
2804 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2807 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2808 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2809 InstrItinClass itin, string OpcodeStr, string Dt,
2810 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
2812 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2813 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2814 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2815 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2816 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2817 (TyD DPR:$Vm)))))))]>;
2819 // Neon Long 3-argument intrinsic. The destination register is
2820 // a quad-register and is also used as the first source operand register.
2821 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2822 InstrItinClass itin, string OpcodeStr, string Dt,
2823 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
2824 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2825 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2826 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2828 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2829 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2830 string OpcodeStr, string Dt,
2831 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2832 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2834 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2836 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2837 [(set (ResTy QPR:$Vd),
2838 (ResTy (IntOp (ResTy QPR:$src1),
2840 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2842 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2843 InstrItinClass itin, string OpcodeStr, string Dt,
2844 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2845 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2847 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2849 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2850 [(set (ResTy QPR:$Vd),
2851 (ResTy (IntOp (ResTy QPR:$src1),
2853 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2856 // Narrowing 3-register intrinsics.
2857 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2858 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2859 SDPatternOperator IntOp, bit Commutable>
2860 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2861 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2862 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2863 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2864 let isCommutable = Commutable;
2867 // Long 3-register operations.
2868 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2869 InstrItinClass itin, string OpcodeStr, string Dt,
2870 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2871 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2872 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2873 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2874 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2875 let isCommutable = Commutable;
2878 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2879 InstrItinClass itin, string OpcodeStr, string Dt,
2880 ValueType TyQ, ValueType TyD, SDNode OpNode>
2881 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2882 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2883 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2885 (TyQ (OpNode (TyD DPR:$Vn),
2886 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2887 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2888 InstrItinClass itin, string OpcodeStr, string Dt,
2889 ValueType TyQ, ValueType TyD, SDNode OpNode>
2890 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2891 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2892 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2894 (TyQ (OpNode (TyD DPR:$Vn),
2895 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2897 // Long 3-register operations with explicitly extended operands.
2898 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2899 InstrItinClass itin, string OpcodeStr, string Dt,
2900 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2902 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2903 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2904 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2905 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2906 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2907 let isCommutable = Commutable;
2910 // Long 3-register intrinsics with explicit extend (VABDL).
2911 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2912 InstrItinClass itin, string OpcodeStr, string Dt,
2913 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
2915 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2916 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2917 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2918 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2919 (TyD DPR:$Vm))))))]> {
2920 let isCommutable = Commutable;
2923 // Long 3-register intrinsics.
2924 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2925 InstrItinClass itin, string OpcodeStr, string Dt,
2926 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, bit Commutable>
2927 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2928 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2929 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2930 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2931 let isCommutable = Commutable;
2934 // Same as above, but not predicated.
2935 class N3VLIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2936 bit op4, InstrItinClass itin, string OpcodeStr,
2937 string Dt, ValueType ResTy, ValueType OpTy,
2938 SDPatternOperator IntOp, bit Commutable>
2939 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2940 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
2941 ResTy, OpTy, IntOp, Commutable,
2942 [(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2944 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2945 string OpcodeStr, string Dt,
2946 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2947 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2948 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2949 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2950 [(set (ResTy QPR:$Vd),
2951 (ResTy (IntOp (OpTy DPR:$Vn),
2952 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2954 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2955 InstrItinClass itin, string OpcodeStr, string Dt,
2956 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2957 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2958 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2959 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2960 [(set (ResTy QPR:$Vd),
2961 (ResTy (IntOp (OpTy DPR:$Vn),
2962 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2965 // Wide 3-register operations.
2966 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2967 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2968 SDNode OpNode, SDNode ExtOp, bit Commutable>
2969 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2970 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2971 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2972 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2973 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2974 // All of these have a two-operand InstAlias.
2975 let TwoOperandAliasConstraint = "$Vn = $Vd";
2976 let isCommutable = Commutable;
2979 // Pairwise long 2-register intrinsics, both double- and quad-register.
2980 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2981 bits<2> op17_16, bits<5> op11_7, bit op4,
2982 string OpcodeStr, string Dt,
2983 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2984 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2985 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2986 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2987 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2988 bits<2> op17_16, bits<5> op11_7, bit op4,
2989 string OpcodeStr, string Dt,
2990 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2991 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2992 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2993 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2995 // Pairwise long 2-register accumulate intrinsics,
2996 // both double- and quad-register.
2997 // The destination register is also used as the first source operand register.
2998 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2999 bits<2> op17_16, bits<5> op11_7, bit op4,
3000 string OpcodeStr, string Dt,
3001 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3002 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
3003 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
3004 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3005 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
3006 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3007 bits<2> op17_16, bits<5> op11_7, bit op4,
3008 string OpcodeStr, string Dt,
3009 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3010 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
3011 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
3012 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3013 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
3015 // Shift by immediate,
3016 // both double- and quad-register.
3017 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3018 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3019 Format f, InstrItinClass itin, Operand ImmTy,
3020 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
3021 : N2VImm<op24, op23, op11_8, op7, 0, op4,
3022 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
3023 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3024 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
3025 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3026 Format f, InstrItinClass itin, Operand ImmTy,
3027 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
3028 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3029 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3030 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3031 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
3034 // Long shift by immediate.
3035 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
3036 string OpcodeStr, string Dt,
3037 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
3038 : N2VImm<op24, op23, op11_8, op7, op6, op4,
3039 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3040 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3041 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
3042 (i32 imm:$SIMM))))]>;
3044 // Narrow shift by immediate.
3045 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
3046 InstrItinClass itin, string OpcodeStr, string Dt,
3047 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
3048 : N2VImm<op24, op23, op11_8, op7, op6, op4,
3049 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3050 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3051 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
3052 (i32 imm:$SIMM))))]>;
3054 // Shift right by immediate and accumulate,
3055 // both double- and quad-register.
3056 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3057 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3058 Operand ImmTy, string OpcodeStr, string Dt,
3059 ValueType Ty, SDNode ShOp>
3060 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3061 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3062 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3063 [(set DPR:$Vd, (Ty (add DPR:$src1,
3064 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
3065 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3066 Operand ImmTy, string OpcodeStr, string Dt,
3067 ValueType Ty, SDNode ShOp>
3068 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3069 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3070 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3071 [(set QPR:$Vd, (Ty (add QPR:$src1,
3072 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
3075 // Shift by immediate and insert,
3076 // both double- and quad-register.
3077 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3078 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3079 Operand ImmTy, Format f, string OpcodeStr, string Dt,
3080 ValueType Ty,SDNode ShOp>
3081 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3082 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
3083 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3084 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
3085 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3086 Operand ImmTy, Format f, string OpcodeStr, string Dt,
3087 ValueType Ty,SDNode ShOp>
3088 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3089 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
3090 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3091 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
3094 // Convert, with fractional bits immediate,
3095 // both double- and quad-register.
3096 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3097 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
3098 SDPatternOperator IntOp>
3099 : N2VImm<op24, op23, op11_8, op7, 0, op4,
3100 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3101 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3102 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
3103 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3104 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
3105 SDPatternOperator IntOp>
3106 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3107 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3108 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3109 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
3111 //===----------------------------------------------------------------------===//
3113 //===----------------------------------------------------------------------===//
3115 // Abbreviations used in multiclass suffixes:
3116 // Q = quarter int (8 bit) elements
3117 // H = half int (16 bit) elements
3118 // S = single int (32 bit) elements
3119 // D = double int (64 bit) elements
3121 // Neon 2-register vector operations and intrinsics.
3123 // Neon 2-register comparisons.
3124 // source operand element sizes of 8, 16 and 32 bits:
3125 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3126 bits<5> op11_7, bit op4, string opc, string Dt,
3127 string asm, SDNode OpNode> {
3128 // 64-bit vector types.
3129 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
3130 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3131 opc, !strconcat(Dt, "8"), asm, "",
3132 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
3133 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3134 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3135 opc, !strconcat(Dt, "16"), asm, "",
3136 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
3137 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3138 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3139 opc, !strconcat(Dt, "32"), asm, "",
3140 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
3141 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3142 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3143 opc, "f32", asm, "",
3144 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
3145 let Inst{10} = 1; // overwrite F = 1
3148 // 128-bit vector types.
3149 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
3150 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3151 opc, !strconcat(Dt, "8"), asm, "",
3152 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
3153 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3154 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3155 opc, !strconcat(Dt, "16"), asm, "",
3156 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
3157 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3158 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3159 opc, !strconcat(Dt, "32"), asm, "",
3160 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
3161 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3162 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3163 opc, "f32", asm, "",
3164 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
3165 let Inst{10} = 1; // overwrite F = 1
3170 // Neon 2-register vector intrinsics,
3171 // element sizes of 8, 16 and 32 bits:
3172 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3173 bits<5> op11_7, bit op4,
3174 InstrItinClass itinD, InstrItinClass itinQ,
3175 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3176 // 64-bit vector types.
3177 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3178 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3179 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3180 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
3181 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3182 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
3184 // 128-bit vector types.
3185 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3186 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
3187 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3188 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
3189 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3190 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
3194 // Neon Narrowing 2-register vector operations,
3195 // source operand element sizes of 16, 32 and 64 bits:
3196 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3197 bits<5> op11_7, bit op6, bit op4,
3198 InstrItinClass itin, string OpcodeStr, string Dt,
3200 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3201 itin, OpcodeStr, !strconcat(Dt, "16"),
3202 v8i8, v8i16, OpNode>;
3203 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3204 itin, OpcodeStr, !strconcat(Dt, "32"),
3205 v4i16, v4i32, OpNode>;
3206 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3207 itin, OpcodeStr, !strconcat(Dt, "64"),
3208 v2i32, v2i64, OpNode>;
3211 // Neon Narrowing 2-register vector intrinsics,
3212 // source operand element sizes of 16, 32 and 64 bits:
3213 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3214 bits<5> op11_7, bit op6, bit op4,
3215 InstrItinClass itin, string OpcodeStr, string Dt,
3216 SDPatternOperator IntOp> {
3217 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3218 itin, OpcodeStr, !strconcat(Dt, "16"),
3219 v8i8, v8i16, IntOp>;
3220 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3221 itin, OpcodeStr, !strconcat(Dt, "32"),
3222 v4i16, v4i32, IntOp>;
3223 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3224 itin, OpcodeStr, !strconcat(Dt, "64"),
3225 v2i32, v2i64, IntOp>;
3229 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
3230 // source operand element sizes of 16, 32 and 64 bits:
3231 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
3232 string OpcodeStr, string Dt, SDNode OpNode> {
3233 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3234 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
3235 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3236 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3237 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3238 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3242 // Neon 3-register vector operations.
3244 // First with only element sizes of 8, 16 and 32 bits:
3245 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3246 InstrItinClass itinD16, InstrItinClass itinD32,
3247 InstrItinClass itinQ16, InstrItinClass itinQ32,
3248 string OpcodeStr, string Dt,
3249 SDNode OpNode, bit Commutable = 0> {
3250 // 64-bit vector types.
3251 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
3252 OpcodeStr, !strconcat(Dt, "8"),
3253 v8i8, v8i8, OpNode, Commutable>;
3254 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
3255 OpcodeStr, !strconcat(Dt, "16"),
3256 v4i16, v4i16, OpNode, Commutable>;
3257 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
3258 OpcodeStr, !strconcat(Dt, "32"),
3259 v2i32, v2i32, OpNode, Commutable>;
3261 // 128-bit vector types.
3262 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
3263 OpcodeStr, !strconcat(Dt, "8"),
3264 v16i8, v16i8, OpNode, Commutable>;
3265 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3266 OpcodeStr, !strconcat(Dt, "16"),
3267 v8i16, v8i16, OpNode, Commutable>;
3268 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
3269 OpcodeStr, !strconcat(Dt, "32"),
3270 v4i32, v4i32, OpNode, Commutable>;
3273 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
3274 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
3275 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>;
3276 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3277 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
3278 v4i32, v2i32, ShOp>;
3281 // ....then also with element size 64 bits:
3282 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3283 InstrItinClass itinD, InstrItinClass itinQ,
3284 string OpcodeStr, string Dt,
3285 SDNode OpNode, bit Commutable = 0>
3286 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
3287 OpcodeStr, Dt, OpNode, Commutable> {
3288 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
3289 OpcodeStr, !strconcat(Dt, "64"),
3290 v1i64, v1i64, OpNode, Commutable>;
3291 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
3292 OpcodeStr, !strconcat(Dt, "64"),
3293 v2i64, v2i64, OpNode, Commutable>;
3297 // Neon 3-register vector intrinsics.
3299 // First with only element sizes of 16 and 32 bits:
3300 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3301 InstrItinClass itinD16, InstrItinClass itinD32,
3302 InstrItinClass itinQ16, InstrItinClass itinQ32,
3303 string OpcodeStr, string Dt,
3304 SDPatternOperator IntOp, bit Commutable = 0> {
3305 // 64-bit vector types.
3306 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
3307 OpcodeStr, !strconcat(Dt, "16"),
3308 v4i16, v4i16, IntOp, Commutable>;
3309 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
3310 OpcodeStr, !strconcat(Dt, "32"),
3311 v2i32, v2i32, IntOp, Commutable>;
3313 // 128-bit vector types.
3314 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3315 OpcodeStr, !strconcat(Dt, "16"),
3316 v8i16, v8i16, IntOp, Commutable>;
3317 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3318 OpcodeStr, !strconcat(Dt, "32"),
3319 v4i32, v4i32, IntOp, Commutable>;
3321 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3322 InstrItinClass itinD16, InstrItinClass itinD32,
3323 InstrItinClass itinQ16, InstrItinClass itinQ32,
3324 string OpcodeStr, string Dt,
3325 SDPatternOperator IntOp> {
3326 // 64-bit vector types.
3327 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3328 OpcodeStr, !strconcat(Dt, "16"),
3329 v4i16, v4i16, IntOp>;
3330 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
3331 OpcodeStr, !strconcat(Dt, "32"),
3332 v2i32, v2i32, IntOp>;
3334 // 128-bit vector types.
3335 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3336 OpcodeStr, !strconcat(Dt, "16"),
3337 v8i16, v8i16, IntOp>;
3338 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3339 OpcodeStr, !strconcat(Dt, "32"),
3340 v4i32, v4i32, IntOp>;
3343 multiclass N3VIntSL_HS<bits<4> op11_8,
3344 InstrItinClass itinD16, InstrItinClass itinD32,
3345 InstrItinClass itinQ16, InstrItinClass itinQ32,
3346 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3347 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
3348 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
3349 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
3350 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
3351 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3352 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3353 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
3354 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
3357 // ....then also with element size of 8 bits:
3358 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3359 InstrItinClass itinD16, InstrItinClass itinD32,
3360 InstrItinClass itinQ16, InstrItinClass itinQ32,
3361 string OpcodeStr, string Dt,
3362 SDPatternOperator IntOp, bit Commutable = 0>
3363 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3364 OpcodeStr, Dt, IntOp, Commutable> {
3365 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
3366 OpcodeStr, !strconcat(Dt, "8"),
3367 v8i8, v8i8, IntOp, Commutable>;
3368 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3369 OpcodeStr, !strconcat(Dt, "8"),
3370 v16i8, v16i8, IntOp, Commutable>;
3372 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3373 InstrItinClass itinD16, InstrItinClass itinD32,
3374 InstrItinClass itinQ16, InstrItinClass itinQ32,
3375 string OpcodeStr, string Dt,
3376 SDPatternOperator IntOp>
3377 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3378 OpcodeStr, Dt, IntOp> {
3379 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
3380 OpcodeStr, !strconcat(Dt, "8"),
3382 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3383 OpcodeStr, !strconcat(Dt, "8"),
3384 v16i8, v16i8, IntOp>;
3388 // ....then also with element size of 64 bits:
3389 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3390 InstrItinClass itinD16, InstrItinClass itinD32,
3391 InstrItinClass itinQ16, InstrItinClass itinQ32,
3392 string OpcodeStr, string Dt,
3393 SDPatternOperator IntOp, bit Commutable = 0>
3394 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3395 OpcodeStr, Dt, IntOp, Commutable> {
3396 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3397 OpcodeStr, !strconcat(Dt, "64"),
3398 v1i64, v1i64, IntOp, Commutable>;
3399 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3400 OpcodeStr, !strconcat(Dt, "64"),
3401 v2i64, v2i64, IntOp, Commutable>;
3403 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3404 InstrItinClass itinD16, InstrItinClass itinD32,
3405 InstrItinClass itinQ16, InstrItinClass itinQ32,
3406 string OpcodeStr, string Dt,
3407 SDPatternOperator IntOp>
3408 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3409 OpcodeStr, Dt, IntOp> {
3410 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3411 OpcodeStr, !strconcat(Dt, "64"),
3412 v1i64, v1i64, IntOp>;
3413 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3414 OpcodeStr, !strconcat(Dt, "64"),
3415 v2i64, v2i64, IntOp>;
3418 // Neon Narrowing 3-register vector intrinsics,
3419 // source operand element sizes of 16, 32 and 64 bits:
3420 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3421 string OpcodeStr, string Dt,
3422 SDPatternOperator IntOp, bit Commutable = 0> {
3423 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
3424 OpcodeStr, !strconcat(Dt, "16"),
3425 v8i8, v8i16, IntOp, Commutable>;
3426 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3427 OpcodeStr, !strconcat(Dt, "32"),
3428 v4i16, v4i32, IntOp, Commutable>;
3429 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
3430 OpcodeStr, !strconcat(Dt, "64"),
3431 v2i32, v2i64, IntOp, Commutable>;
3435 // Neon Long 3-register vector operations.
3437 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3438 InstrItinClass itin16, InstrItinClass itin32,
3439 string OpcodeStr, string Dt,
3440 SDNode OpNode, bit Commutable = 0> {
3441 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3442 OpcodeStr, !strconcat(Dt, "8"),
3443 v8i16, v8i8, OpNode, Commutable>;
3444 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3445 OpcodeStr, !strconcat(Dt, "16"),
3446 v4i32, v4i16, OpNode, Commutable>;
3447 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
3448 OpcodeStr, !strconcat(Dt, "32"),
3449 v2i64, v2i32, OpNode, Commutable>;
3452 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
3453 InstrItinClass itin, string OpcodeStr, string Dt,
3455 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3456 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3457 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
3458 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3461 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3462 InstrItinClass itin16, InstrItinClass itin32,
3463 string OpcodeStr, string Dt,
3464 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3465 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3466 OpcodeStr, !strconcat(Dt, "8"),
3467 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3468 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3469 OpcodeStr, !strconcat(Dt, "16"),
3470 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3471 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3472 OpcodeStr, !strconcat(Dt, "32"),
3473 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3476 // Neon Long 3-register vector intrinsics.
3478 // First with only element sizes of 16 and 32 bits:
3479 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3480 InstrItinClass itin16, InstrItinClass itin32,
3481 string OpcodeStr, string Dt,
3482 SDPatternOperator IntOp, bit Commutable = 0> {
3483 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3484 OpcodeStr, !strconcat(Dt, "16"),
3485 v4i32, v4i16, IntOp, Commutable>;
3486 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
3487 OpcodeStr, !strconcat(Dt, "32"),
3488 v2i64, v2i32, IntOp, Commutable>;
3491 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
3492 InstrItinClass itin, string OpcodeStr, string Dt,
3493 SDPatternOperator IntOp> {
3494 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3495 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3496 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3497 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3500 // ....then also with element size of 8 bits:
3501 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3502 InstrItinClass itin16, InstrItinClass itin32,
3503 string OpcodeStr, string Dt,
3504 SDPatternOperator IntOp, bit Commutable = 0>
3505 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
3506 IntOp, Commutable> {
3507 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3508 OpcodeStr, !strconcat(Dt, "8"),
3509 v8i16, v8i8, IntOp, Commutable>;
3512 // ....with explicit extend (VABDL).
3513 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3514 InstrItinClass itin, string OpcodeStr, string Dt,
3515 SDPatternOperator IntOp, SDNode ExtOp, bit Commutable = 0> {
3516 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3517 OpcodeStr, !strconcat(Dt, "8"),
3518 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3519 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3520 OpcodeStr, !strconcat(Dt, "16"),
3521 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3522 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3523 OpcodeStr, !strconcat(Dt, "32"),
3524 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3528 // Neon Wide 3-register vector intrinsics,
3529 // source operand element sizes of 8, 16 and 32 bits:
3530 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3531 string OpcodeStr, string Dt,
3532 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3533 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3534 OpcodeStr, !strconcat(Dt, "8"),
3535 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3536 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3537 OpcodeStr, !strconcat(Dt, "16"),
3538 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3539 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3540 OpcodeStr, !strconcat(Dt, "32"),
3541 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3545 // Neon Multiply-Op vector operations,
3546 // element sizes of 8, 16 and 32 bits:
3547 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3548 InstrItinClass itinD16, InstrItinClass itinD32,
3549 InstrItinClass itinQ16, InstrItinClass itinQ32,
3550 string OpcodeStr, string Dt, SDNode OpNode> {
3551 // 64-bit vector types.
3552 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3553 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3554 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3555 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3556 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3557 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3559 // 128-bit vector types.
3560 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3561 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3562 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3563 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3564 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3565 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3568 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3569 InstrItinClass itinD16, InstrItinClass itinD32,
3570 InstrItinClass itinQ16, InstrItinClass itinQ32,
3571 string OpcodeStr, string Dt, SDNode ShOp> {
3572 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3573 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3574 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3575 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3576 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3577 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3579 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3580 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3584 // Neon Intrinsic-Op vector operations,
3585 // element sizes of 8, 16 and 32 bits:
3586 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3587 InstrItinClass itinD, InstrItinClass itinQ,
3588 string OpcodeStr, string Dt, SDPatternOperator IntOp,
3590 // 64-bit vector types.
3591 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3592 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3593 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3594 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3595 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3596 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3598 // 128-bit vector types.
3599 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3600 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3601 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3602 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3603 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3604 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3607 // Neon 3-argument intrinsics,
3608 // element sizes of 8, 16 and 32 bits:
3609 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3610 InstrItinClass itinD, InstrItinClass itinQ,
3611 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3612 // 64-bit vector types.
3613 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3614 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3615 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3616 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3617 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3618 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3620 // 128-bit vector types.
3621 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3622 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3623 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3624 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3625 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3626 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3630 // Neon Long Multiply-Op vector operations,
3631 // element sizes of 8, 16 and 32 bits:
3632 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3633 InstrItinClass itin16, InstrItinClass itin32,
3634 string OpcodeStr, string Dt, SDNode MulOp,
3636 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3637 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3638 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3639 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3640 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3641 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3644 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3645 string Dt, SDNode MulOp, SDNode OpNode> {
3646 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3647 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3648 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3649 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3653 // Neon Long 3-argument intrinsics.
3655 // First with only element sizes of 16 and 32 bits:
3656 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3657 InstrItinClass itin16, InstrItinClass itin32,
3658 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3659 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3660 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3661 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3662 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3665 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3666 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3667 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3668 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3669 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3670 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3673 // ....then also with element size of 8 bits:
3674 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3675 InstrItinClass itin16, InstrItinClass itin32,
3676 string OpcodeStr, string Dt, SDPatternOperator IntOp>
3677 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3678 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3679 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3682 // ....with explicit extend (VABAL).
3683 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3684 InstrItinClass itin, string OpcodeStr, string Dt,
3685 SDPatternOperator IntOp, SDNode ExtOp, SDNode OpNode> {
3686 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3687 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3688 IntOp, ExtOp, OpNode>;
3689 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3690 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3691 IntOp, ExtOp, OpNode>;
3692 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3693 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3694 IntOp, ExtOp, OpNode>;
3698 // Neon Pairwise long 2-register intrinsics,
3699 // element sizes of 8, 16 and 32 bits:
3700 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3701 bits<5> op11_7, bit op4,
3702 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3703 // 64-bit vector types.
3704 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3705 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3706 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3707 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3708 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3709 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3711 // 128-bit vector types.
3712 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3713 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3714 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3715 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3716 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3717 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3721 // Neon Pairwise long 2-register accumulate intrinsics,
3722 // element sizes of 8, 16 and 32 bits:
3723 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3724 bits<5> op11_7, bit op4,
3725 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3726 // 64-bit vector types.
3727 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3728 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3729 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3730 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3731 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3732 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3734 // 128-bit vector types.
3735 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3736 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3737 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3738 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3739 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3740 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3744 // Neon 2-register vector shift by immediate,
3745 // with f of either N2RegVShLFrm or N2RegVShRFrm
3746 // element sizes of 8, 16, 32 and 64 bits:
3747 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3748 InstrItinClass itin, string OpcodeStr, string Dt,
3750 // 64-bit vector types.
3751 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3752 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3753 let Inst{21-19} = 0b001; // imm6 = 001xxx
3755 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3756 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3757 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3759 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3760 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3761 let Inst{21} = 0b1; // imm6 = 1xxxxx
3763 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3764 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3767 // 128-bit vector types.
3768 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3769 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3770 let Inst{21-19} = 0b001; // imm6 = 001xxx
3772 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3773 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3774 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3776 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3777 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3778 let Inst{21} = 0b1; // imm6 = 1xxxxx
3780 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3781 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3784 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3785 InstrItinClass itin, string OpcodeStr, string Dt,
3786 string baseOpc, SDNode OpNode> {
3787 // 64-bit vector types.
3788 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3789 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3790 let Inst{21-19} = 0b001; // imm6 = 001xxx
3792 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3793 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3794 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3796 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3797 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3798 let Inst{21} = 0b1; // imm6 = 1xxxxx
3800 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3801 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3804 // 128-bit vector types.
3805 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3806 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3807 let Inst{21-19} = 0b001; // imm6 = 001xxx
3809 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3810 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3811 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3813 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3814 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3815 let Inst{21} = 0b1; // imm6 = 1xxxxx
3817 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3818 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3822 // Neon Shift-Accumulate vector operations,
3823 // element sizes of 8, 16, 32 and 64 bits:
3824 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3825 string OpcodeStr, string Dt, SDNode ShOp> {
3826 // 64-bit vector types.
3827 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3828 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3829 let Inst{21-19} = 0b001; // imm6 = 001xxx
3831 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3832 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3833 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3835 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3836 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3837 let Inst{21} = 0b1; // imm6 = 1xxxxx
3839 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3840 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3843 // 128-bit vector types.
3844 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3845 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3846 let Inst{21-19} = 0b001; // imm6 = 001xxx
3848 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3849 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3850 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3852 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3853 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3854 let Inst{21} = 0b1; // imm6 = 1xxxxx
3856 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3857 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3861 // Neon Shift-Insert vector operations,
3862 // with f of either N2RegVShLFrm or N2RegVShRFrm
3863 // element sizes of 8, 16, 32 and 64 bits:
3864 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3866 // 64-bit vector types.
3867 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3868 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3869 let Inst{21-19} = 0b001; // imm6 = 001xxx
3871 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3872 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3873 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3875 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3876 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3877 let Inst{21} = 0b1; // imm6 = 1xxxxx
3879 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3880 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3883 // 128-bit vector types.
3884 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3885 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3886 let Inst{21-19} = 0b001; // imm6 = 001xxx
3888 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3889 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3890 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3892 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3893 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3894 let Inst{21} = 0b1; // imm6 = 1xxxxx
3896 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3897 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3900 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3902 // 64-bit vector types.
3903 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3904 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3905 let Inst{21-19} = 0b001; // imm6 = 001xxx
3907 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3908 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3909 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3911 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3912 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3913 let Inst{21} = 0b1; // imm6 = 1xxxxx
3915 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3916 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3919 // 128-bit vector types.
3920 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3921 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3922 let Inst{21-19} = 0b001; // imm6 = 001xxx
3924 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3925 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3926 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3928 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3929 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3930 let Inst{21} = 0b1; // imm6 = 1xxxxx
3932 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3933 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3937 // Neon Shift Long operations,
3938 // element sizes of 8, 16, 32 bits:
3939 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3940 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3941 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3942 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
3943 let Inst{21-19} = 0b001; // imm6 = 001xxx
3945 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3946 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
3947 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3949 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3950 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> {
3951 let Inst{21} = 0b1; // imm6 = 1xxxxx
3955 // Neon Shift Narrow operations,
3956 // element sizes of 16, 32, 64 bits:
3957 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3958 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3960 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3961 OpcodeStr, !strconcat(Dt, "16"),
3962 v8i8, v8i16, shr_imm8, OpNode> {
3963 let Inst{21-19} = 0b001; // imm6 = 001xxx
3965 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3966 OpcodeStr, !strconcat(Dt, "32"),
3967 v4i16, v4i32, shr_imm16, OpNode> {
3968 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3970 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3971 OpcodeStr, !strconcat(Dt, "64"),
3972 v2i32, v2i64, shr_imm32, OpNode> {
3973 let Inst{21} = 0b1; // imm6 = 1xxxxx
3977 //===----------------------------------------------------------------------===//
3978 // Instruction Definitions.
3979 //===----------------------------------------------------------------------===//
3981 // Vector Add Operations.
3983 // VADD : Vector Add (integer and floating-point)
3984 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3986 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3987 v2f32, v2f32, fadd, 1>;
3988 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3989 v4f32, v4f32, fadd, 1>;
3990 // VADDL : Vector Add Long (Q = D + D)
3991 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3992 "vaddl", "s", add, sext, 1>;
3993 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3994 "vaddl", "u", add, zext, 1>;
3995 // VADDW : Vector Add Wide (Q = Q + D)
3996 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3997 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3998 // VHADD : Vector Halving Add
3999 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
4000 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4001 "vhadd", "s", int_arm_neon_vhadds, 1>;
4002 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
4003 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4004 "vhadd", "u", int_arm_neon_vhaddu, 1>;
4005 // VRHADD : Vector Rounding Halving Add
4006 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
4007 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4008 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
4009 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
4010 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4011 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
4012 // VQADD : Vector Saturating Add
4013 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
4014 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4015 "vqadd", "s", int_arm_neon_vqadds, 1>;
4016 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
4017 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4018 "vqadd", "u", int_arm_neon_vqaddu, 1>;
4019 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
4020 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i", null_frag, 1>;
4021 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
4022 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
4023 int_arm_neon_vraddhn, 1>;
4025 def : Pat<(v8i8 (trunc (NEONvshru (add (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4026 (VADDHNv8i8 QPR:$Vn, QPR:$Vm)>;
4027 def : Pat<(v4i16 (trunc (NEONvshru (add (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4028 (VADDHNv4i16 QPR:$Vn, QPR:$Vm)>;
4029 def : Pat<(v2i32 (trunc (NEONvshru (add (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4030 (VADDHNv2i32 QPR:$Vn, QPR:$Vm)>;
4032 // Vector Multiply Operations.
4034 // VMUL : Vector Multiply (integer, polynomial and floating-point)
4035 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
4036 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
4037 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
4038 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
4039 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
4040 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
4041 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
4042 v2f32, v2f32, fmul, 1>;
4043 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
4044 v4f32, v4f32, fmul, 1>;
4045 defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>;
4046 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
4047 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
4050 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
4051 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
4052 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
4053 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4054 (DSubReg_i16_reg imm:$lane))),
4055 (SubReg_i16_lane imm:$lane)))>;
4056 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
4057 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
4058 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
4059 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4060 (DSubReg_i32_reg imm:$lane))),
4061 (SubReg_i32_lane imm:$lane)))>;
4062 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
4063 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
4064 (v4f32 (VMULslfq (v4f32 QPR:$src1),
4065 (v2f32 (EXTRACT_SUBREG QPR:$src2,
4066 (DSubReg_i32_reg imm:$lane))),
4067 (SubReg_i32_lane imm:$lane)))>;
4070 def : Pat<(v2f32 (fmul DPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4072 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4074 def : Pat<(v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4076 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4080 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
4081 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
4082 IIC_VMULi16Q, IIC_VMULi32Q,
4083 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
4084 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
4085 IIC_VMULi16Q, IIC_VMULi32Q,
4086 "vqdmulh", "s", int_arm_neon_vqdmulh>;
4087 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
4088 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4090 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
4091 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4092 (DSubReg_i16_reg imm:$lane))),
4093 (SubReg_i16_lane imm:$lane)))>;
4094 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
4095 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4097 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
4098 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4099 (DSubReg_i32_reg imm:$lane))),
4100 (SubReg_i32_lane imm:$lane)))>;
4102 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
4103 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
4104 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
4105 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
4106 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
4107 IIC_VMULi16Q, IIC_VMULi32Q,
4108 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
4109 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
4110 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4112 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
4113 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4114 (DSubReg_i16_reg imm:$lane))),
4115 (SubReg_i16_lane imm:$lane)))>;
4116 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
4117 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4119 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
4120 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4121 (DSubReg_i32_reg imm:$lane))),
4122 (SubReg_i32_lane imm:$lane)))>;
4124 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
4125 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
4126 DecoderNamespace = "NEONData" in {
4127 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4128 "vmull", "s", NEONvmulls, 1>;
4129 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4130 "vmull", "u", NEONvmullu, 1>;
4131 def VMULLp8 : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
4132 v8i16, v8i8, int_arm_neon_vmullp, 1>;
4133 def VMULLp64 : N3VLIntnp<0b00101, 0b10, 0b1110, 0, 0, NoItinerary,
4134 "vmull", "p64", v2i64, v1i64, int_arm_neon_vmullp, 1>,
4135 Requires<[HasV8, HasCrypto]>;
4137 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
4138 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
4140 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
4141 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
4142 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
4143 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
4144 "vqdmull", "s", int_arm_neon_vqdmull>;
4146 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
4148 // VMLA : Vector Multiply Accumulate (integer and floating-point)
4149 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4150 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4151 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
4152 v2f32, fmul_su, fadd_mlx>,
4153 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4154 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
4155 v4f32, fmul_su, fadd_mlx>,
4156 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4157 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
4158 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4159 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
4160 v2f32, fmul_su, fadd_mlx>,
4161 Requires<[HasNEON, UseFPVMLx]>;
4162 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
4163 v4f32, v2f32, fmul_su, fadd_mlx>,
4164 Requires<[HasNEON, UseFPVMLx]>;
4166 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
4167 (mul (v8i16 QPR:$src2),
4168 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4169 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4170 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4171 (DSubReg_i16_reg imm:$lane))),
4172 (SubReg_i16_lane imm:$lane)))>;
4174 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
4175 (mul (v4i32 QPR:$src2),
4176 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4177 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4178 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4179 (DSubReg_i32_reg imm:$lane))),
4180 (SubReg_i32_lane imm:$lane)))>;
4182 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
4183 (fmul_su (v4f32 QPR:$src2),
4184 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4185 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
4187 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4188 (DSubReg_i32_reg imm:$lane))),
4189 (SubReg_i32_lane imm:$lane)))>,
4190 Requires<[HasNEON, UseFPVMLx]>;
4192 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
4193 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4194 "vmlal", "s", NEONvmulls, add>;
4195 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4196 "vmlal", "u", NEONvmullu, add>;
4198 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
4199 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
4201 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
4202 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4203 "vqdmlal", "s", null_frag>;
4204 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", null_frag>;
4206 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4207 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4208 (v4i16 DPR:$Vm))))),
4209 (VQDMLALv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4210 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4211 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4212 (v2i32 DPR:$Vm))))),
4213 (VQDMLALv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4214 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4215 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4216 (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm),
4218 (VQDMLALslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4219 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4220 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4221 (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm),
4223 (VQDMLALslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4225 // VMLS : Vector Multiply Subtract (integer and floating-point)
4226 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4227 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4228 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
4229 v2f32, fmul_su, fsub_mlx>,
4230 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4231 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
4232 v4f32, fmul_su, fsub_mlx>,
4233 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4234 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
4235 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4236 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
4237 v2f32, fmul_su, fsub_mlx>,
4238 Requires<[HasNEON, UseFPVMLx]>;
4239 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
4240 v4f32, v2f32, fmul_su, fsub_mlx>,
4241 Requires<[HasNEON, UseFPVMLx]>;
4243 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
4244 (mul (v8i16 QPR:$src2),
4245 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4246 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4247 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4248 (DSubReg_i16_reg imm:$lane))),
4249 (SubReg_i16_lane imm:$lane)))>;
4251 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
4252 (mul (v4i32 QPR:$src2),
4253 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4254 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4255 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4256 (DSubReg_i32_reg imm:$lane))),
4257 (SubReg_i32_lane imm:$lane)))>;
4259 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
4260 (fmul_su (v4f32 QPR:$src2),
4261 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4262 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
4263 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4264 (DSubReg_i32_reg imm:$lane))),
4265 (SubReg_i32_lane imm:$lane)))>,
4266 Requires<[HasNEON, UseFPVMLx]>;
4268 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
4269 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4270 "vmlsl", "s", NEONvmulls, sub>;
4271 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4272 "vmlsl", "u", NEONvmullu, sub>;
4274 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
4275 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
4277 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
4278 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
4279 "vqdmlsl", "s", null_frag>;
4280 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", null_frag>;
4282 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4283 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4284 (v4i16 DPR:$Vm))))),
4285 (VQDMLSLv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4286 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4287 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4288 (v2i32 DPR:$Vm))))),
4289 (VQDMLSLv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4290 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4291 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4292 (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm),
4294 (VQDMLSLslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4295 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4296 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4297 (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm),
4299 (VQDMLSLslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4301 // Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations.
4302 def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32",
4303 v2f32, fmul_su, fadd_mlx>,
4304 Requires<[HasVFP4,UseFusedMAC]>;
4306 def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32",
4307 v4f32, fmul_su, fadd_mlx>,
4308 Requires<[HasVFP4,UseFusedMAC]>;
4310 // Fused Vector Multiply Subtract (floating-point)
4311 def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32",
4312 v2f32, fmul_su, fsub_mlx>,
4313 Requires<[HasVFP4,UseFusedMAC]>;
4314 def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
4315 v4f32, fmul_su, fsub_mlx>,
4316 Requires<[HasVFP4,UseFusedMAC]>;
4318 // Match @llvm.fma.* intrinsics
4319 def : Pat<(v2f32 (fma DPR:$Vn, DPR:$Vm, DPR:$src1)),
4320 (VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4321 Requires<[HasVFP4]>;
4322 def : Pat<(v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)),
4323 (VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4324 Requires<[HasVFP4]>;
4325 def : Pat<(v2f32 (fma (fneg DPR:$Vn), DPR:$Vm, DPR:$src1)),
4326 (VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4327 Requires<[HasVFP4]>;
4328 def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)),
4329 (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4330 Requires<[HasVFP4]>;
4332 // Vector Subtract Operations.
4334 // VSUB : Vector Subtract (integer and floating-point)
4335 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
4336 "vsub", "i", sub, 0>;
4337 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
4338 v2f32, v2f32, fsub, 0>;
4339 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
4340 v4f32, v4f32, fsub, 0>;
4341 // VSUBL : Vector Subtract Long (Q = D - D)
4342 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4343 "vsubl", "s", sub, sext, 0>;
4344 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4345 "vsubl", "u", sub, zext, 0>;
4346 // VSUBW : Vector Subtract Wide (Q = Q - D)
4347 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
4348 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
4349 // VHSUB : Vector Halving Subtract
4350 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
4351 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4352 "vhsub", "s", int_arm_neon_vhsubs, 0>;
4353 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
4354 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4355 "vhsub", "u", int_arm_neon_vhsubu, 0>;
4356 // VQSUB : Vector Saturing Subtract
4357 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
4358 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4359 "vqsub", "s", int_arm_neon_vqsubs, 0>;
4360 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
4361 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4362 "vqsub", "u", int_arm_neon_vqsubu, 0>;
4363 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
4364 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i", null_frag, 0>;
4365 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
4366 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
4367 int_arm_neon_vrsubhn, 0>;
4369 def : Pat<(v8i8 (trunc (NEONvshru (sub (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4370 (VSUBHNv8i8 QPR:$Vn, QPR:$Vm)>;
4371 def : Pat<(v4i16 (trunc (NEONvshru (sub (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4372 (VSUBHNv4i16 QPR:$Vn, QPR:$Vm)>;
4373 def : Pat<(v2i32 (trunc (NEONvshru (sub (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4374 (VSUBHNv2i32 QPR:$Vn, QPR:$Vm)>;
4376 // Vector Comparisons.
4378 // VCEQ : Vector Compare Equal
4379 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4380 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
4381 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
4383 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
4386 let TwoOperandAliasConstraint = "$Vm = $Vd" in
4387 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
4388 "$Vd, $Vm, #0", NEONvceqz>;
4390 // VCGE : Vector Compare Greater Than or Equal
4391 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4392 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
4393 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4394 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
4395 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
4397 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
4400 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
4401 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
4402 "$Vd, $Vm, #0", NEONvcgez>;
4403 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
4404 "$Vd, $Vm, #0", NEONvclez>;
4407 // VCGT : Vector Compare Greater Than
4408 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4409 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
4410 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4411 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
4412 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
4414 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
4417 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
4418 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
4419 "$Vd, $Vm, #0", NEONvcgtz>;
4420 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
4421 "$Vd, $Vm, #0", NEONvcltz>;
4424 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
4425 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
4426 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
4427 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
4428 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
4429 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
4430 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
4431 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
4432 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
4433 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
4434 // VTST : Vector Test Bits
4435 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
4436 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
4438 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
4439 (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4440 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
4441 (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4442 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
4443 (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4444 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
4445 (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4447 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
4448 (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4449 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
4450 (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4451 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
4452 (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4453 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
4454 (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4456 // Vector Bitwise Operations.
4458 def vnotd : PatFrag<(ops node:$in),
4459 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
4460 def vnotq : PatFrag<(ops node:$in),
4461 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
4464 // VAND : Vector Bitwise AND
4465 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
4466 v2i32, v2i32, and, 1>;
4467 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
4468 v4i32, v4i32, and, 1>;
4470 // VEOR : Vector Bitwise Exclusive OR
4471 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
4472 v2i32, v2i32, xor, 1>;
4473 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
4474 v4i32, v4i32, xor, 1>;
4476 // VORR : Vector Bitwise OR
4477 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
4478 v2i32, v2i32, or, 1>;
4479 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
4480 v4i32, v4i32, or, 1>;
4482 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
4483 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4485 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4487 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4488 let Inst{9} = SIMM{9};
4491 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
4492 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4494 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4496 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4497 let Inst{10-9} = SIMM{10-9};
4500 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
4501 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4503 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4505 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4506 let Inst{9} = SIMM{9};
4509 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
4510 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4512 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4514 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4515 let Inst{10-9} = SIMM{10-9};
4519 // VBIC : Vector Bitwise Bit Clear (AND NOT)
4520 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
4521 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4522 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4523 "vbic", "$Vd, $Vn, $Vm", "",
4524 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4525 (vnotd DPR:$Vm))))]>;
4526 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4527 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4528 "vbic", "$Vd, $Vn, $Vm", "",
4529 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4530 (vnotq QPR:$Vm))))]>;
4533 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
4534 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4536 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4538 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4539 let Inst{9} = SIMM{9};
4542 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
4543 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4545 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4547 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4548 let Inst{10-9} = SIMM{10-9};
4551 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
4552 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4554 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4556 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4557 let Inst{9} = SIMM{9};
4560 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
4561 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4563 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4565 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4566 let Inst{10-9} = SIMM{10-9};
4569 // VORN : Vector Bitwise OR NOT
4570 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4571 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4572 "vorn", "$Vd, $Vn, $Vm", "",
4573 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4574 (vnotd DPR:$Vm))))]>;
4575 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4576 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4577 "vorn", "$Vd, $Vn, $Vm", "",
4578 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4579 (vnotq QPR:$Vm))))]>;
4581 // VMVN : Vector Bitwise NOT (Immediate)
4583 let isReMaterializable = 1 in {
4585 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4586 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4587 "vmvn", "i16", "$Vd, $SIMM", "",
4588 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4589 let Inst{9} = SIMM{9};
4592 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4593 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4594 "vmvn", "i16", "$Vd, $SIMM", "",
4595 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4596 let Inst{9} = SIMM{9};
4599 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4600 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4601 "vmvn", "i32", "$Vd, $SIMM", "",
4602 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4603 let Inst{11-8} = SIMM{11-8};
4606 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4607 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4608 "vmvn", "i32", "$Vd, $SIMM", "",
4609 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4610 let Inst{11-8} = SIMM{11-8};
4614 // VMVN : Vector Bitwise NOT
4615 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
4616 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4617 "vmvn", "$Vd, $Vm", "",
4618 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
4619 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
4620 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4621 "vmvn", "$Vd, $Vm", "",
4622 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4623 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4624 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4626 // VBSL : Vector Bitwise Select
4627 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4628 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4629 N3RegFrm, IIC_VCNTiD,
4630 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4632 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
4633 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 DPR:$src1),
4634 (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))),
4635 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4636 Requires<[HasNEON]>;
4637 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 DPR:$src1),
4638 (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))),
4639 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4640 Requires<[HasNEON]>;
4641 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 DPR:$src1),
4642 (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))),
4643 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4644 Requires<[HasNEON]>;
4645 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 DPR:$src1),
4646 (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))),
4647 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4648 Requires<[HasNEON]>;
4649 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 DPR:$src1),
4650 (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))),
4651 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4652 Requires<[HasNEON]>;
4654 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4655 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4656 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
4657 Requires<[HasNEON]>;
4659 def : Pat<(v1i64 (or (and DPR:$Vn, DPR:$Vd),
4660 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4661 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
4662 Requires<[HasNEON]>;
4664 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4665 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4666 N3RegFrm, IIC_VCNTiQ,
4667 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4669 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4671 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 QPR:$src1),
4672 (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))),
4673 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4674 Requires<[HasNEON]>;
4675 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 QPR:$src1),
4676 (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))),
4677 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4678 Requires<[HasNEON]>;
4679 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 QPR:$src1),
4680 (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))),
4681 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4682 Requires<[HasNEON]>;
4683 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 QPR:$src1),
4684 (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))),
4685 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4686 Requires<[HasNEON]>;
4687 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 QPR:$src1),
4688 (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))),
4689 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4690 Requires<[HasNEON]>;
4692 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4693 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4694 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
4695 Requires<[HasNEON]>;
4696 def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
4697 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4698 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
4699 Requires<[HasNEON]>;
4701 // VBIF : Vector Bitwise Insert if False
4702 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4703 // FIXME: This instruction's encoding MAY NOT BE correct.
4704 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4705 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4706 N3RegFrm, IIC_VBINiD,
4707 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4709 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4710 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4711 N3RegFrm, IIC_VBINiQ,
4712 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4715 // VBIT : Vector Bitwise Insert if True
4716 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4717 // FIXME: This instruction's encoding MAY NOT BE correct.
4718 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4719 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4720 N3RegFrm, IIC_VBINiD,
4721 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4723 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4724 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4725 N3RegFrm, IIC_VBINiQ,
4726 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4729 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4730 // for equivalent operations with different register constraints; it just
4733 // Vector Absolute Differences.
4735 // VABD : Vector Absolute Difference
4736 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
4737 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4738 "vabd", "s", int_arm_neon_vabds, 1>;
4739 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
4740 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4741 "vabd", "u", int_arm_neon_vabdu, 1>;
4742 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
4743 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
4744 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
4745 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
4747 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
4748 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4749 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4750 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4751 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
4753 // VABA : Vector Absolute Difference and Accumulate
4754 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4755 "vaba", "s", int_arm_neon_vabds, add>;
4756 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4757 "vaba", "u", int_arm_neon_vabdu, add>;
4759 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
4760 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4761 "vabal", "s", int_arm_neon_vabds, zext, add>;
4762 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4763 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4765 // Vector Maximum and Minimum.
4767 // VMAX : Vector Maximum
4768 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4769 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4770 "vmax", "s", int_arm_neon_vmaxs, 1>;
4771 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4772 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4773 "vmax", "u", int_arm_neon_vmaxu, 1>;
4774 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4776 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4777 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4779 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4782 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
4783 def VMAXNMND : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1,
4784 N3RegFrm, NoItinerary, "vmaxnm", "f32",
4785 v2f32, v2f32, int_arm_neon_vmaxnm, 1>,
4786 Requires<[HasV8, HasNEON]>;
4787 def VMAXNMNQ : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1,
4788 N3RegFrm, NoItinerary, "vmaxnm", "f32",
4789 v4f32, v4f32, int_arm_neon_vmaxnm, 1>,
4790 Requires<[HasV8, HasNEON]>;
4793 // VMIN : Vector Minimum
4794 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4795 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4796 "vmin", "s", int_arm_neon_vmins, 1>;
4797 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4798 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4799 "vmin", "u", int_arm_neon_vminu, 1>;
4800 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4802 v2f32, v2f32, int_arm_neon_vmins, 1>;
4803 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4805 v4f32, v4f32, int_arm_neon_vmins, 1>;
4808 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
4809 def VMINNMND : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1,
4810 N3RegFrm, NoItinerary, "vminnm", "f32",
4811 v2f32, v2f32, int_arm_neon_vminnm, 1>,
4812 Requires<[HasV8, HasNEON]>;
4813 def VMINNMNQ : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1,
4814 N3RegFrm, NoItinerary, "vminnm", "f32",
4815 v4f32, v4f32, int_arm_neon_vminnm, 1>,
4816 Requires<[HasV8, HasNEON]>;
4819 // Vector Pairwise Operations.
4821 // VPADD : Vector Pairwise Add
4822 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4824 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4825 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4827 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4828 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4830 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4831 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4832 IIC_VPBIND, "vpadd", "f32",
4833 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4835 // VPADDL : Vector Pairwise Add Long
4836 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4837 int_arm_neon_vpaddls>;
4838 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4839 int_arm_neon_vpaddlu>;
4841 // VPADAL : Vector Pairwise Add and Accumulate Long
4842 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4843 int_arm_neon_vpadals>;
4844 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4845 int_arm_neon_vpadalu>;
4847 // VPMAX : Vector Pairwise Maximum
4848 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4849 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4850 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4851 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4852 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4853 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4854 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4855 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4856 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4857 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4858 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4859 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4860 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4861 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4863 // VPMIN : Vector Pairwise Minimum
4864 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4865 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4866 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4867 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4868 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4869 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4870 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4871 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4872 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4873 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4874 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4875 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4876 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4877 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4879 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4881 // VRECPE : Vector Reciprocal Estimate
4882 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4883 IIC_VUNAD, "vrecpe", "u32",
4884 v2i32, v2i32, int_arm_neon_vrecpe>;
4885 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4886 IIC_VUNAQ, "vrecpe", "u32",
4887 v4i32, v4i32, int_arm_neon_vrecpe>;
4888 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4889 IIC_VUNAD, "vrecpe", "f32",
4890 v2f32, v2f32, int_arm_neon_vrecpe>;
4891 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4892 IIC_VUNAQ, "vrecpe", "f32",
4893 v4f32, v4f32, int_arm_neon_vrecpe>;
4895 // VRECPS : Vector Reciprocal Step
4896 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4897 IIC_VRECSD, "vrecps", "f32",
4898 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4899 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4900 IIC_VRECSQ, "vrecps", "f32",
4901 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4903 // VRSQRTE : Vector Reciprocal Square Root Estimate
4904 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4905 IIC_VUNAD, "vrsqrte", "u32",
4906 v2i32, v2i32, int_arm_neon_vrsqrte>;
4907 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4908 IIC_VUNAQ, "vrsqrte", "u32",
4909 v4i32, v4i32, int_arm_neon_vrsqrte>;
4910 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4911 IIC_VUNAD, "vrsqrte", "f32",
4912 v2f32, v2f32, int_arm_neon_vrsqrte>;
4913 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4914 IIC_VUNAQ, "vrsqrte", "f32",
4915 v4f32, v4f32, int_arm_neon_vrsqrte>;
4917 // VRSQRTS : Vector Reciprocal Square Root Step
4918 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4919 IIC_VRECSD, "vrsqrts", "f32",
4920 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4921 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4922 IIC_VRECSQ, "vrsqrts", "f32",
4923 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4927 // VSHL : Vector Shift
4928 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4929 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4930 "vshl", "s", int_arm_neon_vshifts>;
4931 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4932 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4933 "vshl", "u", int_arm_neon_vshiftu>;
4935 // VSHL : Vector Shift Left (Immediate)
4936 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4938 // VSHR : Vector Shift Right (Immediate)
4939 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", "VSHRs",
4941 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", "VSHRu",
4944 // VSHLL : Vector Shift Left Long
4945 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4946 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4948 // VSHLL : Vector Shift Left Long (with maximum shift count)
4949 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4950 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4951 ValueType OpTy, Operand ImmTy, SDNode OpNode>
4952 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4953 ResTy, OpTy, ImmTy, OpNode> {
4954 let Inst{21-16} = op21_16;
4955 let DecoderMethod = "DecodeVSHLMaxInstruction";
4957 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4958 v8i16, v8i8, imm8, NEONvshlli>;
4959 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4960 v4i32, v4i16, imm16, NEONvshlli>;
4961 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4962 v2i64, v2i32, imm32, NEONvshlli>;
4964 // VSHRN : Vector Shift Right and Narrow
4965 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4968 // VRSHL : Vector Rounding Shift
4969 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4970 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4971 "vrshl", "s", int_arm_neon_vrshifts>;
4972 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4973 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4974 "vrshl", "u", int_arm_neon_vrshiftu>;
4975 // VRSHR : Vector Rounding Shift Right
4976 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", "VRSHRs",
4978 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", "VRSHRu",
4981 // VRSHRN : Vector Rounding Shift Right and Narrow
4982 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4985 // VQSHL : Vector Saturating Shift
4986 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4987 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4988 "vqshl", "s", int_arm_neon_vqshifts>;
4989 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4990 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4991 "vqshl", "u", int_arm_neon_vqshiftu>;
4992 // VQSHL : Vector Saturating Shift Left (Immediate)
4993 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4994 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4996 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4997 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4999 // VQSHRN : Vector Saturating Shift Right and Narrow
5000 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
5002 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
5005 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
5006 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
5009 // VQRSHL : Vector Saturating Rounding Shift
5010 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
5011 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5012 "vqrshl", "s", int_arm_neon_vqrshifts>;
5013 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
5014 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5015 "vqrshl", "u", int_arm_neon_vqrshiftu>;
5017 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
5018 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
5020 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
5023 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
5024 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
5027 // VSRA : Vector Shift Right and Accumulate
5028 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
5029 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
5030 // VRSRA : Vector Rounding Shift Right and Accumulate
5031 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
5032 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
5034 // VSLI : Vector Shift Left and Insert
5035 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
5037 // VSRI : Vector Shift Right and Insert
5038 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
5040 // Vector Absolute and Saturating Absolute.
5042 // VABS : Vector Absolute Value
5043 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
5044 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
5046 def VABSfd : N2VD<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
5048 v2f32, v2f32, fabs>;
5049 def VABSfq : N2VQ<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
5051 v4f32, v4f32, fabs>;
5053 def : Pat<(xor (v2i32 (bitconvert (v8i8 (NEONvshrs DPR:$src, (i32 7))))),
5054 (v2i32 (bitconvert (v8i8 (add DPR:$src,
5055 (NEONvshrs DPR:$src, (i32 7))))))),
5056 (VABSv8i8 DPR:$src)>;
5057 def : Pat<(xor (v2i32 (bitconvert (v4i16 (NEONvshrs DPR:$src, (i32 15))))),
5058 (v2i32 (bitconvert (v4i16 (add DPR:$src,
5059 (NEONvshrs DPR:$src, (i32 15))))))),
5060 (VABSv4i16 DPR:$src)>;
5061 def : Pat<(xor (v2i32 (NEONvshrs DPR:$src, (i32 31))),
5062 (v2i32 (add DPR:$src, (NEONvshrs DPR:$src, (i32 31))))),
5063 (VABSv2i32 DPR:$src)>;
5064 def : Pat<(xor (v4i32 (bitconvert (v16i8 (NEONvshrs QPR:$src, (i32 7))))),
5065 (v4i32 (bitconvert (v16i8 (add QPR:$src,
5066 (NEONvshrs QPR:$src, (i32 7))))))),
5067 (VABSv16i8 QPR:$src)>;
5068 def : Pat<(xor (v4i32 (bitconvert (v8i16 (NEONvshrs QPR:$src, (i32 15))))),
5069 (v4i32 (bitconvert (v8i16 (add QPR:$src,
5070 (NEONvshrs QPR:$src, (i32 15))))))),
5071 (VABSv8i16 QPR:$src)>;
5072 def : Pat<(xor (v4i32 (NEONvshrs QPR:$src, (i32 31))),
5073 (v4i32 (add QPR:$src, (NEONvshrs QPR:$src, (i32 31))))),
5074 (VABSv4i32 QPR:$src)>;
5076 def : Pat<(v2f32 (int_arm_neon_vabs (v2f32 DPR:$src))), (VABSfd DPR:$src)>;
5077 def : Pat<(v4f32 (int_arm_neon_vabs (v4f32 QPR:$src))), (VABSfq QPR:$src)>;
5079 // VQABS : Vector Saturating Absolute Value
5080 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
5081 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
5082 int_arm_neon_vqabs>;
5086 def vnegd : PatFrag<(ops node:$in),
5087 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
5088 def vnegq : PatFrag<(ops node:$in),
5089 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
5091 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
5092 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
5093 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
5094 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
5095 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
5096 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
5097 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
5098 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
5100 // VNEG : Vector Negate (integer)
5101 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
5102 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
5103 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
5104 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
5105 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
5106 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
5108 // VNEG : Vector Negate (floating-point)
5109 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
5110 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
5111 "vneg", "f32", "$Vd, $Vm", "",
5112 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
5113 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
5114 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
5115 "vneg", "f32", "$Vd, $Vm", "",
5116 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
5118 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
5119 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
5120 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
5121 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
5122 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
5123 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
5125 // VQNEG : Vector Saturating Negate
5126 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
5127 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
5128 int_arm_neon_vqneg>;
5130 // Vector Bit Counting Operations.
5132 // VCLS : Vector Count Leading Sign Bits
5133 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
5134 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
5136 // VCLZ : Vector Count Leading Zeros
5137 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
5138 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
5140 // VCNT : Vector Count One Bits
5141 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
5142 IIC_VCNTiD, "vcnt", "8",
5144 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
5145 IIC_VCNTiQ, "vcnt", "8",
5146 v16i8, v16i8, ctpop>;
5149 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
5150 (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
5151 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5153 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
5154 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
5155 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5158 // Vector Move Operations.
5160 // VMOV : Vector Move (Register)
5161 def : InstAlias<"vmov${p} $Vd, $Vm",
5162 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
5163 def : InstAlias<"vmov${p} $Vd, $Vm",
5164 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
5166 // VMOV : Vector Move (Immediate)
5168 let isReMaterializable = 1 in {
5169 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
5170 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
5171 "vmov", "i8", "$Vd, $SIMM", "",
5172 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
5173 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
5174 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
5175 "vmov", "i8", "$Vd, $SIMM", "",
5176 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
5178 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
5179 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
5180 "vmov", "i16", "$Vd, $SIMM", "",
5181 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
5182 let Inst{9} = SIMM{9};
5185 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
5186 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
5187 "vmov", "i16", "$Vd, $SIMM", "",
5188 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
5189 let Inst{9} = SIMM{9};
5192 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
5193 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
5194 "vmov", "i32", "$Vd, $SIMM", "",
5195 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
5196 let Inst{11-8} = SIMM{11-8};
5199 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
5200 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
5201 "vmov", "i32", "$Vd, $SIMM", "",
5202 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
5203 let Inst{11-8} = SIMM{11-8};
5206 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
5207 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
5208 "vmov", "i64", "$Vd, $SIMM", "",
5209 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
5210 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
5211 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
5212 "vmov", "i64", "$Vd, $SIMM", "",
5213 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
5215 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
5216 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
5217 "vmov", "f32", "$Vd, $SIMM", "",
5218 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
5219 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
5220 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
5221 "vmov", "f32", "$Vd, $SIMM", "",
5222 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
5223 } // isReMaterializable
5225 // VMOV : Vector Get Lane (move scalar to ARM core register)
5227 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
5228 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5229 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
5230 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
5232 let Inst{21} = lane{2};
5233 let Inst{6-5} = lane{1-0};
5235 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
5236 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5237 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
5238 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
5240 let Inst{21} = lane{1};
5241 let Inst{6} = lane{0};
5243 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
5244 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5245 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
5246 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
5248 let Inst{21} = lane{2};
5249 let Inst{6-5} = lane{1-0};
5251 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
5252 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5253 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
5254 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
5256 let Inst{21} = lane{1};
5257 let Inst{6} = lane{0};
5259 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
5260 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
5261 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
5262 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
5264 Requires<[HasNEON, HasFastVGETLNi32]> {
5265 let Inst{21} = lane{0};
5267 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
5268 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
5269 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5270 (DSubReg_i8_reg imm:$lane))),
5271 (SubReg_i8_lane imm:$lane))>;
5272 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
5273 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5274 (DSubReg_i16_reg imm:$lane))),
5275 (SubReg_i16_lane imm:$lane))>;
5276 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
5277 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5278 (DSubReg_i8_reg imm:$lane))),
5279 (SubReg_i8_lane imm:$lane))>;
5280 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
5281 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5282 (DSubReg_i16_reg imm:$lane))),
5283 (SubReg_i16_lane imm:$lane))>;
5284 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5285 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
5286 (DSubReg_i32_reg imm:$lane))),
5287 (SubReg_i32_lane imm:$lane))>,
5288 Requires<[HasNEON, HasFastVGETLNi32]>;
5289 def : Pat<(extractelt (v2i32 DPR:$src), imm:$lane),
5291 (i32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5292 Requires<[HasNEON, HasSlowVGETLNi32]>;
5293 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5295 (i32 (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5296 Requires<[HasNEON, HasSlowVGETLNi32]>;
5297 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
5298 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
5299 (SSubReg_f32_reg imm:$src2))>;
5300 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
5301 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
5302 (SSubReg_f32_reg imm:$src2))>;
5303 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
5304 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5305 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
5306 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5309 // VMOV : Vector Set Lane (move ARM core register to scalar)
5311 let Constraints = "$src1 = $V" in {
5312 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
5313 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
5314 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
5315 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
5316 GPR:$R, imm:$lane))]> {
5317 let Inst{21} = lane{2};
5318 let Inst{6-5} = lane{1-0};
5320 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
5321 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
5322 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
5323 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
5324 GPR:$R, imm:$lane))]> {
5325 let Inst{21} = lane{1};
5326 let Inst{6} = lane{0};
5328 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
5329 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
5330 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
5331 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
5332 GPR:$R, imm:$lane))]> {
5333 let Inst{21} = lane{0};
5336 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
5337 (v16i8 (INSERT_SUBREG QPR:$src1,
5338 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
5339 (DSubReg_i8_reg imm:$lane))),
5340 GPR:$src2, (SubReg_i8_lane imm:$lane))),
5341 (DSubReg_i8_reg imm:$lane)))>;
5342 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
5343 (v8i16 (INSERT_SUBREG QPR:$src1,
5344 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
5345 (DSubReg_i16_reg imm:$lane))),
5346 GPR:$src2, (SubReg_i16_lane imm:$lane))),
5347 (DSubReg_i16_reg imm:$lane)))>;
5348 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
5349 (v4i32 (INSERT_SUBREG QPR:$src1,
5350 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
5351 (DSubReg_i32_reg imm:$lane))),
5352 GPR:$src2, (SubReg_i32_lane imm:$lane))),
5353 (DSubReg_i32_reg imm:$lane)))>;
5355 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
5356 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
5357 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5358 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
5359 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
5360 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5362 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5363 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5364 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5365 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5367 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
5368 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5369 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
5370 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
5371 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
5372 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5374 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
5375 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5376 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
5377 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5378 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
5379 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5381 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
5382 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
5383 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5385 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
5386 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
5387 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5389 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
5390 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
5391 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5394 // VDUP : Vector Duplicate (from ARM core register to all elements)
5396 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5397 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
5398 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5399 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5400 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5401 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
5402 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5403 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5405 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
5406 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
5407 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>,
5408 Requires<[HasNEON, HasFastVDUP32]>;
5409 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
5410 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
5411 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
5413 // NEONvdup patterns for uarchs with fast VDUP.32.
5414 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>,
5415 Requires<[HasNEON,HasFastVDUP32]>;
5416 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
5418 // NEONvdup patterns for uarchs with slow VDUP.32 - use VMOVDRR instead.
5419 def : Pat<(v2i32 (NEONvdup (i32 GPR:$R))), (VMOVDRR GPR:$R, GPR:$R)>,
5420 Requires<[HasNEON,HasSlowVDUP32]>;
5421 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VMOVDRR GPR:$R, GPR:$R)>,
5422 Requires<[HasNEON,HasSlowVDUP32]>;
5424 // VDUP : Vector Duplicate Lane (from scalar to all elements)
5426 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
5427 ValueType Ty, Operand IdxTy>
5428 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5429 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
5430 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
5432 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
5433 ValueType ResTy, ValueType OpTy, Operand IdxTy>
5434 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5435 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
5436 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
5437 VectorIndex32:$lane)))]>;
5439 // Inst{19-16} is partially specified depending on the element size.
5441 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
5443 let Inst{19-17} = lane{2-0};
5445 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
5447 let Inst{19-18} = lane{1-0};
5449 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
5451 let Inst{19} = lane{0};
5453 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
5455 let Inst{19-17} = lane{2-0};
5457 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
5459 let Inst{19-18} = lane{1-0};
5461 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
5463 let Inst{19} = lane{0};
5466 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5467 (VDUPLN32d DPR:$Vm, imm:$lane)>;
5469 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5470 (VDUPLN32q DPR:$Vm, imm:$lane)>;
5472 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
5473 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
5474 (DSubReg_i8_reg imm:$lane))),
5475 (SubReg_i8_lane imm:$lane)))>;
5476 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
5477 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
5478 (DSubReg_i16_reg imm:$lane))),
5479 (SubReg_i16_lane imm:$lane)))>;
5480 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
5481 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
5482 (DSubReg_i32_reg imm:$lane))),
5483 (SubReg_i32_lane imm:$lane)))>;
5484 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
5485 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
5486 (DSubReg_i32_reg imm:$lane))),
5487 (SubReg_i32_lane imm:$lane)))>;
5489 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
5490 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
5491 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
5492 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
5494 // VMOVN : Vector Narrowing Move
5495 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
5496 "vmovn", "i", trunc>;
5497 // VQMOVN : Vector Saturating Narrowing Move
5498 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
5499 "vqmovn", "s", int_arm_neon_vqmovns>;
5500 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
5501 "vqmovn", "u", int_arm_neon_vqmovnu>;
5502 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
5503 "vqmovun", "s", int_arm_neon_vqmovnsu>;
5504 // VMOVL : Vector Lengthening Move
5505 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
5506 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
5507 def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
5508 def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>;
5509 def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>;
5511 // Vector Conversions.
5513 // VCVT : Vector Convert Between Floating-Point and Integers
5514 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5515 v2i32, v2f32, fp_to_sint>;
5516 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5517 v2i32, v2f32, fp_to_uint>;
5518 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5519 v2f32, v2i32, sint_to_fp>;
5520 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5521 v2f32, v2i32, uint_to_fp>;
5523 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5524 v4i32, v4f32, fp_to_sint>;
5525 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5526 v4i32, v4f32, fp_to_uint>;
5527 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5528 v4f32, v4i32, sint_to_fp>;
5529 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5530 v4f32, v4i32, uint_to_fp>;
5533 multiclass VCVT_FPI<string op, bits<3> op10_8, SDPatternOperator IntS,
5534 SDPatternOperator IntU> {
5535 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
5536 def SD : N2VDIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
5537 "s32.f32", v2i32, v2f32, IntS>, Requires<[HasV8, HasNEON]>;
5538 def SQ : N2VQIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
5539 "s32.f32", v4i32, v4f32, IntS>, Requires<[HasV8, HasNEON]>;
5540 def UD : N2VDIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
5541 "u32.f32", v2i32, v2f32, IntU>, Requires<[HasV8, HasNEON]>;
5542 def UQ : N2VQIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
5543 "u32.f32", v4i32, v4f32, IntU>, Requires<[HasV8, HasNEON]>;
5547 defm VCVTAN : VCVT_FPI<"a", 0b000, int_arm_neon_vcvtas, int_arm_neon_vcvtau>;
5548 defm VCVTNN : VCVT_FPI<"n", 0b001, int_arm_neon_vcvtns, int_arm_neon_vcvtnu>;
5549 defm VCVTPN : VCVT_FPI<"p", 0b010, int_arm_neon_vcvtps, int_arm_neon_vcvtpu>;
5550 defm VCVTMN : VCVT_FPI<"m", 0b011, int_arm_neon_vcvtms, int_arm_neon_vcvtmu>;
5552 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
5553 let DecoderMethod = "DecodeVCVTD" in {
5554 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5555 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
5556 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5557 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
5558 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5559 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
5560 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5561 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
5564 let DecoderMethod = "DecodeVCVTQ" in {
5565 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5566 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
5567 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5568 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
5569 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5570 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
5571 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5572 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
5575 def : NEONInstAlias<"vcvt${p}.s32.f32 $Dd, $Dm, #0",
5576 (VCVTf2sd DPR:$Dd, DPR:$Dm, pred:$p)>;
5577 def : NEONInstAlias<"vcvt${p}.u32.f32 $Dd, $Dm, #0",
5578 (VCVTf2ud DPR:$Dd, DPR:$Dm, pred:$p)>;
5579 def : NEONInstAlias<"vcvt${p}.f32.s32 $Dd, $Dm, #0",
5580 (VCVTs2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
5581 def : NEONInstAlias<"vcvt${p}.f32.u32 $Dd, $Dm, #0",
5582 (VCVTu2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
5584 def : NEONInstAlias<"vcvt${p}.s32.f32 $Qd, $Qm, #0",
5585 (VCVTf2sq QPR:$Qd, QPR:$Qm, pred:$p)>;
5586 def : NEONInstAlias<"vcvt${p}.u32.f32 $Qd, $Qm, #0",
5587 (VCVTf2uq QPR:$Qd, QPR:$Qm, pred:$p)>;
5588 def : NEONInstAlias<"vcvt${p}.f32.s32 $Qd, $Qm, #0",
5589 (VCVTs2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5590 def : NEONInstAlias<"vcvt${p}.f32.u32 $Qd, $Qm, #0",
5591 (VCVTu2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5594 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
5595 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
5596 IIC_VUNAQ, "vcvt", "f16.f32",
5597 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
5598 Requires<[HasNEON, HasFP16]>;
5599 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
5600 IIC_VUNAQ, "vcvt", "f32.f16",
5601 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
5602 Requires<[HasNEON, HasFP16]>;
5606 // VREV64 : Vector Reverse elements within 64-bit doublewords
5608 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5609 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
5610 (ins DPR:$Vm), IIC_VMOVD,
5611 OpcodeStr, Dt, "$Vd, $Vm", "",
5612 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
5613 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5614 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
5615 (ins QPR:$Vm), IIC_VMOVQ,
5616 OpcodeStr, Dt, "$Vd, $Vm", "",
5617 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
5619 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
5620 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
5621 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
5622 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
5624 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
5625 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5626 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
5627 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
5629 // VREV32 : Vector Reverse elements within 32-bit words
5631 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5632 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
5633 (ins DPR:$Vm), IIC_VMOVD,
5634 OpcodeStr, Dt, "$Vd, $Vm", "",
5635 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
5636 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5637 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
5638 (ins QPR:$Vm), IIC_VMOVQ,
5639 OpcodeStr, Dt, "$Vd, $Vm", "",
5640 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
5642 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
5643 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
5645 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
5646 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
5648 // VREV16 : Vector Reverse elements within 16-bit halfwords
5650 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5651 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
5652 (ins DPR:$Vm), IIC_VMOVD,
5653 OpcodeStr, Dt, "$Vd, $Vm", "",
5654 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
5655 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5656 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
5657 (ins QPR:$Vm), IIC_VMOVQ,
5658 OpcodeStr, Dt, "$Vd, $Vm", "",
5659 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
5661 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
5662 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
5664 // Other Vector Shuffles.
5666 // Aligned extractions: really just dropping registers
5668 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
5669 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
5670 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
5672 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
5674 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
5676 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
5678 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
5680 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
5683 // VEXT : Vector Extract
5686 // All of these have a two-operand InstAlias.
5687 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
5688 class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5689 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
5690 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
5691 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5692 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
5693 (Ty DPR:$Vm), imm:$index)))]> {
5696 let Inst{10-8} = index{2-0};
5699 class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5700 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
5701 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
5702 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5703 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
5704 (Ty QPR:$Vm), imm:$index)))]> {
5706 let Inst{11-8} = index{3-0};
5710 def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> {
5711 let Inst{10-8} = index{2-0};
5713 def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> {
5714 let Inst{10-9} = index{1-0};
5717 def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> {
5718 let Inst{10} = index{0};
5719 let Inst{9-8} = 0b00;
5721 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
5724 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
5726 def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> {
5727 let Inst{11-8} = index{3-0};
5729 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
5730 let Inst{11-9} = index{2-0};
5733 def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
5734 let Inst{11-10} = index{1-0};
5735 let Inst{9-8} = 0b00;
5737 def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> {
5738 let Inst{11} = index{0};
5739 let Inst{10-8} = 0b000;
5741 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
5744 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
5746 // VTRN : Vector Transpose
5748 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
5749 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
5750 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
5752 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
5753 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
5754 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
5756 // VUZP : Vector Unzip (Deinterleave)
5758 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
5759 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
5760 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5761 def : NEONInstAlias<"vuzp${p}.32 $Dd, $Dm",
5762 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
5764 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
5765 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
5766 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
5768 // VZIP : Vector Zip (Interleave)
5770 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
5771 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
5772 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5773 def : NEONInstAlias<"vzip${p}.32 $Dd, $Dm",
5774 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
5776 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
5777 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
5778 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
5780 // Vector Table Lookup and Table Extension.
5782 // VTBL : Vector Table Lookup
5783 let DecoderMethod = "DecodeTBLInstruction" in {
5785 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
5786 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
5787 "vtbl", "8", "$Vd, $Vn, $Vm", "",
5788 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
5789 let hasExtraSrcRegAllocReq = 1 in {
5791 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
5792 (ins VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
5793 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5795 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
5796 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
5797 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5799 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
5800 (ins VecListFourD:$Vn, DPR:$Vm),
5802 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5803 } // hasExtraSrcRegAllocReq = 1
5806 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
5808 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
5810 // VTBX : Vector Table Extension
5812 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
5813 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
5814 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
5815 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
5816 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
5817 let hasExtraSrcRegAllocReq = 1 in {
5819 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
5820 (ins DPR:$orig, VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
5821 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
5823 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
5824 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
5825 NVTBLFrm, IIC_VTBX3,
5826 "vtbx", "8", "$Vd, $Vn, $Vm",
5829 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
5830 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
5831 "vtbx", "8", "$Vd, $Vn, $Vm",
5833 } // hasExtraSrcRegAllocReq = 1
5836 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5837 IIC_VTBX3, "$orig = $dst", []>;
5839 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5840 IIC_VTBX4, "$orig = $dst", []>;
5841 } // DecoderMethod = "DecodeTBLInstruction"
5843 // VRINT : Vector Rounding
5844 multiclass VRINT_FPI<string op, bits<3> op9_7, SDPatternOperator Int> {
5845 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
5846 def D : N2VDIntnp<0b10, 0b100, 0, NoItinerary,
5847 !strconcat("vrint", op), "f32",
5848 v2f32, v2f32, Int>, Requires<[HasV8, HasNEON]> {
5849 let Inst{9-7} = op9_7;
5851 def Q : N2VQIntnp<0b10, 0b100, 0, NoItinerary,
5852 !strconcat("vrint", op), "f32",
5853 v4f32, v4f32, Int>, Requires<[HasV8, HasNEON]> {
5854 let Inst{9-7} = op9_7;
5858 def : NEONInstAlias<!strconcat("vrint", op, ".f32.f32\t$Dd, $Dm"),
5859 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>;
5860 def : NEONInstAlias<!strconcat("vrint", op, ".f32.f32\t$Qd, $Qm"),
5861 (!cast<Instruction>(NAME#"Q") QPR:$Qd, QPR:$Qm)>;
5864 defm VRINTNN : VRINT_FPI<"n", 0b000, int_arm_neon_vrintn>;
5865 defm VRINTXN : VRINT_FPI<"x", 0b001, int_arm_neon_vrintx>;
5866 defm VRINTAN : VRINT_FPI<"a", 0b010, int_arm_neon_vrinta>;
5867 defm VRINTZN : VRINT_FPI<"z", 0b011, int_arm_neon_vrintz>;
5868 defm VRINTMN : VRINT_FPI<"m", 0b101, int_arm_neon_vrintm>;
5869 defm VRINTPN : VRINT_FPI<"p", 0b111, int_arm_neon_vrintp>;
5871 // Cryptography instructions
5872 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
5873 DecoderNamespace = "v8Crypto" in {
5874 class AES<string op, bit op7, bit op6, SDPatternOperator Int>
5875 : N2VQIntXnp<0b00, 0b00, 0b011, op6, op7, NoItinerary,
5876 !strconcat("aes", op), "8", v16i8, v16i8, Int>,
5877 Requires<[HasV8, HasCrypto]>;
5878 class AES2Op<string op, bit op7, bit op6, SDPatternOperator Int>
5879 : N2VQIntX2np<0b00, 0b00, 0b011, op6, op7, NoItinerary,
5880 !strconcat("aes", op), "8", v16i8, v16i8, Int>,
5881 Requires<[HasV8, HasCrypto]>;
5882 class N2SHA<string op, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
5883 SDPatternOperator Int>
5884 : N2VQIntXnp<0b10, op17_16, op10_8, op6, op7, NoItinerary,
5885 !strconcat("sha", op), "32", v4i32, v4i32, Int>,
5886 Requires<[HasV8, HasCrypto]>;
5887 class N2SHA2Op<string op, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
5888 SDPatternOperator Int>
5889 : N2VQIntX2np<0b10, op17_16, op10_8, op6, op7, NoItinerary,
5890 !strconcat("sha", op), "32", v4i32, v4i32, Int>,
5891 Requires<[HasV8, HasCrypto]>;
5892 class N3SHA3Op<string op, bits<5> op27_23, bits<2> op21_20, SDPatternOperator Int>
5893 : N3VQInt3np<op27_23, op21_20, 0b1100, 1, 0, N3RegFrm, NoItinerary,
5894 !strconcat("sha", op), "32", v4i32, v4i32, Int, 0>,
5895 Requires<[HasV8, HasCrypto]>;
5898 def AESD : AES2Op<"d", 0, 1, int_arm_neon_aesd>;
5899 def AESE : AES2Op<"e", 0, 0, int_arm_neon_aese>;
5900 def AESIMC : AES<"imc", 1, 1, int_arm_neon_aesimc>;
5901 def AESMC : AES<"mc", 1, 0, int_arm_neon_aesmc>;
5903 def SHA1H : N2SHA<"1h", 0b01, 0b010, 1, 1, int_arm_neon_sha1h>;
5904 def SHA1SU1 : N2SHA2Op<"1su1", 0b10, 0b011, 1, 0, int_arm_neon_sha1su1>;
5905 def SHA256SU0 : N2SHA2Op<"256su0", 0b10, 0b011, 1, 1, int_arm_neon_sha256su0>;
5906 def SHA1C : N3SHA3Op<"1c", 0b00100, 0b00, int_arm_neon_sha1c>;
5907 def SHA1M : N3SHA3Op<"1m", 0b00100, 0b10, int_arm_neon_sha1m>;
5908 def SHA1P : N3SHA3Op<"1p", 0b00100, 0b01, int_arm_neon_sha1p>;
5909 def SHA1SU0 : N3SHA3Op<"1su0", 0b00100, 0b11, int_arm_neon_sha1su0>;
5910 def SHA256H : N3SHA3Op<"256h", 0b00110, 0b00, int_arm_neon_sha256h>;
5911 def SHA256H2 : N3SHA3Op<"256h2", 0b00110, 0b01, int_arm_neon_sha256h2>;
5912 def SHA256SU1 : N3SHA3Op<"256su1", 0b00110, 0b10, int_arm_neon_sha256su1>;
5914 //===----------------------------------------------------------------------===//
5915 // NEON instructions for single-precision FP math
5916 //===----------------------------------------------------------------------===//
5918 class N2VSPat<SDNode OpNode, NeonI Inst>
5919 : NEONFPPat<(f32 (OpNode SPR:$a)),
5921 (v2f32 (COPY_TO_REGCLASS (Inst
5923 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5924 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
5926 class N3VSPat<SDNode OpNode, NeonI Inst>
5927 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
5929 (v2f32 (COPY_TO_REGCLASS (Inst
5931 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5934 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5935 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5937 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
5938 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
5940 (v2f32 (COPY_TO_REGCLASS (Inst
5942 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5945 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5948 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5949 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5951 def : N3VSPat<fadd, VADDfd>;
5952 def : N3VSPat<fsub, VSUBfd>;
5953 def : N3VSPat<fmul, VMULfd>;
5954 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
5955 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
5956 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
5957 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
5958 def : N3VSMulOpPat<fmul, fadd, VFMAfd>,
5959 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
5960 def : N3VSMulOpPat<fmul, fsub, VFMSfd>,
5961 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
5962 def : N2VSPat<fabs, VABSfd>;
5963 def : N2VSPat<fneg, VNEGfd>;
5964 def : N3VSPat<NEONfmax, VMAXfd>;
5965 def : N3VSPat<NEONfmin, VMINfd>;
5966 def : N2VSPat<arm_ftosi, VCVTf2sd>;
5967 def : N2VSPat<arm_ftoui, VCVTf2ud>;
5968 def : N2VSPat<arm_sitof, VCVTs2fd>;
5969 def : N2VSPat<arm_uitof, VCVTu2fd>;
5971 // Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers.
5972 def : Pat<(f32 (bitconvert GPR:$a)),
5973 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
5974 Requires<[HasNEON, DontUseVMOVSR]>;
5976 //===----------------------------------------------------------------------===//
5977 // Non-Instruction Patterns
5978 //===----------------------------------------------------------------------===//
5981 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
5982 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
5983 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
5984 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
5985 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
5986 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
5987 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
5988 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
5989 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
5990 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
5991 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
5992 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
5993 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
5994 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
5995 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
5996 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
5997 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
5998 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
5999 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
6000 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
6001 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
6002 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
6003 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
6004 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
6005 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
6006 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
6007 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
6008 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
6009 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
6010 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
6012 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
6013 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
6014 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
6015 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
6016 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
6017 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
6018 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
6019 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
6020 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
6021 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
6022 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
6023 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
6024 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
6025 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
6026 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
6027 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
6028 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
6029 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
6030 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
6031 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
6032 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
6033 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
6034 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
6035 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
6036 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
6037 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
6038 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
6039 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
6040 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
6041 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
6043 // Fold extracting an element out of a v2i32 into a vfp register.
6044 def : Pat<(f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane)))),
6045 (f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6047 // Vector lengthening move with load, matching extending loads.
6049 // extload, zextload and sextload for a standard lengthening load. Example:
6050 // Lengthen_Single<"8", "i16", "8"> =
6051 // Pat<(v8i16 (extloadvi8 addrmode6:$addr))
6052 // (VMOVLuv8i16 (VLD1d8 addrmode6:$addr,
6053 // (f64 (IMPLICIT_DEF)), (i32 0)))>;
6054 multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> {
6055 let AddedComplexity = 10 in {
6056 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6057 (!cast<PatFrag>("extloadvi" # SrcTy) addrmode6:$addr)),
6058 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
6059 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6061 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6062 (!cast<PatFrag>("zextloadvi" # SrcTy) addrmode6:$addr)),
6063 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
6064 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6066 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6067 (!cast<PatFrag>("sextloadvi" # SrcTy) addrmode6:$addr)),
6068 (!cast<Instruction>("VMOVLsv" # DestLanes # DestTy)
6069 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6073 // extload, zextload and sextload for a lengthening load which only uses
6074 // half the lanes available. Example:
6075 // Lengthen_HalfSingle<"4", "i16", "8", "i16", "i8"> =
6076 // Pat<(v4i16 (extloadvi8 addrmode6oneL32:$addr)),
6077 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
6078 // (f64 (IMPLICIT_DEF)), (i32 0))),
6080 multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
6081 string InsnLanes, string InsnTy> {
6082 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6083 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6084 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6085 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6087 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6088 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6089 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6090 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6092 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6093 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6094 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
6095 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6099 // extload, zextload and sextload for a lengthening load followed by another
6100 // lengthening load, to quadruple the initial length.
6102 // Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32"> =
6103 // Pat<(v4i32 (extloadvi8 addrmode6oneL32:$addr))
6104 // (EXTRACT_SUBREG (VMOVLuv4i32
6105 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
6106 // (f64 (IMPLICIT_DEF)),
6110 multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
6111 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6113 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6114 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6115 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6116 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6117 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6119 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6120 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6121 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6122 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6123 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6125 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6126 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6127 (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6128 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6129 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6133 // extload, zextload and sextload for a lengthening load followed by another
6134 // lengthening load, to quadruple the initial length, but which ends up only
6135 // requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
6137 // Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> =
6138 // Pat<(v2i32 (extloadvi8 addrmode6:$addr))
6139 // (EXTRACT_SUBREG (VMOVLuv4i32
6140 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr,
6141 // (f64 (IMPLICIT_DEF)), (i32 0))),
6144 multiclass Lengthen_HalfDouble<string DestLanes, string DestTy, string SrcTy,
6145 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6147 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6148 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6:$addr)),
6149 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6150 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6151 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6154 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6155 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6:$addr)),
6156 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6157 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6158 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6161 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6162 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6:$addr)),
6163 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6164 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6165 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6170 defm : Lengthen_Single<"8", "i16", "8">; // v8i8 -> v8i16
6171 defm : Lengthen_Single<"4", "i32", "16">; // v4i16 -> v4i32
6172 defm : Lengthen_Single<"2", "i64", "32">; // v2i32 -> v2i64
6174 defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16
6175 defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
6177 // Double lengthening - v4i8 -> v4i16 -> v4i32
6178 defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32">;
6179 // v2i8 -> v2i16 -> v2i32
6180 defm : Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32">;
6181 // v2i16 -> v2i32 -> v2i64
6182 defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64">;
6184 // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
6185 def : Pat<(v2i64 (extloadvi8 addrmode6:$addr)),
6186 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6187 (VLD1LNd16 addrmode6:$addr,
6188 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6189 def : Pat<(v2i64 (zextloadvi8 addrmode6:$addr)),
6190 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6191 (VLD1LNd16 addrmode6:$addr,
6192 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6193 def : Pat<(v2i64 (sextloadvi8 addrmode6:$addr)),
6194 (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
6195 (VLD1LNd16 addrmode6:$addr,
6196 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6198 //===----------------------------------------------------------------------===//
6199 // Assembler aliases
6202 def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
6203 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
6204 def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
6205 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;
6207 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
6208 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
6209 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6210 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
6211 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6212 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
6213 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6214 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
6215 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6216 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
6217 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6218 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
6219 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6220 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
6221 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6222 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
6223 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6224 // ... two-operand aliases
6225 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
6226 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6227 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
6228 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6229 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
6230 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6231 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
6232 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6233 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
6234 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6235 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
6236 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6238 // VLD1 single-lane pseudo-instructions. These need special handling for
6239 // the lane index that an InstAlias can't handle, so we use these instead.
6240 def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
6241 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6242 def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr",
6243 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6244 def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr",
6245 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6247 def VLD1LNdWB_fixed_Asm_8 :
6248 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!",
6249 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6250 def VLD1LNdWB_fixed_Asm_16 :
6251 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!",
6252 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6253 def VLD1LNdWB_fixed_Asm_32 :
6254 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!",
6255 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6256 def VLD1LNdWB_register_Asm_8 :
6257 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm",
6258 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
6259 rGPR:$Rm, pred:$p)>;
6260 def VLD1LNdWB_register_Asm_16 :
6261 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm",
6262 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
6263 rGPR:$Rm, pred:$p)>;
6264 def VLD1LNdWB_register_Asm_32 :
6265 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm",
6266 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
6267 rGPR:$Rm, pred:$p)>;
6270 // VST1 single-lane pseudo-instructions. These need special handling for
6271 // the lane index that an InstAlias can't handle, so we use these instead.
6272 def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr",
6273 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6274 def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr",
6275 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6276 def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr",
6277 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6279 def VST1LNdWB_fixed_Asm_8 :
6280 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!",
6281 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6282 def VST1LNdWB_fixed_Asm_16 :
6283 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!",
6284 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6285 def VST1LNdWB_fixed_Asm_32 :
6286 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!",
6287 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6288 def VST1LNdWB_register_Asm_8 :
6289 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm",
6290 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
6291 rGPR:$Rm, pred:$p)>;
6292 def VST1LNdWB_register_Asm_16 :
6293 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm",
6294 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
6295 rGPR:$Rm, pred:$p)>;
6296 def VST1LNdWB_register_Asm_32 :
6297 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm",
6298 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
6299 rGPR:$Rm, pred:$p)>;
6301 // VLD2 single-lane pseudo-instructions. These need special handling for
6302 // the lane index that an InstAlias can't handle, so we use these instead.
6303 def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr",
6304 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6305 def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6306 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6307 def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6308 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6309 def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6310 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6311 def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6312 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6314 def VLD2LNdWB_fixed_Asm_8 :
6315 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!",
6316 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6317 def VLD2LNdWB_fixed_Asm_16 :
6318 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6319 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6320 def VLD2LNdWB_fixed_Asm_32 :
6321 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6322 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6323 def VLD2LNqWB_fixed_Asm_16 :
6324 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6325 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6326 def VLD2LNqWB_fixed_Asm_32 :
6327 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6328 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6329 def VLD2LNdWB_register_Asm_8 :
6330 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm",
6331 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
6332 rGPR:$Rm, pred:$p)>;
6333 def VLD2LNdWB_register_Asm_16 :
6334 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6335 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
6336 rGPR:$Rm, pred:$p)>;
6337 def VLD2LNdWB_register_Asm_32 :
6338 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6339 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
6340 rGPR:$Rm, pred:$p)>;
6341 def VLD2LNqWB_register_Asm_16 :
6342 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6343 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
6344 rGPR:$Rm, pred:$p)>;
6345 def VLD2LNqWB_register_Asm_32 :
6346 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6347 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
6348 rGPR:$Rm, pred:$p)>;
6351 // VST2 single-lane pseudo-instructions. These need special handling for
6352 // the lane index that an InstAlias can't handle, so we use these instead.
6353 def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr",
6354 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6355 def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6356 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6357 def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6358 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6359 def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6360 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6361 def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6362 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6364 def VST2LNdWB_fixed_Asm_8 :
6365 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!",
6366 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6367 def VST2LNdWB_fixed_Asm_16 :
6368 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6369 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6370 def VST2LNdWB_fixed_Asm_32 :
6371 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6372 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6373 def VST2LNqWB_fixed_Asm_16 :
6374 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6375 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6376 def VST2LNqWB_fixed_Asm_32 :
6377 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6378 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6379 def VST2LNdWB_register_Asm_8 :
6380 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm",
6381 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
6382 rGPR:$Rm, pred:$p)>;
6383 def VST2LNdWB_register_Asm_16 :
6384 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6385 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
6386 rGPR:$Rm, pred:$p)>;
6387 def VST2LNdWB_register_Asm_32 :
6388 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6389 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
6390 rGPR:$Rm, pred:$p)>;
6391 def VST2LNqWB_register_Asm_16 :
6392 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6393 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr,
6394 rGPR:$Rm, pred:$p)>;
6395 def VST2LNqWB_register_Asm_32 :
6396 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6397 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr,
6398 rGPR:$Rm, pred:$p)>;
6400 // VLD3 all-lanes pseudo-instructions. These need special handling for
6401 // the lane index that an InstAlias can't handle, so we use these instead.
6402 def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6403 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6404 def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6405 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6406 def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6407 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6408 def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6409 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6410 def VLD3DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6411 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6412 def VLD3DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6413 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6415 def VLD3DUPdWB_fixed_Asm_8 :
6416 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6417 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6418 def VLD3DUPdWB_fixed_Asm_16 :
6419 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6420 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6421 def VLD3DUPdWB_fixed_Asm_32 :
6422 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6423 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6424 def VLD3DUPqWB_fixed_Asm_8 :
6425 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6426 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6427 def VLD3DUPqWB_fixed_Asm_16 :
6428 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6429 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6430 def VLD3DUPqWB_fixed_Asm_32 :
6431 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6432 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6433 def VLD3DUPdWB_register_Asm_8 :
6434 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6435 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6436 rGPR:$Rm, pred:$p)>;
6437 def VLD3DUPdWB_register_Asm_16 :
6438 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6439 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6440 rGPR:$Rm, pred:$p)>;
6441 def VLD3DUPdWB_register_Asm_32 :
6442 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6443 (ins VecListThreeDAllLanes:$list, addrmode6:$addr,
6444 rGPR:$Rm, pred:$p)>;
6445 def VLD3DUPqWB_register_Asm_8 :
6446 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6447 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6448 rGPR:$Rm, pred:$p)>;
6449 def VLD3DUPqWB_register_Asm_16 :
6450 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6451 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6452 rGPR:$Rm, pred:$p)>;
6453 def VLD3DUPqWB_register_Asm_32 :
6454 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6455 (ins VecListThreeQAllLanes:$list, addrmode6:$addr,
6456 rGPR:$Rm, pred:$p)>;
6459 // VLD3 single-lane pseudo-instructions. These need special handling for
6460 // the lane index that an InstAlias can't handle, so we use these instead.
6461 def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6462 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6463 def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6464 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6465 def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6466 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6467 def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6468 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6469 def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6470 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6472 def VLD3LNdWB_fixed_Asm_8 :
6473 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6474 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6475 def VLD3LNdWB_fixed_Asm_16 :
6476 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6477 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6478 def VLD3LNdWB_fixed_Asm_32 :
6479 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6480 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6481 def VLD3LNqWB_fixed_Asm_16 :
6482 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6483 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6484 def VLD3LNqWB_fixed_Asm_32 :
6485 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6486 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6487 def VLD3LNdWB_register_Asm_8 :
6488 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6489 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
6490 rGPR:$Rm, pred:$p)>;
6491 def VLD3LNdWB_register_Asm_16 :
6492 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6493 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6494 rGPR:$Rm, pred:$p)>;
6495 def VLD3LNdWB_register_Asm_32 :
6496 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6497 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
6498 rGPR:$Rm, pred:$p)>;
6499 def VLD3LNqWB_register_Asm_16 :
6500 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6501 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6502 rGPR:$Rm, pred:$p)>;
6503 def VLD3LNqWB_register_Asm_32 :
6504 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6505 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
6506 rGPR:$Rm, pred:$p)>;
6508 // VLD3 multiple structure pseudo-instructions. These need special handling for
6509 // the vector operands that the normal instructions don't yet model.
6510 // FIXME: Remove these when the register classes and instructions are updated.
6511 def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6512 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6513 def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6514 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6515 def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6516 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6517 def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6518 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6519 def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6520 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6521 def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6522 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6524 def VLD3dWB_fixed_Asm_8 :
6525 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6526 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6527 def VLD3dWB_fixed_Asm_16 :
6528 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6529 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6530 def VLD3dWB_fixed_Asm_32 :
6531 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6532 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6533 def VLD3qWB_fixed_Asm_8 :
6534 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6535 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6536 def VLD3qWB_fixed_Asm_16 :
6537 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6538 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6539 def VLD3qWB_fixed_Asm_32 :
6540 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6541 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6542 def VLD3dWB_register_Asm_8 :
6543 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6544 (ins VecListThreeD:$list, addrmode6:$addr,
6545 rGPR:$Rm, pred:$p)>;
6546 def VLD3dWB_register_Asm_16 :
6547 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6548 (ins VecListThreeD:$list, addrmode6:$addr,
6549 rGPR:$Rm, pred:$p)>;
6550 def VLD3dWB_register_Asm_32 :
6551 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6552 (ins VecListThreeD:$list, addrmode6:$addr,
6553 rGPR:$Rm, pred:$p)>;
6554 def VLD3qWB_register_Asm_8 :
6555 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6556 (ins VecListThreeQ:$list, addrmode6:$addr,
6557 rGPR:$Rm, pred:$p)>;
6558 def VLD3qWB_register_Asm_16 :
6559 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6560 (ins VecListThreeQ:$list, addrmode6:$addr,
6561 rGPR:$Rm, pred:$p)>;
6562 def VLD3qWB_register_Asm_32 :
6563 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6564 (ins VecListThreeQ:$list, addrmode6:$addr,
6565 rGPR:$Rm, pred:$p)>;
6567 // VST3 single-lane pseudo-instructions. These need special handling for
6568 // the lane index that an InstAlias can't handle, so we use these instead.
6569 def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6570 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6571 def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6572 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6573 def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6574 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6575 def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6576 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6577 def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6578 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6580 def VST3LNdWB_fixed_Asm_8 :
6581 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6582 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6583 def VST3LNdWB_fixed_Asm_16 :
6584 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6585 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6586 def VST3LNdWB_fixed_Asm_32 :
6587 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6588 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6589 def VST3LNqWB_fixed_Asm_16 :
6590 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6591 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6592 def VST3LNqWB_fixed_Asm_32 :
6593 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6594 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6595 def VST3LNdWB_register_Asm_8 :
6596 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6597 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr,
6598 rGPR:$Rm, pred:$p)>;
6599 def VST3LNdWB_register_Asm_16 :
6600 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6601 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr,
6602 rGPR:$Rm, pred:$p)>;
6603 def VST3LNdWB_register_Asm_32 :
6604 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6605 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr,
6606 rGPR:$Rm, pred:$p)>;
6607 def VST3LNqWB_register_Asm_16 :
6608 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6609 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr,
6610 rGPR:$Rm, pred:$p)>;
6611 def VST3LNqWB_register_Asm_32 :
6612 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6613 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr,
6614 rGPR:$Rm, pred:$p)>;
6617 // VST3 multiple structure pseudo-instructions. These need special handling for
6618 // the vector operands that the normal instructions don't yet model.
6619 // FIXME: Remove these when the register classes and instructions are updated.
6620 def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6621 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6622 def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6623 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6624 def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6625 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6626 def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6627 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6628 def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6629 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6630 def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6631 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6633 def VST3dWB_fixed_Asm_8 :
6634 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6635 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6636 def VST3dWB_fixed_Asm_16 :
6637 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6638 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6639 def VST3dWB_fixed_Asm_32 :
6640 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6641 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>;
6642 def VST3qWB_fixed_Asm_8 :
6643 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6644 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6645 def VST3qWB_fixed_Asm_16 :
6646 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6647 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6648 def VST3qWB_fixed_Asm_32 :
6649 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6650 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>;
6651 def VST3dWB_register_Asm_8 :
6652 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6653 (ins VecListThreeD:$list, addrmode6:$addr,
6654 rGPR:$Rm, pred:$p)>;
6655 def VST3dWB_register_Asm_16 :
6656 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6657 (ins VecListThreeD:$list, addrmode6:$addr,
6658 rGPR:$Rm, pred:$p)>;
6659 def VST3dWB_register_Asm_32 :
6660 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6661 (ins VecListThreeD:$list, addrmode6:$addr,
6662 rGPR:$Rm, pred:$p)>;
6663 def VST3qWB_register_Asm_8 :
6664 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6665 (ins VecListThreeQ:$list, addrmode6:$addr,
6666 rGPR:$Rm, pred:$p)>;
6667 def VST3qWB_register_Asm_16 :
6668 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6669 (ins VecListThreeQ:$list, addrmode6:$addr,
6670 rGPR:$Rm, pred:$p)>;
6671 def VST3qWB_register_Asm_32 :
6672 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6673 (ins VecListThreeQ:$list, addrmode6:$addr,
6674 rGPR:$Rm, pred:$p)>;
6676 // VLD4 all-lanes pseudo-instructions. These need special handling for
6677 // the lane index that an InstAlias can't handle, so we use these instead.
6678 def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6679 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6680 def VLD4DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6681 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6682 def VLD4DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6683 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6684 def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6685 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6686 def VLD4DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6687 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6688 def VLD4DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6689 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6691 def VLD4DUPdWB_fixed_Asm_8 :
6692 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6693 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6694 def VLD4DUPdWB_fixed_Asm_16 :
6695 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6696 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6697 def VLD4DUPdWB_fixed_Asm_32 :
6698 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6699 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
6700 def VLD4DUPqWB_fixed_Asm_8 :
6701 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6702 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6703 def VLD4DUPqWB_fixed_Asm_16 :
6704 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6705 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6706 def VLD4DUPqWB_fixed_Asm_32 :
6707 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6708 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
6709 def VLD4DUPdWB_register_Asm_8 :
6710 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6711 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6712 rGPR:$Rm, pred:$p)>;
6713 def VLD4DUPdWB_register_Asm_16 :
6714 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6715 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6716 rGPR:$Rm, pred:$p)>;
6717 def VLD4DUPdWB_register_Asm_32 :
6718 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6719 (ins VecListFourDAllLanes:$list, addrmode6:$addr,
6720 rGPR:$Rm, pred:$p)>;
6721 def VLD4DUPqWB_register_Asm_8 :
6722 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6723 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6724 rGPR:$Rm, pred:$p)>;
6725 def VLD4DUPqWB_register_Asm_16 :
6726 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6727 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6728 rGPR:$Rm, pred:$p)>;
6729 def VLD4DUPqWB_register_Asm_32 :
6730 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6731 (ins VecListFourQAllLanes:$list, addrmode6:$addr,
6732 rGPR:$Rm, pred:$p)>;
6735 // VLD4 single-lane pseudo-instructions. These need special handling for
6736 // the lane index that an InstAlias can't handle, so we use these instead.
6737 def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6738 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6739 def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6740 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6741 def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6742 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6743 def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6744 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6745 def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6746 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6748 def VLD4LNdWB_fixed_Asm_8 :
6749 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6750 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6751 def VLD4LNdWB_fixed_Asm_16 :
6752 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6753 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6754 def VLD4LNdWB_fixed_Asm_32 :
6755 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6756 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6757 def VLD4LNqWB_fixed_Asm_16 :
6758 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6759 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6760 def VLD4LNqWB_fixed_Asm_32 :
6761 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6762 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6763 def VLD4LNdWB_register_Asm_8 :
6764 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6765 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
6766 rGPR:$Rm, pred:$p)>;
6767 def VLD4LNdWB_register_Asm_16 :
6768 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6769 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
6770 rGPR:$Rm, pred:$p)>;
6771 def VLD4LNdWB_register_Asm_32 :
6772 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6773 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6774 rGPR:$Rm, pred:$p)>;
6775 def VLD4LNqWB_register_Asm_16 :
6776 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6777 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
6778 rGPR:$Rm, pred:$p)>;
6779 def VLD4LNqWB_register_Asm_32 :
6780 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6781 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6782 rGPR:$Rm, pred:$p)>;
6786 // VLD4 multiple structure pseudo-instructions. These need special handling for
6787 // the vector operands that the normal instructions don't yet model.
6788 // FIXME: Remove these when the register classes and instructions are updated.
6789 def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6790 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6791 def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6792 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6793 def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6794 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6795 def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6796 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6797 def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6798 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6799 def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6800 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6802 def VLD4dWB_fixed_Asm_8 :
6803 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6804 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6805 def VLD4dWB_fixed_Asm_16 :
6806 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6807 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6808 def VLD4dWB_fixed_Asm_32 :
6809 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6810 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6811 def VLD4qWB_fixed_Asm_8 :
6812 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6813 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6814 def VLD4qWB_fixed_Asm_16 :
6815 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6816 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6817 def VLD4qWB_fixed_Asm_32 :
6818 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6819 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6820 def VLD4dWB_register_Asm_8 :
6821 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6822 (ins VecListFourD:$list, addrmode6:$addr,
6823 rGPR:$Rm, pred:$p)>;
6824 def VLD4dWB_register_Asm_16 :
6825 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6826 (ins VecListFourD:$list, addrmode6:$addr,
6827 rGPR:$Rm, pred:$p)>;
6828 def VLD4dWB_register_Asm_32 :
6829 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6830 (ins VecListFourD:$list, addrmode6:$addr,
6831 rGPR:$Rm, pred:$p)>;
6832 def VLD4qWB_register_Asm_8 :
6833 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6834 (ins VecListFourQ:$list, addrmode6:$addr,
6835 rGPR:$Rm, pred:$p)>;
6836 def VLD4qWB_register_Asm_16 :
6837 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6838 (ins VecListFourQ:$list, addrmode6:$addr,
6839 rGPR:$Rm, pred:$p)>;
6840 def VLD4qWB_register_Asm_32 :
6841 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6842 (ins VecListFourQ:$list, addrmode6:$addr,
6843 rGPR:$Rm, pred:$p)>;
6845 // VST4 single-lane pseudo-instructions. These need special handling for
6846 // the lane index that an InstAlias can't handle, so we use these instead.
6847 def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6848 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6849 def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6850 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6851 def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6852 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6853 def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6854 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6855 def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6856 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6858 def VST4LNdWB_fixed_Asm_8 :
6859 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6860 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
6861 def VST4LNdWB_fixed_Asm_16 :
6862 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6863 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6864 def VST4LNdWB_fixed_Asm_32 :
6865 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6866 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6867 def VST4LNqWB_fixed_Asm_16 :
6868 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6869 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6870 def VST4LNqWB_fixed_Asm_32 :
6871 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6872 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>;
6873 def VST4LNdWB_register_Asm_8 :
6874 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6875 (ins VecListFourDByteIndexed:$list, addrmode6:$addr,
6876 rGPR:$Rm, pred:$p)>;
6877 def VST4LNdWB_register_Asm_16 :
6878 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6879 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr,
6880 rGPR:$Rm, pred:$p)>;
6881 def VST4LNdWB_register_Asm_32 :
6882 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6883 (ins VecListFourDWordIndexed:$list, addrmode6:$addr,
6884 rGPR:$Rm, pred:$p)>;
6885 def VST4LNqWB_register_Asm_16 :
6886 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6887 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr,
6888 rGPR:$Rm, pred:$p)>;
6889 def VST4LNqWB_register_Asm_32 :
6890 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6891 (ins VecListFourQWordIndexed:$list, addrmode6:$addr,
6892 rGPR:$Rm, pred:$p)>;
6895 // VST4 multiple structure pseudo-instructions. These need special handling for
6896 // the vector operands that the normal instructions don't yet model.
6897 // FIXME: Remove these when the register classes and instructions are updated.
6898 def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6899 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6900 def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6901 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6902 def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6903 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6904 def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
6905 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6906 def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
6907 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6908 def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
6909 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6911 def VST4dWB_fixed_Asm_8 :
6912 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6913 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6914 def VST4dWB_fixed_Asm_16 :
6915 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6916 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6917 def VST4dWB_fixed_Asm_32 :
6918 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6919 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>;
6920 def VST4qWB_fixed_Asm_8 :
6921 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
6922 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6923 def VST4qWB_fixed_Asm_16 :
6924 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
6925 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6926 def VST4qWB_fixed_Asm_32 :
6927 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
6928 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>;
6929 def VST4dWB_register_Asm_8 :
6930 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6931 (ins VecListFourD:$list, addrmode6:$addr,
6932 rGPR:$Rm, pred:$p)>;
6933 def VST4dWB_register_Asm_16 :
6934 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6935 (ins VecListFourD:$list, addrmode6:$addr,
6936 rGPR:$Rm, pred:$p)>;
6937 def VST4dWB_register_Asm_32 :
6938 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6939 (ins VecListFourD:$list, addrmode6:$addr,
6940 rGPR:$Rm, pred:$p)>;
6941 def VST4qWB_register_Asm_8 :
6942 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
6943 (ins VecListFourQ:$list, addrmode6:$addr,
6944 rGPR:$Rm, pred:$p)>;
6945 def VST4qWB_register_Asm_16 :
6946 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
6947 (ins VecListFourQ:$list, addrmode6:$addr,
6948 rGPR:$Rm, pred:$p)>;
6949 def VST4qWB_register_Asm_32 :
6950 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
6951 (ins VecListFourQ:$list, addrmode6:$addr,
6952 rGPR:$Rm, pred:$p)>;
6954 // VMOV/VMVN takes an optional datatype suffix
6955 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
6956 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
6957 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
6958 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
6960 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
6961 (VMVNd DPR:$Vd, DPR:$Vm, pred:$p)>;
6962 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
6963 (VMVNq QPR:$Vd, QPR:$Vm, pred:$p)>;
6965 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
6966 // D-register versions.
6967 def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm",
6968 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6969 def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm",
6970 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6971 def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm",
6972 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6973 def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm",
6974 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6975 def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm",
6976 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6977 def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm",
6978 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6979 def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm",
6980 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
6981 // Q-register versions.
6982 def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
6983 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6984 def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
6985 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6986 def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
6987 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6988 def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
6989 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6990 def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
6991 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6992 def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
6993 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6994 def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
6995 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
6997 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
6998 // D-register versions.
6999 def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
7000 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7001 def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
7002 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7003 def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
7004 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7005 def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
7006 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7007 def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
7008 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7009 def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
7010 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7011 def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
7012 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7013 // Q-register versions.
7014 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
7015 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7016 def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
7017 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7018 def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm",
7019 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7020 def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm",
7021 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7022 def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm",
7023 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7024 def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
7025 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7026 def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
7027 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7029 // VSWP allows, but does not require, a type suffix.
7030 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
7031 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
7032 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
7033 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
7035 // VBIF, VBIT, and VBSL allow, but do not require, a type suffix.
7036 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
7037 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7038 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
7039 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7040 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
7041 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7042 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
7043 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7044 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
7045 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7046 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
7047 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7049 // "vmov Rd, #-imm" can be handled via "vmvn".
7050 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
7051 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7052 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
7053 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7054 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
7055 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7056 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
7057 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7059 // 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
7060 // these should restrict to just the Q register variants, but the register
7061 // classes are enough to match correctly regardless, so we keep it simple
7062 // and just use MnemonicAlias.
7063 def : NEONMnemonicAlias<"vbicq", "vbic">;
7064 def : NEONMnemonicAlias<"vandq", "vand">;
7065 def : NEONMnemonicAlias<"veorq", "veor">;
7066 def : NEONMnemonicAlias<"vorrq", "vorr">;
7068 def : NEONMnemonicAlias<"vmovq", "vmov">;
7069 def : NEONMnemonicAlias<"vmvnq", "vmvn">;
7070 // Explicit versions for floating point so that the FPImm variants get
7071 // handled early. The parser gets confused otherwise.
7072 def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">;
7073 def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">;
7075 def : NEONMnemonicAlias<"vaddq", "vadd">;
7076 def : NEONMnemonicAlias<"vsubq", "vsub">;
7078 def : NEONMnemonicAlias<"vminq", "vmin">;
7079 def : NEONMnemonicAlias<"vmaxq", "vmax">;
7081 def : NEONMnemonicAlias<"vmulq", "vmul">;
7083 def : NEONMnemonicAlias<"vabsq", "vabs">;
7085 def : NEONMnemonicAlias<"vshlq", "vshl">;
7086 def : NEONMnemonicAlias<"vshrq", "vshr">;
7088 def : NEONMnemonicAlias<"vcvtq", "vcvt">;
7090 def : NEONMnemonicAlias<"vcleq", "vcle">;
7091 def : NEONMnemonicAlias<"vceqq", "vceq">;
7093 def : NEONMnemonicAlias<"vzipq", "vzip">;
7094 def : NEONMnemonicAlias<"vswpq", "vswp">;
7096 def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">;
7097 def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">;
7100 // Alias for loading floating point immediates that aren't representable
7101 // using the vmov.f32 encoding but the bitpattern is representable using
7102 // the .i32 encoding.
7103 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
7104 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
7105 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
7106 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;