1 //===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
16 def op_addr_mode1 : Operand<iPTR> {
17 let PrintMethod = "printAddrMode1";
18 let NumMIOperands = 1;
19 let MIOperandInfo = (ops ptr_rc);
22 def memri : Operand<iPTR> {
23 let PrintMethod = "printMemRegImm";
24 let NumMIOperands = 2;
25 let MIOperandInfo = (ops i32imm, ptr_rc);
28 // Define ARM specific addressing mode.
29 //Addressing Mode 1: data processing operands
30 def addr_mode1 : ComplexPattern<iPTR, 1, "SelectAddrMode1", [imm]>;
32 //register plus/minus 12 bit offset
33 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex]>;
34 //register plus scaled register
35 //def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", []>;
37 //===----------------------------------------------------------------------===//
39 //===----------------------------------------------------------------------===//
41 class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
42 let Namespace = "ARM";
44 dag OperandList = ops;
45 let AsmString = asmstr;
46 let Pattern = pattern;
49 def brtarget : Operand<OtherVT>;
51 // Operand for printing out a condition code.
52 let PrintMethod = "printCCOperand" in
53 def CCOp : Operand<i32>;
55 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
56 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
57 [SDNPHasChain, SDNPOutFlag]>;
58 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
59 [SDNPHasChain, SDNPOutFlag]>;
61 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
62 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
63 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
64 def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
65 [SDNPHasChain, SDNPOptInFlag]>;
67 def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>;
69 def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
71 def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
72 def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
74 def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
75 def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
77 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
78 "!ADJCALLSTACKUP $amt",
79 [(callseq_end imm:$amt)]>;
81 def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
82 "!ADJCALLSTACKDOWN $amt",
83 [(callseq_start imm:$amt)]>;
86 def bx: InstARM<(ops), "bx r14", [(retflag)]>;
89 let Defs = [R0, R1, R2, R3, R14] in {
90 def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
93 def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
95 [(set IntRegs:$dst, (load iaddr:$addr))]>;
97 def str : InstARM<(ops IntRegs:$src, memri:$addr),
99 [(store IntRegs:$src, iaddr:$addr)]>;
101 def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
102 "mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
104 def ADD : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
106 [(set IntRegs:$dst, (add IntRegs:$a, addr_mode1:$b))]>;
108 // "LEA" forms of add
109 def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
110 "add $dst, ${addr:arith}",
111 [(set IntRegs:$dst, iaddr:$addr)]>;
114 def SUB : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
116 [(set IntRegs:$dst, (sub IntRegs:$a, addr_mode1:$b))]>;
118 def AND : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
120 [(set IntRegs:$dst, (and IntRegs:$a, addr_mode1:$b))]>;
122 // All arm data processing instructions have a shift. Maybe we don't have
124 def SHL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
125 "mov $dst, $a, lsl $b",
126 [(set IntRegs:$dst, (shl IntRegs:$a, IntRegs:$b))]>;
128 def SRA : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
129 "mov $dst, $a, asr $b",
130 [(set IntRegs:$dst, (sra IntRegs:$a, IntRegs:$b))]>;
132 def SRL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
133 "mov $dst, $a, lsr $b",
134 [(set IntRegs:$dst, (srl IntRegs:$a, IntRegs:$b))]>;
137 def EOR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
139 [(set IntRegs:$dst, (xor IntRegs:$a, addr_mode1:$b))]>;
141 def ORR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
143 [(set IntRegs:$dst, (or IntRegs:$a, addr_mode1:$b))]>;
145 let isTwoAddress = 1 in {
146 def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
147 op_addr_mode1:$true, CCOp:$cc),
148 "mov$cc $dst, $true",
149 [(set IntRegs:$dst, (armselect addr_mode1:$true,
150 IntRegs:$false, imm:$cc))]>;
153 def MUL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
155 [(set IntRegs:$dst, (mul IntRegs:$a, IntRegs:$b))]>;
157 def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
159 [(armbr bb:$dst, imm:$cc)]>;
161 def b : InstARM<(ops brtarget:$dst),
165 def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b),
167 [(armcmp IntRegs:$a, addr_mode1:$b)]>;