1 //===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
16 def memri : Operand<iPTR> {
17 let PrintMethod = "printMemRegImm";
18 let NumMIOperands = 2;
19 let MIOperandInfo = (ops i32imm, ptr_rc);
22 // Define ARM specific addressing mode.
23 //register plus/minus 12 bit offset
24 def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex]>;
25 //register plus scaled register
26 //def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", []>;
28 //===----------------------------------------------------------------------===//
30 //===----------------------------------------------------------------------===//
32 class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
33 let Namespace = "ARM";
35 dag OperandList = ops;
36 let AsmString = asmstr;
37 let Pattern = pattern;
40 def brtarget : Operand<OtherVT>;
42 // Operand for printing out a condition code.
43 let PrintMethod = "printCCOperand" in
44 def CCOp : Operand<i32>;
46 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
47 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
48 [SDNPHasChain, SDNPOutFlag]>;
49 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
50 [SDNPHasChain, SDNPOutFlag]>;
52 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
53 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
54 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
55 def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
56 [SDNPHasChain, SDNPOptInFlag]>;
58 def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisVT<2, i32>]>;
60 def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
62 def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
63 def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag]>;
65 def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
66 def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
68 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
69 "!ADJCALLSTACKUP $amt",
70 [(callseq_end imm:$amt)]>;
72 def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
73 "!ADJCALLSTACKDOWN $amt",
74 [(callseq_start imm:$amt)]>;
77 def bx: InstARM<(ops), "bx r14", [(retflag)]>;
80 let Defs = [R0, R1, R2, R3, R14] in {
81 def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", [(ARMcall tglobaladdr:$func)]>;
84 def ldr : InstARM<(ops IntRegs:$dst, memri:$addr),
86 [(set IntRegs:$dst, (load iaddr:$addr))]>;
88 def str : InstARM<(ops IntRegs:$src, memri:$addr),
90 [(store IntRegs:$src, iaddr:$addr)]>;
92 def movrr : InstARM<(ops IntRegs:$dst, IntRegs:$src),
93 "mov $dst, $src", []>;
95 def movri : InstARM<(ops IntRegs:$dst, i32imm:$src),
96 "mov $dst, $src", [(set IntRegs:$dst, imm:$src)]>;
98 def addri : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
100 [(set IntRegs:$dst, (add IntRegs:$a, imm:$b))]>;
102 // "LEA" forms of add
103 def lea_addri : InstARM<(ops IntRegs:$dst, memri:$addr),
104 "add $dst, ${addr:arith}",
105 [(set IntRegs:$dst, iaddr:$addr)]>;
108 def subri : InstARM<(ops IntRegs:$dst, IntRegs:$a, i32imm:$b),
110 [(set IntRegs:$dst, (sub IntRegs:$a, imm:$b))]>;
112 def andrr : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
114 [(set IntRegs:$dst, (and IntRegs:$a, IntRegs:$b))]>;
117 // All arm data processing instructions have a shift. Maybe we don't have
119 def SHL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
120 "mov $dst, $a, lsl $b",
121 [(set IntRegs:$dst, (shl IntRegs:$a, IntRegs:$b))]>;
123 def SRA : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
124 "mov $dst, $a, asr $b",
125 [(set IntRegs:$dst, (sra IntRegs:$a, IntRegs:$b))]>;
128 def eor_rr : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
130 [(set IntRegs:$dst, (xor IntRegs:$a, IntRegs:$b))]>;
132 def orr_rr : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
134 [(set IntRegs:$dst, (or IntRegs:$a, IntRegs:$b))]>;
137 let isTwoAddress = 1 in {
138 def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false, IntRegs:$true, CCOp:$cc),
139 "mov$cc $dst, $true",
140 [(set IntRegs:$dst, (armselect IntRegs:$true, IntRegs:$false, imm:$cc))]>;
143 def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
145 [(armbr bb:$dst, imm:$cc)]>;
147 def b : InstARM<(ops brtarget:$dst),
151 def cmp : InstARM<(ops IntRegs:$a, IntRegs:$b),
153 [(armcmp IntRegs:$a, IntRegs:$b)]>;