1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
75 def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
77 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
80 SDTCisInt<0>, SDTCisVT<1, i32>]>;
82 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
83 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
90 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
91 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
92 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
93 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
94 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
97 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
98 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
99 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
100 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
102 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
103 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
104 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
105 [SDNPHasChain, SDNPSideEffect,
106 SDNPOptInGlue, SDNPOutGlue]>;
107 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
109 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
110 SDNPMayStore, SDNPMayLoad]>;
112 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
115 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
118 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
119 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
122 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
123 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
124 def ARMintretflag : SDNode<"ARMISD::INTRET_FLAG", SDT_ARMcall,
125 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
126 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
129 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
130 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
132 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
134 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
137 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
140 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
143 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
146 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
147 [SDNPOutGlue, SDNPCommutative]>;
149 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
151 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
152 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
153 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
155 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
157 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
158 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
159 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
161 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
162 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
163 SDT_ARMEH_SJLJ_Setjmp,
164 [SDNPHasChain, SDNPSideEffect]>;
165 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
166 SDT_ARMEH_SJLJ_Longjmp,
167 [SDNPHasChain, SDNPSideEffect]>;
169 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
170 [SDNPHasChain, SDNPSideEffect]>;
171 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
172 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
174 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
176 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
177 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
179 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
181 def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
182 def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
184 //===----------------------------------------------------------------------===//
185 // ARM Instruction Predicate Definitions.
187 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
188 AssemblerPredicate<"HasV4TOps", "armv4t">;
189 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
190 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
191 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
192 AssemblerPredicate<"HasV5TEOps", "armv5te">;
193 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
194 AssemblerPredicate<"HasV6Ops", "armv6">;
195 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
196 def HasV6M : Predicate<"Subtarget->hasV6MOps()">,
197 AssemblerPredicate<"HasV6MOps",
198 "armv6m or armv6t2">;
199 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
200 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
201 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
202 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
203 AssemblerPredicate<"HasV7Ops", "armv7">;
204 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
205 AssemblerPredicate<"HasV8Ops", "armv8">;
206 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
207 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
208 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
209 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
210 AssemblerPredicate<"FeatureVFP2", "VFP2">;
211 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
212 AssemblerPredicate<"FeatureVFP3", "VFP3">;
213 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
214 AssemblerPredicate<"FeatureVFP4", "VFP4">;
215 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
216 AssemblerPredicate<"FeatureFPARMv8", "FPARMv8">;
217 def HasNEON : Predicate<"Subtarget->hasNEON()">,
218 AssemblerPredicate<"FeatureNEON", "NEON">;
219 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
220 AssemblerPredicate<"FeatureCrypto", "crypto">;
221 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
222 AssemblerPredicate<"FeatureFP16","half-float">;
223 def HasDivide : Predicate<"Subtarget->hasDivide()">,
224 AssemblerPredicate<"FeatureHWDiv", "divide">;
225 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
226 AssemblerPredicate<"FeatureHWDivARM">;
227 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
228 AssemblerPredicate<"FeatureT2XtPk",
230 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
231 AssemblerPredicate<"FeatureDSPThumb2",
233 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
234 AssemblerPredicate<"FeatureDB",
236 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
237 AssemblerPredicate<"FeatureMP",
239 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
240 AssemblerPredicate<"FeatureTrustZone",
242 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
243 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
244 def IsThumb : Predicate<"Subtarget->isThumb()">,
245 AssemblerPredicate<"ModeThumb", "thumb">;
246 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
247 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
248 AssemblerPredicate<"ModeThumb,FeatureThumb2",
250 def IsMClass : Predicate<"Subtarget->isMClass()">,
251 AssemblerPredicate<"FeatureMClass", "armv*m">;
252 def IsNotMClass : Predicate<"!Subtarget->isMClass()">,
253 AssemblerPredicate<"!FeatureMClass",
255 def IsARM : Predicate<"!Subtarget->isThumb()">,
256 AssemblerPredicate<"!ModeThumb", "arm-mode">;
257 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
258 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
259 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
260 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
261 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
262 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
264 // FIXME: Eventually this will be just "hasV6T2Ops".
265 def UseMovt : Predicate<"Subtarget->useMovt()">;
266 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
267 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
268 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
270 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
271 // But only select them if more precision in FP computation is allowed.
272 // Do not use them for Darwin platforms.
273 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
274 " FPOpFusion::Fast) && "
275 "!Subtarget->isTargetDarwin()">;
276 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
277 " FPOpFusion::Fast &&"
278 " Subtarget->hasVFP4()) || "
279 "Subtarget->isTargetDarwin()">;
281 // VGETLNi32 is microcoded on Swift - prefer VMOV.
282 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
283 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
285 // VDUP.32 is microcoded on Swift - prefer VMOV.
286 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
287 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
289 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
290 // this allows more effective execution domain optimization. See
291 // setExecutionDomain().
292 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
293 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
295 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
296 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
298 //===----------------------------------------------------------------------===//
299 // ARM Flag Definitions.
301 class RegConstraint<string C> {
302 string Constraints = C;
305 //===----------------------------------------------------------------------===//
306 // ARM specific transformation functions and pattern fragments.
309 // imm_neg_XFORM - Return the negation of an i32 immediate value.
310 def imm_neg_XFORM : SDNodeXForm<imm, [{
311 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
314 // imm_not_XFORM - Return the complement of a i32 immediate value.
315 def imm_not_XFORM : SDNodeXForm<imm, [{
316 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
319 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
320 def imm16_31 : ImmLeaf<i32, [{
321 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
324 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
325 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
326 unsigned Value = -(unsigned)N->getZExtValue();
327 return Value && ARM_AM::getSOImmVal(Value) != -1;
329 let ParserMatchClass = so_imm_neg_asmoperand;
332 // Note: this pattern doesn't require an encoder method and such, as it's
333 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
334 // is handled by the destination instructions, which use so_imm.
335 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
336 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
337 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
339 let ParserMatchClass = so_imm_not_asmoperand;
342 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
343 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
344 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
347 /// Split a 32-bit immediate into two 16 bit parts.
348 def hi16 : SDNodeXForm<imm, [{
349 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
352 def lo16AllZero : PatLeaf<(i32 imm), [{
353 // Returns true if all low 16-bits are 0.
354 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
357 class BinOpWithFlagFrag<dag res> :
358 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
359 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
360 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
362 // An 'and' node with a single use.
363 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
364 return N->hasOneUse();
367 // An 'xor' node with a single use.
368 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
369 return N->hasOneUse();
372 // An 'fmul' node with a single use.
373 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
374 return N->hasOneUse();
377 // An 'fadd' node which checks for single non-hazardous use.
378 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
379 return hasNoVMLxHazardUse(N);
382 // An 'fsub' node which checks for single non-hazardous use.
383 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
384 return hasNoVMLxHazardUse(N);
387 //===----------------------------------------------------------------------===//
388 // Operand Definitions.
391 // Immediate operands with a shared generic asm render method.
392 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
395 // FIXME: rename brtarget to t2_brtarget
396 def brtarget : Operand<OtherVT> {
397 let EncoderMethod = "getBranchTargetOpValue";
398 let OperandType = "OPERAND_PCREL";
399 let DecoderMethod = "DecodeT2BROperand";
402 // FIXME: get rid of this one?
403 def uncondbrtarget : Operand<OtherVT> {
404 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
405 let OperandType = "OPERAND_PCREL";
408 // Branch target for ARM. Handles conditional/unconditional
409 def br_target : Operand<OtherVT> {
410 let EncoderMethod = "getARMBranchTargetOpValue";
411 let OperandType = "OPERAND_PCREL";
415 // FIXME: rename bltarget to t2_bl_target?
416 def bltarget : Operand<i32> {
417 // Encoded the same as branch targets.
418 let EncoderMethod = "getBranchTargetOpValue";
419 let OperandType = "OPERAND_PCREL";
422 // Call target for ARM. Handles conditional/unconditional
423 // FIXME: rename bl_target to t2_bltarget?
424 def bl_target : Operand<i32> {
425 let EncoderMethod = "getARMBLTargetOpValue";
426 let OperandType = "OPERAND_PCREL";
429 def blx_target : Operand<i32> {
430 let EncoderMethod = "getARMBLXTargetOpValue";
431 let OperandType = "OPERAND_PCREL";
434 // A list of registers separated by comma. Used by load/store multiple.
435 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
436 def reglist : Operand<i32> {
437 let EncoderMethod = "getRegisterListOpValue";
438 let ParserMatchClass = RegListAsmOperand;
439 let PrintMethod = "printRegisterList";
440 let DecoderMethod = "DecodeRegListOperand";
443 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
445 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
446 def dpr_reglist : Operand<i32> {
447 let EncoderMethod = "getRegisterListOpValue";
448 let ParserMatchClass = DPRRegListAsmOperand;
449 let PrintMethod = "printRegisterList";
450 let DecoderMethod = "DecodeDPRRegListOperand";
453 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
454 def spr_reglist : Operand<i32> {
455 let EncoderMethod = "getRegisterListOpValue";
456 let ParserMatchClass = SPRRegListAsmOperand;
457 let PrintMethod = "printRegisterList";
458 let DecoderMethod = "DecodeSPRRegListOperand";
461 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
462 def cpinst_operand : Operand<i32> {
463 let PrintMethod = "printCPInstOperand";
467 def pclabel : Operand<i32> {
468 let PrintMethod = "printPCLabel";
471 // ADR instruction labels.
472 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
473 def adrlabel : Operand<i32> {
474 let EncoderMethod = "getAdrLabelOpValue";
475 let ParserMatchClass = AdrLabelAsmOperand;
476 let PrintMethod = "printAdrLabelOperand<0>";
479 def neon_vcvt_imm32 : Operand<i32> {
480 let EncoderMethod = "getNEONVcvtImm32OpValue";
481 let DecoderMethod = "DecodeVCVTImmOperand";
484 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
485 def rot_imm_XFORM: SDNodeXForm<imm, [{
486 switch (N->getZExtValue()){
488 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
489 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
490 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
491 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
494 def RotImmAsmOperand : AsmOperandClass {
496 let ParserMethod = "parseRotImm";
498 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
499 int32_t v = N->getZExtValue();
500 return v == 8 || v == 16 || v == 24; }],
502 let PrintMethod = "printRotImmOperand";
503 let ParserMatchClass = RotImmAsmOperand;
506 // shift_imm: An integer that encodes a shift amount and the type of shift
507 // (asr or lsl). The 6-bit immediate encodes as:
510 // {4-0} imm5 shift amount.
511 // asr #32 encoded as imm5 == 0.
512 def ShifterImmAsmOperand : AsmOperandClass {
513 let Name = "ShifterImm";
514 let ParserMethod = "parseShifterImm";
516 def shift_imm : Operand<i32> {
517 let PrintMethod = "printShiftImmOperand";
518 let ParserMatchClass = ShifterImmAsmOperand;
521 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
522 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
523 def so_reg_reg : Operand<i32>, // reg reg imm
524 ComplexPattern<i32, 3, "SelectRegShifterOperand",
525 [shl, srl, sra, rotr]> {
526 let EncoderMethod = "getSORegRegOpValue";
527 let PrintMethod = "printSORegRegOperand";
528 let DecoderMethod = "DecodeSORegRegOperand";
529 let ParserMatchClass = ShiftedRegAsmOperand;
530 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
533 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
534 def so_reg_imm : Operand<i32>, // reg imm
535 ComplexPattern<i32, 2, "SelectImmShifterOperand",
536 [shl, srl, sra, rotr]> {
537 let EncoderMethod = "getSORegImmOpValue";
538 let PrintMethod = "printSORegImmOperand";
539 let DecoderMethod = "DecodeSORegImmOperand";
540 let ParserMatchClass = ShiftedImmAsmOperand;
541 let MIOperandInfo = (ops GPR, i32imm);
544 // FIXME: Does this need to be distinct from so_reg?
545 def shift_so_reg_reg : Operand<i32>, // reg reg imm
546 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
547 [shl,srl,sra,rotr]> {
548 let EncoderMethod = "getSORegRegOpValue";
549 let PrintMethod = "printSORegRegOperand";
550 let DecoderMethod = "DecodeSORegRegOperand";
551 let ParserMatchClass = ShiftedRegAsmOperand;
552 let MIOperandInfo = (ops GPR, GPR, i32imm);
555 // FIXME: Does this need to be distinct from so_reg?
556 def shift_so_reg_imm : Operand<i32>, // reg reg imm
557 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
558 [shl,srl,sra,rotr]> {
559 let EncoderMethod = "getSORegImmOpValue";
560 let PrintMethod = "printSORegImmOperand";
561 let DecoderMethod = "DecodeSORegImmOperand";
562 let ParserMatchClass = ShiftedImmAsmOperand;
563 let MIOperandInfo = (ops GPR, i32imm);
567 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
568 // 8-bit immediate rotated by an arbitrary number of bits.
569 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
570 def so_imm : Operand<i32>, ImmLeaf<i32, [{
571 return ARM_AM::getSOImmVal(Imm) != -1;
573 let EncoderMethod = "getSOImmOpValue";
574 let ParserMatchClass = SOImmAsmOperand;
575 let DecoderMethod = "DecodeSOImmOperand";
578 // Break so_imm's up into two pieces. This handles immediates with up to 16
579 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
580 // get the first/second pieces.
581 def so_imm2part : PatLeaf<(imm), [{
582 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
585 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
587 def arm_i32imm : PatLeaf<(imm), [{
588 if (Subtarget->hasV6T2Ops())
590 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
593 /// imm0_1 predicate - Immediate in the range [0,1].
594 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
595 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
597 /// imm0_3 predicate - Immediate in the range [0,3].
598 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
599 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
601 /// imm0_7 predicate - Immediate in the range [0,7].
602 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
603 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
604 return Imm >= 0 && Imm < 8;
606 let ParserMatchClass = Imm0_7AsmOperand;
609 /// imm8 predicate - Immediate is exactly 8.
610 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
611 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
612 let ParserMatchClass = Imm8AsmOperand;
615 /// imm16 predicate - Immediate is exactly 16.
616 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
617 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
618 let ParserMatchClass = Imm16AsmOperand;
621 /// imm32 predicate - Immediate is exactly 32.
622 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
623 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
624 let ParserMatchClass = Imm32AsmOperand;
627 /// imm1_7 predicate - Immediate in the range [1,7].
628 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
629 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
630 let ParserMatchClass = Imm1_7AsmOperand;
633 /// imm1_15 predicate - Immediate in the range [1,15].
634 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
635 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
636 let ParserMatchClass = Imm1_15AsmOperand;
639 /// imm1_31 predicate - Immediate in the range [1,31].
640 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
641 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
642 let ParserMatchClass = Imm1_31AsmOperand;
645 /// imm0_15 predicate - Immediate in the range [0,15].
646 def Imm0_15AsmOperand: ImmAsmOperand {
647 let Name = "Imm0_15";
648 let DiagnosticType = "ImmRange0_15";
650 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
651 return Imm >= 0 && Imm < 16;
653 let ParserMatchClass = Imm0_15AsmOperand;
656 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
657 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
658 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
659 return Imm >= 0 && Imm < 32;
661 let ParserMatchClass = Imm0_31AsmOperand;
664 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
665 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
666 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
667 return Imm >= 0 && Imm < 32;
669 let ParserMatchClass = Imm0_32AsmOperand;
672 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
673 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
674 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
675 return Imm >= 0 && Imm < 64;
677 let ParserMatchClass = Imm0_63AsmOperand;
680 /// imm0_255 predicate - Immediate in the range [0,255].
681 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
682 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
683 let ParserMatchClass = Imm0_255AsmOperand;
686 /// imm0_65535 - An immediate is in the range [0.65535].
687 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
688 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
689 return Imm >= 0 && Imm < 65536;
691 let ParserMatchClass = Imm0_65535AsmOperand;
694 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
695 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
696 return -Imm >= 0 && -Imm < 65536;
699 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
700 // a relocatable expression.
702 // FIXME: This really needs a Thumb version separate from the ARM version.
703 // While the range is the same, and can thus use the same match class,
704 // the encoding is different so it should have a different encoder method.
705 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
706 def imm0_65535_expr : Operand<i32> {
707 let EncoderMethod = "getHiLo16ImmOpValue";
708 let ParserMatchClass = Imm0_65535ExprAsmOperand;
711 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
712 def imm256_65535_expr : Operand<i32> {
713 let ParserMatchClass = Imm256_65535ExprAsmOperand;
716 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
717 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
718 def imm24b : Operand<i32>, ImmLeaf<i32, [{
719 return Imm >= 0 && Imm <= 0xffffff;
721 let ParserMatchClass = Imm24bitAsmOperand;
725 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
727 def BitfieldAsmOperand : AsmOperandClass {
728 let Name = "Bitfield";
729 let ParserMethod = "parseBitfield";
732 def bf_inv_mask_imm : Operand<i32>,
734 return ARM::isBitFieldInvertedMask(N->getZExtValue());
736 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
737 let PrintMethod = "printBitfieldInvMaskImmOperand";
738 let DecoderMethod = "DecodeBitfieldMaskOperand";
739 let ParserMatchClass = BitfieldAsmOperand;
742 def imm1_32_XFORM: SDNodeXForm<imm, [{
743 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
745 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
746 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
747 uint64_t Imm = N->getZExtValue();
748 return Imm > 0 && Imm <= 32;
751 let PrintMethod = "printImmPlusOneOperand";
752 let ParserMatchClass = Imm1_32AsmOperand;
755 def imm1_16_XFORM: SDNodeXForm<imm, [{
756 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
758 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
759 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
761 let PrintMethod = "printImmPlusOneOperand";
762 let ParserMatchClass = Imm1_16AsmOperand;
765 // Define ARM specific addressing modes.
766 // addrmode_imm12 := reg +/- imm12
768 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
769 class AddrMode_Imm12 : Operand<i32>,
770 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
771 // 12-bit immediate operand. Note that instructions using this encode
772 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
773 // immediate values are as normal.
775 let EncoderMethod = "getAddrModeImm12OpValue";
776 let DecoderMethod = "DecodeAddrModeImm12Operand";
777 let ParserMatchClass = MemImm12OffsetAsmOperand;
778 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
781 def addrmode_imm12 : AddrMode_Imm12 {
782 let PrintMethod = "printAddrModeImm12Operand<false>";
785 def addrmode_imm12_pre : AddrMode_Imm12 {
786 let PrintMethod = "printAddrModeImm12Operand<true>";
789 // ldst_so_reg := reg +/- reg shop imm
791 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
792 def ldst_so_reg : Operand<i32>,
793 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
794 let EncoderMethod = "getLdStSORegOpValue";
795 // FIXME: Simplify the printer
796 let PrintMethod = "printAddrMode2Operand";
797 let DecoderMethod = "DecodeSORegMemOperand";
798 let ParserMatchClass = MemRegOffsetAsmOperand;
799 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
802 // postidx_imm8 := +/- [0,255]
805 // {8} 1 is imm8 is non-negative. 0 otherwise.
806 // {7-0} [0,255] imm8 value.
807 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
808 def postidx_imm8 : Operand<i32> {
809 let PrintMethod = "printPostIdxImm8Operand";
810 let ParserMatchClass = PostIdxImm8AsmOperand;
811 let MIOperandInfo = (ops i32imm);
814 // postidx_imm8s4 := +/- [0,1020]
817 // {8} 1 is imm8 is non-negative. 0 otherwise.
818 // {7-0} [0,255] imm8 value, scaled by 4.
819 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
820 def postidx_imm8s4 : Operand<i32> {
821 let PrintMethod = "printPostIdxImm8s4Operand";
822 let ParserMatchClass = PostIdxImm8s4AsmOperand;
823 let MIOperandInfo = (ops i32imm);
827 // postidx_reg := +/- reg
829 def PostIdxRegAsmOperand : AsmOperandClass {
830 let Name = "PostIdxReg";
831 let ParserMethod = "parsePostIdxReg";
833 def postidx_reg : Operand<i32> {
834 let EncoderMethod = "getPostIdxRegOpValue";
835 let DecoderMethod = "DecodePostIdxReg";
836 let PrintMethod = "printPostIdxRegOperand";
837 let ParserMatchClass = PostIdxRegAsmOperand;
838 let MIOperandInfo = (ops GPRnopc, i32imm);
842 // addrmode2 := reg +/- imm12
843 // := reg +/- reg shop imm
845 // FIXME: addrmode2 should be refactored the rest of the way to always
846 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
847 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
848 def addrmode2 : Operand<i32>,
849 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
850 let EncoderMethod = "getAddrMode2OpValue";
851 let PrintMethod = "printAddrMode2Operand";
852 let ParserMatchClass = AddrMode2AsmOperand;
853 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
856 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
857 let Name = "PostIdxRegShifted";
858 let ParserMethod = "parsePostIdxReg";
860 def am2offset_reg : Operand<i32>,
861 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
862 [], [SDNPWantRoot]> {
863 let EncoderMethod = "getAddrMode2OffsetOpValue";
864 let PrintMethod = "printAddrMode2OffsetOperand";
865 // When using this for assembly, it's always as a post-index offset.
866 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
867 let MIOperandInfo = (ops GPRnopc, i32imm);
870 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
871 // the GPR is purely vestigal at this point.
872 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
873 def am2offset_imm : Operand<i32>,
874 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
875 [], [SDNPWantRoot]> {
876 let EncoderMethod = "getAddrMode2OffsetOpValue";
877 let PrintMethod = "printAddrMode2OffsetOperand";
878 let ParserMatchClass = AM2OffsetImmAsmOperand;
879 let MIOperandInfo = (ops GPRnopc, i32imm);
883 // addrmode3 := reg +/- reg
884 // addrmode3 := reg +/- imm8
886 // FIXME: split into imm vs. reg versions.
887 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
888 class AddrMode3 : Operand<i32>,
889 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
890 let EncoderMethod = "getAddrMode3OpValue";
891 let ParserMatchClass = AddrMode3AsmOperand;
892 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
895 def addrmode3 : AddrMode3
897 let PrintMethod = "printAddrMode3Operand<false>";
900 def addrmode3_pre : AddrMode3
902 let PrintMethod = "printAddrMode3Operand<true>";
905 // FIXME: split into imm vs. reg versions.
906 // FIXME: parser method to handle +/- register.
907 def AM3OffsetAsmOperand : AsmOperandClass {
908 let Name = "AM3Offset";
909 let ParserMethod = "parseAM3Offset";
911 def am3offset : Operand<i32>,
912 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
913 [], [SDNPWantRoot]> {
914 let EncoderMethod = "getAddrMode3OffsetOpValue";
915 let PrintMethod = "printAddrMode3OffsetOperand";
916 let ParserMatchClass = AM3OffsetAsmOperand;
917 let MIOperandInfo = (ops GPR, i32imm);
920 // ldstm_mode := {ia, ib, da, db}
922 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
923 let EncoderMethod = "getLdStmModeOpValue";
924 let PrintMethod = "printLdStmModeOperand";
927 // addrmode5 := reg +/- imm8*4
929 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
930 class AddrMode5 : Operand<i32>,
931 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
932 let EncoderMethod = "getAddrMode5OpValue";
933 let DecoderMethod = "DecodeAddrMode5Operand";
934 let ParserMatchClass = AddrMode5AsmOperand;
935 let MIOperandInfo = (ops GPR:$base, i32imm);
938 def addrmode5 : AddrMode5 {
939 let PrintMethod = "printAddrMode5Operand<false>";
942 def addrmode5_pre : AddrMode5 {
943 let PrintMethod = "printAddrMode5Operand<true>";
946 // addrmode6 := reg with optional alignment
948 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
949 def addrmode6 : Operand<i32>,
950 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
951 let PrintMethod = "printAddrMode6Operand";
952 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
953 let EncoderMethod = "getAddrMode6AddressOpValue";
954 let DecoderMethod = "DecodeAddrMode6Operand";
955 let ParserMatchClass = AddrMode6AsmOperand;
958 def am6offset : Operand<i32>,
959 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
960 [], [SDNPWantRoot]> {
961 let PrintMethod = "printAddrMode6OffsetOperand";
962 let MIOperandInfo = (ops GPR);
963 let EncoderMethod = "getAddrMode6OffsetOpValue";
964 let DecoderMethod = "DecodeGPRRegisterClass";
967 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
968 // (single element from one lane) for size 32.
969 def addrmode6oneL32 : Operand<i32>,
970 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
971 let PrintMethod = "printAddrMode6Operand";
972 let MIOperandInfo = (ops GPR:$addr, i32imm);
973 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
976 // Special version of addrmode6 to handle alignment encoding for VLD-dup
977 // instructions, specifically VLD4-dup.
978 def addrmode6dup : Operand<i32>,
979 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
980 let PrintMethod = "printAddrMode6Operand";
981 let MIOperandInfo = (ops GPR:$addr, i32imm);
982 let EncoderMethod = "getAddrMode6DupAddressOpValue";
983 // FIXME: This is close, but not quite right. The alignment specifier is
985 let ParserMatchClass = AddrMode6AsmOperand;
988 // addrmodepc := pc + reg
990 def addrmodepc : Operand<i32>,
991 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
992 let PrintMethod = "printAddrModePCOperand";
993 let MIOperandInfo = (ops GPR, i32imm);
996 // addr_offset_none := reg
998 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
999 def addr_offset_none : Operand<i32>,
1000 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1001 let PrintMethod = "printAddrMode7Operand";
1002 let DecoderMethod = "DecodeAddrMode7Operand";
1003 let ParserMatchClass = MemNoOffsetAsmOperand;
1004 let MIOperandInfo = (ops GPR:$base);
1007 def nohash_imm : Operand<i32> {
1008 let PrintMethod = "printNoHashImmediate";
1011 def CoprocNumAsmOperand : AsmOperandClass {
1012 let Name = "CoprocNum";
1013 let ParserMethod = "parseCoprocNumOperand";
1015 def p_imm : Operand<i32> {
1016 let PrintMethod = "printPImmediate";
1017 let ParserMatchClass = CoprocNumAsmOperand;
1018 let DecoderMethod = "DecodeCoprocessor";
1021 def CoprocRegAsmOperand : AsmOperandClass {
1022 let Name = "CoprocReg";
1023 let ParserMethod = "parseCoprocRegOperand";
1025 def c_imm : Operand<i32> {
1026 let PrintMethod = "printCImmediate";
1027 let ParserMatchClass = CoprocRegAsmOperand;
1029 def CoprocOptionAsmOperand : AsmOperandClass {
1030 let Name = "CoprocOption";
1031 let ParserMethod = "parseCoprocOptionOperand";
1033 def coproc_option_imm : Operand<i32> {
1034 let PrintMethod = "printCoprocOptionImm";
1035 let ParserMatchClass = CoprocOptionAsmOperand;
1038 //===----------------------------------------------------------------------===//
1040 include "ARMInstrFormats.td"
1042 //===----------------------------------------------------------------------===//
1043 // Multiclass helpers...
1046 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1047 /// binop that produces a value.
1048 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1049 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1050 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1051 PatFrag opnode, bit Commutable = 0> {
1052 // The register-immediate version is re-materializable. This is useful
1053 // in particular for taking the address of a local.
1054 let isReMaterializable = 1 in {
1055 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1056 iii, opc, "\t$Rd, $Rn, $imm",
1057 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1058 Sched<[WriteALU, ReadALU]> {
1063 let Inst{19-16} = Rn;
1064 let Inst{15-12} = Rd;
1065 let Inst{11-0} = imm;
1068 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1069 iir, opc, "\t$Rd, $Rn, $Rm",
1070 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1071 Sched<[WriteALU, ReadALU, ReadALU]> {
1076 let isCommutable = Commutable;
1077 let Inst{19-16} = Rn;
1078 let Inst{15-12} = Rd;
1079 let Inst{11-4} = 0b00000000;
1083 def rsi : AsI1<opcod, (outs GPR:$Rd),
1084 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1085 iis, opc, "\t$Rd, $Rn, $shift",
1086 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1087 Sched<[WriteALUsi, ReadALU]> {
1092 let Inst{19-16} = Rn;
1093 let Inst{15-12} = Rd;
1094 let Inst{11-5} = shift{11-5};
1096 let Inst{3-0} = shift{3-0};
1099 def rsr : AsI1<opcod, (outs GPR:$Rd),
1100 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1101 iis, opc, "\t$Rd, $Rn, $shift",
1102 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1103 Sched<[WriteALUsr, ReadALUsr]> {
1108 let Inst{19-16} = Rn;
1109 let Inst{15-12} = Rd;
1110 let Inst{11-8} = shift{11-8};
1112 let Inst{6-5} = shift{6-5};
1114 let Inst{3-0} = shift{3-0};
1118 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1119 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1120 /// it is equivalent to the AsI1_bin_irs counterpart.
1121 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1122 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1123 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1124 PatFrag opnode, bit Commutable = 0> {
1125 // The register-immediate version is re-materializable. This is useful
1126 // in particular for taking the address of a local.
1127 let isReMaterializable = 1 in {
1128 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1129 iii, opc, "\t$Rd, $Rn, $imm",
1130 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1131 Sched<[WriteALU, ReadALU]> {
1136 let Inst{19-16} = Rn;
1137 let Inst{15-12} = Rd;
1138 let Inst{11-0} = imm;
1141 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1142 iir, opc, "\t$Rd, $Rn, $Rm",
1143 [/* pattern left blank */]>,
1144 Sched<[WriteALU, ReadALU, ReadALU]> {
1148 let Inst{11-4} = 0b00000000;
1151 let Inst{15-12} = Rd;
1152 let Inst{19-16} = Rn;
1155 def rsi : AsI1<opcod, (outs GPR:$Rd),
1156 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1157 iis, opc, "\t$Rd, $Rn, $shift",
1158 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1159 Sched<[WriteALUsi, ReadALU]> {
1164 let Inst{19-16} = Rn;
1165 let Inst{15-12} = Rd;
1166 let Inst{11-5} = shift{11-5};
1168 let Inst{3-0} = shift{3-0};
1171 def rsr : AsI1<opcod, (outs GPR:$Rd),
1172 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1173 iis, opc, "\t$Rd, $Rn, $shift",
1174 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1175 Sched<[WriteALUsr, ReadALUsr]> {
1180 let Inst{19-16} = Rn;
1181 let Inst{15-12} = Rd;
1182 let Inst{11-8} = shift{11-8};
1184 let Inst{6-5} = shift{6-5};
1186 let Inst{3-0} = shift{3-0};
1190 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1192 /// These opcodes will be converted to the real non-S opcodes by
1193 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1194 let hasPostISelHook = 1, Defs = [CPSR] in {
1195 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1196 InstrItinClass iis, PatFrag opnode,
1197 bit Commutable = 0> {
1198 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1200 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1201 Sched<[WriteALU, ReadALU]>;
1203 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1205 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1206 Sched<[WriteALU, ReadALU, ReadALU]> {
1207 let isCommutable = Commutable;
1209 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1210 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1212 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1213 so_reg_imm:$shift))]>,
1214 Sched<[WriteALUsi, ReadALU]>;
1216 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1217 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1219 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1220 so_reg_reg:$shift))]>,
1221 Sched<[WriteALUSsr, ReadALUsr]>;
1225 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1226 /// operands are reversed.
1227 let hasPostISelHook = 1, Defs = [CPSR] in {
1228 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1229 InstrItinClass iis, PatFrag opnode,
1230 bit Commutable = 0> {
1231 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1233 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1234 Sched<[WriteALU, ReadALU]>;
1236 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1237 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1239 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1241 Sched<[WriteALUsi, ReadALU]>;
1243 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1244 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1246 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1248 Sched<[WriteALUSsr, ReadALUsr]>;
1252 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1253 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1254 /// a explicit result, only implicitly set CPSR.
1255 let isCompare = 1, Defs = [CPSR] in {
1256 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1257 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1258 PatFrag opnode, bit Commutable = 0> {
1259 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1261 [(opnode GPR:$Rn, so_imm:$imm)]>,
1262 Sched<[WriteCMP, ReadALU]> {
1267 let Inst{19-16} = Rn;
1268 let Inst{15-12} = 0b0000;
1269 let Inst{11-0} = imm;
1271 let Unpredictable{15-12} = 0b1111;
1273 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1275 [(opnode GPR:$Rn, GPR:$Rm)]>,
1276 Sched<[WriteCMP, ReadALU, ReadALU]> {
1279 let isCommutable = Commutable;
1282 let Inst{19-16} = Rn;
1283 let Inst{15-12} = 0b0000;
1284 let Inst{11-4} = 0b00000000;
1287 let Unpredictable{15-12} = 0b1111;
1289 def rsi : AI1<opcod, (outs),
1290 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1291 opc, "\t$Rn, $shift",
1292 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1293 Sched<[WriteCMPsi, ReadALU]> {
1298 let Inst{19-16} = Rn;
1299 let Inst{15-12} = 0b0000;
1300 let Inst{11-5} = shift{11-5};
1302 let Inst{3-0} = shift{3-0};
1304 let Unpredictable{15-12} = 0b1111;
1306 def rsr : AI1<opcod, (outs),
1307 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1308 opc, "\t$Rn, $shift",
1309 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1310 Sched<[WriteCMPsr, ReadALU]> {
1315 let Inst{19-16} = Rn;
1316 let Inst{15-12} = 0b0000;
1317 let Inst{11-8} = shift{11-8};
1319 let Inst{6-5} = shift{6-5};
1321 let Inst{3-0} = shift{3-0};
1323 let Unpredictable{15-12} = 0b1111;
1329 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1330 /// register and one whose operand is a register rotated by 8/16/24.
1331 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1332 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1333 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1334 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1335 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1336 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1340 let Inst{19-16} = 0b1111;
1341 let Inst{15-12} = Rd;
1342 let Inst{11-10} = rot;
1346 class AI_ext_rrot_np<bits<8> opcod, string opc>
1347 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1348 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1349 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1351 let Inst{19-16} = 0b1111;
1352 let Inst{11-10} = rot;
1355 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1356 /// register and one whose operand is a register rotated by 8/16/24.
1357 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1358 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1359 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1360 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1361 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1362 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1367 let Inst{19-16} = Rn;
1368 let Inst{15-12} = Rd;
1369 let Inst{11-10} = rot;
1370 let Inst{9-4} = 0b000111;
1374 class AI_exta_rrot_np<bits<8> opcod, string opc>
1375 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1376 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1377 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1380 let Inst{19-16} = Rn;
1381 let Inst{11-10} = rot;
1384 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1385 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1386 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1387 bit Commutable = 0> {
1388 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1389 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1390 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1391 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1393 Sched<[WriteALU, ReadALU]> {
1398 let Inst{15-12} = Rd;
1399 let Inst{19-16} = Rn;
1400 let Inst{11-0} = imm;
1402 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1403 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1404 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1406 Sched<[WriteALU, ReadALU, ReadALU]> {
1410 let Inst{11-4} = 0b00000000;
1412 let isCommutable = Commutable;
1414 let Inst{15-12} = Rd;
1415 let Inst{19-16} = Rn;
1417 def rsi : AsI1<opcod, (outs GPR:$Rd),
1418 (ins GPR:$Rn, so_reg_imm:$shift),
1419 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1420 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1422 Sched<[WriteALUsi, ReadALU]> {
1427 let Inst{19-16} = Rn;
1428 let Inst{15-12} = Rd;
1429 let Inst{11-5} = shift{11-5};
1431 let Inst{3-0} = shift{3-0};
1433 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1434 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1435 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1436 [(set GPRnopc:$Rd, CPSR,
1437 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1439 Sched<[WriteALUsr, ReadALUsr]> {
1444 let Inst{19-16} = Rn;
1445 let Inst{15-12} = Rd;
1446 let Inst{11-8} = shift{11-8};
1448 let Inst{6-5} = shift{6-5};
1450 let Inst{3-0} = shift{3-0};
1455 /// AI1_rsc_irs - Define instructions and patterns for rsc
1456 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1457 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1458 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1459 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1460 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1461 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1463 Sched<[WriteALU, ReadALU]> {
1468 let Inst{15-12} = Rd;
1469 let Inst{19-16} = Rn;
1470 let Inst{11-0} = imm;
1472 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1473 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1474 [/* pattern left blank */]>,
1475 Sched<[WriteALU, ReadALU, ReadALU]> {
1479 let Inst{11-4} = 0b00000000;
1482 let Inst{15-12} = Rd;
1483 let Inst{19-16} = Rn;
1485 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1486 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1487 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1489 Sched<[WriteALUsi, ReadALU]> {
1494 let Inst{19-16} = Rn;
1495 let Inst{15-12} = Rd;
1496 let Inst{11-5} = shift{11-5};
1498 let Inst{3-0} = shift{3-0};
1500 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1501 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1502 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1504 Sched<[WriteALUsr, ReadALUsr]> {
1509 let Inst{19-16} = Rn;
1510 let Inst{15-12} = Rd;
1511 let Inst{11-8} = shift{11-8};
1513 let Inst{6-5} = shift{6-5};
1515 let Inst{3-0} = shift{3-0};
1520 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1521 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1522 InstrItinClass iir, PatFrag opnode> {
1523 // Note: We use the complex addrmode_imm12 rather than just an input
1524 // GPR and a constrained immediate so that we can use this to match
1525 // frame index references and avoid matching constant pool references.
1526 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1527 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1528 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1531 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1532 let Inst{19-16} = addr{16-13}; // Rn
1533 let Inst{15-12} = Rt;
1534 let Inst{11-0} = addr{11-0}; // imm12
1536 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1537 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1538 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1541 let shift{4} = 0; // Inst{4} = 0
1542 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1543 let Inst{19-16} = shift{16-13}; // Rn
1544 let Inst{15-12} = Rt;
1545 let Inst{11-0} = shift{11-0};
1550 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1551 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1552 InstrItinClass iir, PatFrag opnode> {
1553 // Note: We use the complex addrmode_imm12 rather than just an input
1554 // GPR and a constrained immediate so that we can use this to match
1555 // frame index references and avoid matching constant pool references.
1556 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1557 (ins addrmode_imm12:$addr),
1558 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1559 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1562 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1563 let Inst{19-16} = addr{16-13}; // Rn
1564 let Inst{15-12} = Rt;
1565 let Inst{11-0} = addr{11-0}; // imm12
1567 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1568 (ins ldst_so_reg:$shift),
1569 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1570 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1573 let shift{4} = 0; // Inst{4} = 0
1574 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1575 let Inst{19-16} = shift{16-13}; // Rn
1576 let Inst{15-12} = Rt;
1577 let Inst{11-0} = shift{11-0};
1583 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1584 InstrItinClass iir, PatFrag opnode> {
1585 // Note: We use the complex addrmode_imm12 rather than just an input
1586 // GPR and a constrained immediate so that we can use this to match
1587 // frame index references and avoid matching constant pool references.
1588 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1589 (ins GPR:$Rt, addrmode_imm12:$addr),
1590 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1591 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1594 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1595 let Inst{19-16} = addr{16-13}; // Rn
1596 let Inst{15-12} = Rt;
1597 let Inst{11-0} = addr{11-0}; // imm12
1599 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1600 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1601 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1604 let shift{4} = 0; // Inst{4} = 0
1605 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1606 let Inst{19-16} = shift{16-13}; // Rn
1607 let Inst{15-12} = Rt;
1608 let Inst{11-0} = shift{11-0};
1612 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1613 InstrItinClass iir, PatFrag opnode> {
1614 // Note: We use the complex addrmode_imm12 rather than just an input
1615 // GPR and a constrained immediate so that we can use this to match
1616 // frame index references and avoid matching constant pool references.
1617 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1618 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1619 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1620 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1623 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1624 let Inst{19-16} = addr{16-13}; // Rn
1625 let Inst{15-12} = Rt;
1626 let Inst{11-0} = addr{11-0}; // imm12
1628 def rs : AI2ldst<0b011, 0, isByte, (outs),
1629 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1630 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1631 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1634 let shift{4} = 0; // Inst{4} = 0
1635 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1636 let Inst{19-16} = shift{16-13}; // Rn
1637 let Inst{15-12} = Rt;
1638 let Inst{11-0} = shift{11-0};
1643 //===----------------------------------------------------------------------===//
1645 //===----------------------------------------------------------------------===//
1647 //===----------------------------------------------------------------------===//
1648 // Miscellaneous Instructions.
1651 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1652 /// the function. The first operand is the ID# for this instruction, the second
1653 /// is the index into the MachineConstantPool that this is, the third is the
1654 /// size in bytes of this constant pool entry.
1655 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1656 def CONSTPOOL_ENTRY :
1657 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1658 i32imm:$size), NoItinerary, []>;
1660 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1661 // from removing one half of the matched pairs. That breaks PEI, which assumes
1662 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1663 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1664 def ADJCALLSTACKUP :
1665 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1666 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1668 def ADJCALLSTACKDOWN :
1669 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1670 [(ARMcallseq_start timm:$amt)]>;
1673 def HINT : AI<(outs), (ins imm0_255:$imm), MiscFrm, NoItinerary,
1674 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1676 let Inst{27-8} = 0b00110010000011110000;
1677 let Inst{7-0} = imm;
1680 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1681 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1682 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1683 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1684 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1685 def : InstAlias<"sevl$p", (HINT 5, pred:$p)>, Requires<[IsARM, HasV8]>;
1687 def : Pat<(int_arm_sevl), (HINT 5)>;
1689 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1690 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1695 let Inst{15-12} = Rd;
1696 let Inst{19-16} = Rn;
1697 let Inst{27-20} = 0b01101000;
1698 let Inst{7-4} = 0b1011;
1699 let Inst{11-8} = 0b1111;
1700 let Unpredictable{11-8} = 0b1111;
1703 // The 16-bit operand $val can be used by a debugger to store more information
1704 // about the breakpoint.
1705 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1706 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1708 let Inst{3-0} = val{3-0};
1709 let Inst{19-8} = val{15-4};
1710 let Inst{27-20} = 0b00010010;
1711 let Inst{31-28} = 0xe; // AL
1712 let Inst{7-4} = 0b0111;
1715 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1716 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1718 let Inst{3-0} = val{3-0};
1719 let Inst{19-8} = val{15-4};
1720 let Inst{27-20} = 0b00010000;
1721 let Inst{31-28} = 0xe; // AL
1722 let Inst{7-4} = 0b0111;
1725 // Change Processor State
1726 // FIXME: We should use InstAlias to handle the optional operands.
1727 class CPS<dag iops, string asm_ops>
1728 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1729 []>, Requires<[IsARM]> {
1735 let Inst{31-28} = 0b1111;
1736 let Inst{27-20} = 0b00010000;
1737 let Inst{19-18} = imod;
1738 let Inst{17} = M; // Enabled if mode is set;
1739 let Inst{16-9} = 0b00000000;
1740 let Inst{8-6} = iflags;
1742 let Inst{4-0} = mode;
1745 let DecoderMethod = "DecodeCPSInstruction" in {
1747 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1748 "$imod\t$iflags, $mode">;
1749 let mode = 0, M = 0 in
1750 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1752 let imod = 0, iflags = 0, M = 1 in
1753 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1756 // Preload signals the memory system of possible future data/instruction access.
1757 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1759 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1760 !strconcat(opc, "\t$addr"),
1761 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1762 Sched<[WritePreLd]> {
1765 let Inst{31-26} = 0b111101;
1766 let Inst{25} = 0; // 0 for immediate form
1767 let Inst{24} = data;
1768 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1769 let Inst{22} = read;
1770 let Inst{21-20} = 0b01;
1771 let Inst{19-16} = addr{16-13}; // Rn
1772 let Inst{15-12} = 0b1111;
1773 let Inst{11-0} = addr{11-0}; // imm12
1776 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1777 !strconcat(opc, "\t$shift"),
1778 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1779 Sched<[WritePreLd]> {
1781 let Inst{31-26} = 0b111101;
1782 let Inst{25} = 1; // 1 for register form
1783 let Inst{24} = data;
1784 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1785 let Inst{22} = read;
1786 let Inst{21-20} = 0b01;
1787 let Inst{19-16} = shift{16-13}; // Rn
1788 let Inst{15-12} = 0b1111;
1789 let Inst{11-0} = shift{11-0};
1794 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1795 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1796 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1798 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1799 "setend\t$end", []>, Requires<[IsARM]>, Deprecated<HasV8Ops> {
1801 let Inst{31-10} = 0b1111000100000001000000;
1806 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1807 []>, Requires<[IsARM, HasV7]> {
1809 let Inst{27-4} = 0b001100100000111100001111;
1810 let Inst{3-0} = opt;
1814 * A5.4 Permanently UNDEFINED instructions.
1816 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1817 * Other UDF encodings generate SIGILL.
1819 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1821 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1823 * 1101 1110 iiii iiii
1824 * It uses the following encoding:
1825 * 1110 0111 1111 1110 1101 1110 1111 0000
1826 * - In ARM: UDF #60896;
1827 * - In Thumb: UDF #254 followed by a branch-to-self.
1829 let isBarrier = 1, isTerminator = 1 in
1830 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
1832 Requires<[IsARM,UseNaClTrap]> {
1833 let Inst = 0xe7fedef0;
1835 let isBarrier = 1, isTerminator = 1 in
1836 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1838 Requires<[IsARM,DontUseNaClTrap]> {
1839 let Inst = 0xe7ffdefe;
1842 // Address computation and loads and stores in PIC mode.
1843 let isNotDuplicable = 1 in {
1844 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1846 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
1847 Sched<[WriteALU, ReadALU]>;
1849 let AddedComplexity = 10 in {
1850 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1852 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1854 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1856 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1858 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1860 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1862 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1864 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1866 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1868 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1870 let AddedComplexity = 10 in {
1871 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1872 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1874 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1875 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1876 addrmodepc:$addr)]>;
1878 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1879 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1881 } // isNotDuplicable = 1
1884 // LEApcrel - Load a pc-relative address into a register without offending the
1886 let neverHasSideEffects = 1, isReMaterializable = 1 in
1887 // The 'adr' mnemonic encodes differently if the label is before or after
1888 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1889 // know until then which form of the instruction will be used.
1890 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1891 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
1892 Sched<[WriteALU, ReadALU]> {
1895 let Inst{27-25} = 0b001;
1897 let Inst{23-22} = label{13-12};
1900 let Inst{19-16} = 0b1111;
1901 let Inst{15-12} = Rd;
1902 let Inst{11-0} = label{11-0};
1905 let hasSideEffects = 1 in {
1906 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1907 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1909 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1910 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1911 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1914 //===----------------------------------------------------------------------===//
1915 // Control Flow Instructions.
1918 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1920 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1921 "bx", "\tlr", [(ARMretflag)]>,
1922 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1923 let Inst{27-0} = 0b0001001011111111111100011110;
1927 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1928 "mov", "\tpc, lr", [(ARMretflag)]>,
1929 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
1930 let Inst{27-0} = 0b0001101000001111000000001110;
1933 // Exception return: N.b. doesn't set CPSR as far as we're concerned (it sets
1934 // the user-space one).
1935 def SUBS_PC_LR : ARMPseudoInst<(outs), (ins i32imm:$offset, pred:$p),
1937 [(ARMintretflag imm:$offset)]>;
1940 // Indirect branches
1941 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1943 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1944 [(brind GPR:$dst)]>,
1945 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1947 let Inst{31-4} = 0b1110000100101111111111110001;
1948 let Inst{3-0} = dst;
1951 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1952 "bx", "\t$dst", [/* pattern left blank */]>,
1953 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1955 let Inst{27-4} = 0b000100101111111111110001;
1956 let Inst{3-0} = dst;
1960 // SP is marked as a use to prevent stack-pointer assignments that appear
1961 // immediately before calls from potentially appearing dead.
1963 // FIXME: Do we really need a non-predicated version? If so, it should
1964 // at least be a pseudo instruction expanding to the predicated version
1965 // at MC lowering time.
1966 Defs = [LR], Uses = [SP] in {
1967 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1968 IIC_Br, "bl\t$func",
1969 [(ARMcall tglobaladdr:$func)]>,
1970 Requires<[IsARM]>, Sched<[WriteBrL]> {
1971 let Inst{31-28} = 0b1110;
1973 let Inst{23-0} = func;
1974 let DecoderMethod = "DecodeBranchImmInstruction";
1977 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1978 IIC_Br, "bl", "\t$func",
1979 [(ARMcall_pred tglobaladdr:$func)]>,
1980 Requires<[IsARM]>, Sched<[WriteBrL]> {
1982 let Inst{23-0} = func;
1983 let DecoderMethod = "DecodeBranchImmInstruction";
1987 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
1988 IIC_Br, "blx\t$func",
1989 [(ARMcall GPR:$func)]>,
1990 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
1992 let Inst{31-4} = 0b1110000100101111111111110011;
1993 let Inst{3-0} = func;
1996 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
1997 IIC_Br, "blx", "\t$func",
1998 [(ARMcall_pred GPR:$func)]>,
1999 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2001 let Inst{27-4} = 0b000100101111111111110011;
2002 let Inst{3-0} = func;
2006 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2007 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2008 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2009 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2012 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2013 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2014 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2016 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2017 // return stack predictor.
2018 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2019 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2020 Requires<[IsARM]>, Sched<[WriteBr]>;
2023 let isBranch = 1, isTerminator = 1 in {
2024 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2025 // a two-value operand where a dag node expects two operands. :(
2026 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2027 IIC_Br, "b", "\t$target",
2028 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2031 let Inst{23-0} = target;
2032 let DecoderMethod = "DecodeBranchImmInstruction";
2035 let isBarrier = 1 in {
2036 // B is "predicable" since it's just a Bcc with an 'always' condition.
2037 let isPredicable = 1 in
2038 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2039 // should be sufficient.
2040 // FIXME: Is B really a Barrier? That doesn't seem right.
2041 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2042 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2045 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2046 def BR_JTr : ARMPseudoInst<(outs),
2047 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2049 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
2051 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2052 // into i12 and rs suffixed versions.
2053 def BR_JTm : ARMPseudoInst<(outs),
2054 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2056 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2057 imm:$id)]>, Sched<[WriteBrTbl]>;
2058 def BR_JTadd : ARMPseudoInst<(outs),
2059 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2061 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2062 imm:$id)]>, Sched<[WriteBrTbl]>;
2063 } // isNotDuplicable = 1, isIndirectBranch = 1
2069 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2070 "blx\t$target", []>,
2071 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2072 let Inst{31-25} = 0b1111101;
2074 let Inst{23-0} = target{24-1};
2075 let Inst{24} = target{0};
2078 // Branch and Exchange Jazelle
2079 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2080 [/* pattern left blank */]>, Sched<[WriteBr]> {
2082 let Inst{23-20} = 0b0010;
2083 let Inst{19-8} = 0xfff;
2084 let Inst{7-4} = 0b0010;
2085 let Inst{3-0} = func;
2090 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2091 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2094 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2097 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2099 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2100 Requires<[IsARM]>, Sched<[WriteBr]>;
2102 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2104 (BX GPR:$dst)>, Sched<[WriteBr]>,
2108 // Secure Monitor Call is a system instruction.
2109 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2110 []>, Requires<[IsARM, HasTrustZone]> {
2112 let Inst{23-4} = 0b01100000000000000111;
2113 let Inst{3-0} = opt;
2116 // Supervisor Call (Software Interrupt)
2117 let isCall = 1, Uses = [SP] in {
2118 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2121 let Inst{23-0} = svc;
2125 // Store Return State
2126 class SRSI<bit wb, string asm>
2127 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2128 NoItinerary, asm, "", []> {
2130 let Inst{31-28} = 0b1111;
2131 let Inst{27-25} = 0b100;
2135 let Inst{19-16} = 0b1101; // SP
2136 let Inst{15-5} = 0b00000101000;
2137 let Inst{4-0} = mode;
2140 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2141 let Inst{24-23} = 0;
2143 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2144 let Inst{24-23} = 0;
2146 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2147 let Inst{24-23} = 0b10;
2149 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2150 let Inst{24-23} = 0b10;
2152 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2153 let Inst{24-23} = 0b01;
2155 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2156 let Inst{24-23} = 0b01;
2158 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2159 let Inst{24-23} = 0b11;
2161 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2162 let Inst{24-23} = 0b11;
2165 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2166 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2168 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2169 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2171 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2172 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2174 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2175 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2177 // Return From Exception
2178 class RFEI<bit wb, string asm>
2179 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2180 NoItinerary, asm, "", []> {
2182 let Inst{31-28} = 0b1111;
2183 let Inst{27-25} = 0b100;
2187 let Inst{19-16} = Rn;
2188 let Inst{15-0} = 0xa00;
2191 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2192 let Inst{24-23} = 0;
2194 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2195 let Inst{24-23} = 0;
2197 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2198 let Inst{24-23} = 0b10;
2200 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2201 let Inst{24-23} = 0b10;
2203 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2204 let Inst{24-23} = 0b01;
2206 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2207 let Inst{24-23} = 0b01;
2209 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2210 let Inst{24-23} = 0b11;
2212 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2213 let Inst{24-23} = 0b11;
2216 //===----------------------------------------------------------------------===//
2217 // Load / Store Instructions.
2223 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2224 UnOpFrag<(load node:$Src)>>;
2225 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2226 UnOpFrag<(zextloadi8 node:$Src)>>;
2227 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2228 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2229 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2230 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2232 // Special LDR for loads from non-pc-relative constpools.
2233 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2234 isReMaterializable = 1, isCodeGenOnly = 1 in
2235 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2236 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2240 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2241 let Inst{19-16} = 0b1111;
2242 let Inst{15-12} = Rt;
2243 let Inst{11-0} = addr{11-0}; // imm12
2246 // Loads with zero extension
2247 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2248 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2249 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2251 // Loads with sign extension
2252 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2253 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2254 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2256 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2257 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2258 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2260 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2262 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2263 (ins addrmode3:$addr), LdMiscFrm,
2264 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2265 []>, Requires<[IsARM, HasV5TE]>;
2268 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2269 NoItinerary, "lda", "\t$Rt, $addr", []>;
2270 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2271 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2272 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2273 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2276 multiclass AI2_ldridx<bit isByte, string opc,
2277 InstrItinClass iii, InstrItinClass iir> {
2278 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2279 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2280 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2283 let Inst{23} = addr{12};
2284 let Inst{19-16} = addr{16-13};
2285 let Inst{11-0} = addr{11-0};
2286 let DecoderMethod = "DecodeLDRPreImm";
2289 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2290 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2291 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2294 let Inst{23} = addr{12};
2295 let Inst{19-16} = addr{16-13};
2296 let Inst{11-0} = addr{11-0};
2298 let DecoderMethod = "DecodeLDRPreReg";
2301 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2302 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2303 IndexModePost, LdFrm, iir,
2304 opc, "\t$Rt, $addr, $offset",
2305 "$addr.base = $Rn_wb", []> {
2311 let Inst{23} = offset{12};
2312 let Inst{19-16} = addr;
2313 let Inst{11-0} = offset{11-0};
2316 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2319 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2320 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2321 IndexModePost, LdFrm, iii,
2322 opc, "\t$Rt, $addr, $offset",
2323 "$addr.base = $Rn_wb", []> {
2329 let Inst{23} = offset{12};
2330 let Inst{19-16} = addr;
2331 let Inst{11-0} = offset{11-0};
2333 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2338 let mayLoad = 1, neverHasSideEffects = 1 in {
2339 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2340 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2341 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2342 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2345 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2346 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2347 (ins addrmode3_pre:$addr), IndexModePre,
2349 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2351 let Inst{23} = addr{8}; // U bit
2352 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2353 let Inst{19-16} = addr{12-9}; // Rn
2354 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2355 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2356 let DecoderMethod = "DecodeAddrMode3Instruction";
2358 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2359 (ins addr_offset_none:$addr, am3offset:$offset),
2360 IndexModePost, LdMiscFrm, itin,
2361 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2365 let Inst{23} = offset{8}; // U bit
2366 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2367 let Inst{19-16} = addr;
2368 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2369 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2370 let DecoderMethod = "DecodeAddrMode3Instruction";
2374 let mayLoad = 1, neverHasSideEffects = 1 in {
2375 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2376 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2377 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2378 let hasExtraDefRegAllocReq = 1 in {
2379 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2380 (ins addrmode3_pre:$addr), IndexModePre,
2381 LdMiscFrm, IIC_iLoad_d_ru,
2382 "ldrd", "\t$Rt, $Rt2, $addr!",
2383 "$addr.base = $Rn_wb", []> {
2385 let Inst{23} = addr{8}; // U bit
2386 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2387 let Inst{19-16} = addr{12-9}; // Rn
2388 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2389 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2390 let DecoderMethod = "DecodeAddrMode3Instruction";
2392 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2393 (ins addr_offset_none:$addr, am3offset:$offset),
2394 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2395 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2396 "$addr.base = $Rn_wb", []> {
2399 let Inst{23} = offset{8}; // U bit
2400 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2401 let Inst{19-16} = addr;
2402 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2403 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2404 let DecoderMethod = "DecodeAddrMode3Instruction";
2406 } // hasExtraDefRegAllocReq = 1
2407 } // mayLoad = 1, neverHasSideEffects = 1
2409 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2410 let mayLoad = 1, neverHasSideEffects = 1 in {
2411 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2412 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2413 IndexModePost, LdFrm, IIC_iLoad_ru,
2414 "ldrt", "\t$Rt, $addr, $offset",
2415 "$addr.base = $Rn_wb", []> {
2421 let Inst{23} = offset{12};
2422 let Inst{21} = 1; // overwrite
2423 let Inst{19-16} = addr;
2424 let Inst{11-5} = offset{11-5};
2426 let Inst{3-0} = offset{3-0};
2427 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2430 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2431 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2432 IndexModePost, LdFrm, IIC_iLoad_ru,
2433 "ldrt", "\t$Rt, $addr, $offset",
2434 "$addr.base = $Rn_wb", []> {
2440 let Inst{23} = offset{12};
2441 let Inst{21} = 1; // overwrite
2442 let Inst{19-16} = addr;
2443 let Inst{11-0} = offset{11-0};
2444 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2447 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2448 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2449 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2450 "ldrbt", "\t$Rt, $addr, $offset",
2451 "$addr.base = $Rn_wb", []> {
2457 let Inst{23} = offset{12};
2458 let Inst{21} = 1; // overwrite
2459 let Inst{19-16} = addr;
2460 let Inst{11-5} = offset{11-5};
2462 let Inst{3-0} = offset{3-0};
2463 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2466 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2467 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2468 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2469 "ldrbt", "\t$Rt, $addr, $offset",
2470 "$addr.base = $Rn_wb", []> {
2476 let Inst{23} = offset{12};
2477 let Inst{21} = 1; // overwrite
2478 let Inst{19-16} = addr;
2479 let Inst{11-0} = offset{11-0};
2480 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2483 multiclass AI3ldrT<bits<4> op, string opc> {
2484 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2485 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2486 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2487 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2489 let Inst{23} = offset{8};
2491 let Inst{11-8} = offset{7-4};
2492 let Inst{3-0} = offset{3-0};
2494 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2495 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2496 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2497 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2499 let Inst{23} = Rm{4};
2502 let Unpredictable{11-8} = 0b1111;
2503 let Inst{3-0} = Rm{3-0};
2504 let DecoderMethod = "DecodeLDR";
2508 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2509 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2510 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2515 // Stores with truncate
2516 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2517 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2518 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2521 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2522 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2523 StMiscFrm, IIC_iStore_d_r,
2524 "strd", "\t$Rt, $src2, $addr", []>,
2525 Requires<[IsARM, HasV5TE]> {
2530 multiclass AI2_stridx<bit isByte, string opc,
2531 InstrItinClass iii, InstrItinClass iir> {
2532 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2533 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2535 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2538 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2539 let Inst{19-16} = addr{16-13}; // Rn
2540 let Inst{11-0} = addr{11-0}; // imm12
2541 let DecoderMethod = "DecodeSTRPreImm";
2544 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2545 (ins GPR:$Rt, ldst_so_reg:$addr),
2546 IndexModePre, StFrm, iir,
2547 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2550 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2551 let Inst{19-16} = addr{16-13}; // Rn
2552 let Inst{11-0} = addr{11-0};
2553 let Inst{4} = 0; // Inst{4} = 0
2554 let DecoderMethod = "DecodeSTRPreReg";
2556 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2557 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2558 IndexModePost, StFrm, iir,
2559 opc, "\t$Rt, $addr, $offset",
2560 "$addr.base = $Rn_wb", []> {
2566 let Inst{23} = offset{12};
2567 let Inst{19-16} = addr;
2568 let Inst{11-0} = offset{11-0};
2571 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2574 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2575 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2576 IndexModePost, StFrm, iii,
2577 opc, "\t$Rt, $addr, $offset",
2578 "$addr.base = $Rn_wb", []> {
2584 let Inst{23} = offset{12};
2585 let Inst{19-16} = addr;
2586 let Inst{11-0} = offset{11-0};
2588 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2592 let mayStore = 1, neverHasSideEffects = 1 in {
2593 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2594 // IIC_iStore_siu depending on whether it the offset register is shifted.
2595 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2596 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2599 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2600 am2offset_reg:$offset),
2601 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2602 am2offset_reg:$offset)>;
2603 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2604 am2offset_imm:$offset),
2605 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2606 am2offset_imm:$offset)>;
2607 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2608 am2offset_reg:$offset),
2609 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2610 am2offset_reg:$offset)>;
2611 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2612 am2offset_imm:$offset),
2613 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2614 am2offset_imm:$offset)>;
2616 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2617 // put the patterns on the instruction definitions directly as ISel wants
2618 // the address base and offset to be separate operands, not a single
2619 // complex operand like we represent the instructions themselves. The
2620 // pseudos map between the two.
2621 let usesCustomInserter = 1,
2622 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2623 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2624 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2627 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2628 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2629 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2632 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2633 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2634 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2637 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2638 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2639 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2642 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2643 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2644 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2647 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2652 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2653 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2654 StMiscFrm, IIC_iStore_bh_ru,
2655 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2657 let Inst{23} = addr{8}; // U bit
2658 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2659 let Inst{19-16} = addr{12-9}; // Rn
2660 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2661 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2662 let DecoderMethod = "DecodeAddrMode3Instruction";
2665 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2666 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2667 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2668 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2669 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2670 addr_offset_none:$addr,
2671 am3offset:$offset))]> {
2674 let Inst{23} = offset{8}; // U bit
2675 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2676 let Inst{19-16} = addr;
2677 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2678 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2679 let DecoderMethod = "DecodeAddrMode3Instruction";
2682 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2683 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2684 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2685 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2686 "strd", "\t$Rt, $Rt2, $addr!",
2687 "$addr.base = $Rn_wb", []> {
2689 let Inst{23} = addr{8}; // U bit
2690 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2691 let Inst{19-16} = addr{12-9}; // Rn
2692 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2693 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2694 let DecoderMethod = "DecodeAddrMode3Instruction";
2697 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2698 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2700 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2701 "strd", "\t$Rt, $Rt2, $addr, $offset",
2702 "$addr.base = $Rn_wb", []> {
2705 let Inst{23} = offset{8}; // U bit
2706 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2707 let Inst{19-16} = addr;
2708 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2709 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2710 let DecoderMethod = "DecodeAddrMode3Instruction";
2712 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2714 // STRT, STRBT, and STRHT
2716 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2717 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2718 IndexModePost, StFrm, IIC_iStore_bh_ru,
2719 "strbt", "\t$Rt, $addr, $offset",
2720 "$addr.base = $Rn_wb", []> {
2726 let Inst{23} = offset{12};
2727 let Inst{21} = 1; // overwrite
2728 let Inst{19-16} = addr;
2729 let Inst{11-5} = offset{11-5};
2731 let Inst{3-0} = offset{3-0};
2732 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2735 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2736 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2737 IndexModePost, StFrm, IIC_iStore_bh_ru,
2738 "strbt", "\t$Rt, $addr, $offset",
2739 "$addr.base = $Rn_wb", []> {
2745 let Inst{23} = offset{12};
2746 let Inst{21} = 1; // overwrite
2747 let Inst{19-16} = addr;
2748 let Inst{11-0} = offset{11-0};
2749 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2752 let mayStore = 1, neverHasSideEffects = 1 in {
2753 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2754 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2755 IndexModePost, StFrm, IIC_iStore_ru,
2756 "strt", "\t$Rt, $addr, $offset",
2757 "$addr.base = $Rn_wb", []> {
2763 let Inst{23} = offset{12};
2764 let Inst{21} = 1; // overwrite
2765 let Inst{19-16} = addr;
2766 let Inst{11-5} = offset{11-5};
2768 let Inst{3-0} = offset{3-0};
2769 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2772 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2773 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2774 IndexModePost, StFrm, IIC_iStore_ru,
2775 "strt", "\t$Rt, $addr, $offset",
2776 "$addr.base = $Rn_wb", []> {
2782 let Inst{23} = offset{12};
2783 let Inst{21} = 1; // overwrite
2784 let Inst{19-16} = addr;
2785 let Inst{11-0} = offset{11-0};
2786 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2791 multiclass AI3strT<bits<4> op, string opc> {
2792 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2793 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2794 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2795 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2797 let Inst{23} = offset{8};
2799 let Inst{11-8} = offset{7-4};
2800 let Inst{3-0} = offset{3-0};
2802 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2803 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2804 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2805 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2807 let Inst{23} = Rm{4};
2810 let Inst{3-0} = Rm{3-0};
2815 defm STRHT : AI3strT<0b1011, "strht">;
2817 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2818 NoItinerary, "stl", "\t$Rt, $addr", []>;
2819 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2820 NoItinerary, "stlb", "\t$Rt, $addr", []>;
2821 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2822 NoItinerary, "stlh", "\t$Rt, $addr", []>;
2824 //===----------------------------------------------------------------------===//
2825 // Load / store multiple Instructions.
2828 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2829 InstrItinClass itin, InstrItinClass itin_upd> {
2830 // IA is the default, so no need for an explicit suffix on the
2831 // mnemonic here. Without it is the canonical spelling.
2833 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2834 IndexModeNone, f, itin,
2835 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2836 let Inst{24-23} = 0b01; // Increment After
2837 let Inst{22} = P_bit;
2838 let Inst{21} = 0; // No writeback
2839 let Inst{20} = L_bit;
2842 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2843 IndexModeUpd, f, itin_upd,
2844 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2845 let Inst{24-23} = 0b01; // Increment After
2846 let Inst{22} = P_bit;
2847 let Inst{21} = 1; // Writeback
2848 let Inst{20} = L_bit;
2850 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2853 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2854 IndexModeNone, f, itin,
2855 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2856 let Inst{24-23} = 0b00; // Decrement After
2857 let Inst{22} = P_bit;
2858 let Inst{21} = 0; // No writeback
2859 let Inst{20} = L_bit;
2862 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2863 IndexModeUpd, f, itin_upd,
2864 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2865 let Inst{24-23} = 0b00; // Decrement After
2866 let Inst{22} = P_bit;
2867 let Inst{21} = 1; // Writeback
2868 let Inst{20} = L_bit;
2870 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2873 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2874 IndexModeNone, f, itin,
2875 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2876 let Inst{24-23} = 0b10; // Decrement Before
2877 let Inst{22} = P_bit;
2878 let Inst{21} = 0; // No writeback
2879 let Inst{20} = L_bit;
2882 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2883 IndexModeUpd, f, itin_upd,
2884 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2885 let Inst{24-23} = 0b10; // Decrement Before
2886 let Inst{22} = P_bit;
2887 let Inst{21} = 1; // Writeback
2888 let Inst{20} = L_bit;
2890 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2893 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2894 IndexModeNone, f, itin,
2895 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2896 let Inst{24-23} = 0b11; // Increment Before
2897 let Inst{22} = P_bit;
2898 let Inst{21} = 0; // No writeback
2899 let Inst{20} = L_bit;
2902 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2903 IndexModeUpd, f, itin_upd,
2904 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2905 let Inst{24-23} = 0b11; // Increment Before
2906 let Inst{22} = P_bit;
2907 let Inst{21} = 1; // Writeback
2908 let Inst{20} = L_bit;
2910 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2914 let neverHasSideEffects = 1 in {
2916 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2917 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2920 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2921 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2924 } // neverHasSideEffects
2926 // FIXME: remove when we have a way to marking a MI with these properties.
2927 // FIXME: Should pc be an implicit operand like PICADD, etc?
2928 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2929 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2930 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2931 reglist:$regs, variable_ops),
2932 4, IIC_iLoad_mBr, [],
2933 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2934 RegConstraint<"$Rn = $wb">;
2936 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2937 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2940 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2941 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2946 //===----------------------------------------------------------------------===//
2947 // Move Instructions.
2950 let neverHasSideEffects = 1 in
2951 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2952 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2956 let Inst{19-16} = 0b0000;
2957 let Inst{11-4} = 0b00000000;
2960 let Inst{15-12} = Rd;
2963 // A version for the smaller set of tail call registers.
2964 let neverHasSideEffects = 1 in
2965 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2966 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2970 let Inst{11-4} = 0b00000000;
2973 let Inst{15-12} = Rd;
2976 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2977 DPSoRegRegFrm, IIC_iMOVsr,
2978 "mov", "\t$Rd, $src",
2979 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
2983 let Inst{15-12} = Rd;
2984 let Inst{19-16} = 0b0000;
2985 let Inst{11-8} = src{11-8};
2987 let Inst{6-5} = src{6-5};
2989 let Inst{3-0} = src{3-0};
2993 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2994 DPSoRegImmFrm, IIC_iMOVsr,
2995 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2996 UnaryDP, Sched<[WriteALU]> {
2999 let Inst{15-12} = Rd;
3000 let Inst{19-16} = 0b0000;
3001 let Inst{11-5} = src{11-5};
3003 let Inst{3-0} = src{3-0};
3007 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3008 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3009 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
3014 let Inst{15-12} = Rd;
3015 let Inst{19-16} = 0b0000;
3016 let Inst{11-0} = imm;
3019 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3020 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3022 "movw", "\t$Rd, $imm",
3023 [(set GPR:$Rd, imm0_65535:$imm)]>,
3024 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3027 let Inst{15-12} = Rd;
3028 let Inst{11-0} = imm{11-0};
3029 let Inst{19-16} = imm{15-12};
3032 let DecoderMethod = "DecodeArmMOVTWInstruction";
3035 def : InstAlias<"mov${p} $Rd, $imm",
3036 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3039 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3040 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3043 let Constraints = "$src = $Rd" in {
3044 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3045 (ins GPR:$src, imm0_65535_expr:$imm),
3047 "movt", "\t$Rd, $imm",
3049 (or (and GPR:$src, 0xffff),
3050 lo16AllZero:$imm))]>, UnaryDP,
3051 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3054 let Inst{15-12} = Rd;
3055 let Inst{11-0} = imm{11-0};
3056 let Inst{19-16} = imm{15-12};
3059 let DecoderMethod = "DecodeArmMOVTWInstruction";
3062 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3063 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3068 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3069 Requires<[IsARM, HasV6T2]>;
3071 let Uses = [CPSR] in
3072 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3073 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3074 Requires<[IsARM]>, Sched<[WriteALU]>;
3076 // These aren't really mov instructions, but we have to define them this way
3077 // due to flag operands.
3079 let Defs = [CPSR] in {
3080 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3081 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3082 Sched<[WriteALU]>, Requires<[IsARM]>;
3083 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3084 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3085 Sched<[WriteALU]>, Requires<[IsARM]>;
3088 //===----------------------------------------------------------------------===//
3089 // Extend Instructions.
3094 def SXTB : AI_ext_rrot<0b01101010,
3095 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3096 def SXTH : AI_ext_rrot<0b01101011,
3097 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3099 def SXTAB : AI_exta_rrot<0b01101010,
3100 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3101 def SXTAH : AI_exta_rrot<0b01101011,
3102 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3104 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3106 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3110 let AddedComplexity = 16 in {
3111 def UXTB : AI_ext_rrot<0b01101110,
3112 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3113 def UXTH : AI_ext_rrot<0b01101111,
3114 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3115 def UXTB16 : AI_ext_rrot<0b01101100,
3116 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3118 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3119 // The transformation should probably be done as a combiner action
3120 // instead so we can include a check for masking back in the upper
3121 // eight bits of the source into the lower eight bits of the result.
3122 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3123 // (UXTB16r_rot GPR:$Src, 3)>;
3124 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3125 (UXTB16 GPR:$Src, 1)>;
3127 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3128 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3129 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3130 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3133 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3134 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3137 def SBFX : I<(outs GPRnopc:$Rd),
3138 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3139 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3140 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3141 Requires<[IsARM, HasV6T2]> {
3146 let Inst{27-21} = 0b0111101;
3147 let Inst{6-4} = 0b101;
3148 let Inst{20-16} = width;
3149 let Inst{15-12} = Rd;
3150 let Inst{11-7} = lsb;
3154 def UBFX : I<(outs GPR:$Rd),
3155 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3156 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3157 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3158 Requires<[IsARM, HasV6T2]> {
3163 let Inst{27-21} = 0b0111111;
3164 let Inst{6-4} = 0b101;
3165 let Inst{20-16} = width;
3166 let Inst{15-12} = Rd;
3167 let Inst{11-7} = lsb;
3171 //===----------------------------------------------------------------------===//
3172 // Arithmetic Instructions.
3175 defm ADD : AsI1_bin_irs<0b0100, "add",
3176 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3177 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3178 defm SUB : AsI1_bin_irs<0b0010, "sub",
3179 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3180 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3182 // ADD and SUB with 's' bit set.
3184 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3185 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3186 // AdjustInstrPostInstrSelection where we determine whether or not to
3187 // set the "s" bit based on CPSR liveness.
3189 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3190 // support for an optional CPSR definition that corresponds to the DAG
3191 // node's second value. We can then eliminate the implicit def of CPSR.
3192 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3193 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3194 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3195 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3197 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3198 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3199 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3200 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3202 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3203 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3204 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3206 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3207 // CPSR and the implicit def of CPSR is not needed.
3208 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3209 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3211 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3212 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3214 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3215 // The assume-no-carry-in form uses the negation of the input since add/sub
3216 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3217 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3219 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3220 (SUBri GPR:$src, so_imm_neg:$imm)>;
3221 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3222 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3224 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3225 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3226 Requires<[IsARM, HasV6T2]>;
3227 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3228 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3229 Requires<[IsARM, HasV6T2]>;
3231 // The with-carry-in form matches bitwise not instead of the negation.
3232 // Effectively, the inverse interpretation of the carry flag already accounts
3233 // for part of the negation.
3234 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3235 (SBCri GPR:$src, so_imm_not:$imm)>;
3236 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3237 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3239 // Note: These are implemented in C++ code, because they have to generate
3240 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3242 // (mul X, 2^n+1) -> (add (X << n), X)
3243 // (mul X, 2^n-1) -> (rsb X, (X << n))
3245 // ARM Arithmetic Instruction
3246 // GPR:$dst = GPR:$a op GPR:$b
3247 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3248 list<dag> pattern = [],
3249 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3250 string asm = "\t$Rd, $Rn, $Rm">
3251 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3252 Sched<[WriteALU, ReadALU, ReadALU]> {
3256 let Inst{27-20} = op27_20;
3257 let Inst{11-4} = op11_4;
3258 let Inst{19-16} = Rn;
3259 let Inst{15-12} = Rd;
3262 let Unpredictable{11-8} = 0b1111;
3265 // Saturating add/subtract
3267 let DecoderMethod = "DecodeQADDInstruction" in
3268 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3269 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3270 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3272 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3273 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3274 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3275 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3276 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3278 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3279 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3282 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3283 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3284 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3285 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3286 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3287 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3288 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3289 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3290 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3291 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3292 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3293 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3295 // Signed/Unsigned add/subtract
3297 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3298 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3299 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3300 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3301 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3302 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3303 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3304 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3305 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3306 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3307 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3308 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3310 // Signed/Unsigned halving add/subtract
3312 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3313 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3314 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3315 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3316 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3317 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3318 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3319 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3320 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3321 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3322 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3323 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3325 // Unsigned Sum of Absolute Differences [and Accumulate].
3327 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3328 MulFrm /* for convenience */, NoItinerary, "usad8",
3329 "\t$Rd, $Rn, $Rm", []>,
3330 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3334 let Inst{27-20} = 0b01111000;
3335 let Inst{15-12} = 0b1111;
3336 let Inst{7-4} = 0b0001;
3337 let Inst{19-16} = Rd;
3338 let Inst{11-8} = Rm;
3341 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3342 MulFrm /* for convenience */, NoItinerary, "usada8",
3343 "\t$Rd, $Rn, $Rm, $Ra", []>,
3344 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3349 let Inst{27-20} = 0b01111000;
3350 let Inst{7-4} = 0b0001;
3351 let Inst{19-16} = Rd;
3352 let Inst{15-12} = Ra;
3353 let Inst{11-8} = Rm;
3357 // Signed/Unsigned saturate
3359 def SSAT : AI<(outs GPRnopc:$Rd),
3360 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3361 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3366 let Inst{27-21} = 0b0110101;
3367 let Inst{5-4} = 0b01;
3368 let Inst{20-16} = sat_imm;
3369 let Inst{15-12} = Rd;
3370 let Inst{11-7} = sh{4-0};
3371 let Inst{6} = sh{5};
3375 def SSAT16 : AI<(outs GPRnopc:$Rd),
3376 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3377 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3381 let Inst{27-20} = 0b01101010;
3382 let Inst{11-4} = 0b11110011;
3383 let Inst{15-12} = Rd;
3384 let Inst{19-16} = sat_imm;
3388 def USAT : AI<(outs GPRnopc:$Rd),
3389 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3390 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3395 let Inst{27-21} = 0b0110111;
3396 let Inst{5-4} = 0b01;
3397 let Inst{15-12} = Rd;
3398 let Inst{11-7} = sh{4-0};
3399 let Inst{6} = sh{5};
3400 let Inst{20-16} = sat_imm;
3404 def USAT16 : AI<(outs GPRnopc:$Rd),
3405 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3406 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3410 let Inst{27-20} = 0b01101110;
3411 let Inst{11-4} = 0b11110011;
3412 let Inst{15-12} = Rd;
3413 let Inst{19-16} = sat_imm;
3417 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3418 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3419 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3420 (USAT imm:$pos, GPRnopc:$a, 0)>;
3422 //===----------------------------------------------------------------------===//
3423 // Bitwise Instructions.
3426 defm AND : AsI1_bin_irs<0b0000, "and",
3427 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3428 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3429 defm ORR : AsI1_bin_irs<0b1100, "orr",
3430 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3431 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3432 defm EOR : AsI1_bin_irs<0b0001, "eor",
3433 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3434 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3435 defm BIC : AsI1_bin_irs<0b1110, "bic",
3436 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3437 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3439 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3440 // like in the actual instruction encoding. The complexity of mapping the mask
3441 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3442 // instruction description.
3443 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3444 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3445 "bfc", "\t$Rd, $imm", "$src = $Rd",
3446 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3447 Requires<[IsARM, HasV6T2]> {
3450 let Inst{27-21} = 0b0111110;
3451 let Inst{6-0} = 0b0011111;
3452 let Inst{15-12} = Rd;
3453 let Inst{11-7} = imm{4-0}; // lsb
3454 let Inst{20-16} = imm{9-5}; // msb
3457 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3458 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3459 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3460 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3461 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3462 bf_inv_mask_imm:$imm))]>,
3463 Requires<[IsARM, HasV6T2]> {
3467 let Inst{27-21} = 0b0111110;
3468 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3469 let Inst{15-12} = Rd;
3470 let Inst{11-7} = imm{4-0}; // lsb
3471 let Inst{20-16} = imm{9-5}; // width
3475 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3476 "mvn", "\t$Rd, $Rm",
3477 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3481 let Inst{19-16} = 0b0000;
3482 let Inst{11-4} = 0b00000000;
3483 let Inst{15-12} = Rd;
3486 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3487 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3488 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3493 let Inst{19-16} = 0b0000;
3494 let Inst{15-12} = Rd;
3495 let Inst{11-5} = shift{11-5};
3497 let Inst{3-0} = shift{3-0};
3499 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3500 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3501 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3506 let Inst{19-16} = 0b0000;
3507 let Inst{15-12} = Rd;
3508 let Inst{11-8} = shift{11-8};
3510 let Inst{6-5} = shift{6-5};
3512 let Inst{3-0} = shift{3-0};
3514 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3515 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3516 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3517 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3521 let Inst{19-16} = 0b0000;
3522 let Inst{15-12} = Rd;
3523 let Inst{11-0} = imm;
3526 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3527 (BICri GPR:$src, so_imm_not:$imm)>;
3529 //===----------------------------------------------------------------------===//
3530 // Multiply Instructions.
3532 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3533 string opc, string asm, list<dag> pattern>
3534 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3538 let Inst{19-16} = Rd;
3539 let Inst{11-8} = Rm;
3542 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3543 string opc, string asm, list<dag> pattern>
3544 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3549 let Inst{19-16} = RdHi;
3550 let Inst{15-12} = RdLo;
3551 let Inst{11-8} = Rm;
3554 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3555 string opc, string asm, list<dag> pattern>
3556 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3561 let Inst{19-16} = RdHi;
3562 let Inst{15-12} = RdLo;
3563 let Inst{11-8} = Rm;
3567 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3568 // property. Remove them when it's possible to add those properties
3569 // on an individual MachineInstr, not just an instruction description.
3570 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3571 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3572 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3573 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3574 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3575 Requires<[IsARM, HasV6]> {
3576 let Inst{15-12} = 0b0000;
3577 let Unpredictable{15-12} = 0b1111;
3580 let Constraints = "@earlyclobber $Rd" in
3581 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3582 pred:$p, cc_out:$s),
3584 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3585 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3586 Requires<[IsARM, NoV6, UseMulOps]>;
3589 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3590 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3591 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3592 Requires<[IsARM, HasV6, UseMulOps]> {
3594 let Inst{15-12} = Ra;
3597 let Constraints = "@earlyclobber $Rd" in
3598 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3599 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3601 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3602 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3603 Requires<[IsARM, NoV6]>;
3605 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3606 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3607 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3608 Requires<[IsARM, HasV6T2, UseMulOps]> {
3613 let Inst{19-16} = Rd;
3614 let Inst{15-12} = Ra;
3615 let Inst{11-8} = Rm;
3619 // Extra precision multiplies with low / high results
3620 let neverHasSideEffects = 1 in {
3621 let isCommutable = 1 in {
3622 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3623 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3624 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3625 Requires<[IsARM, HasV6]>;
3627 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3628 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3629 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3630 Requires<[IsARM, HasV6]>;
3632 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3633 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3634 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3636 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3637 Requires<[IsARM, NoV6]>;
3639 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3640 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3642 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3643 Requires<[IsARM, NoV6]>;
3647 // Multiply + accumulate
3648 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3649 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3650 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3651 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3652 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3653 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3654 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3655 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3657 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3658 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3659 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3660 Requires<[IsARM, HasV6]> {
3665 let Inst{19-16} = RdHi;
3666 let Inst{15-12} = RdLo;
3667 let Inst{11-8} = Rm;
3671 let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
3672 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3673 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3675 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3676 pred:$p, cc_out:$s)>,
3677 Requires<[IsARM, NoV6]>;
3678 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3679 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3681 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3682 pred:$p, cc_out:$s)>,
3683 Requires<[IsARM, NoV6]>;
3686 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3687 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3688 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3690 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3691 Requires<[IsARM, NoV6]>;
3694 } // neverHasSideEffects
3696 // Most significant word multiply
3697 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3698 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3699 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3700 Requires<[IsARM, HasV6]> {
3701 let Inst{15-12} = 0b1111;
3704 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3705 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3706 Requires<[IsARM, HasV6]> {
3707 let Inst{15-12} = 0b1111;
3710 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3711 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3712 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3713 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3714 Requires<[IsARM, HasV6, UseMulOps]>;
3716 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3717 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3718 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3719 Requires<[IsARM, HasV6]>;
3721 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3722 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3723 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3724 Requires<[IsARM, HasV6, UseMulOps]>;
3726 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3727 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3728 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3729 Requires<[IsARM, HasV6]>;
3731 multiclass AI_smul<string opc, PatFrag opnode> {
3732 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3733 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3734 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3735 (sext_inreg GPR:$Rm, i16)))]>,
3736 Requires<[IsARM, HasV5TE]>;
3738 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3739 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3740 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3741 (sra GPR:$Rm, (i32 16))))]>,
3742 Requires<[IsARM, HasV5TE]>;
3744 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3745 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3746 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3747 (sext_inreg GPR:$Rm, i16)))]>,
3748 Requires<[IsARM, HasV5TE]>;
3750 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3751 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3752 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3753 (sra GPR:$Rm, (i32 16))))]>,
3754 Requires<[IsARM, HasV5TE]>;
3756 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3757 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3758 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3759 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3760 Requires<[IsARM, HasV5TE]>;
3762 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3763 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3764 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3765 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3766 Requires<[IsARM, HasV5TE]>;
3770 multiclass AI_smla<string opc, PatFrag opnode> {
3771 let DecoderMethod = "DecodeSMLAInstruction" in {
3772 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3773 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3774 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3775 [(set GPRnopc:$Rd, (add GPR:$Ra,
3776 (opnode (sext_inreg GPRnopc:$Rn, i16),
3777 (sext_inreg GPRnopc:$Rm, i16))))]>,
3778 Requires<[IsARM, HasV5TE, UseMulOps]>;
3780 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3781 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3782 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3784 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3785 (sra GPRnopc:$Rm, (i32 16)))))]>,
3786 Requires<[IsARM, HasV5TE, UseMulOps]>;
3788 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3789 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3790 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3792 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3793 (sext_inreg GPRnopc:$Rm, i16))))]>,
3794 Requires<[IsARM, HasV5TE, UseMulOps]>;
3796 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3797 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3798 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3800 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3801 (sra GPRnopc:$Rm, (i32 16)))))]>,
3802 Requires<[IsARM, HasV5TE, UseMulOps]>;
3804 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3805 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3806 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3808 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3809 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3810 Requires<[IsARM, HasV5TE, UseMulOps]>;
3812 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3813 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3814 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3816 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3817 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3818 Requires<[IsARM, HasV5TE, UseMulOps]>;
3822 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3823 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3825 // Halfword multiply accumulate long: SMLAL<x><y>.
3826 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3827 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3828 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3829 Requires<[IsARM, HasV5TE]>;
3831 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3832 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3833 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3834 Requires<[IsARM, HasV5TE]>;
3836 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3837 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3838 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3839 Requires<[IsARM, HasV5TE]>;
3841 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3842 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3843 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3844 Requires<[IsARM, HasV5TE]>;
3846 // Helper class for AI_smld.
3847 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3848 InstrItinClass itin, string opc, string asm>
3849 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3852 let Inst{27-23} = 0b01110;
3853 let Inst{22} = long;
3854 let Inst{21-20} = 0b00;
3855 let Inst{11-8} = Rm;
3862 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3863 InstrItinClass itin, string opc, string asm>
3864 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3866 let Inst{15-12} = 0b1111;
3867 let Inst{19-16} = Rd;
3869 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3870 InstrItinClass itin, string opc, string asm>
3871 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3874 let Inst{19-16} = Rd;
3875 let Inst{15-12} = Ra;
3877 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3878 InstrItinClass itin, string opc, string asm>
3879 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3882 let Inst{19-16} = RdHi;
3883 let Inst{15-12} = RdLo;
3886 multiclass AI_smld<bit sub, string opc> {
3888 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3889 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3890 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3892 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3893 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3894 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3896 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3897 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3898 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3900 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3901 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3902 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3906 defm SMLA : AI_smld<0, "smla">;
3907 defm SMLS : AI_smld<1, "smls">;
3909 multiclass AI_sdml<bit sub, string opc> {
3911 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3912 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3913 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3914 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3917 defm SMUA : AI_sdml<0, "smua">;
3918 defm SMUS : AI_sdml<1, "smus">;
3920 //===----------------------------------------------------------------------===//
3921 // Division Instructions (ARMv7-A with virtualization extension)
3923 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3924 "sdiv", "\t$Rd, $Rn, $Rm",
3925 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3926 Requires<[IsARM, HasDivideInARM]>;
3928 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3929 "udiv", "\t$Rd, $Rn, $Rm",
3930 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3931 Requires<[IsARM, HasDivideInARM]>;
3933 //===----------------------------------------------------------------------===//
3934 // Misc. Arithmetic Instructions.
3937 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3938 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3939 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
3942 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3943 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3944 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3945 Requires<[IsARM, HasV6T2]>,
3948 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3949 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3950 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
3953 let AddedComplexity = 5 in
3954 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3955 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3956 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3957 Requires<[IsARM, HasV6]>,
3960 let AddedComplexity = 5 in
3961 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3962 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3963 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3964 Requires<[IsARM, HasV6]>,
3967 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3968 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3971 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3972 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3973 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3974 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3975 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3977 Requires<[IsARM, HasV6]>,
3978 Sched<[WriteALUsi, ReadALU]>;
3980 // Alternate cases for PKHBT where identities eliminate some nodes.
3981 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3982 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3983 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3984 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3986 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3987 // will match the pattern below.
3988 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3989 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3990 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3991 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3992 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3994 Requires<[IsARM, HasV6]>,
3995 Sched<[WriteALUsi, ReadALU]>;
3997 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3998 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3999 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4000 // pkhtb src1, src2, asr (17..31).
4001 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4002 (srl GPRnopc:$src2, imm16:$sh)),
4003 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4004 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4005 (sra GPRnopc:$src2, imm16_31:$sh)),
4006 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4007 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4008 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4009 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4011 //===----------------------------------------------------------------------===//
4015 // + CRC32{B,H,W} 0x04C11DB7
4016 // + CRC32C{B,H,W} 0x1EDC6F41
4019 class AI_crc32<bit C, bits<2> sz, string suffix, SDPatternOperator builtin>
4020 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4021 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4022 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4023 Requires<[IsARM, HasV8]> {
4028 let Inst{31-28} = 0b1110;
4029 let Inst{27-23} = 0b00010;
4030 let Inst{22-21} = sz;
4032 let Inst{19-16} = Rn;
4033 let Inst{15-12} = Rd;
4034 let Inst{11-10} = 0b00;
4037 let Inst{7-4} = 0b0100;
4040 let Unpredictable{11-8} = 0b1101;
4043 def CRC32B : AI_crc32<0, 0b00, "b", int_arm_crc32b>;
4044 def CRC32CB : AI_crc32<1, 0b00, "cb", int_arm_crc32cb>;
4045 def CRC32H : AI_crc32<0, 0b01, "h", int_arm_crc32h>;
4046 def CRC32CH : AI_crc32<1, 0b01, "ch", int_arm_crc32ch>;
4047 def CRC32W : AI_crc32<0, 0b10, "w", int_arm_crc32w>;
4048 def CRC32CW : AI_crc32<1, 0b10, "cw", int_arm_crc32cw>;
4050 //===----------------------------------------------------------------------===//
4051 // Comparison Instructions...
4054 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4055 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4056 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4058 // ARMcmpZ can re-use the above instruction definitions.
4059 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
4060 (CMPri GPR:$src, so_imm:$imm)>;
4061 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4062 (CMPrr GPR:$src, GPR:$rhs)>;
4063 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4064 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4065 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4066 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4068 // CMN register-integer
4069 let isCompare = 1, Defs = [CPSR] in {
4070 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
4071 "cmn", "\t$Rn, $imm",
4072 [(ARMcmn GPR:$Rn, so_imm:$imm)]>,
4073 Sched<[WriteCMP, ReadALU]> {
4078 let Inst{19-16} = Rn;
4079 let Inst{15-12} = 0b0000;
4080 let Inst{11-0} = imm;
4082 let Unpredictable{15-12} = 0b1111;
4085 // CMN register-register/shift
4086 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4087 "cmn", "\t$Rn, $Rm",
4088 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4089 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4092 let isCommutable = 1;
4095 let Inst{19-16} = Rn;
4096 let Inst{15-12} = 0b0000;
4097 let Inst{11-4} = 0b00000000;
4100 let Unpredictable{15-12} = 0b1111;
4103 def CMNzrsi : AI1<0b1011, (outs),
4104 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4105 "cmn", "\t$Rn, $shift",
4106 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4107 GPR:$Rn, so_reg_imm:$shift)]>,
4108 Sched<[WriteCMPsi, ReadALU]> {
4113 let Inst{19-16} = Rn;
4114 let Inst{15-12} = 0b0000;
4115 let Inst{11-5} = shift{11-5};
4117 let Inst{3-0} = shift{3-0};
4119 let Unpredictable{15-12} = 0b1111;
4122 def CMNzrsr : AI1<0b1011, (outs),
4123 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4124 "cmn", "\t$Rn, $shift",
4125 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4126 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4127 Sched<[WriteCMPsr, ReadALU]> {
4132 let Inst{19-16} = Rn;
4133 let Inst{15-12} = 0b0000;
4134 let Inst{11-8} = shift{11-8};
4136 let Inst{6-5} = shift{6-5};
4138 let Inst{3-0} = shift{3-0};
4140 let Unpredictable{15-12} = 0b1111;
4145 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4146 (CMNri GPR:$src, so_imm_neg:$imm)>;
4148 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4149 (CMNri GPR:$src, so_imm_neg:$imm)>;
4151 // Note that TST/TEQ don't set all the same flags that CMP does!
4152 defm TST : AI1_cmp_irs<0b1000, "tst",
4153 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4154 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4155 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4156 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4157 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4159 // Pseudo i64 compares for some floating point compares.
4160 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4162 def BCCi64 : PseudoInst<(outs),
4163 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4165 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4168 def BCCZi64 : PseudoInst<(outs),
4169 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4170 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4172 } // usesCustomInserter
4175 // Conditional moves
4176 let neverHasSideEffects = 1 in {
4178 let isCommutable = 1, isSelect = 1 in
4179 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4180 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4182 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4184 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4186 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4187 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4190 (ARMcmov GPR:$false, so_reg_imm:$shift,
4192 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4193 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4194 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4196 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4198 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4201 let isMoveImm = 1 in
4203 : ARMPseudoInst<(outs GPR:$Rd),
4204 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4206 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4208 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4211 let isMoveImm = 1 in
4212 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4213 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4215 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm,
4217 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4219 // Two instruction predicate mov immediate.
4220 let isMoveImm = 1 in
4222 : ARMPseudoInst<(outs GPR:$Rd),
4223 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4225 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4227 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4229 let isMoveImm = 1 in
4230 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4231 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4233 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm,
4235 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4237 } // neverHasSideEffects
4240 //===----------------------------------------------------------------------===//
4241 // Atomic operations intrinsics
4244 def MemBarrierOptOperand : AsmOperandClass {
4245 let Name = "MemBarrierOpt";
4246 let ParserMethod = "parseMemBarrierOptOperand";
4248 def memb_opt : Operand<i32> {
4249 let PrintMethod = "printMemBOption";
4250 let ParserMatchClass = MemBarrierOptOperand;
4251 let DecoderMethod = "DecodeMemBarrierOption";
4254 def InstSyncBarrierOptOperand : AsmOperandClass {
4255 let Name = "InstSyncBarrierOpt";
4256 let ParserMethod = "parseInstSyncBarrierOptOperand";
4258 def instsyncb_opt : Operand<i32> {
4259 let PrintMethod = "printInstSyncBOption";
4260 let ParserMatchClass = InstSyncBarrierOptOperand;
4261 let DecoderMethod = "DecodeInstSyncBarrierOption";
4264 // memory barriers protect the atomic sequences
4265 let hasSideEffects = 1 in {
4266 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4267 "dmb", "\t$opt", [(int_arm_dmb (i32 imm0_15:$opt))]>,
4268 Requires<[IsARM, HasDB]> {
4270 let Inst{31-4} = 0xf57ff05;
4271 let Inst{3-0} = opt;
4275 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4276 "dsb", "\t$opt", [(int_arm_dsb (i32 imm0_15:$opt))]>,
4277 Requires<[IsARM, HasDB]> {
4279 let Inst{31-4} = 0xf57ff04;
4280 let Inst{3-0} = opt;
4283 // ISB has only full system option
4284 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4285 "isb", "\t$opt", []>,
4286 Requires<[IsARM, HasDB]> {
4288 let Inst{31-4} = 0xf57ff06;
4289 let Inst{3-0} = opt;
4292 let usesCustomInserter = 1, Defs = [CPSR] in {
4294 // Pseudo instruction that combines movs + predicated rsbmi
4295 // to implement integer ABS
4296 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4298 // Atomic pseudo-insts which will be lowered to ldrex/strex loops.
4299 // (64-bit pseudos use a hand-written selection code).
4300 let mayLoad = 1, mayStore = 1 in {
4301 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4303 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4305 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4307 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4309 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4311 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4313 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4315 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4317 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4319 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4321 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4323 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4325 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4327 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4329 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4331 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4333 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4335 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4337 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4339 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4341 def ATOMIC_SWAP_I8 : PseudoInst<
4343 (ins GPR:$ptr, GPR:$new, i32imm:$ordering),
4345 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4347 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering),
4349 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4351 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4353 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4355 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4357 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4359 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4361 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4363 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4365 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4367 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4369 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4371 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4373 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4375 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4377 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4379 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4381 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4383 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4385 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4387 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4389 def ATOMIC_SWAP_I16 : PseudoInst<
4391 (ins GPR:$ptr, GPR:$new, i32imm:$ordering),
4393 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4395 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering),
4397 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4399 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4401 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4403 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4405 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4407 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4409 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4411 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4413 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4415 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4417 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4419 (ins GPR:$ptr, GPR:$incr, i32imm:$ordering),
4421 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4423 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4425 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4427 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4429 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4431 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4433 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4435 (ins GPR:$ptr, GPR:$val, i32imm:$ordering),
4437 def ATOMIC_SWAP_I32 : PseudoInst<
4439 (ins GPR:$ptr, GPR:$new, i32imm:$ordering),
4441 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4443 (ins GPR:$ptr, GPR:$old, GPR:$new, i32imm:$ordering),
4445 def ATOMIC_LOAD_ADD_I64 : PseudoInst<
4446 (outs GPR:$dst1, GPR:$dst2),
4447 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4449 def ATOMIC_LOAD_SUB_I64 : PseudoInst<
4450 (outs GPR:$dst1, GPR:$dst2),
4451 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4453 def ATOMIC_LOAD_AND_I64 : PseudoInst<
4454 (outs GPR:$dst1, GPR:$dst2),
4455 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4457 def ATOMIC_LOAD_OR_I64 : PseudoInst<
4458 (outs GPR:$dst1, GPR:$dst2),
4459 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4461 def ATOMIC_LOAD_XOR_I64 : PseudoInst<
4462 (outs GPR:$dst1, GPR:$dst2),
4463 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4465 def ATOMIC_LOAD_NAND_I64 : PseudoInst<
4466 (outs GPR:$dst1, GPR:$dst2),
4467 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4469 def ATOMIC_LOAD_MIN_I64 : PseudoInst<
4470 (outs GPR:$dst1, GPR:$dst2),
4471 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4473 def ATOMIC_LOAD_MAX_I64 : PseudoInst<
4474 (outs GPR:$dst1, GPR:$dst2),
4475 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4477 def ATOMIC_LOAD_UMIN_I64 : PseudoInst<
4478 (outs GPR:$dst1, GPR:$dst2),
4479 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4481 def ATOMIC_LOAD_UMAX_I64 : PseudoInst<
4482 (outs GPR:$dst1, GPR:$dst2),
4483 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4485 def ATOMIC_SWAP_I64 : PseudoInst<
4486 (outs GPR:$dst1, GPR:$dst2),
4487 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4489 def ATOMIC_CMP_SWAP_I64 : PseudoInst<
4490 (outs GPR:$dst1, GPR:$dst2),
4491 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
4492 GPR:$set1, GPR:$set2, i32imm:$ordering),
4496 def ATOMIC_LOAD_I64 : PseudoInst<
4497 (outs GPR:$dst1, GPR:$dst2),
4498 (ins GPR:$addr, i32imm:$ordering),
4501 def ATOMIC_STORE_I64 : PseudoInst<
4502 (outs GPR:$dst1, GPR:$dst2),
4503 (ins GPR:$addr, GPR:$src1, GPR:$src2, i32imm:$ordering),
4507 let usesCustomInserter = 1 in {
4508 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4509 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4511 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4514 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4515 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4518 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4519 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4522 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4523 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4526 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4527 (int_arm_strex node:$val, node:$ptr), [{
4528 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4531 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4532 (int_arm_strex node:$val, node:$ptr), [{
4533 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4536 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4537 (int_arm_strex node:$val, node:$ptr), [{
4538 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4541 let mayLoad = 1 in {
4542 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4543 NoItinerary, "ldrexb", "\t$Rt, $addr",
4544 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4545 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4546 NoItinerary, "ldrexh", "\t$Rt, $addr",
4547 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4548 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4549 NoItinerary, "ldrex", "\t$Rt, $addr",
4550 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4551 let hasExtraDefRegAllocReq = 1 in
4552 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4553 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4554 let DecoderMethod = "DecodeDoubleRegLoad";
4557 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4558 NoItinerary, "ldaexb", "\t$Rt, $addr", []>;
4559 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4560 NoItinerary, "ldaexh", "\t$Rt, $addr", []>;
4561 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4562 NoItinerary, "ldaex", "\t$Rt, $addr", []>;
4563 let hasExtraDefRegAllocReq = 1 in
4564 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4565 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4566 let DecoderMethod = "DecodeDoubleRegLoad";
4570 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4571 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4572 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4573 [(set GPR:$Rd, (strex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4574 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4575 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4576 [(set GPR:$Rd, (strex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4577 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4578 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4579 [(set GPR:$Rd, (strex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4580 let hasExtraSrcRegAllocReq = 1 in
4581 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4582 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4583 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4584 let DecoderMethod = "DecodeDoubleRegStore";
4586 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4587 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4589 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4590 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4592 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4593 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4595 let hasExtraSrcRegAllocReq = 1 in
4596 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4597 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4598 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4599 let DecoderMethod = "DecodeDoubleRegStore";
4603 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4605 Requires<[IsARM, HasV7]> {
4606 let Inst{31-0} = 0b11110101011111111111000000011111;
4609 def : ARMPat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
4610 (LDREXB addr_offset_none:$addr)>;
4611 def : ARMPat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
4612 (LDREXH addr_offset_none:$addr)>;
4613 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4614 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4615 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4616 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4618 class acquiring_load<PatFrag base>
4619 : PatFrag<(ops node:$ptr), (base node:$ptr), [{
4620 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4621 return Ordering == Acquire || Ordering == SequentiallyConsistent;
4624 def atomic_load_acquire_8 : acquiring_load<atomic_load_8>;
4625 def atomic_load_acquire_16 : acquiring_load<atomic_load_16>;
4626 def atomic_load_acquire_32 : acquiring_load<atomic_load_32>;
4628 class releasing_store<PatFrag base>
4629 : PatFrag<(ops node:$ptr, node:$val), (base node:$ptr, node:$val), [{
4630 AtomicOrdering Ordering = cast<AtomicSDNode>(N)->getOrdering();
4631 return Ordering == Release || Ordering == SequentiallyConsistent;
4634 def atomic_store_release_8 : releasing_store<atomic_store_8>;
4635 def atomic_store_release_16 : releasing_store<atomic_store_16>;
4636 def atomic_store_release_32 : releasing_store<atomic_store_32>;
4638 let AddedComplexity = 8 in {
4639 def : ARMPat<(atomic_load_acquire_8 addr_offset_none:$addr), (LDAB addr_offset_none:$addr)>;
4640 def : ARMPat<(atomic_load_acquire_16 addr_offset_none:$addr), (LDAH addr_offset_none:$addr)>;
4641 def : ARMPat<(atomic_load_acquire_32 addr_offset_none:$addr), (LDA addr_offset_none:$addr)>;
4642 def : ARMPat<(atomic_store_release_8 addr_offset_none:$addr, GPR:$val), (STLB GPR:$val, addr_offset_none:$addr)>;
4643 def : ARMPat<(atomic_store_release_16 addr_offset_none:$addr, GPR:$val), (STLH GPR:$val, addr_offset_none:$addr)>;
4644 def : ARMPat<(atomic_store_release_32 addr_offset_none:$addr, GPR:$val), (STL GPR:$val, addr_offset_none:$addr)>;
4647 // SWP/SWPB are deprecated in V6/V7.
4648 let mayLoad = 1, mayStore = 1 in {
4649 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4650 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4652 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4653 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4657 //===----------------------------------------------------------------------===//
4658 // Coprocessor Instructions.
4661 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4662 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4663 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4664 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4665 imm:$CRm, imm:$opc2)]> {
4673 let Inst{3-0} = CRm;
4675 let Inst{7-5} = opc2;
4676 let Inst{11-8} = cop;
4677 let Inst{15-12} = CRd;
4678 let Inst{19-16} = CRn;
4679 let Inst{23-20} = opc1;
4682 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4683 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4684 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4685 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4686 imm:$CRm, imm:$opc2)]> {
4687 let Inst{31-28} = 0b1111;
4695 let Inst{3-0} = CRm;
4697 let Inst{7-5} = opc2;
4698 let Inst{11-8} = cop;
4699 let Inst{15-12} = CRd;
4700 let Inst{19-16} = CRn;
4701 let Inst{23-20} = opc1;
4704 class ACI<dag oops, dag iops, string opc, string asm,
4705 IndexMode im = IndexModeNone>
4706 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4708 let Inst{27-25} = 0b110;
4710 class ACInoP<dag oops, dag iops, string opc, string asm,
4711 IndexMode im = IndexModeNone>
4712 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4714 let Inst{31-28} = 0b1111;
4715 let Inst{27-25} = 0b110;
4717 multiclass LdStCop<bit load, bit Dbit, string asm> {
4718 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4719 asm, "\t$cop, $CRd, $addr"> {
4723 let Inst{24} = 1; // P = 1
4724 let Inst{23} = addr{8};
4725 let Inst{22} = Dbit;
4726 let Inst{21} = 0; // W = 0
4727 let Inst{20} = load;
4728 let Inst{19-16} = addr{12-9};
4729 let Inst{15-12} = CRd;
4730 let Inst{11-8} = cop;
4731 let Inst{7-0} = addr{7-0};
4732 let DecoderMethod = "DecodeCopMemInstruction";
4734 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4735 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4739 let Inst{24} = 1; // P = 1
4740 let Inst{23} = addr{8};
4741 let Inst{22} = Dbit;
4742 let Inst{21} = 1; // W = 1
4743 let Inst{20} = load;
4744 let Inst{19-16} = addr{12-9};
4745 let Inst{15-12} = CRd;
4746 let Inst{11-8} = cop;
4747 let Inst{7-0} = addr{7-0};
4748 let DecoderMethod = "DecodeCopMemInstruction";
4750 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4751 postidx_imm8s4:$offset),
4752 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4757 let Inst{24} = 0; // P = 0
4758 let Inst{23} = offset{8};
4759 let Inst{22} = Dbit;
4760 let Inst{21} = 1; // W = 1
4761 let Inst{20} = load;
4762 let Inst{19-16} = addr;
4763 let Inst{15-12} = CRd;
4764 let Inst{11-8} = cop;
4765 let Inst{7-0} = offset{7-0};
4766 let DecoderMethod = "DecodeCopMemInstruction";
4768 def _OPTION : ACI<(outs),
4769 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4770 coproc_option_imm:$option),
4771 asm, "\t$cop, $CRd, $addr, $option"> {
4776 let Inst{24} = 0; // P = 0
4777 let Inst{23} = 1; // U = 1
4778 let Inst{22} = Dbit;
4779 let Inst{21} = 0; // W = 0
4780 let Inst{20} = load;
4781 let Inst{19-16} = addr;
4782 let Inst{15-12} = CRd;
4783 let Inst{11-8} = cop;
4784 let Inst{7-0} = option;
4785 let DecoderMethod = "DecodeCopMemInstruction";
4788 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4789 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4790 asm, "\t$cop, $CRd, $addr"> {
4794 let Inst{24} = 1; // P = 1
4795 let Inst{23} = addr{8};
4796 let Inst{22} = Dbit;
4797 let Inst{21} = 0; // W = 0
4798 let Inst{20} = load;
4799 let Inst{19-16} = addr{12-9};
4800 let Inst{15-12} = CRd;
4801 let Inst{11-8} = cop;
4802 let Inst{7-0} = addr{7-0};
4803 let DecoderMethod = "DecodeCopMemInstruction";
4805 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4806 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4810 let Inst{24} = 1; // P = 1
4811 let Inst{23} = addr{8};
4812 let Inst{22} = Dbit;
4813 let Inst{21} = 1; // W = 1
4814 let Inst{20} = load;
4815 let Inst{19-16} = addr{12-9};
4816 let Inst{15-12} = CRd;
4817 let Inst{11-8} = cop;
4818 let Inst{7-0} = addr{7-0};
4819 let DecoderMethod = "DecodeCopMemInstruction";
4821 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4822 postidx_imm8s4:$offset),
4823 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4828 let Inst{24} = 0; // P = 0
4829 let Inst{23} = offset{8};
4830 let Inst{22} = Dbit;
4831 let Inst{21} = 1; // W = 1
4832 let Inst{20} = load;
4833 let Inst{19-16} = addr;
4834 let Inst{15-12} = CRd;
4835 let Inst{11-8} = cop;
4836 let Inst{7-0} = offset{7-0};
4837 let DecoderMethod = "DecodeCopMemInstruction";
4839 def _OPTION : ACInoP<(outs),
4840 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4841 coproc_option_imm:$option),
4842 asm, "\t$cop, $CRd, $addr, $option"> {
4847 let Inst{24} = 0; // P = 0
4848 let Inst{23} = 1; // U = 1
4849 let Inst{22} = Dbit;
4850 let Inst{21} = 0; // W = 0
4851 let Inst{20} = load;
4852 let Inst{19-16} = addr;
4853 let Inst{15-12} = CRd;
4854 let Inst{11-8} = cop;
4855 let Inst{7-0} = option;
4856 let DecoderMethod = "DecodeCopMemInstruction";
4860 defm LDC : LdStCop <1, 0, "ldc">;
4861 defm LDCL : LdStCop <1, 1, "ldcl">;
4862 defm STC : LdStCop <0, 0, "stc">;
4863 defm STCL : LdStCop <0, 1, "stcl">;
4864 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4865 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4866 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4867 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4869 //===----------------------------------------------------------------------===//
4870 // Move between coprocessor and ARM core register.
4873 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4875 : ABI<0b1110, oops, iops, NoItinerary, opc,
4876 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4877 let Inst{20} = direction;
4887 let Inst{15-12} = Rt;
4888 let Inst{11-8} = cop;
4889 let Inst{23-21} = opc1;
4890 let Inst{7-5} = opc2;
4891 let Inst{3-0} = CRm;
4892 let Inst{19-16} = CRn;
4895 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4897 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4898 c_imm:$CRm, imm0_7:$opc2),
4899 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4900 imm:$CRm, imm:$opc2)]>,
4901 ComplexDeprecationPredicate<"MCR">;
4902 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4903 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4904 c_imm:$CRm, 0, pred:$p)>;
4905 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4906 (outs GPRwithAPSR:$Rt),
4907 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4909 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4910 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4911 c_imm:$CRm, 0, pred:$p)>;
4913 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4914 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4916 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4918 : ABXI<0b1110, oops, iops, NoItinerary,
4919 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4920 let Inst{31-24} = 0b11111110;
4921 let Inst{20} = direction;
4931 let Inst{15-12} = Rt;
4932 let Inst{11-8} = cop;
4933 let Inst{23-21} = opc1;
4934 let Inst{7-5} = opc2;
4935 let Inst{3-0} = CRm;
4936 let Inst{19-16} = CRn;
4939 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4941 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4942 c_imm:$CRm, imm0_7:$opc2),
4943 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4944 imm:$CRm, imm:$opc2)]>;
4945 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4946 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4948 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4949 (outs GPRwithAPSR:$Rt),
4950 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4952 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4953 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4956 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4957 imm:$CRm, imm:$opc2),
4958 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4960 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4961 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4962 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4963 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4964 let Inst{23-21} = 0b010;
4965 let Inst{20} = direction;
4973 let Inst{15-12} = Rt;
4974 let Inst{19-16} = Rt2;
4975 let Inst{11-8} = cop;
4976 let Inst{7-4} = opc1;
4977 let Inst{3-0} = CRm;
4980 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4981 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4982 GPRnopc:$Rt2, imm:$CRm)]>;
4983 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4985 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4986 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4987 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4988 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4989 let Inst{31-28} = 0b1111;
4990 let Inst{23-21} = 0b010;
4991 let Inst{20} = direction;
4999 let Inst{15-12} = Rt;
5000 let Inst{19-16} = Rt2;
5001 let Inst{11-8} = cop;
5002 let Inst{7-4} = opc1;
5003 let Inst{3-0} = CRm;
5005 let DecoderMethod = "DecodeMRRC2";
5008 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
5009 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
5010 GPRnopc:$Rt2, imm:$CRm)]>;
5011 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
5013 //===----------------------------------------------------------------------===//
5014 // Move between special register and ARM core register
5017 // Move to ARM core register from Special Register
5018 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5019 "mrs", "\t$Rd, apsr", []> {
5021 let Inst{23-16} = 0b00001111;
5022 let Unpredictable{19-17} = 0b111;
5024 let Inst{15-12} = Rd;
5026 let Inst{11-0} = 0b000000000000;
5027 let Unpredictable{11-0} = 0b110100001111;
5030 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
5033 // The MRSsys instruction is the MRS instruction from the ARM ARM,
5034 // section B9.3.9, with the R bit set to 1.
5035 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
5036 "mrs", "\t$Rd, spsr", []> {
5038 let Inst{23-16} = 0b01001111;
5039 let Unpredictable{19-16} = 0b1111;
5041 let Inst{15-12} = Rd;
5043 let Inst{11-0} = 0b000000000000;
5044 let Unpredictable{11-0} = 0b110100001111;
5047 // Move from ARM core register to Special Register
5049 // No need to have both system and application versions, the encodings are the
5050 // same and the assembly parser has no way to distinguish between them. The mask
5051 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
5052 // the mask with the fields to be accessed in the special register.
5053 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5054 "msr", "\t$mask, $Rn", []> {
5059 let Inst{22} = mask{4}; // R bit
5060 let Inst{21-20} = 0b10;
5061 let Inst{19-16} = mask{3-0};
5062 let Inst{15-12} = 0b1111;
5063 let Inst{11-4} = 0b00000000;
5067 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
5068 "msr", "\t$mask, $a", []> {
5073 let Inst{22} = mask{4}; // R bit
5074 let Inst{21-20} = 0b10;
5075 let Inst{19-16} = mask{3-0};
5076 let Inst{15-12} = 0b1111;
5080 //===----------------------------------------------------------------------===//
5084 // __aeabi_read_tp preserves the registers r1-r3.
5085 // This is a pseudo inst so that we can get the encoding right,
5086 // complete with fixup for the aeabi_read_tp function.
5088 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
5089 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
5090 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
5093 //===----------------------------------------------------------------------===//
5094 // SJLJ Exception handling intrinsics
5095 // eh_sjlj_setjmp() is an instruction sequence to store the return
5096 // address and save #0 in R0 for the non-longjmp case.
5097 // Since by its nature we may be coming from some other function to get
5098 // here, and we're using the stack frame for the containing function to
5099 // save/restore registers, we can't keep anything live in regs across
5100 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
5101 // when we get here from a longjmp(). We force everything out of registers
5102 // except for our own input by listing the relevant registers in Defs. By
5103 // doing so, we also cause the prologue/epilogue code to actively preserve
5104 // all of the callee-saved resgisters, which is exactly what we want.
5105 // A constant value is passed in $val, and we use the location as a scratch.
5107 // These are pseudo-instructions and are lowered to individual MC-insts, so
5108 // no encoding information is necessary.
5110 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
5111 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
5112 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5113 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5115 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5116 Requires<[IsARM, HasVFP2]>;
5120 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
5121 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
5122 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5124 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5125 Requires<[IsARM, NoVFP]>;
5128 // FIXME: Non-IOS version(s)
5129 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5130 Defs = [ R7, LR, SP ] in {
5131 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5133 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5134 Requires<[IsARM, IsIOS]>;
5137 // eh.sjlj.dispatchsetup pseudo-instruction.
5138 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5139 // the pseudo is expanded (which happens before any passes that need the
5140 // instruction size).
5141 let isBarrier = 1 in
5142 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5145 //===----------------------------------------------------------------------===//
5146 // Non-Instruction Patterns
5149 // ARMv4 indirect branch using (MOVr PC, dst)
5150 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5151 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5152 4, IIC_Br, [(brind GPR:$dst)],
5153 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5154 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5156 // Large immediate handling.
5158 // 32-bit immediate using two piece so_imms or movw + movt.
5159 // This is a single pseudo instruction, the benefit is that it can be remat'd
5160 // as a single unit instead of having to handle reg inputs.
5161 // FIXME: Remove this when we can do generalized remat.
5162 let isReMaterializable = 1, isMoveImm = 1 in
5163 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5164 [(set GPR:$dst, (arm_i32imm:$src))]>,
5167 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5168 // It also makes it possible to rematerialize the instructions.
5169 // FIXME: Remove this when we can do generalized remat and when machine licm
5170 // can properly the instructions.
5171 let isReMaterializable = 1 in {
5172 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5174 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5175 Requires<[IsARM, UseMovt]>;
5177 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5179 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
5180 Requires<[IsARM, UseMovt]>;
5182 let AddedComplexity = 10 in
5183 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5185 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5186 Requires<[IsARM, UseMovt]>;
5187 } // isReMaterializable
5189 // ConstantPool, GlobalAddress, and JumpTable
5190 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
5191 Requires<[IsARM, DontUseMovt]>;
5192 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5193 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5194 Requires<[IsARM, UseMovt]>;
5195 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
5196 (LEApcrelJT tjumptable:$dst, imm:$id)>;
5198 // TODO: add,sub,and, 3-instr forms?
5200 // Tail calls. These patterns also apply to Thumb mode.
5201 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5202 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5203 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5206 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5207 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5208 (BMOVPCB_CALL texternalsym:$func)>;
5210 // zextload i1 -> zextload i8
5211 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5212 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5214 // extload -> zextload
5215 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5216 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5217 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5218 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5220 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5222 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5223 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5226 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5227 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5228 (SMULBB GPR:$a, GPR:$b)>;
5229 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5230 (SMULBB GPR:$a, GPR:$b)>;
5231 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5232 (sra GPR:$b, (i32 16))),
5233 (SMULBT GPR:$a, GPR:$b)>;
5234 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5235 (SMULBT GPR:$a, GPR:$b)>;
5236 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5237 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5238 (SMULTB GPR:$a, GPR:$b)>;
5239 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5240 (SMULTB GPR:$a, GPR:$b)>;
5241 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5243 (SMULWB GPR:$a, GPR:$b)>;
5244 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
5245 (SMULWB GPR:$a, GPR:$b)>;
5247 def : ARMV5MOPat<(add GPR:$acc,
5248 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5249 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5250 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5251 def : ARMV5MOPat<(add GPR:$acc,
5252 (mul sext_16_node:$a, sext_16_node:$b)),
5253 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5254 def : ARMV5MOPat<(add GPR:$acc,
5255 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5256 (sra GPR:$b, (i32 16)))),
5257 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5258 def : ARMV5MOPat<(add GPR:$acc,
5259 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5260 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5261 def : ARMV5MOPat<(add GPR:$acc,
5262 (mul (sra GPR:$a, (i32 16)),
5263 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5264 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5265 def : ARMV5MOPat<(add GPR:$acc,
5266 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5267 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5268 def : ARMV5MOPat<(add GPR:$acc,
5269 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5271 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5272 def : ARMV5MOPat<(add GPR:$acc,
5273 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
5274 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5277 // Pre-v7 uses MCR for synchronization barriers.
5278 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5279 Requires<[IsARM, HasV6]>;
5281 // SXT/UXT with no rotate
5282 let AddedComplexity = 16 in {
5283 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5284 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5285 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5286 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5287 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5288 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5289 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5292 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5293 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5295 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5296 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5297 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5298 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5300 // Atomic load/store patterns
5301 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5302 (LDRBrs ldst_so_reg:$src)>;
5303 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5304 (LDRBi12 addrmode_imm12:$src)>;
5305 def : ARMPat<(atomic_load_16 addrmode3:$src),
5306 (LDRH addrmode3:$src)>;
5307 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5308 (LDRrs ldst_so_reg:$src)>;
5309 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5310 (LDRi12 addrmode_imm12:$src)>;
5311 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5312 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5313 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5314 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5315 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5316 (STRH GPR:$val, addrmode3:$ptr)>;
5317 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5318 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5319 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5320 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5323 //===----------------------------------------------------------------------===//
5327 include "ARMInstrThumb.td"
5329 //===----------------------------------------------------------------------===//
5333 include "ARMInstrThumb2.td"
5335 //===----------------------------------------------------------------------===//
5336 // Floating Point Support
5339 include "ARMInstrVFP.td"
5341 //===----------------------------------------------------------------------===//
5342 // Advanced SIMD (NEON) Support
5345 include "ARMInstrNEON.td"
5347 //===----------------------------------------------------------------------===//
5348 // Assembler aliases
5352 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5353 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5354 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5356 // System instructions
5357 def : MnemonicAlias<"swi", "svc">;
5359 // Load / Store Multiple
5360 def : MnemonicAlias<"ldmfd", "ldm">;
5361 def : MnemonicAlias<"ldmia", "ldm">;
5362 def : MnemonicAlias<"ldmea", "ldmdb">;
5363 def : MnemonicAlias<"stmfd", "stmdb">;
5364 def : MnemonicAlias<"stmia", "stm">;
5365 def : MnemonicAlias<"stmea", "stm">;
5367 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5368 // shift amount is zero (i.e., unspecified).
5369 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5370 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5371 Requires<[IsARM, HasV6]>;
5372 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5373 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5374 Requires<[IsARM, HasV6]>;
5376 // PUSH/POP aliases for STM/LDM
5377 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5378 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5380 // SSAT/USAT optional shift operand.
5381 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5382 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5383 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5384 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5387 // Extend instruction optional rotate operand.
5388 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5389 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5390 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5391 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5392 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5393 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5394 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5395 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5396 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5397 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5398 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5399 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5401 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5402 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5403 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5404 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5405 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5406 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5407 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5408 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5409 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5410 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5411 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5412 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5416 def : MnemonicAlias<"rfefa", "rfeda">;
5417 def : MnemonicAlias<"rfeea", "rfedb">;
5418 def : MnemonicAlias<"rfefd", "rfeia">;
5419 def : MnemonicAlias<"rfeed", "rfeib">;
5420 def : MnemonicAlias<"rfe", "rfeia">;
5423 def : MnemonicAlias<"srsfa", "srsib">;
5424 def : MnemonicAlias<"srsea", "srsia">;
5425 def : MnemonicAlias<"srsfd", "srsdb">;
5426 def : MnemonicAlias<"srsed", "srsda">;
5427 def : MnemonicAlias<"srs", "srsia">;
5430 def : MnemonicAlias<"qsubaddx", "qsax">;
5432 def : MnemonicAlias<"saddsubx", "sasx">;
5433 // SHASX == SHADDSUBX
5434 def : MnemonicAlias<"shaddsubx", "shasx">;
5435 // SHSAX == SHSUBADDX
5436 def : MnemonicAlias<"shsubaddx", "shsax">;
5438 def : MnemonicAlias<"ssubaddx", "ssax">;
5440 def : MnemonicAlias<"uaddsubx", "uasx">;
5441 // UHASX == UHADDSUBX
5442 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5443 // UHSAX == UHSUBADDX
5444 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5445 // UQASX == UQADDSUBX
5446 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5447 // UQSAX == UQSUBADDX
5448 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5450 def : MnemonicAlias<"usubaddx", "usax">;
5452 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5454 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5455 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5456 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5457 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5458 // Same for AND <--> BIC
5459 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5460 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5461 pred:$p, cc_out:$s)>;
5462 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5463 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5464 pred:$p, cc_out:$s)>;
5465 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5466 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5467 pred:$p, cc_out:$s)>;
5468 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5469 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5470 pred:$p, cc_out:$s)>;
5472 // Likewise, "add Rd, so_imm_neg" -> sub
5473 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5474 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5475 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5476 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5477 // Same for CMP <--> CMN via so_imm_neg
5478 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5479 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5480 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5481 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5483 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5484 // LSR, ROR, and RRX instructions.
5485 // FIXME: We need C++ parser hooks to map the alias to the MOV
5486 // encoding. It seems we should be able to do that sort of thing
5487 // in tblgen, but it could get ugly.
5488 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5489 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5490 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5492 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5493 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5495 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5496 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5498 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5499 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5502 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5503 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5504 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5505 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5506 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5508 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5509 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5511 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5512 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5514 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5515 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5519 // "neg" is and alias for "rsb rd, rn, #0"
5520 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5521 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5523 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5524 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5525 Requires<[IsARM, NoV6]>;
5527 // UMULL/SMULL are available on all arches, but the instruction definitions
5528 // need difference constraints pre-v6. Use these aliases for the assembly
5529 // parsing on pre-v6.
5530 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5531 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5532 Requires<[IsARM, NoV6]>;
5533 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5534 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5535 Requires<[IsARM, NoV6]>;
5537 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5539 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>,
5540 ComplexDeprecationPredicate<"IT">;