1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
153 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
154 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
155 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
156 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
157 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
158 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
159 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
160 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
162 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
164 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
166 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
167 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
168 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
169 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
170 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
171 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
172 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
173 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
175 // FIXME: Eventually this will be just "hasV6T2Ops".
176 def UseMovt : Predicate<"Subtarget->useMovt()">;
177 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
178 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
180 //===----------------------------------------------------------------------===//
181 // ARM Flag Definitions.
183 class RegConstraint<string C> {
184 string Constraints = C;
187 //===----------------------------------------------------------------------===//
188 // ARM specific transformation functions and pattern fragments.
191 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
192 // so_imm_neg def below.
193 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
194 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
197 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
198 // so_imm_not def below.
199 def so_imm_not_XFORM : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
203 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
204 def imm1_15 : PatLeaf<(i32 imm), [{
205 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
208 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
209 def imm16_31 : PatLeaf<(i32 imm), [{
210 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
215 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
216 }], so_imm_neg_XFORM>;
220 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
221 }], so_imm_not_XFORM>;
223 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
224 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
225 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
228 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
230 def bf_inv_mask_imm : Operand<i32>,
232 return ARM::isBitFieldInvertedMask(N->getZExtValue());
234 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
235 let PrintMethod = "printBitfieldInvMaskImmOperand";
238 /// Split a 32-bit immediate into two 16 bit parts.
239 def hi16 : SDNodeXForm<imm, [{
240 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
243 def lo16AllZero : PatLeaf<(i32 imm), [{
244 // Returns true if all low 16-bits are 0.
245 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
248 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
250 def imm0_65535 : PatLeaf<(i32 imm), [{
251 return (uint32_t)N->getZExtValue() < 65536;
254 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
255 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
257 /// adde and sube predicates - True based on whether the carry flag output
258 /// will be needed or not.
259 def adde_dead_carry :
260 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
261 [{return !N->hasAnyUseOfValue(1);}]>;
262 def sube_dead_carry :
263 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
264 [{return !N->hasAnyUseOfValue(1);}]>;
265 def adde_live_carry :
266 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
267 [{return N->hasAnyUseOfValue(1);}]>;
268 def sube_live_carry :
269 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
270 [{return N->hasAnyUseOfValue(1);}]>;
272 // An 'and' node with a single use.
273 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
274 return N->hasOneUse();
277 // An 'xor' node with a single use.
278 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
279 return N->hasOneUse();
282 //===----------------------------------------------------------------------===//
283 // Operand Definitions.
287 def brtarget : Operand<OtherVT> {
288 let EncoderMethod = "getBranchTargetOpValue";
292 def bltarget : Operand<i32> {
293 // Encoded the same as branch targets.
294 let EncoderMethod = "getBranchTargetOpValue";
297 // A list of registers separated by comma. Used by load/store multiple.
298 def RegListAsmOperand : AsmOperandClass {
299 let Name = "RegList";
300 let SuperClasses = [];
303 def DPRRegListAsmOperand : AsmOperandClass {
304 let Name = "DPRRegList";
305 let SuperClasses = [];
308 def SPRRegListAsmOperand : AsmOperandClass {
309 let Name = "SPRRegList";
310 let SuperClasses = [];
313 def reglist : Operand<i32> {
314 let EncoderMethod = "getRegisterListOpValue";
315 let ParserMatchClass = RegListAsmOperand;
316 let PrintMethod = "printRegisterList";
319 def dpr_reglist : Operand<i32> {
320 let EncoderMethod = "getRegisterListOpValue";
321 let ParserMatchClass = DPRRegListAsmOperand;
322 let PrintMethod = "printRegisterList";
325 def spr_reglist : Operand<i32> {
326 let EncoderMethod = "getRegisterListOpValue";
327 let ParserMatchClass = SPRRegListAsmOperand;
328 let PrintMethod = "printRegisterList";
331 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
332 def cpinst_operand : Operand<i32> {
333 let PrintMethod = "printCPInstOperand";
337 def pclabel : Operand<i32> {
338 let PrintMethod = "printPCLabel";
341 def neon_vcvt_imm32 : Operand<i32> {
342 let EncoderMethod = "getNEONVcvtImm32OpValue";
345 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
346 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
347 int32_t v = (int32_t)N->getZExtValue();
348 return v == 8 || v == 16 || v == 24; }]> {
349 let EncoderMethod = "getRotImmOpValue";
352 // shift_imm: An integer that encodes a shift amount and the type of shift
353 // (currently either asr or lsl) using the same encoding used for the
354 // immediates in so_reg operands.
355 def shift_imm : Operand<i32> {
356 let PrintMethod = "printShiftImmOperand";
359 // shifter_operand operands: so_reg and so_imm.
360 def so_reg : Operand<i32>, // reg reg imm
361 ComplexPattern<i32, 3, "SelectShifterOperandReg",
362 [shl,srl,sra,rotr]> {
363 let EncoderMethod = "getSORegOpValue";
364 let PrintMethod = "printSORegOperand";
365 let MIOperandInfo = (ops GPR, GPR, i32imm);
367 def shift_so_reg : Operand<i32>, // reg reg imm
368 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
369 [shl,srl,sra,rotr]> {
370 let EncoderMethod = "getSORegOpValue";
371 let PrintMethod = "printSORegOperand";
372 let MIOperandInfo = (ops GPR, GPR, i32imm);
375 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
376 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
377 // represented in the imm field in the same 12-bit form that they are encoded
378 // into so_imm instructions: the 8-bit immediate is the least significant bits
379 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
380 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
381 let EncoderMethod = "getSOImmOpValue";
382 let PrintMethod = "printSOImmOperand";
385 // Break so_imm's up into two pieces. This handles immediates with up to 16
386 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
387 // get the first/second pieces.
388 def so_imm2part : PatLeaf<(imm), [{
389 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
392 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
394 def arm_i32imm : PatLeaf<(imm), [{
395 if (Subtarget->hasV6T2Ops())
397 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
400 def so_imm2part_1 : SDNodeXForm<imm, [{
401 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
402 return CurDAG->getTargetConstant(V, MVT::i32);
405 def so_imm2part_2 : SDNodeXForm<imm, [{
406 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
407 return CurDAG->getTargetConstant(V, MVT::i32);
410 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
411 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
413 let PrintMethod = "printSOImm2PartOperand";
416 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
417 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
418 return CurDAG->getTargetConstant(V, MVT::i32);
421 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
422 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
423 return CurDAG->getTargetConstant(V, MVT::i32);
426 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
427 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
428 return (int32_t)N->getZExtValue() < 32;
431 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
432 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
433 return (int32_t)N->getZExtValue() < 32;
435 let EncoderMethod = "getImmMinusOneOpValue";
438 // For movt/movw - sets the MC Encoder method.
439 // The imm is split into imm{15-12}, imm{11-0}
441 def movt_imm : Operand<i32> {
442 let EncoderMethod = "getMovtImmOpValue";
445 // Define ARM specific addressing modes.
448 // addrmode_imm12 := reg +/- imm12
450 def addrmode_imm12 : Operand<i32>,
451 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
452 // 12-bit immediate operand. Note that instructions using this encode
453 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
454 // immediate values are as normal.
456 let EncoderMethod = "getAddrModeImm12OpValue";
457 let PrintMethod = "printAddrModeImm12Operand";
458 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
460 // ldst_so_reg := reg +/- reg shop imm
462 def ldst_so_reg : Operand<i32>,
463 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
464 let EncoderMethod = "getLdStSORegOpValue";
465 // FIXME: Simplify the printer
466 let PrintMethod = "printAddrMode2Operand";
467 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
470 // addrmode2 := reg +/- imm12
471 // := reg +/- reg shop imm
473 def addrmode2 : Operand<i32>,
474 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
475 string EncoderMethod = "getAddrMode2OpValue";
476 let PrintMethod = "printAddrMode2Operand";
477 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
480 def am2offset : Operand<i32>,
481 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
482 [], [SDNPWantRoot]> {
483 string EncoderMethod = "getAddrMode2OffsetOpValue";
484 let PrintMethod = "printAddrMode2OffsetOperand";
485 let MIOperandInfo = (ops GPR, i32imm);
488 // addrmode3 := reg +/- reg
489 // addrmode3 := reg +/- imm8
491 def addrmode3 : Operand<i32>,
492 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
493 let EncoderMethod = "getAddrMode3OpValue";
494 let PrintMethod = "printAddrMode3Operand";
495 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
498 def am3offset : Operand<i32>,
499 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
500 [], [SDNPWantRoot]> {
501 let EncoderMethod = "getAddrMode3OffsetOpValue";
502 let PrintMethod = "printAddrMode3OffsetOperand";
503 let MIOperandInfo = (ops GPR, i32imm);
506 // ldstm_mode := {ia, ib, da, db}
508 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
509 let EncoderMethod = "getLdStmModeOpValue";
510 let PrintMethod = "printLdStmModeOperand";
513 def MemMode5AsmOperand : AsmOperandClass {
514 let Name = "MemMode5";
515 let SuperClasses = [];
518 // addrmode5 := reg +/- imm8*4
520 def addrmode5 : Operand<i32>,
521 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
522 let PrintMethod = "printAddrMode5Operand";
523 let MIOperandInfo = (ops GPR:$base, i32imm);
524 let ParserMatchClass = MemMode5AsmOperand;
525 let EncoderMethod = "getAddrMode5OpValue";
528 // addrmode6 := reg with optional writeback
530 def addrmode6 : Operand<i32>,
531 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
532 let PrintMethod = "printAddrMode6Operand";
533 let MIOperandInfo = (ops GPR:$addr, i32imm);
534 let EncoderMethod = "getAddrMode6AddressOpValue";
537 def am6offset : Operand<i32> {
538 let PrintMethod = "printAddrMode6OffsetOperand";
539 let MIOperandInfo = (ops GPR);
540 let EncoderMethod = "getAddrMode6OffsetOpValue";
543 // Special version of addrmode6 to handle alignment encoding for VLD-dup
544 // instructions, specifically VLD4-dup.
545 def addrmode6dup : Operand<i32>,
546 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
547 let PrintMethod = "printAddrMode6Operand";
548 let MIOperandInfo = (ops GPR:$addr, i32imm);
549 let EncoderMethod = "getAddrMode6DupAddressOpValue";
552 // addrmodepc := pc + reg
554 def addrmodepc : Operand<i32>,
555 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
556 let PrintMethod = "printAddrModePCOperand";
557 let MIOperandInfo = (ops GPR, i32imm);
560 def nohash_imm : Operand<i32> {
561 let PrintMethod = "printNoHashImmediate";
564 //===----------------------------------------------------------------------===//
566 include "ARMInstrFormats.td"
568 //===----------------------------------------------------------------------===//
569 // Multiclass helpers...
572 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
573 /// binop that produces a value.
574 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
575 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
576 PatFrag opnode, bit Commutable = 0> {
577 // The register-immediate version is re-materializable. This is useful
578 // in particular for taking the address of a local.
579 let isReMaterializable = 1 in {
580 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
581 iii, opc, "\t$Rd, $Rn, $imm",
582 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
587 let Inst{19-16} = Rn;
588 let Inst{15-12} = Rd;
589 let Inst{11-0} = imm;
592 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
593 iir, opc, "\t$Rd, $Rn, $Rm",
594 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
599 let isCommutable = Commutable;
600 let Inst{19-16} = Rn;
601 let Inst{15-12} = Rd;
602 let Inst{11-4} = 0b00000000;
605 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
606 iis, opc, "\t$Rd, $Rn, $shift",
607 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
612 let Inst{19-16} = Rn;
613 let Inst{15-12} = Rd;
614 let Inst{11-0} = shift;
618 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
619 /// instruction modifies the CPSR register.
620 let Defs = [CPSR] in {
621 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
622 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
623 PatFrag opnode, bit Commutable = 0> {
624 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
625 iii, opc, "\t$Rd, $Rn, $imm",
626 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
632 let Inst{19-16} = Rn;
633 let Inst{15-12} = Rd;
634 let Inst{11-0} = imm;
636 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
637 iir, opc, "\t$Rd, $Rn, $Rm",
638 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
642 let isCommutable = Commutable;
645 let Inst{19-16} = Rn;
646 let Inst{15-12} = Rd;
647 let Inst{11-4} = 0b00000000;
650 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
651 iis, opc, "\t$Rd, $Rn, $shift",
652 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
658 let Inst{19-16} = Rn;
659 let Inst{15-12} = Rd;
660 let Inst{11-0} = shift;
665 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
666 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
667 /// a explicit result, only implicitly set CPSR.
668 let isCompare = 1, Defs = [CPSR] in {
669 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
670 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
671 PatFrag opnode, bit Commutable = 0> {
672 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
674 [(opnode GPR:$Rn, so_imm:$imm)]> {
679 let Inst{19-16} = Rn;
680 let Inst{15-12} = 0b0000;
681 let Inst{11-0} = imm;
683 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
685 [(opnode GPR:$Rn, GPR:$Rm)]> {
688 let isCommutable = Commutable;
691 let Inst{19-16} = Rn;
692 let Inst{15-12} = 0b0000;
693 let Inst{11-4} = 0b00000000;
696 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
697 opc, "\t$Rn, $shift",
698 [(opnode GPR:$Rn, so_reg:$shift)]> {
703 let Inst{19-16} = Rn;
704 let Inst{15-12} = 0b0000;
705 let Inst{11-0} = shift;
710 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
711 /// register and one whose operand is a register rotated by 8/16/24.
712 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
713 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
714 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
715 IIC_iEXTr, opc, "\t$Rd, $Rm",
716 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
717 Requires<[IsARM, HasV6]> {
720 let Inst{19-16} = 0b1111;
721 let Inst{15-12} = Rd;
722 let Inst{11-10} = 0b00;
725 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
726 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
727 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
728 Requires<[IsARM, HasV6]> {
732 let Inst{19-16} = 0b1111;
733 let Inst{15-12} = Rd;
734 let Inst{11-10} = rot;
739 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
740 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
741 IIC_iEXTr, opc, "\t$Rd, $Rm",
742 [/* For disassembly only; pattern left blank */]>,
743 Requires<[IsARM, HasV6]> {
744 let Inst{19-16} = 0b1111;
745 let Inst{11-10} = 0b00;
747 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
748 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
749 [/* For disassembly only; pattern left blank */]>,
750 Requires<[IsARM, HasV6]> {
752 let Inst{19-16} = 0b1111;
753 let Inst{11-10} = rot;
757 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
758 /// register and one whose operand is a register rotated by 8/16/24.
759 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
760 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
761 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
762 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
763 Requires<[IsARM, HasV6]> {
767 let Inst{19-16} = Rn;
768 let Inst{15-12} = Rd;
769 let Inst{11-10} = 0b00;
770 let Inst{9-4} = 0b000111;
773 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
775 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
776 [(set GPR:$Rd, (opnode GPR:$Rn,
777 (rotr GPR:$Rm, rot_imm:$rot)))]>,
778 Requires<[IsARM, HasV6]> {
783 let Inst{19-16} = Rn;
784 let Inst{15-12} = Rd;
785 let Inst{11-10} = rot;
786 let Inst{9-4} = 0b000111;
791 // For disassembly only.
792 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
793 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
794 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
795 [/* For disassembly only; pattern left blank */]>,
796 Requires<[IsARM, HasV6]> {
797 let Inst{11-10} = 0b00;
799 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
801 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
802 [/* For disassembly only; pattern left blank */]>,
803 Requires<[IsARM, HasV6]> {
806 let Inst{19-16} = Rn;
807 let Inst{11-10} = rot;
811 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
812 let Uses = [CPSR] in {
813 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
814 bit Commutable = 0> {
815 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
816 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
817 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
823 let Inst{15-12} = Rd;
824 let Inst{19-16} = Rn;
825 let Inst{11-0} = imm;
827 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
828 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
829 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
834 let Inst{11-4} = 0b00000000;
836 let isCommutable = Commutable;
838 let Inst{15-12} = Rd;
839 let Inst{19-16} = Rn;
841 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
842 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
843 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
849 let Inst{11-0} = shift;
850 let Inst{15-12} = Rd;
851 let Inst{19-16} = Rn;
854 // Carry setting variants
855 let Defs = [CPSR] in {
856 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
857 bit Commutable = 0> {
858 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
859 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
860 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
865 let Inst{15-12} = Rd;
866 let Inst{19-16} = Rn;
867 let Inst{11-0} = imm;
871 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
872 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
873 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
878 let Inst{11-4} = 0b00000000;
879 let isCommutable = Commutable;
881 let Inst{15-12} = Rd;
882 let Inst{19-16} = Rn;
886 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
887 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
888 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
893 let Inst{11-0} = shift;
894 let Inst{15-12} = Rd;
895 let Inst{19-16} = Rn;
903 let canFoldAsLoad = 1, isReMaterializable = 1 in {
904 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
905 InstrItinClass iir, PatFrag opnode> {
906 // Note: We use the complex addrmode_imm12 rather than just an input
907 // GPR and a constrained immediate so that we can use this to match
908 // frame index references and avoid matching constant pool references.
909 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
910 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
911 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
914 let Inst{23} = addr{12}; // U (add = ('U' == 1))
915 let Inst{19-16} = addr{16-13}; // Rn
916 let Inst{15-12} = Rt;
917 let Inst{11-0} = addr{11-0}; // imm12
919 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
920 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
921 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
924 let Inst{23} = shift{12}; // U (add = ('U' == 1))
925 let Inst{19-16} = shift{16-13}; // Rn
926 let Inst{15-12} = Rt;
927 let Inst{11-0} = shift{11-0};
932 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
933 InstrItinClass iir, PatFrag opnode> {
934 // Note: We use the complex addrmode_imm12 rather than just an input
935 // GPR and a constrained immediate so that we can use this to match
936 // frame index references and avoid matching constant pool references.
937 def i12 : AI2ldst<0b010, 0, isByte, (outs),
938 (ins GPR:$Rt, addrmode_imm12:$addr),
939 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
940 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
943 let Inst{23} = addr{12}; // U (add = ('U' == 1))
944 let Inst{19-16} = addr{16-13}; // Rn
945 let Inst{15-12} = Rt;
946 let Inst{11-0} = addr{11-0}; // imm12
948 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
949 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
950 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
953 let Inst{23} = shift{12}; // U (add = ('U' == 1))
954 let Inst{19-16} = shift{16-13}; // Rn
955 let Inst{15-12} = Rt;
956 let Inst{11-0} = shift{11-0};
959 //===----------------------------------------------------------------------===//
961 //===----------------------------------------------------------------------===//
963 //===----------------------------------------------------------------------===//
964 // Miscellaneous Instructions.
967 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
968 /// the function. The first operand is the ID# for this instruction, the second
969 /// is the index into the MachineConstantPool that this is, the third is the
970 /// size in bytes of this constant pool entry.
971 let neverHasSideEffects = 1, isNotDuplicable = 1 in
972 def CONSTPOOL_ENTRY :
973 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
974 i32imm:$size), NoItinerary, []>;
976 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
977 // from removing one half of the matched pairs. That breaks PEI, which assumes
978 // these will always be in pairs, and asserts if it finds otherwise. Better way?
979 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
981 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
982 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
984 def ADJCALLSTACKDOWN :
985 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
986 [(ARMcallseq_start timm:$amt)]>;
989 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
990 [/* For disassembly only; pattern left blank */]>,
991 Requires<[IsARM, HasV6T2]> {
992 let Inst{27-16} = 0b001100100000;
993 let Inst{15-8} = 0b11110000;
994 let Inst{7-0} = 0b00000000;
997 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
998 [/* For disassembly only; pattern left blank */]>,
999 Requires<[IsARM, HasV6T2]> {
1000 let Inst{27-16} = 0b001100100000;
1001 let Inst{15-8} = 0b11110000;
1002 let Inst{7-0} = 0b00000001;
1005 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1006 [/* For disassembly only; pattern left blank */]>,
1007 Requires<[IsARM, HasV6T2]> {
1008 let Inst{27-16} = 0b001100100000;
1009 let Inst{15-8} = 0b11110000;
1010 let Inst{7-0} = 0b00000010;
1013 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1014 [/* For disassembly only; pattern left blank */]>,
1015 Requires<[IsARM, HasV6T2]> {
1016 let Inst{27-16} = 0b001100100000;
1017 let Inst{15-8} = 0b11110000;
1018 let Inst{7-0} = 0b00000011;
1021 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1023 [/* For disassembly only; pattern left blank */]>,
1024 Requires<[IsARM, HasV6]> {
1029 let Inst{15-12} = Rd;
1030 let Inst{19-16} = Rn;
1031 let Inst{27-20} = 0b01101000;
1032 let Inst{7-4} = 0b1011;
1033 let Inst{11-8} = 0b1111;
1036 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1037 [/* For disassembly only; pattern left blank */]>,
1038 Requires<[IsARM, HasV6T2]> {
1039 let Inst{27-16} = 0b001100100000;
1040 let Inst{15-8} = 0b11110000;
1041 let Inst{7-0} = 0b00000100;
1044 // The i32imm operand $val can be used by a debugger to store more information
1045 // about the breakpoint.
1046 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1047 [/* For disassembly only; pattern left blank */]>,
1050 let Inst{3-0} = val{3-0};
1051 let Inst{19-8} = val{15-4};
1052 let Inst{27-20} = 0b00010010;
1053 let Inst{7-4} = 0b0111;
1056 // Change Processor State is a system instruction -- for disassembly only.
1057 // The singleton $opt operand contains the following information:
1058 // opt{4-0} = mode from Inst{4-0}
1059 // opt{5} = changemode from Inst{17}
1060 // opt{8-6} = AIF from Inst{8-6}
1061 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
1062 // FIXME: Integrated assembler will need these split out.
1063 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
1064 [/* For disassembly only; pattern left blank */]>,
1066 let Inst{31-28} = 0b1111;
1067 let Inst{27-20} = 0b00010000;
1072 // Preload signals the memory system of possible future data/instruction access.
1073 // These are for disassembly only.
1074 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1076 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1077 !strconcat(opc, "\t$addr"),
1078 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1081 let Inst{31-26} = 0b111101;
1082 let Inst{25} = 0; // 0 for immediate form
1083 let Inst{24} = data;
1084 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1085 let Inst{22} = read;
1086 let Inst{21-20} = 0b01;
1087 let Inst{19-16} = addr{16-13}; // Rn
1088 let Inst{15-12} = Rt;
1089 let Inst{11-0} = addr{11-0}; // imm12
1092 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1093 !strconcat(opc, "\t$shift"),
1094 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1097 let Inst{31-26} = 0b111101;
1098 let Inst{25} = 1; // 1 for register form
1099 let Inst{24} = data;
1100 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1101 let Inst{22} = read;
1102 let Inst{21-20} = 0b01;
1103 let Inst{19-16} = shift{16-13}; // Rn
1104 let Inst{11-0} = shift{11-0};
1108 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1109 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1110 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1112 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1114 [/* For disassembly only; pattern left blank */]>,
1117 let Inst{31-10} = 0b1111000100000001000000;
1122 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1123 [/* For disassembly only; pattern left blank */]>,
1124 Requires<[IsARM, HasV7]> {
1126 let Inst{27-4} = 0b001100100000111100001111;
1127 let Inst{3-0} = opt;
1130 // A5.4 Permanently UNDEFINED instructions.
1131 let isBarrier = 1, isTerminator = 1 in
1132 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1135 let Inst = 0xe7ffdefe;
1138 // Address computation and loads and stores in PIC mode.
1139 let isNotDuplicable = 1 in {
1140 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1141 Size4Bytes, IIC_iALUr,
1142 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1144 let AddedComplexity = 10 in {
1145 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1146 Size4Bytes, IIC_iLoad_r,
1147 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1149 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1150 Size4Bytes, IIC_iLoad_bh_r,
1151 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1153 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1154 Size4Bytes, IIC_iLoad_bh_r,
1155 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1157 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1158 Size4Bytes, IIC_iLoad_bh_r,
1159 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1161 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1162 Size4Bytes, IIC_iLoad_bh_r,
1163 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1165 let AddedComplexity = 10 in {
1166 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1167 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1169 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1170 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1172 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1173 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1175 } // isNotDuplicable = 1
1178 // LEApcrel - Load a pc-relative address into a register without offending the
1180 let neverHasSideEffects = 1, isReMaterializable = 1 in
1181 // FIXME: We want one cannonical LEApcrel instruction and to express one or
1182 // both of these as pseudo-instructions that get expanded to it.
1183 def LEApcrel : AXI1<0, (outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1185 "adr${p}\t$Rd, #$label", []>;
1187 def LEApcrelJT : AXI1<0b0100, (outs GPR:$Rd),
1188 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1190 "adr${p}\t$Rd, #${label}_${id}", []> {
1193 let Inst{31-28} = p;
1194 let Inst{27-25} = 0b001;
1196 let Inst{19-16} = 0b1111;
1197 let Inst{15-12} = Rd;
1198 // FIXME: Add label encoding/fixup
1201 //===----------------------------------------------------------------------===//
1202 // Control Flow Instructions.
1205 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1207 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1208 "bx", "\tlr", [(ARMretflag)]>,
1209 Requires<[IsARM, HasV4T]> {
1210 let Inst{27-0} = 0b0001001011111111111100011110;
1214 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1215 "mov", "\tpc, lr", [(ARMretflag)]>,
1216 Requires<[IsARM, NoV4T]> {
1217 let Inst{27-0} = 0b0001101000001111000000001110;
1221 // Indirect branches
1222 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1224 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1225 [(brind GPR:$dst)]>,
1226 Requires<[IsARM, HasV4T]> {
1228 let Inst{31-4} = 0b1110000100101111111111110001;
1229 let Inst{3-0} = dst;
1233 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
1234 [(brind GPR:$dst)]>,
1235 Requires<[IsARM, NoV4T]> {
1237 let Inst{31-4} = 0b1110000110100000111100000000;
1238 let Inst{3-0} = dst;
1242 // All calls clobber the non-callee saved registers. SP is marked as
1243 // a use to prevent stack-pointer assignments that appear immediately
1244 // before calls from potentially appearing dead.
1246 // On non-Darwin platforms R9 is callee-saved.
1247 Defs = [R0, R1, R2, R3, R12, LR,
1248 D0, D1, D2, D3, D4, D5, D6, D7,
1249 D16, D17, D18, D19, D20, D21, D22, D23,
1250 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1252 def BL : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1253 IIC_Br, "bl\t$func",
1254 [(ARMcall tglobaladdr:$func)]>,
1255 Requires<[IsARM, IsNotDarwin]> {
1256 let Inst{31-28} = 0b1110;
1258 let Inst{23-0} = func;
1261 def BL_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1262 IIC_Br, "bl", "\t$func",
1263 [(ARMcall_pred tglobaladdr:$func)]>,
1264 Requires<[IsARM, IsNotDarwin]> {
1266 let Inst{23-0} = func;
1270 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1271 IIC_Br, "blx\t$func",
1272 [(ARMcall GPR:$func)]>,
1273 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1275 let Inst{31-4} = 0b1110000100101111111111110011;
1276 let Inst{3-0} = func;
1280 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1281 // FIXME: x2 insn patterns like this need to be pseudo instructions.
1282 def BX_CALL : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1283 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1284 [(ARMcall_nolink tGPR:$func)]>,
1285 Requires<[IsARM, HasV4T, IsNotDarwin]> {
1287 let Inst{27-4} = 0b000100101111111111110001;
1288 let Inst{3-0} = func;
1292 def BMOVPCRX_CALL : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1293 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1294 [(ARMcall_nolink tGPR:$func)]>,
1295 Requires<[IsARM, NoV4T, IsNotDarwin]> {
1297 let Inst{27-4} = 0b000110100000111100000000;
1298 let Inst{3-0} = func;
1303 // On Darwin R9 is call-clobbered.
1304 // R7 is marked as a use to prevent frame-pointer assignments from being
1305 // moved above / below calls.
1306 Defs = [R0, R1, R2, R3, R9, R12, LR,
1307 D0, D1, D2, D3, D4, D5, D6, D7,
1308 D16, D17, D18, D19, D20, D21, D22, D23,
1309 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1310 Uses = [R7, SP] in {
1311 def BLr9 : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1312 IIC_Br, "bl\t$func",
1313 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1314 let Inst{31-28} = 0b1110;
1316 let Inst{23-0} = func;
1319 def BLr9_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1320 IIC_Br, "bl", "\t$func",
1321 [(ARMcall_pred tglobaladdr:$func)]>,
1322 Requires<[IsARM, IsDarwin]> {
1324 let Inst{23-0} = func;
1328 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1329 IIC_Br, "blx\t$func",
1330 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1332 let Inst{31-4} = 0b1110000100101111111111110011;
1333 let Inst{3-0} = func;
1337 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1338 def BXr9_CALL : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1339 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1340 [(ARMcall_nolink tGPR:$func)]>,
1341 Requires<[IsARM, HasV4T, IsDarwin]> {
1343 let Inst{27-4} = 0b000100101111111111110001;
1344 let Inst{3-0} = func;
1348 def BMOVPCRXr9_CALL : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1349 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1350 [(ARMcall_nolink tGPR:$func)]>,
1351 Requires<[IsARM, NoV4T, IsDarwin]> {
1353 let Inst{27-4} = 0b000110100000111100000000;
1354 let Inst{3-0} = func;
1360 // FIXME: These should probably be xformed into the non-TC versions of the
1361 // instructions as part of MC lowering.
1362 // FIXME: These seem to be used for both Thumb and ARM instruction selection.
1363 // Thumb should have its own version since the instruction is actually
1364 // different, even though the mnemonic is the same.
1365 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1367 let Defs = [R0, R1, R2, R3, R9, R12,
1368 D0, D1, D2, D3, D4, D5, D6, D7,
1369 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1370 D27, D28, D29, D30, D31, PC],
1372 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1373 IIC_Br, []>, Requires<[IsDarwin]>;
1375 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1376 IIC_Br, []>, Requires<[IsDarwin]>;
1378 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1379 IIC_Br, "b\t$dst @ TAILCALL",
1380 []>, Requires<[IsARM, IsDarwin]>;
1382 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1383 IIC_Br, "b.w\t$dst @ TAILCALL",
1384 []>, Requires<[IsThumb, IsDarwin]>;
1386 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1387 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1388 []>, Requires<[IsDarwin]> {
1390 let Inst{31-4} = 0b1110000100101111111111110001;
1391 let Inst{3-0} = dst;
1395 // Non-Darwin versions (the difference is R9).
1396 let Defs = [R0, R1, R2, R3, R12,
1397 D0, D1, D2, D3, D4, D5, D6, D7,
1398 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1399 D27, D28, D29, D30, D31, PC],
1401 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1402 IIC_Br, []>, Requires<[IsNotDarwin]>;
1404 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1405 IIC_Br, []>, Requires<[IsNotDarwin]>;
1407 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1408 IIC_Br, "b\t$dst @ TAILCALL",
1409 []>, Requires<[IsARM, IsNotDarwin]>;
1411 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1412 IIC_Br, "b.w\t$dst @ TAILCALL",
1413 []>, Requires<[IsThumb, IsNotDarwin]>;
1415 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1416 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1417 []>, Requires<[IsNotDarwin]> {
1419 let Inst{31-4} = 0b1110000100101111111111110001;
1420 let Inst{3-0} = dst;
1425 let isBranch = 1, isTerminator = 1 in {
1426 // B is "predicable" since it can be xformed into a Bcc.
1427 let isBarrier = 1 in {
1428 let isPredicable = 1 in
1429 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1430 "b\t$target", [(br bb:$target)]> {
1432 let Inst{31-28} = 0b1110;
1433 let Inst{23-0} = target;
1436 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1437 def BR_JTr : ARMPseudoInst<(outs),
1438 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1439 SizeSpecial, IIC_Br,
1440 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1441 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1442 // into i12 and rs suffixed versions.
1443 def BR_JTm : ARMPseudoInst<(outs),
1444 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1445 SizeSpecial, IIC_Br,
1446 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1448 def BR_JTadd : ARMPseudoInst<(outs),
1449 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1450 SizeSpecial, IIC_Br,
1451 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1453 } // isNotDuplicable = 1, isIndirectBranch = 1
1456 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1457 // a two-value operand where a dag node expects two operands. :(
1458 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1459 IIC_Br, "b", "\t$target",
1460 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1462 let Inst{23-0} = target;
1466 // Branch and Exchange Jazelle -- for disassembly only
1467 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1468 [/* For disassembly only; pattern left blank */]> {
1469 let Inst{23-20} = 0b0010;
1470 //let Inst{19-8} = 0xfff;
1471 let Inst{7-4} = 0b0010;
1474 // Secure Monitor Call is a system instruction -- for disassembly only
1475 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1476 [/* For disassembly only; pattern left blank */]> {
1478 let Inst{23-4} = 0b01100000000000000111;
1479 let Inst{3-0} = opt;
1482 // Supervisor Call (Software Interrupt) -- for disassembly only
1483 let isCall = 1, Uses = [SP] in {
1484 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1485 [/* For disassembly only; pattern left blank */]> {
1487 let Inst{23-0} = svc;
1491 // Store Return State is a system instruction -- for disassembly only
1492 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1493 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1494 NoItinerary, "srs${amode}\tsp!, $mode",
1495 [/* For disassembly only; pattern left blank */]> {
1496 let Inst{31-28} = 0b1111;
1497 let Inst{22-20} = 0b110; // W = 1
1500 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1501 NoItinerary, "srs${amode}\tsp, $mode",
1502 [/* For disassembly only; pattern left blank */]> {
1503 let Inst{31-28} = 0b1111;
1504 let Inst{22-20} = 0b100; // W = 0
1507 // Return From Exception is a system instruction -- for disassembly only
1508 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1509 NoItinerary, "rfe${amode}\t$base!",
1510 [/* For disassembly only; pattern left blank */]> {
1511 let Inst{31-28} = 0b1111;
1512 let Inst{22-20} = 0b011; // W = 1
1515 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1516 NoItinerary, "rfe${amode}\t$base",
1517 [/* For disassembly only; pattern left blank */]> {
1518 let Inst{31-28} = 0b1111;
1519 let Inst{22-20} = 0b001; // W = 0
1521 } // isCodeGenOnly = 1
1523 //===----------------------------------------------------------------------===//
1524 // Load / store Instructions.
1530 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1531 UnOpFrag<(load node:$Src)>>;
1532 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1533 UnOpFrag<(zextloadi8 node:$Src)>>;
1534 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1535 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1536 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1537 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1539 // Special LDR for loads from non-pc-relative constpools.
1540 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1541 isReMaterializable = 1 in
1542 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1543 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1547 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1548 let Inst{19-16} = 0b1111;
1549 let Inst{15-12} = Rt;
1550 let Inst{11-0} = addr{11-0}; // imm12
1553 // Loads with zero extension
1554 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1555 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1556 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1558 // Loads with sign extension
1559 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1560 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1561 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1563 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1564 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1565 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1567 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1568 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1569 // FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1)
1570 // how to represent that such that tblgen is happy and we don't
1571 // mark this codegen only?
1573 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1574 (ins addrmode3:$addr), LdMiscFrm,
1575 IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
1576 []>, Requires<[IsARM, HasV5TE]>;
1580 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1581 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1582 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1583 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1585 // {13} 1 == Rm, 0 == imm12
1589 let Inst{25} = addr{13};
1590 let Inst{23} = addr{12};
1591 let Inst{19-16} = addr{17-14};
1592 let Inst{11-0} = addr{11-0};
1594 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1595 (ins GPR:$Rn, am2offset:$offset),
1596 IndexModePost, LdFrm, itin,
1597 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1598 // {13} 1 == Rm, 0 == imm12
1603 let Inst{25} = offset{13};
1604 let Inst{23} = offset{12};
1605 let Inst{19-16} = Rn;
1606 let Inst{11-0} = offset{11-0};
1610 let mayLoad = 1, neverHasSideEffects = 1 in {
1611 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1612 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1615 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1616 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1617 (ins addrmode3:$addr), IndexModePre,
1619 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1621 let Inst{23} = addr{8}; // U bit
1622 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1623 let Inst{19-16} = addr{12-9}; // Rn
1624 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1625 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1627 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1628 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1630 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1633 let Inst{23} = offset{8}; // U bit
1634 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1635 let Inst{19-16} = Rn;
1636 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1637 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1641 let mayLoad = 1, neverHasSideEffects = 1 in {
1642 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1643 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1644 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1645 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1646 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1647 } // mayLoad = 1, neverHasSideEffects = 1
1649 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1650 let mayLoad = 1, neverHasSideEffects = 1 in {
1651 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1652 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1653 LdFrm, IIC_iLoad_ru,
1654 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1655 let Inst{21} = 1; // overwrite
1657 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1658 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1659 LdFrm, IIC_iLoad_bh_ru,
1660 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1661 let Inst{21} = 1; // overwrite
1663 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1664 (ins GPR:$base, am3offset:$offset), IndexModePost,
1665 LdMiscFrm, IIC_iLoad_bh_ru,
1666 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1667 let Inst{21} = 1; // overwrite
1669 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1670 (ins GPR:$base, am3offset:$offset), IndexModePost,
1671 LdMiscFrm, IIC_iLoad_bh_ru,
1672 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1673 let Inst{21} = 1; // overwrite
1675 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1676 (ins GPR:$base, am3offset:$offset), IndexModePost,
1677 LdMiscFrm, IIC_iLoad_bh_ru,
1678 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1679 let Inst{21} = 1; // overwrite
1685 // Stores with truncate
1686 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1687 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1688 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1691 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1692 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1693 def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1694 StMiscFrm, IIC_iStore_d_r,
1695 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1698 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1699 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1700 IndexModePre, StFrm, IIC_iStore_ru,
1701 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1703 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1705 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1706 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1707 IndexModePost, StFrm, IIC_iStore_ru,
1708 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1710 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1712 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1713 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1714 IndexModePre, StFrm, IIC_iStore_bh_ru,
1715 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1716 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1717 GPR:$Rn, am2offset:$offset))]>;
1718 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1719 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1720 IndexModePost, StFrm, IIC_iStore_bh_ru,
1721 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1722 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1723 GPR:$Rn, am2offset:$offset))]>;
1725 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1726 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1727 IndexModePre, StMiscFrm, IIC_iStore_ru,
1728 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1730 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1732 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1733 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1734 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1735 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1736 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1737 GPR:$Rn, am3offset:$offset))]>;
1739 // For disassembly only
1740 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1741 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1742 StMiscFrm, IIC_iStore_d_ru,
1743 "strd", "\t$src1, $src2, [$base, $offset]!",
1744 "$base = $base_wb", []>;
1746 // For disassembly only
1747 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1748 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1749 StMiscFrm, IIC_iStore_d_ru,
1750 "strd", "\t$src1, $src2, [$base], $offset",
1751 "$base = $base_wb", []>;
1753 // STRT, STRBT, and STRHT are for disassembly only.
1755 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1756 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
1757 IndexModeNone, StFrm, IIC_iStore_ru,
1758 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1759 [/* For disassembly only; pattern left blank */]> {
1760 let Inst{21} = 1; // overwrite
1763 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1764 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1765 IndexModeNone, StFrm, IIC_iStore_bh_ru,
1766 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1767 [/* For disassembly only; pattern left blank */]> {
1768 let Inst{21} = 1; // overwrite
1771 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1772 (ins GPR:$src, GPR:$base,am3offset:$offset),
1773 StMiscFrm, IIC_iStore_bh_ru,
1774 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1775 [/* For disassembly only; pattern left blank */]> {
1776 let Inst{21} = 1; // overwrite
1779 //===----------------------------------------------------------------------===//
1780 // Load / store multiple Instructions.
1783 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1784 InstrItinClass itin, InstrItinClass itin_upd> {
1786 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1787 IndexModeNone, f, itin,
1788 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1789 let Inst{24-23} = 0b01; // Increment After
1790 let Inst{21} = 0; // No writeback
1791 let Inst{20} = L_bit;
1794 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1795 IndexModeUpd, f, itin_upd,
1796 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1797 let Inst{24-23} = 0b01; // Increment After
1798 let Inst{21} = 1; // Writeback
1799 let Inst{20} = L_bit;
1802 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1803 IndexModeNone, f, itin,
1804 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1805 let Inst{24-23} = 0b00; // Decrement After
1806 let Inst{21} = 0; // No writeback
1807 let Inst{20} = L_bit;
1810 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1811 IndexModeUpd, f, itin_upd,
1812 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1813 let Inst{24-23} = 0b00; // Decrement After
1814 let Inst{21} = 1; // Writeback
1815 let Inst{20} = L_bit;
1818 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1819 IndexModeNone, f, itin,
1820 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1821 let Inst{24-23} = 0b10; // Decrement Before
1822 let Inst{21} = 0; // No writeback
1823 let Inst{20} = L_bit;
1826 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1827 IndexModeUpd, f, itin_upd,
1828 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1829 let Inst{24-23} = 0b10; // Decrement Before
1830 let Inst{21} = 1; // Writeback
1831 let Inst{20} = L_bit;
1834 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1835 IndexModeNone, f, itin,
1836 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1837 let Inst{24-23} = 0b11; // Increment Before
1838 let Inst{21} = 0; // No writeback
1839 let Inst{20} = L_bit;
1842 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1843 IndexModeUpd, f, itin_upd,
1844 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1845 let Inst{24-23} = 0b11; // Increment Before
1846 let Inst{21} = 1; // Writeback
1847 let Inst{20} = L_bit;
1851 let neverHasSideEffects = 1 in {
1853 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1854 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1856 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1857 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1859 } // neverHasSideEffects
1861 // Load / Store Multiple Mnemnoic Aliases
1862 def : MnemonicAlias<"ldm", "ldmia">;
1863 def : MnemonicAlias<"stm", "stmia">;
1865 // FIXME: remove when we have a way to marking a MI with these properties.
1866 // FIXME: Should pc be an implicit operand like PICADD, etc?
1867 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1868 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1869 def LDMIA_RET : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1870 reglist:$regs, variable_ops),
1871 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1872 "ldmia${p}\t$Rn!, $regs",
1874 let Inst{24-23} = 0b01; // Increment After
1875 let Inst{21} = 1; // Writeback
1876 let Inst{20} = 1; // Load
1879 //===----------------------------------------------------------------------===//
1880 // Move Instructions.
1883 let neverHasSideEffects = 1 in
1884 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1885 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1889 let Inst{11-4} = 0b00000000;
1892 let Inst{15-12} = Rd;
1895 // A version for the smaller set of tail call registers.
1896 let neverHasSideEffects = 1 in
1897 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1898 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1902 let Inst{11-4} = 0b00000000;
1905 let Inst{15-12} = Rd;
1908 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1909 DPSoRegFrm, IIC_iMOVsr,
1910 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1914 let Inst{15-12} = Rd;
1915 let Inst{11-0} = src;
1919 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1920 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1921 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1925 let Inst{15-12} = Rd;
1926 let Inst{19-16} = 0b0000;
1927 let Inst{11-0} = imm;
1930 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1931 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins movt_imm:$imm),
1933 "movw", "\t$Rd, $imm",
1934 [(set GPR:$Rd, imm0_65535:$imm)]>,
1935 Requires<[IsARM, HasV6T2]>, UnaryDP {
1938 let Inst{15-12} = Rd;
1939 let Inst{11-0} = imm{11-0};
1940 let Inst{19-16} = imm{15-12};
1945 let Constraints = "$src = $Rd" in
1946 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, movt_imm:$imm),
1948 "movt", "\t$Rd, $imm",
1950 (or (and GPR:$src, 0xffff),
1951 lo16AllZero:$imm))]>, UnaryDP,
1952 Requires<[IsARM, HasV6T2]> {
1955 let Inst{15-12} = Rd;
1956 let Inst{11-0} = imm{11-0};
1957 let Inst{19-16} = imm{15-12};
1962 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1963 Requires<[IsARM, HasV6T2]>;
1965 let Uses = [CPSR] in
1966 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
1967 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1970 // These aren't really mov instructions, but we have to define them this way
1971 // due to flag operands.
1973 let Defs = [CPSR] in {
1974 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1975 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1977 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1978 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1982 //===----------------------------------------------------------------------===//
1983 // Extend Instructions.
1988 defm SXTB : AI_ext_rrot<0b01101010,
1989 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1990 defm SXTH : AI_ext_rrot<0b01101011,
1991 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1993 defm SXTAB : AI_exta_rrot<0b01101010,
1994 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1995 defm SXTAH : AI_exta_rrot<0b01101011,
1996 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
1998 // For disassembly only
1999 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2001 // For disassembly only
2002 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2006 let AddedComplexity = 16 in {
2007 defm UXTB : AI_ext_rrot<0b01101110,
2008 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2009 defm UXTH : AI_ext_rrot<0b01101111,
2010 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2011 defm UXTB16 : AI_ext_rrot<0b01101100,
2012 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2014 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2015 // The transformation should probably be done as a combiner action
2016 // instead so we can include a check for masking back in the upper
2017 // eight bits of the source into the lower eight bits of the result.
2018 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2019 // (UXTB16r_rot GPR:$Src, 24)>;
2020 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2021 (UXTB16r_rot GPR:$Src, 8)>;
2023 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2024 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2025 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2026 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2029 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2030 // For disassembly only
2031 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2034 def SBFX : I<(outs GPR:$Rd),
2035 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2036 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2037 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2038 Requires<[IsARM, HasV6T2]> {
2043 let Inst{27-21} = 0b0111101;
2044 let Inst{6-4} = 0b101;
2045 let Inst{20-16} = width;
2046 let Inst{15-12} = Rd;
2047 let Inst{11-7} = lsb;
2051 def UBFX : I<(outs GPR:$Rd),
2052 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2053 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2054 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2055 Requires<[IsARM, HasV6T2]> {
2060 let Inst{27-21} = 0b0111111;
2061 let Inst{6-4} = 0b101;
2062 let Inst{20-16} = width;
2063 let Inst{15-12} = Rd;
2064 let Inst{11-7} = lsb;
2068 //===----------------------------------------------------------------------===//
2069 // Arithmetic Instructions.
2072 defm ADD : AsI1_bin_irs<0b0100, "add",
2073 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2074 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2075 defm SUB : AsI1_bin_irs<0b0010, "sub",
2076 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2077 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2079 // ADD and SUB with 's' bit set.
2080 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2081 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2082 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2083 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2084 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2085 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2087 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2088 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2089 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2090 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2091 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2092 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2093 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2094 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2096 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2097 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2098 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2103 let Inst{15-12} = Rd;
2104 let Inst{19-16} = Rn;
2105 let Inst{11-0} = imm;
2108 // The reg/reg form is only defined for the disassembler; for codegen it is
2109 // equivalent to SUBrr.
2110 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2111 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2112 [/* For disassembly only; pattern left blank */]> {
2116 let Inst{11-4} = 0b00000000;
2119 let Inst{15-12} = Rd;
2120 let Inst{19-16} = Rn;
2123 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2124 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2125 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2130 let Inst{11-0} = shift;
2131 let Inst{15-12} = Rd;
2132 let Inst{19-16} = Rn;
2135 // RSB with 's' bit set.
2136 let Defs = [CPSR] in {
2137 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2138 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2139 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2145 let Inst{15-12} = Rd;
2146 let Inst{19-16} = Rn;
2147 let Inst{11-0} = imm;
2149 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2150 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2151 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2157 let Inst{11-0} = shift;
2158 let Inst{15-12} = Rd;
2159 let Inst{19-16} = Rn;
2163 let Uses = [CPSR] in {
2164 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2165 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2166 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2172 let Inst{15-12} = Rd;
2173 let Inst{19-16} = Rn;
2174 let Inst{11-0} = imm;
2176 // The reg/reg form is only defined for the disassembler; for codegen it is
2177 // equivalent to SUBrr.
2178 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2179 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2180 [/* For disassembly only; pattern left blank */]> {
2184 let Inst{11-4} = 0b00000000;
2187 let Inst{15-12} = Rd;
2188 let Inst{19-16} = Rn;
2190 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2191 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2192 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2198 let Inst{11-0} = shift;
2199 let Inst{15-12} = Rd;
2200 let Inst{19-16} = Rn;
2204 // FIXME: Allow these to be predicated.
2205 let Defs = [CPSR], Uses = [CPSR] in {
2206 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2207 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2208 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2215 let Inst{15-12} = Rd;
2216 let Inst{19-16} = Rn;
2217 let Inst{11-0} = imm;
2219 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2220 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2221 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2228 let Inst{11-0} = shift;
2229 let Inst{15-12} = Rd;
2230 let Inst{19-16} = Rn;
2234 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2235 // The assume-no-carry-in form uses the negation of the input since add/sub
2236 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2237 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2239 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2240 (SUBri GPR:$src, so_imm_neg:$imm)>;
2241 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2242 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2243 // The with-carry-in form matches bitwise not instead of the negation.
2244 // Effectively, the inverse interpretation of the carry flag already accounts
2245 // for part of the negation.
2246 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2247 (SBCri GPR:$src, so_imm_not:$imm)>;
2249 // Note: These are implemented in C++ code, because they have to generate
2250 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2252 // (mul X, 2^n+1) -> (add (X << n), X)
2253 // (mul X, 2^n-1) -> (rsb X, (X << n))
2255 // ARM Arithmetic Instruction -- for disassembly only
2256 // GPR:$dst = GPR:$a op GPR:$b
2257 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2258 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2259 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2260 opc, "\t$Rd, $Rn, $Rm", pattern> {
2264 let Inst{27-20} = op27_20;
2265 let Inst{11-4} = op11_4;
2266 let Inst{19-16} = Rn;
2267 let Inst{15-12} = Rd;
2271 // Saturating add/subtract -- for disassembly only
2273 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2274 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2275 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2276 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2277 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2278 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2280 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2281 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2282 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2283 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2284 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2285 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2286 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2287 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2288 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2289 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2290 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2291 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2293 // Signed/Unsigned add/subtract -- for disassembly only
2295 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2296 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2297 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2298 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2299 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2300 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2301 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2302 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2303 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2304 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2305 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2306 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2308 // Signed/Unsigned halving add/subtract -- for disassembly only
2310 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2311 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2312 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2313 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2314 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2315 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2316 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2317 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2318 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2319 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2320 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2321 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2323 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2325 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2326 MulFrm /* for convenience */, NoItinerary, "usad8",
2327 "\t$Rd, $Rn, $Rm", []>,
2328 Requires<[IsARM, HasV6]> {
2332 let Inst{27-20} = 0b01111000;
2333 let Inst{15-12} = 0b1111;
2334 let Inst{7-4} = 0b0001;
2335 let Inst{19-16} = Rd;
2336 let Inst{11-8} = Rm;
2339 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2340 MulFrm /* for convenience */, NoItinerary, "usada8",
2341 "\t$Rd, $Rn, $Rm, $Ra", []>,
2342 Requires<[IsARM, HasV6]> {
2347 let Inst{27-20} = 0b01111000;
2348 let Inst{7-4} = 0b0001;
2349 let Inst{19-16} = Rd;
2350 let Inst{15-12} = Ra;
2351 let Inst{11-8} = Rm;
2355 // Signed/Unsigned saturate -- for disassembly only
2357 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2358 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2359 [/* For disassembly only; pattern left blank */]> {
2364 let Inst{27-21} = 0b0110101;
2365 let Inst{5-4} = 0b01;
2366 let Inst{20-16} = sat_imm;
2367 let Inst{15-12} = Rd;
2368 let Inst{11-7} = sh{7-3};
2369 let Inst{6} = sh{0};
2373 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2374 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2375 [/* For disassembly only; pattern left blank */]> {
2379 let Inst{27-20} = 0b01101010;
2380 let Inst{11-4} = 0b11110011;
2381 let Inst{15-12} = Rd;
2382 let Inst{19-16} = sat_imm;
2386 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2387 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2388 [/* For disassembly only; pattern left blank */]> {
2393 let Inst{27-21} = 0b0110111;
2394 let Inst{5-4} = 0b01;
2395 let Inst{15-12} = Rd;
2396 let Inst{11-7} = sh{7-3};
2397 let Inst{6} = sh{0};
2398 let Inst{20-16} = sat_imm;
2402 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2403 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2404 [/* For disassembly only; pattern left blank */]> {
2408 let Inst{27-20} = 0b01101110;
2409 let Inst{11-4} = 0b11110011;
2410 let Inst{15-12} = Rd;
2411 let Inst{19-16} = sat_imm;
2415 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2416 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2418 //===----------------------------------------------------------------------===//
2419 // Bitwise Instructions.
2422 defm AND : AsI1_bin_irs<0b0000, "and",
2423 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2424 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2425 defm ORR : AsI1_bin_irs<0b1100, "orr",
2426 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2427 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2428 defm EOR : AsI1_bin_irs<0b0001, "eor",
2429 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2430 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2431 defm BIC : AsI1_bin_irs<0b1110, "bic",
2432 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2433 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2435 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2436 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2437 "bfc", "\t$Rd, $imm", "$src = $Rd",
2438 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2439 Requires<[IsARM, HasV6T2]> {
2442 let Inst{27-21} = 0b0111110;
2443 let Inst{6-0} = 0b0011111;
2444 let Inst{15-12} = Rd;
2445 let Inst{11-7} = imm{4-0}; // lsb
2446 let Inst{20-16} = imm{9-5}; // width
2449 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2450 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2451 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2452 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2453 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2454 bf_inv_mask_imm:$imm))]>,
2455 Requires<[IsARM, HasV6T2]> {
2459 let Inst{27-21} = 0b0111110;
2460 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2461 let Inst{15-12} = Rd;
2462 let Inst{11-7} = imm{4-0}; // lsb
2463 let Inst{20-16} = imm{9-5}; // width
2467 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2468 "mvn", "\t$Rd, $Rm",
2469 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2473 let Inst{19-16} = 0b0000;
2474 let Inst{11-4} = 0b00000000;
2475 let Inst{15-12} = Rd;
2478 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2479 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2480 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2484 let Inst{19-16} = 0b0000;
2485 let Inst{15-12} = Rd;
2486 let Inst{11-0} = shift;
2488 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2489 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2490 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2491 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2495 let Inst{19-16} = 0b0000;
2496 let Inst{15-12} = Rd;
2497 let Inst{11-0} = imm;
2500 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2501 (BICri GPR:$src, so_imm_not:$imm)>;
2503 //===----------------------------------------------------------------------===//
2504 // Multiply Instructions.
2506 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2507 string opc, string asm, list<dag> pattern>
2508 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2512 let Inst{19-16} = Rd;
2513 let Inst{11-8} = Rm;
2516 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2517 string opc, string asm, list<dag> pattern>
2518 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2523 let Inst{19-16} = RdHi;
2524 let Inst{15-12} = RdLo;
2525 let Inst{11-8} = Rm;
2529 let isCommutable = 1 in
2530 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2531 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2532 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2534 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2535 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2536 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2538 let Inst{15-12} = Ra;
2541 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2542 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2543 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2544 Requires<[IsARM, HasV6T2]> {
2549 let Inst{19-16} = Rd;
2550 let Inst{15-12} = Ra;
2551 let Inst{11-8} = Rm;
2555 // Extra precision multiplies with low / high results
2557 let neverHasSideEffects = 1 in {
2558 let isCommutable = 1 in {
2559 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2560 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2561 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2563 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2564 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2565 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2568 // Multiply + accumulate
2569 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2570 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2571 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2573 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2574 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2575 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2577 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2578 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2579 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2580 Requires<[IsARM, HasV6]> {
2585 let Inst{19-16} = RdLo;
2586 let Inst{15-12} = RdHi;
2587 let Inst{11-8} = Rm;
2590 } // neverHasSideEffects
2592 // Most significant word multiply
2593 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2594 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2595 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2596 Requires<[IsARM, HasV6]> {
2597 let Inst{15-12} = 0b1111;
2600 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2601 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2602 [/* For disassembly only; pattern left blank */]>,
2603 Requires<[IsARM, HasV6]> {
2604 let Inst{15-12} = 0b1111;
2607 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2608 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2609 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2610 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2611 Requires<[IsARM, HasV6]>;
2613 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2614 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2615 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2616 [/* For disassembly only; pattern left blank */]>,
2617 Requires<[IsARM, HasV6]>;
2619 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2620 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2621 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2622 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2623 Requires<[IsARM, HasV6]>;
2625 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2626 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2627 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2628 [/* For disassembly only; pattern left blank */]>,
2629 Requires<[IsARM, HasV6]>;
2631 multiclass AI_smul<string opc, PatFrag opnode> {
2632 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2633 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2634 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2635 (sext_inreg GPR:$Rm, i16)))]>,
2636 Requires<[IsARM, HasV5TE]>;
2638 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2639 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2640 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2641 (sra GPR:$Rm, (i32 16))))]>,
2642 Requires<[IsARM, HasV5TE]>;
2644 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2645 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2646 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2647 (sext_inreg GPR:$Rm, i16)))]>,
2648 Requires<[IsARM, HasV5TE]>;
2650 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2651 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2652 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2653 (sra GPR:$Rm, (i32 16))))]>,
2654 Requires<[IsARM, HasV5TE]>;
2656 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2657 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2658 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2659 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2660 Requires<[IsARM, HasV5TE]>;
2662 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2663 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2664 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2665 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2666 Requires<[IsARM, HasV5TE]>;
2670 multiclass AI_smla<string opc, PatFrag opnode> {
2671 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2672 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2673 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2674 [(set GPR:$Rd, (add GPR:$Ra,
2675 (opnode (sext_inreg GPR:$Rn, i16),
2676 (sext_inreg GPR:$Rm, i16))))]>,
2677 Requires<[IsARM, HasV5TE]>;
2679 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2680 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2681 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2682 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2683 (sra GPR:$Rm, (i32 16)))))]>,
2684 Requires<[IsARM, HasV5TE]>;
2686 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2687 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2688 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2689 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2690 (sext_inreg GPR:$Rm, i16))))]>,
2691 Requires<[IsARM, HasV5TE]>;
2693 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2694 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2695 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2696 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2697 (sra GPR:$Rm, (i32 16)))))]>,
2698 Requires<[IsARM, HasV5TE]>;
2700 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2701 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2702 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2703 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2704 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2705 Requires<[IsARM, HasV5TE]>;
2707 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2708 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2709 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2710 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2711 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2712 Requires<[IsARM, HasV5TE]>;
2715 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2716 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2718 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2719 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2720 (ins GPR:$Rn, GPR:$Rm),
2721 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2722 [/* For disassembly only; pattern left blank */]>,
2723 Requires<[IsARM, HasV5TE]>;
2725 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2726 (ins GPR:$Rn, GPR:$Rm),
2727 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2728 [/* For disassembly only; pattern left blank */]>,
2729 Requires<[IsARM, HasV5TE]>;
2731 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2732 (ins GPR:$Rn, GPR:$Rm),
2733 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2734 [/* For disassembly only; pattern left blank */]>,
2735 Requires<[IsARM, HasV5TE]>;
2737 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2738 (ins GPR:$Rn, GPR:$Rm),
2739 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2740 [/* For disassembly only; pattern left blank */]>,
2741 Requires<[IsARM, HasV5TE]>;
2743 // Helper class for AI_smld -- for disassembly only
2744 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2745 InstrItinClass itin, string opc, string asm>
2746 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2753 let Inst{21-20} = 0b00;
2754 let Inst{22} = long;
2755 let Inst{27-23} = 0b01110;
2756 let Inst{11-8} = Rm;
2759 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2760 InstrItinClass itin, string opc, string asm>
2761 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2763 let Inst{15-12} = 0b1111;
2764 let Inst{19-16} = Rd;
2766 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2767 InstrItinClass itin, string opc, string asm>
2768 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2770 let Inst{15-12} = Ra;
2772 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2773 InstrItinClass itin, string opc, string asm>
2774 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2777 let Inst{19-16} = RdHi;
2778 let Inst{15-12} = RdLo;
2781 multiclass AI_smld<bit sub, string opc> {
2783 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2784 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2786 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2787 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2789 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2790 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2791 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2793 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2794 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2795 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2799 defm SMLA : AI_smld<0, "smla">;
2800 defm SMLS : AI_smld<1, "smls">;
2802 multiclass AI_sdml<bit sub, string opc> {
2804 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2805 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2806 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2807 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2810 defm SMUA : AI_sdml<0, "smua">;
2811 defm SMUS : AI_sdml<1, "smus">;
2813 //===----------------------------------------------------------------------===//
2814 // Misc. Arithmetic Instructions.
2817 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2818 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2819 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2821 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2822 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2823 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2824 Requires<[IsARM, HasV6T2]>;
2826 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2827 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2828 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2830 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2831 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2833 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2834 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2835 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2836 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2837 Requires<[IsARM, HasV6]>;
2839 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2840 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2843 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2844 (shl GPR:$Rm, (i32 8))), i16))]>,
2845 Requires<[IsARM, HasV6]>;
2847 def lsl_shift_imm : SDNodeXForm<imm, [{
2848 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2849 return CurDAG->getTargetConstant(Sh, MVT::i32);
2852 def lsl_amt : PatLeaf<(i32 imm), [{
2853 return (N->getZExtValue() < 32);
2856 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2857 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2858 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2859 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2860 (and (shl GPR:$Rm, lsl_amt:$sh),
2862 Requires<[IsARM, HasV6]>;
2864 // Alternate cases for PKHBT where identities eliminate some nodes.
2865 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2866 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2867 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2868 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2870 def asr_shift_imm : SDNodeXForm<imm, [{
2871 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2872 return CurDAG->getTargetConstant(Sh, MVT::i32);
2875 def asr_amt : PatLeaf<(i32 imm), [{
2876 return (N->getZExtValue() <= 32);
2879 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2880 // will match the pattern below.
2881 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2882 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2883 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2884 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2885 (and (sra GPR:$Rm, asr_amt:$sh),
2887 Requires<[IsARM, HasV6]>;
2889 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2890 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2891 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2892 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2893 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2894 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2895 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2897 //===----------------------------------------------------------------------===//
2898 // Comparison Instructions...
2901 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2902 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2903 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2905 // FIXME: We have to be careful when using the CMN instruction and comparison
2906 // with 0. One would expect these two pieces of code should give identical
2922 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2923 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2924 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2925 // value of r0 and the carry bit (because the "carry bit" parameter to
2926 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2927 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2928 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2929 // parameter to AddWithCarry is defined as 0).
2931 // When x is 0 and unsigned:
2935 // ~x + 1 = 0x1 0000 0000
2936 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2938 // Therefore, we should disable CMN when comparing against zero, until we can
2939 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2940 // when it's a comparison which doesn't look at the 'carry' flag).
2942 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2944 // This is related to <rdar://problem/7569620>.
2946 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2947 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2949 // Note that TST/TEQ don't set all the same flags that CMP does!
2950 defm TST : AI1_cmp_irs<0b1000, "tst",
2951 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2952 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
2953 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2954 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2955 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
2957 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2958 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2959 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2960 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2961 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2962 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2964 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2965 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2967 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2968 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2970 // Pseudo i64 compares for some floating point compares.
2971 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2973 def BCCi64 : PseudoInst<(outs),
2974 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2976 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2978 def BCCZi64 : PseudoInst<(outs),
2979 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
2980 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2981 } // usesCustomInserter
2984 // Conditional moves
2985 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2986 // a two-value operand where a dag node expects two operands. :(
2987 // FIXME: These should all be pseudo-instructions that get expanded to
2988 // the normal MOV instructions. That would fix the dependency on
2989 // special casing them in tblgen.
2990 let neverHasSideEffects = 1 in {
2991 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
2992 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
2993 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
2994 RegConstraint<"$false = $Rd">, UnaryDP {
2999 let Inst{15-12} = Rd;
3000 let Inst{11-4} = 0b00000000;
3004 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
3005 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
3006 "mov", "\t$Rd, $shift",
3007 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3008 RegConstraint<"$false = $Rd">, UnaryDP {
3013 let Inst{19-16} = 0;
3014 let Inst{15-12} = Rd;
3015 let Inst{11-0} = shift;
3018 let isMoveImm = 1 in
3019 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, movt_imm:$imm),
3021 "movw", "\t$Rd, $imm",
3023 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
3029 let Inst{19-16} = imm{15-12};
3030 let Inst{15-12} = Rd;
3031 let Inst{11-0} = imm{11-0};
3034 let isMoveImm = 1 in
3035 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
3036 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3037 "mov", "\t$Rd, $imm",
3038 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3039 RegConstraint<"$false = $Rd">, UnaryDP {
3044 let Inst{19-16} = 0b0000;
3045 let Inst{15-12} = Rd;
3046 let Inst{11-0} = imm;
3049 // Two instruction predicate mov immediate.
3050 let isMoveImm = 1 in
3051 def MOVCCi32imm : PseudoInst<(outs GPR:$Rd),
3052 (ins GPR:$false, i32imm:$src, pred:$p),
3053 IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3055 let isMoveImm = 1 in
3056 def MVNCCi : AI1<0b1111, (outs GPR:$Rd),
3057 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3058 "mvn", "\t$Rd, $imm",
3059 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3060 RegConstraint<"$false = $Rd">, UnaryDP {
3065 let Inst{19-16} = 0b0000;
3066 let Inst{15-12} = Rd;
3067 let Inst{11-0} = imm;
3069 } // neverHasSideEffects
3071 //===----------------------------------------------------------------------===//
3072 // Atomic operations intrinsics
3075 def memb_opt : Operand<i32> {
3076 let PrintMethod = "printMemBOption";
3079 // memory barriers protect the atomic sequences
3080 let hasSideEffects = 1 in {
3081 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3082 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3083 Requires<[IsARM, HasDB]> {
3085 let Inst{31-4} = 0xf57ff05;
3086 let Inst{3-0} = opt;
3089 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
3090 "mcr", "\tp15, 0, $zero, c7, c10, 5",
3091 [(ARMMemBarrierMCR GPR:$zero)]>,
3092 Requires<[IsARM, HasV6]> {
3093 // FIXME: add encoding
3097 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3099 [/* For disassembly only; pattern left blank */]>,
3100 Requires<[IsARM, HasDB]> {
3102 let Inst{31-4} = 0xf57ff04;
3103 let Inst{3-0} = opt;
3106 // ISB has only full system option -- for disassembly only
3107 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3108 Requires<[IsARM, HasDB]> {
3109 let Inst{31-4} = 0xf57ff06;
3110 let Inst{3-0} = 0b1111;
3113 let usesCustomInserter = 1 in {
3114 let Uses = [CPSR] in {
3115 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3116 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3117 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3118 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3119 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3120 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3121 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3122 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3123 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3124 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3125 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3126 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3127 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3128 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3129 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3130 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3131 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3132 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3133 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3134 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3135 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3136 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3137 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3138 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3139 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3140 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3141 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3142 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3143 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3144 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3145 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3146 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3147 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3148 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3149 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3150 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3151 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3152 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3153 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3154 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3155 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3156 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3157 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3158 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3159 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3160 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3161 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3162 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3163 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3164 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3165 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3166 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3167 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3168 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3170 def ATOMIC_SWAP_I8 : PseudoInst<
3171 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3172 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3173 def ATOMIC_SWAP_I16 : PseudoInst<
3174 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3175 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3176 def ATOMIC_SWAP_I32 : PseudoInst<
3177 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3178 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3180 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3181 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3182 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3183 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3184 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3185 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3186 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3187 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3188 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3192 let mayLoad = 1 in {
3193 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3194 "ldrexb", "\t$Rt, [$Rn]",
3196 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3197 "ldrexh", "\t$Rt, [$Rn]",
3199 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3200 "ldrex", "\t$Rt, [$Rn]",
3202 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3204 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3208 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3209 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3211 "strexb", "\t$Rd, $src, [$Rn]",
3213 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3215 "strexh", "\t$Rd, $Rt, [$Rn]",
3217 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3219 "strex", "\t$Rd, $Rt, [$Rn]",
3221 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3222 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3224 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3228 // Clear-Exclusive is for disassembly only.
3229 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3230 [/* For disassembly only; pattern left blank */]>,
3231 Requires<[IsARM, HasV7]> {
3232 let Inst{31-0} = 0b11110101011111111111000000011111;
3235 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3236 let mayLoad = 1 in {
3237 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3238 [/* For disassembly only; pattern left blank */]>;
3239 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3240 [/* For disassembly only; pattern left blank */]>;
3243 //===----------------------------------------------------------------------===//
3247 // __aeabi_read_tp preserves the registers r1-r3.
3248 // FIXME: This needs to be a pseudo of some sort so that we can get the
3249 // encoding right, complete with fixup for the aeabi_read_tp function.
3251 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3252 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
3253 "bl\t__aeabi_read_tp",
3254 [(set R0, ARMthread_pointer)]>;
3257 //===----------------------------------------------------------------------===//
3258 // SJLJ Exception handling intrinsics
3259 // eh_sjlj_setjmp() is an instruction sequence to store the return
3260 // address and save #0 in R0 for the non-longjmp case.
3261 // Since by its nature we may be coming from some other function to get
3262 // here, and we're using the stack frame for the containing function to
3263 // save/restore registers, we can't keep anything live in regs across
3264 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3265 // when we get here from a longjmp(). We force everthing out of registers
3266 // except for our own input by listing the relevant registers in Defs. By
3267 // doing so, we also cause the prologue/epilogue code to actively preserve
3268 // all of the callee-saved resgisters, which is exactly what we want.
3269 // A constant value is passed in $val, and we use the location as a scratch.
3271 // These are pseudo-instructions and are lowered to individual MC-insts, so
3272 // no encoding information is necessary.
3274 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3275 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3276 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3277 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3278 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3280 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3281 Requires<[IsARM, HasVFP2]>;
3285 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3286 hasSideEffects = 1, isBarrier = 1 in {
3287 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3289 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3290 Requires<[IsARM, NoVFP]>;
3293 // FIXME: Non-Darwin version(s)
3294 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3295 Defs = [ R7, LR, SP ] in {
3296 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3298 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3299 Requires<[IsARM, IsDarwin]>;
3302 // eh.sjlj.dispatchsetup pseudo-instruction.
3303 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3304 // handled when the pseudo is expanded (which happens before any passes
3305 // that need the instruction size).
3306 let isBarrier = 1, hasSideEffects = 1 in
3307 def Int_eh_sjlj_dispatchsetup :
3308 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3309 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3310 Requires<[IsDarwin]>;
3312 //===----------------------------------------------------------------------===//
3313 // Non-Instruction Patterns
3316 // Large immediate handling.
3318 // 32-bit immediate using two piece so_imms or movw + movt.
3319 // This is a single pseudo instruction, the benefit is that it can be remat'd
3320 // as a single unit instead of having to handle reg inputs.
3321 // FIXME: Remove this when we can do generalized remat.
3322 let isReMaterializable = 1, isMoveImm = 1 in
3323 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3324 [(set GPR:$dst, (arm_i32imm:$src))]>,
3327 // ConstantPool, GlobalAddress, and JumpTable
3328 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3329 Requires<[IsARM, DontUseMovt]>;
3330 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3331 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3332 Requires<[IsARM, UseMovt]>;
3333 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3334 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3336 // TODO: add,sub,and, 3-instr forms?
3339 def : ARMPat<(ARMtcret tcGPR:$dst),
3340 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3342 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3343 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3345 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3346 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3348 def : ARMPat<(ARMtcret tcGPR:$dst),
3349 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3351 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3352 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3354 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3355 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3358 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3359 Requires<[IsARM, IsNotDarwin]>;
3360 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3361 Requires<[IsARM, IsDarwin]>;
3363 // zextload i1 -> zextload i8
3364 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3365 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3367 // extload -> zextload
3368 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3369 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3370 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3371 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3373 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3375 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3376 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3379 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3380 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3381 (SMULBB GPR:$a, GPR:$b)>;
3382 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3383 (SMULBB GPR:$a, GPR:$b)>;
3384 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3385 (sra GPR:$b, (i32 16))),
3386 (SMULBT GPR:$a, GPR:$b)>;
3387 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3388 (SMULBT GPR:$a, GPR:$b)>;
3389 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3390 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3391 (SMULTB GPR:$a, GPR:$b)>;
3392 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3393 (SMULTB GPR:$a, GPR:$b)>;
3394 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3396 (SMULWB GPR:$a, GPR:$b)>;
3397 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3398 (SMULWB GPR:$a, GPR:$b)>;
3400 def : ARMV5TEPat<(add GPR:$acc,
3401 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3402 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3403 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3404 def : ARMV5TEPat<(add GPR:$acc,
3405 (mul sext_16_node:$a, sext_16_node:$b)),
3406 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3407 def : ARMV5TEPat<(add GPR:$acc,
3408 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3409 (sra GPR:$b, (i32 16)))),
3410 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3411 def : ARMV5TEPat<(add GPR:$acc,
3412 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3413 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3414 def : ARMV5TEPat<(add GPR:$acc,
3415 (mul (sra GPR:$a, (i32 16)),
3416 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3417 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3418 def : ARMV5TEPat<(add GPR:$acc,
3419 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3420 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3421 def : ARMV5TEPat<(add GPR:$acc,
3422 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3424 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3425 def : ARMV5TEPat<(add GPR:$acc,
3426 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3427 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3429 //===----------------------------------------------------------------------===//
3433 include "ARMInstrThumb.td"
3435 //===----------------------------------------------------------------------===//
3439 include "ARMInstrThumb2.td"
3441 //===----------------------------------------------------------------------===//
3442 // Floating Point Support
3445 include "ARMInstrVFP.td"
3447 //===----------------------------------------------------------------------===//
3448 // Advanced SIMD (NEON) Support
3451 include "ARMInstrNEON.td"
3453 //===----------------------------------------------------------------------===//
3454 // Coprocessor Instructions. For disassembly only.
3457 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3458 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3459 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3460 [/* For disassembly only; pattern left blank */]> {
3464 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3465 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3466 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3467 [/* For disassembly only; pattern left blank */]> {
3468 let Inst{31-28} = 0b1111;
3472 class ACI<dag oops, dag iops, string opc, string asm>
3473 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3474 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3475 let Inst{27-25} = 0b110;
3478 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3480 def _OFFSET : ACI<(outs),
3481 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3482 opc, "\tp$cop, cr$CRd, $addr"> {
3483 let Inst{31-28} = op31_28;
3484 let Inst{24} = 1; // P = 1
3485 let Inst{21} = 0; // W = 0
3486 let Inst{22} = 0; // D = 0
3487 let Inst{20} = load;
3490 def _PRE : ACI<(outs),
3491 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3492 opc, "\tp$cop, cr$CRd, $addr!"> {
3493 let Inst{31-28} = op31_28;
3494 let Inst{24} = 1; // P = 1
3495 let Inst{21} = 1; // W = 1
3496 let Inst{22} = 0; // D = 0
3497 let Inst{20} = load;
3500 def _POST : ACI<(outs),
3501 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3502 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3503 let Inst{31-28} = op31_28;
3504 let Inst{24} = 0; // P = 0
3505 let Inst{21} = 1; // W = 1
3506 let Inst{22} = 0; // D = 0
3507 let Inst{20} = load;
3510 def _OPTION : ACI<(outs),
3511 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3512 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3513 let Inst{31-28} = op31_28;
3514 let Inst{24} = 0; // P = 0
3515 let Inst{23} = 1; // U = 1
3516 let Inst{21} = 0; // W = 0
3517 let Inst{22} = 0; // D = 0
3518 let Inst{20} = load;
3521 def L_OFFSET : ACI<(outs),
3522 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3523 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3524 let Inst{31-28} = op31_28;
3525 let Inst{24} = 1; // P = 1
3526 let Inst{21} = 0; // W = 0
3527 let Inst{22} = 1; // D = 1
3528 let Inst{20} = load;
3531 def L_PRE : ACI<(outs),
3532 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3533 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3534 let Inst{31-28} = op31_28;
3535 let Inst{24} = 1; // P = 1
3536 let Inst{21} = 1; // W = 1
3537 let Inst{22} = 1; // D = 1
3538 let Inst{20} = load;
3541 def L_POST : ACI<(outs),
3542 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3543 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3544 let Inst{31-28} = op31_28;
3545 let Inst{24} = 0; // P = 0
3546 let Inst{21} = 1; // W = 1
3547 let Inst{22} = 1; // D = 1
3548 let Inst{20} = load;
3551 def L_OPTION : ACI<(outs),
3552 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3553 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3554 let Inst{31-28} = op31_28;
3555 let Inst{24} = 0; // P = 0
3556 let Inst{23} = 1; // U = 1
3557 let Inst{21} = 0; // W = 0
3558 let Inst{22} = 1; // D = 1
3559 let Inst{20} = load;
3563 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3564 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3565 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3566 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3568 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3569 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3570 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3571 [/* For disassembly only; pattern left blank */]> {
3576 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3577 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3578 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3579 [/* For disassembly only; pattern left blank */]> {
3580 let Inst{31-28} = 0b1111;
3585 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3586 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3587 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3588 [/* For disassembly only; pattern left blank */]> {
3593 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3594 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3595 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3596 [/* For disassembly only; pattern left blank */]> {
3597 let Inst{31-28} = 0b1111;
3602 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3603 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3604 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3605 [/* For disassembly only; pattern left blank */]> {
3606 let Inst{23-20} = 0b0100;
3609 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3610 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3611 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3612 [/* For disassembly only; pattern left blank */]> {
3613 let Inst{31-28} = 0b1111;
3614 let Inst{23-20} = 0b0100;
3617 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3618 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3619 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3620 [/* For disassembly only; pattern left blank */]> {
3621 let Inst{23-20} = 0b0101;
3624 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3625 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3626 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3627 [/* For disassembly only; pattern left blank */]> {
3628 let Inst{31-28} = 0b1111;
3629 let Inst{23-20} = 0b0101;
3632 //===----------------------------------------------------------------------===//
3633 // Move between special register and ARM core register -- for disassembly only
3636 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3637 [/* For disassembly only; pattern left blank */]> {
3638 let Inst{23-20} = 0b0000;
3639 let Inst{7-4} = 0b0000;
3642 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3643 [/* For disassembly only; pattern left blank */]> {
3644 let Inst{23-20} = 0b0100;
3645 let Inst{7-4} = 0b0000;
3648 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3649 "msr", "\tcpsr$mask, $src",
3650 [/* For disassembly only; pattern left blank */]> {
3651 let Inst{23-20} = 0b0010;
3652 let Inst{7-4} = 0b0000;
3655 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3656 "msr", "\tcpsr$mask, $a",
3657 [/* For disassembly only; pattern left blank */]> {
3658 let Inst{23-20} = 0b0010;
3659 let Inst{7-4} = 0b0000;
3662 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3663 "msr", "\tspsr$mask, $src",
3664 [/* For disassembly only; pattern left blank */]> {
3665 let Inst{23-20} = 0b0110;
3666 let Inst{7-4} = 0b0000;
3669 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3670 "msr", "\tspsr$mask, $a",
3671 [/* For disassembly only; pattern left blank */]> {
3672 let Inst{23-20} = 0b0110;
3673 let Inst{7-4} = 0b0000;