1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
73 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
74 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
76 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
77 [SDNPHasChain, SDNPOutGlue]>;
78 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
81 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
84 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
91 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
92 [SDNPHasChain, SDNPOptInGlue]>;
94 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutGlue, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
153 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
154 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
155 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
156 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
157 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
158 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
159 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
160 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
161 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
162 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
164 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
166 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
168 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
169 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
170 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
171 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
172 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
173 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
174 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
175 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
177 // FIXME: Eventually this will be just "hasV6T2Ops".
178 def UseMovt : Predicate<"Subtarget->useMovt()">;
179 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
180 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
182 //===----------------------------------------------------------------------===//
183 // ARM Flag Definitions.
185 class RegConstraint<string C> {
186 string Constraints = C;
189 //===----------------------------------------------------------------------===//
190 // ARM specific transformation functions and pattern fragments.
193 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_neg def below.
195 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
199 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
200 // so_imm_not def below.
201 def so_imm_not_XFORM : SDNodeXForm<imm, [{
202 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
205 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
206 def imm1_15 : PatLeaf<(i32 imm), [{
207 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
210 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
211 def imm16_31 : PatLeaf<(i32 imm), [{
212 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
217 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
218 }], so_imm_neg_XFORM>;
222 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
223 }], so_imm_not_XFORM>;
225 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
226 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
227 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
230 /// Split a 32-bit immediate into two 16 bit parts.
231 def hi16 : SDNodeXForm<imm, [{
232 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
235 def lo16AllZero : PatLeaf<(i32 imm), [{
236 // Returns true if all low 16-bits are 0.
237 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
240 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
242 def imm0_65535 : PatLeaf<(i32 imm), [{
243 return (uint32_t)N->getZExtValue() < 65536;
246 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
247 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
249 /// adde and sube predicates - True based on whether the carry flag output
250 /// will be needed or not.
251 def adde_dead_carry :
252 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
253 [{return !N->hasAnyUseOfValue(1);}]>;
254 def sube_dead_carry :
255 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
256 [{return !N->hasAnyUseOfValue(1);}]>;
257 def adde_live_carry :
258 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
259 [{return N->hasAnyUseOfValue(1);}]>;
260 def sube_live_carry :
261 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
262 [{return N->hasAnyUseOfValue(1);}]>;
264 // An 'and' node with a single use.
265 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
266 return N->hasOneUse();
269 // An 'xor' node with a single use.
270 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
271 return N->hasOneUse();
274 // An 'fmul' node with a single use.
275 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
276 return N->hasOneUse();
279 // An 'fadd' node which checks for single non-hazardous use.
280 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
281 return hasNoVMLxHazardUse(N);
284 // An 'fsub' node which checks for single non-hazardous use.
285 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
286 return hasNoVMLxHazardUse(N);
289 //===----------------------------------------------------------------------===//
290 // Operand Definitions.
294 // FIXME: rename brtarget to t2_brtarget
295 def brtarget : Operand<OtherVT> {
296 let EncoderMethod = "getBranchTargetOpValue";
299 // FIXME: get rid of this one?
300 def uncondbrtarget : Operand<OtherVT> {
301 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
304 // Branch target for ARM. Handles conditional/unconditional
305 def br_target : Operand<OtherVT> {
306 let EncoderMethod = "getARMBranchTargetOpValue";
310 // FIXME: rename bltarget to t2_bl_target?
311 def bltarget : Operand<i32> {
312 // Encoded the same as branch targets.
313 let EncoderMethod = "getBranchTargetOpValue";
316 // Call target for ARM. Handles conditional/unconditional
317 // FIXME: rename bl_target to t2_bltarget?
318 def bl_target : Operand<i32> {
319 // Encoded the same as branch targets.
320 let EncoderMethod = "getARMBranchTargetOpValue";
324 // A list of registers separated by comma. Used by load/store multiple.
325 def RegListAsmOperand : AsmOperandClass {
326 let Name = "RegList";
327 let SuperClasses = [];
330 def DPRRegListAsmOperand : AsmOperandClass {
331 let Name = "DPRRegList";
332 let SuperClasses = [];
335 def SPRRegListAsmOperand : AsmOperandClass {
336 let Name = "SPRRegList";
337 let SuperClasses = [];
340 def reglist : Operand<i32> {
341 let EncoderMethod = "getRegisterListOpValue";
342 let ParserMatchClass = RegListAsmOperand;
343 let PrintMethod = "printRegisterList";
346 def dpr_reglist : Operand<i32> {
347 let EncoderMethod = "getRegisterListOpValue";
348 let ParserMatchClass = DPRRegListAsmOperand;
349 let PrintMethod = "printRegisterList";
352 def spr_reglist : Operand<i32> {
353 let EncoderMethod = "getRegisterListOpValue";
354 let ParserMatchClass = SPRRegListAsmOperand;
355 let PrintMethod = "printRegisterList";
358 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
359 def cpinst_operand : Operand<i32> {
360 let PrintMethod = "printCPInstOperand";
364 def pclabel : Operand<i32> {
365 let PrintMethod = "printPCLabel";
368 // ADR instruction labels.
369 def adrlabel : Operand<i32> {
370 let EncoderMethod = "getAdrLabelOpValue";
373 def neon_vcvt_imm32 : Operand<i32> {
374 let EncoderMethod = "getNEONVcvtImm32OpValue";
377 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
378 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
379 int32_t v = (int32_t)N->getZExtValue();
380 return v == 8 || v == 16 || v == 24; }]> {
381 let EncoderMethod = "getRotImmOpValue";
384 def ShifterAsmOperand : AsmOperandClass {
385 let Name = "Shifter";
386 let SuperClasses = [];
389 // shift_imm: An integer that encodes a shift amount and the type of shift
390 // (currently either asr or lsl) using the same encoding used for the
391 // immediates in so_reg operands.
392 def shift_imm : Operand<i32> {
393 let PrintMethod = "printShiftImmOperand";
394 let ParserMatchClass = ShifterAsmOperand;
397 // shifter_operand operands: so_reg and so_imm.
398 def so_reg : Operand<i32>, // reg reg imm
399 ComplexPattern<i32, 3, "SelectShifterOperandReg",
400 [shl,srl,sra,rotr]> {
401 let EncoderMethod = "getSORegOpValue";
402 let PrintMethod = "printSORegOperand";
403 let MIOperandInfo = (ops GPR, GPR, shift_imm);
405 def shift_so_reg : Operand<i32>, // reg reg imm
406 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
407 [shl,srl,sra,rotr]> {
408 let EncoderMethod = "getSORegOpValue";
409 let PrintMethod = "printSORegOperand";
410 let MIOperandInfo = (ops GPR, GPR, shift_imm);
413 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
414 // 8-bit immediate rotated by an arbitrary number of bits.
415 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
416 let EncoderMethod = "getSOImmOpValue";
417 let PrintMethod = "printSOImmOperand";
420 // Break so_imm's up into two pieces. This handles immediates with up to 16
421 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
422 // get the first/second pieces.
423 def so_imm2part : PatLeaf<(imm), [{
424 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
427 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
429 def arm_i32imm : PatLeaf<(imm), [{
430 if (Subtarget->hasV6T2Ops())
432 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
435 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
436 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
437 return (int32_t)N->getZExtValue() < 32;
440 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
441 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
442 return (int32_t)N->getZExtValue() < 32;
444 let EncoderMethod = "getImmMinusOneOpValue";
447 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
448 // The imm is split into imm{15-12}, imm{11-0}
450 def i32imm_hilo16 : Operand<i32> {
451 let EncoderMethod = "getHiLo16ImmOpValue";
454 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
456 def bf_inv_mask_imm : Operand<i32>,
458 return ARM::isBitFieldInvertedMask(N->getZExtValue());
460 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
461 let PrintMethod = "printBitfieldInvMaskImmOperand";
464 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
465 def lsb_pos_imm : Operand<i32>, PatLeaf<(imm), [{
466 return isInt<5>(N->getSExtValue());
469 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
470 def width_imm : Operand<i32>, PatLeaf<(imm), [{
471 return N->getSExtValue() > 0 && N->getSExtValue() <= 32;
473 let EncoderMethod = "getMsbOpValue";
476 // Define ARM specific addressing modes.
479 // addrmode_imm12 := reg +/- imm12
481 def addrmode_imm12 : Operand<i32>,
482 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
483 // 12-bit immediate operand. Note that instructions using this encode
484 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
485 // immediate values are as normal.
487 let EncoderMethod = "getAddrModeImm12OpValue";
488 let PrintMethod = "printAddrModeImm12Operand";
489 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
491 // ldst_so_reg := reg +/- reg shop imm
493 def ldst_so_reg : Operand<i32>,
494 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
495 let EncoderMethod = "getLdStSORegOpValue";
496 // FIXME: Simplify the printer
497 let PrintMethod = "printAddrMode2Operand";
498 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
501 // addrmode2 := reg +/- imm12
502 // := reg +/- reg shop imm
504 def addrmode2 : Operand<i32>,
505 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
506 let EncoderMethod = "getAddrMode2OpValue";
507 let PrintMethod = "printAddrMode2Operand";
508 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
511 def am2offset : Operand<i32>,
512 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
513 [], [SDNPWantRoot]> {
514 let EncoderMethod = "getAddrMode2OffsetOpValue";
515 let PrintMethod = "printAddrMode2OffsetOperand";
516 let MIOperandInfo = (ops GPR, i32imm);
519 // addrmode3 := reg +/- reg
520 // addrmode3 := reg +/- imm8
522 def addrmode3 : Operand<i32>,
523 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
524 let EncoderMethod = "getAddrMode3OpValue";
525 let PrintMethod = "printAddrMode3Operand";
526 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
529 def am3offset : Operand<i32>,
530 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
531 [], [SDNPWantRoot]> {
532 let EncoderMethod = "getAddrMode3OffsetOpValue";
533 let PrintMethod = "printAddrMode3OffsetOperand";
534 let MIOperandInfo = (ops GPR, i32imm);
537 // ldstm_mode := {ia, ib, da, db}
539 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
540 let EncoderMethod = "getLdStmModeOpValue";
541 let PrintMethod = "printLdStmModeOperand";
544 def MemMode5AsmOperand : AsmOperandClass {
545 let Name = "MemMode5";
546 let SuperClasses = [];
549 // addrmode5 := reg +/- imm8*4
551 def addrmode5 : Operand<i32>,
552 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
553 let PrintMethod = "printAddrMode5Operand";
554 let MIOperandInfo = (ops GPR:$base, i32imm);
555 let ParserMatchClass = MemMode5AsmOperand;
556 let EncoderMethod = "getAddrMode5OpValue";
559 // addrmode6 := reg with optional alignment
561 def addrmode6 : Operand<i32>,
562 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
563 let PrintMethod = "printAddrMode6Operand";
564 let MIOperandInfo = (ops GPR:$addr, i32imm);
565 let EncoderMethod = "getAddrMode6AddressOpValue";
568 def am6offset : Operand<i32>,
569 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
570 [], [SDNPWantRoot]> {
571 let PrintMethod = "printAddrMode6OffsetOperand";
572 let MIOperandInfo = (ops GPR);
573 let EncoderMethod = "getAddrMode6OffsetOpValue";
576 // Special version of addrmode6 to handle alignment encoding for VLD-dup
577 // instructions, specifically VLD4-dup.
578 def addrmode6dup : Operand<i32>,
579 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
580 let PrintMethod = "printAddrMode6Operand";
581 let MIOperandInfo = (ops GPR:$addr, i32imm);
582 let EncoderMethod = "getAddrMode6DupAddressOpValue";
585 // addrmodepc := pc + reg
587 def addrmodepc : Operand<i32>,
588 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
589 let PrintMethod = "printAddrModePCOperand";
590 let MIOperandInfo = (ops GPR, i32imm);
593 def nohash_imm : Operand<i32> {
594 let PrintMethod = "printNoHashImmediate";
597 def CoprocNumAsmOperand : AsmOperandClass {
598 let Name = "CoprocNum";
599 let SuperClasses = [];
600 let ParserMethod = "tryParseCoprocNumOperand";
603 def CoprocRegAsmOperand : AsmOperandClass {
604 let Name = "CoprocReg";
605 let SuperClasses = [];
606 let ParserMethod = "tryParseCoprocRegOperand";
609 def p_imm : Operand<i32> {
610 let PrintMethod = "printPImmediate";
611 let ParserMatchClass = CoprocNumAsmOperand;
614 def c_imm : Operand<i32> {
615 let PrintMethod = "printCImmediate";
616 let ParserMatchClass = CoprocRegAsmOperand;
619 //===----------------------------------------------------------------------===//
621 include "ARMInstrFormats.td"
623 //===----------------------------------------------------------------------===//
624 // Multiclass helpers...
627 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
628 /// binop that produces a value.
629 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
630 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
631 PatFrag opnode, bit Commutable = 0> {
632 // The register-immediate version is re-materializable. This is useful
633 // in particular for taking the address of a local.
634 let isReMaterializable = 1 in {
635 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
636 iii, opc, "\t$Rd, $Rn, $imm",
637 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
642 let Inst{19-16} = Rn;
643 let Inst{15-12} = Rd;
644 let Inst{11-0} = imm;
647 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
648 iir, opc, "\t$Rd, $Rn, $Rm",
649 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
654 let isCommutable = Commutable;
655 let Inst{19-16} = Rn;
656 let Inst{15-12} = Rd;
657 let Inst{11-4} = 0b00000000;
660 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
661 iis, opc, "\t$Rd, $Rn, $shift",
662 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
667 let Inst{19-16} = Rn;
668 let Inst{15-12} = Rd;
669 let Inst{11-0} = shift;
673 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
674 /// instruction modifies the CPSR register.
675 let isCodeGenOnly = 1, Defs = [CPSR] in {
676 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
677 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
678 PatFrag opnode, bit Commutable = 0> {
679 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
680 iii, opc, "\t$Rd, $Rn, $imm",
681 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
687 let Inst{19-16} = Rn;
688 let Inst{15-12} = Rd;
689 let Inst{11-0} = imm;
691 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
692 iir, opc, "\t$Rd, $Rn, $Rm",
693 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
697 let isCommutable = Commutable;
700 let Inst{19-16} = Rn;
701 let Inst{15-12} = Rd;
702 let Inst{11-4} = 0b00000000;
705 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
706 iis, opc, "\t$Rd, $Rn, $shift",
707 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
713 let Inst{19-16} = Rn;
714 let Inst{15-12} = Rd;
715 let Inst{11-0} = shift;
720 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
721 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
722 /// a explicit result, only implicitly set CPSR.
723 let isCompare = 1, Defs = [CPSR] in {
724 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
725 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
726 PatFrag opnode, bit Commutable = 0> {
727 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
729 [(opnode GPR:$Rn, so_imm:$imm)]> {
734 let Inst{19-16} = Rn;
735 let Inst{15-12} = 0b0000;
736 let Inst{11-0} = imm;
738 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
740 [(opnode GPR:$Rn, GPR:$Rm)]> {
743 let isCommutable = Commutable;
746 let Inst{19-16} = Rn;
747 let Inst{15-12} = 0b0000;
748 let Inst{11-4} = 0b00000000;
751 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
752 opc, "\t$Rn, $shift",
753 [(opnode GPR:$Rn, so_reg:$shift)]> {
758 let Inst{19-16} = Rn;
759 let Inst{15-12} = 0b0000;
760 let Inst{11-0} = shift;
765 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
766 /// register and one whose operand is a register rotated by 8/16/24.
767 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
768 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
769 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
770 IIC_iEXTr, opc, "\t$Rd, $Rm",
771 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
772 Requires<[IsARM, HasV6]> {
775 let Inst{19-16} = 0b1111;
776 let Inst{15-12} = Rd;
777 let Inst{11-10} = 0b00;
780 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
781 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
782 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
783 Requires<[IsARM, HasV6]> {
787 let Inst{19-16} = 0b1111;
788 let Inst{15-12} = Rd;
789 let Inst{11-10} = rot;
794 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
795 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
796 IIC_iEXTr, opc, "\t$Rd, $Rm",
797 [/* For disassembly only; pattern left blank */]>,
798 Requires<[IsARM, HasV6]> {
799 let Inst{19-16} = 0b1111;
800 let Inst{11-10} = 0b00;
802 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
803 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
804 [/* For disassembly only; pattern left blank */]>,
805 Requires<[IsARM, HasV6]> {
807 let Inst{19-16} = 0b1111;
808 let Inst{11-10} = rot;
812 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
813 /// register and one whose operand is a register rotated by 8/16/24.
814 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
815 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
816 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
817 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
818 Requires<[IsARM, HasV6]> {
822 let Inst{19-16} = Rn;
823 let Inst{15-12} = Rd;
824 let Inst{11-10} = 0b00;
825 let Inst{9-4} = 0b000111;
828 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
830 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
831 [(set GPR:$Rd, (opnode GPR:$Rn,
832 (rotr GPR:$Rm, rot_imm:$rot)))]>,
833 Requires<[IsARM, HasV6]> {
838 let Inst{19-16} = Rn;
839 let Inst{15-12} = Rd;
840 let Inst{11-10} = rot;
841 let Inst{9-4} = 0b000111;
846 // For disassembly only.
847 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
848 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
849 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
850 [/* For disassembly only; pattern left blank */]>,
851 Requires<[IsARM, HasV6]> {
852 let Inst{11-10} = 0b00;
854 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
856 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
857 [/* For disassembly only; pattern left blank */]>,
858 Requires<[IsARM, HasV6]> {
861 let Inst{19-16} = Rn;
862 let Inst{11-10} = rot;
866 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
867 let Uses = [CPSR] in {
868 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
869 bit Commutable = 0> {
870 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
871 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
872 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
878 let Inst{15-12} = Rd;
879 let Inst{19-16} = Rn;
880 let Inst{11-0} = imm;
882 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
883 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
884 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
889 let Inst{11-4} = 0b00000000;
891 let isCommutable = Commutable;
893 let Inst{15-12} = Rd;
894 let Inst{19-16} = Rn;
896 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
897 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
898 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
904 let Inst{11-0} = shift;
905 let Inst{15-12} = Rd;
906 let Inst{19-16} = Rn;
909 // Carry setting variants
910 let isCodeGenOnly = 1, Defs = [CPSR] in {
911 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
912 bit Commutable = 0> {
913 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
914 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
915 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
920 let Inst{15-12} = Rd;
921 let Inst{19-16} = Rn;
922 let Inst{11-0} = imm;
926 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
927 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
928 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
933 let Inst{11-4} = 0b00000000;
934 let isCommutable = Commutable;
936 let Inst{15-12} = Rd;
937 let Inst{19-16} = Rn;
941 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
942 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
943 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
948 let Inst{11-0} = shift;
949 let Inst{15-12} = Rd;
950 let Inst{19-16} = Rn;
958 let canFoldAsLoad = 1, isReMaterializable = 1 in {
959 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
960 InstrItinClass iir, PatFrag opnode> {
961 // Note: We use the complex addrmode_imm12 rather than just an input
962 // GPR and a constrained immediate so that we can use this to match
963 // frame index references and avoid matching constant pool references.
964 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
965 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
966 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
969 let Inst{23} = addr{12}; // U (add = ('U' == 1))
970 let Inst{19-16} = addr{16-13}; // Rn
971 let Inst{15-12} = Rt;
972 let Inst{11-0} = addr{11-0}; // imm12
974 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
975 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
976 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
979 let Inst{23} = shift{12}; // U (add = ('U' == 1))
980 let Inst{19-16} = shift{16-13}; // Rn
981 let Inst{15-12} = Rt;
982 let Inst{11-0} = shift{11-0};
987 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
988 InstrItinClass iir, PatFrag opnode> {
989 // Note: We use the complex addrmode_imm12 rather than just an input
990 // GPR and a constrained immediate so that we can use this to match
991 // frame index references and avoid matching constant pool references.
992 def i12 : AI2ldst<0b010, 0, isByte, (outs),
993 (ins GPR:$Rt, addrmode_imm12:$addr),
994 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
995 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
998 let Inst{23} = addr{12}; // U (add = ('U' == 1))
999 let Inst{19-16} = addr{16-13}; // Rn
1000 let Inst{15-12} = Rt;
1001 let Inst{11-0} = addr{11-0}; // imm12
1003 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1004 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1005 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1008 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1009 let Inst{19-16} = shift{16-13}; // Rn
1010 let Inst{15-12} = Rt;
1011 let Inst{11-0} = shift{11-0};
1014 //===----------------------------------------------------------------------===//
1016 //===----------------------------------------------------------------------===//
1018 //===----------------------------------------------------------------------===//
1019 // Miscellaneous Instructions.
1022 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1023 /// the function. The first operand is the ID# for this instruction, the second
1024 /// is the index into the MachineConstantPool that this is, the third is the
1025 /// size in bytes of this constant pool entry.
1026 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1027 def CONSTPOOL_ENTRY :
1028 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1029 i32imm:$size), NoItinerary, []>;
1031 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1032 // from removing one half of the matched pairs. That breaks PEI, which assumes
1033 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1034 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1035 def ADJCALLSTACKUP :
1036 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1037 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1039 def ADJCALLSTACKDOWN :
1040 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1041 [(ARMcallseq_start timm:$amt)]>;
1044 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1045 [/* For disassembly only; pattern left blank */]>,
1046 Requires<[IsARM, HasV6T2]> {
1047 let Inst{27-16} = 0b001100100000;
1048 let Inst{15-8} = 0b11110000;
1049 let Inst{7-0} = 0b00000000;
1052 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1053 [/* For disassembly only; pattern left blank */]>,
1054 Requires<[IsARM, HasV6T2]> {
1055 let Inst{27-16} = 0b001100100000;
1056 let Inst{15-8} = 0b11110000;
1057 let Inst{7-0} = 0b00000001;
1060 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1061 [/* For disassembly only; pattern left blank */]>,
1062 Requires<[IsARM, HasV6T2]> {
1063 let Inst{27-16} = 0b001100100000;
1064 let Inst{15-8} = 0b11110000;
1065 let Inst{7-0} = 0b00000010;
1068 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1069 [/* For disassembly only; pattern left blank */]>,
1070 Requires<[IsARM, HasV6T2]> {
1071 let Inst{27-16} = 0b001100100000;
1072 let Inst{15-8} = 0b11110000;
1073 let Inst{7-0} = 0b00000011;
1076 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1078 [/* For disassembly only; pattern left blank */]>,
1079 Requires<[IsARM, HasV6]> {
1084 let Inst{15-12} = Rd;
1085 let Inst{19-16} = Rn;
1086 let Inst{27-20} = 0b01101000;
1087 let Inst{7-4} = 0b1011;
1088 let Inst{11-8} = 0b1111;
1091 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1092 [/* For disassembly only; pattern left blank */]>,
1093 Requires<[IsARM, HasV6T2]> {
1094 let Inst{27-16} = 0b001100100000;
1095 let Inst{15-8} = 0b11110000;
1096 let Inst{7-0} = 0b00000100;
1099 // The i32imm operand $val can be used by a debugger to store more information
1100 // about the breakpoint.
1101 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1102 [/* For disassembly only; pattern left blank */]>,
1105 let Inst{3-0} = val{3-0};
1106 let Inst{19-8} = val{15-4};
1107 let Inst{27-20} = 0b00010010;
1108 let Inst{7-4} = 0b0111;
1111 // Change Processor State is a system instruction -- for disassembly and
1113 // FIXME: Since the asm parser has currently no clean way to handle optional
1114 // operands, create 3 versions of the same instruction. Once there's a clean
1115 // framework to represent optional operands, change this behavior.
1116 class CPS<dag iops, string asm_ops>
1117 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1118 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1124 let Inst{31-28} = 0b1111;
1125 let Inst{27-20} = 0b00010000;
1126 let Inst{19-18} = imod;
1127 let Inst{17} = M; // Enabled if mode is set;
1129 let Inst{8-6} = iflags;
1131 let Inst{4-0} = mode;
1135 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1136 "$imod\t$iflags, $mode">;
1137 let mode = 0, M = 0 in
1138 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1140 let imod = 0, iflags = 0, M = 1 in
1141 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1143 // Preload signals the memory system of possible future data/instruction access.
1144 // These are for disassembly only.
1145 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1147 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1148 !strconcat(opc, "\t$addr"),
1149 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1152 let Inst{31-26} = 0b111101;
1153 let Inst{25} = 0; // 0 for immediate form
1154 let Inst{24} = data;
1155 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1156 let Inst{22} = read;
1157 let Inst{21-20} = 0b01;
1158 let Inst{19-16} = addr{16-13}; // Rn
1159 let Inst{15-12} = 0b1111;
1160 let Inst{11-0} = addr{11-0}; // imm12
1163 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1164 !strconcat(opc, "\t$shift"),
1165 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1167 let Inst{31-26} = 0b111101;
1168 let Inst{25} = 1; // 1 for register form
1169 let Inst{24} = data;
1170 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1171 let Inst{22} = read;
1172 let Inst{21-20} = 0b01;
1173 let Inst{19-16} = shift{16-13}; // Rn
1174 let Inst{15-12} = 0b1111;
1175 let Inst{11-0} = shift{11-0};
1179 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1180 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1181 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1183 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1185 [/* For disassembly only; pattern left blank */]>,
1188 let Inst{31-10} = 0b1111000100000001000000;
1193 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1194 [/* For disassembly only; pattern left blank */]>,
1195 Requires<[IsARM, HasV7]> {
1197 let Inst{27-4} = 0b001100100000111100001111;
1198 let Inst{3-0} = opt;
1201 // A5.4 Permanently UNDEFINED instructions.
1202 let isBarrier = 1, isTerminator = 1 in
1203 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1206 let Inst = 0xe7ffdefe;
1209 // Address computation and loads and stores in PIC mode.
1210 let isNotDuplicable = 1 in {
1211 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1212 Size4Bytes, IIC_iALUr,
1213 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1215 let AddedComplexity = 10 in {
1216 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1217 Size4Bytes, IIC_iLoad_r,
1218 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1220 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1221 Size4Bytes, IIC_iLoad_bh_r,
1222 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1224 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1225 Size4Bytes, IIC_iLoad_bh_r,
1226 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1228 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1229 Size4Bytes, IIC_iLoad_bh_r,
1230 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1232 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1233 Size4Bytes, IIC_iLoad_bh_r,
1234 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1236 let AddedComplexity = 10 in {
1237 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1238 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1240 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1241 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1242 addrmodepc:$addr)]>;
1244 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1245 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1247 } // isNotDuplicable = 1
1250 // LEApcrel - Load a pc-relative address into a register without offending the
1252 let neverHasSideEffects = 1, isReMaterializable = 1 in
1253 // The 'adr' mnemonic encodes differently if the label is before or after
1254 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1255 // know until then which form of the instruction will be used.
1256 def ADR : AI1<0, (outs GPR:$Rd), (ins adrlabel:$label),
1257 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1260 let Inst{27-25} = 0b001;
1262 let Inst{19-16} = 0b1111;
1263 let Inst{15-12} = Rd;
1264 let Inst{11-0} = label;
1266 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1267 Size4Bytes, IIC_iALUi, []>;
1269 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1270 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1271 Size4Bytes, IIC_iALUi, []>;
1273 //===----------------------------------------------------------------------===//
1274 // Control Flow Instructions.
1277 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1279 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1280 "bx", "\tlr", [(ARMretflag)]>,
1281 Requires<[IsARM, HasV4T]> {
1282 let Inst{27-0} = 0b0001001011111111111100011110;
1286 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1287 "mov", "\tpc, lr", [(ARMretflag)]>,
1288 Requires<[IsARM, NoV4T]> {
1289 let Inst{27-0} = 0b0001101000001111000000001110;
1293 // Indirect branches
1294 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1296 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1297 [(brind GPR:$dst)]>,
1298 Requires<[IsARM, HasV4T]> {
1300 let Inst{31-4} = 0b1110000100101111111111110001;
1301 let Inst{3-0} = dst;
1305 // FIXME: We would really like to define this as a vanilla ARMPat like:
1306 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1307 // With that, however, we can't set isBranch, isTerminator, etc..
1308 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1309 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1310 Requires<[IsARM, NoV4T]>;
1313 // All calls clobber the non-callee saved registers. SP is marked as
1314 // a use to prevent stack-pointer assignments that appear immediately
1315 // before calls from potentially appearing dead.
1317 // On non-Darwin platforms R9 is callee-saved.
1318 // FIXME: Do we really need a non-predicated version? If so, it should
1319 // at least be a pseudo instruction expanding to the predicated version
1320 // at MC lowering time.
1321 Defs = [R0, R1, R2, R3, R12, LR,
1322 D0, D1, D2, D3, D4, D5, D6, D7,
1323 D16, D17, D18, D19, D20, D21, D22, D23,
1324 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1326 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1327 IIC_Br, "bl\t$func",
1328 [(ARMcall tglobaladdr:$func)]>,
1329 Requires<[IsARM, IsNotDarwin]> {
1330 let Inst{31-28} = 0b1110;
1332 let Inst{23-0} = func;
1335 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1336 IIC_Br, "bl", "\t$func",
1337 [(ARMcall_pred tglobaladdr:$func)]>,
1338 Requires<[IsARM, IsNotDarwin]> {
1340 let Inst{23-0} = func;
1344 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1345 IIC_Br, "blx\t$func",
1346 [(ARMcall GPR:$func)]>,
1347 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1349 let Inst{31-4} = 0b1110000100101111111111110011;
1350 let Inst{3-0} = func;
1353 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1354 IIC_Br, "blx", "\t$func",
1355 [(ARMcall_pred GPR:$func)]>,
1356 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1358 let Inst{27-4} = 0b000100101111111111110011;
1359 let Inst{3-0} = func;
1363 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1364 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1365 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1366 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1369 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1370 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1371 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1375 // On Darwin R9 is call-clobbered.
1376 // R7 is marked as a use to prevent frame-pointer assignments from being
1377 // moved above / below calls.
1378 Defs = [R0, R1, R2, R3, R9, R12, LR,
1379 D0, D1, D2, D3, D4, D5, D6, D7,
1380 D16, D17, D18, D19, D20, D21, D22, D23,
1381 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1382 Uses = [R7, SP] in {
1383 def BLr9 : ARMPseudoInst<(outs), (ins bltarget:$func, variable_ops),
1385 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
1387 def BLr9_pred : ARMPseudoInst<(outs),
1388 (ins bltarget:$func, pred:$p, variable_ops),
1390 [(ARMcall_pred tglobaladdr:$func)]>,
1391 Requires<[IsARM, IsDarwin]>;
1394 def BLXr9 : ARMPseudoInst<(outs), (ins GPR:$func, variable_ops),
1396 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]>;
1398 def BLXr9_pred: ARMPseudoInst<(outs), (ins GPR:$func, pred:$p, variable_ops),
1400 [(ARMcall_pred GPR:$func)]>,
1401 Requires<[IsARM, HasV5T, IsDarwin]>;
1404 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1405 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1406 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1407 Requires<[IsARM, HasV4T, IsDarwin]>;
1410 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1411 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1412 Requires<[IsARM, NoV4T, IsDarwin]>;
1417 // FIXME: The Thumb versions of these should live in ARMInstrThumb.td
1418 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1420 let Defs = [R0, R1, R2, R3, R9, R12,
1421 D0, D1, D2, D3, D4, D5, D6, D7,
1422 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1423 D27, D28, D29, D30, D31, PC],
1425 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1426 IIC_Br, []>, Requires<[IsDarwin]>;
1428 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1429 IIC_Br, []>, Requires<[IsDarwin]>;
1431 def TAILJMPd : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1433 []>, Requires<[IsARM, IsDarwin]>;
1435 def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1437 []>, Requires<[IsThumb, IsDarwin]>;
1439 def TAILJMPr : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1441 []>, Requires<[IsARM, IsDarwin]>;
1443 def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1445 []>, Requires<[IsThumb, IsDarwin]>;
1448 // Non-Darwin versions (the difference is R9).
1449 let Defs = [R0, R1, R2, R3, R12,
1450 D0, D1, D2, D3, D4, D5, D6, D7,
1451 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1452 D27, D28, D29, D30, D31, PC],
1454 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1455 IIC_Br, []>, Requires<[IsNotDarwin]>;
1457 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1458 IIC_Br, []>, Requires<[IsNotDarwin]>;
1460 def TAILJMPdND : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1462 []>, Requires<[IsARM, IsNotDarwin]>;
1464 def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1466 []>, Requires<[IsThumb, IsNotDarwin]>;
1468 def TAILJMPrND : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1470 []>, Requires<[IsARM, IsNotDarwin]>;
1471 def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1473 []>, Requires<[IsThumb, IsNotDarwin]>;
1477 let isBranch = 1, isTerminator = 1 in {
1478 // B is "predicable" since it's just a Bcc with an 'always' condition.
1479 let isBarrier = 1 in {
1480 let isPredicable = 1 in
1481 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1482 // should be sufficient.
1483 def B : ARMPseudoInst<(outs), (ins brtarget:$target), Size4Bytes, IIC_Br,
1486 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1487 def BR_JTr : ARMPseudoInst<(outs),
1488 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1489 SizeSpecial, IIC_Br,
1490 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1491 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1492 // into i12 and rs suffixed versions.
1493 def BR_JTm : ARMPseudoInst<(outs),
1494 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1495 SizeSpecial, IIC_Br,
1496 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1498 def BR_JTadd : ARMPseudoInst<(outs),
1499 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1500 SizeSpecial, IIC_Br,
1501 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1503 } // isNotDuplicable = 1, isIndirectBranch = 1
1506 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1507 // a two-value operand where a dag node expects two operands. :(
1508 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1509 IIC_Br, "b", "\t$target",
1510 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1512 let Inst{23-0} = target;
1516 // Branch and Exchange Jazelle -- for disassembly only
1517 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1518 [/* For disassembly only; pattern left blank */]> {
1519 let Inst{23-20} = 0b0010;
1520 //let Inst{19-8} = 0xfff;
1521 let Inst{7-4} = 0b0010;
1524 // Secure Monitor Call is a system instruction -- for disassembly only
1525 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1526 [/* For disassembly only; pattern left blank */]> {
1528 let Inst{23-4} = 0b01100000000000000111;
1529 let Inst{3-0} = opt;
1532 // Supervisor Call (Software Interrupt) -- for disassembly only
1533 let isCall = 1, Uses = [SP] in {
1534 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1535 [/* For disassembly only; pattern left blank */]> {
1537 let Inst{23-0} = svc;
1540 def : MnemonicAlias<"swi", "svc">;
1542 // Store Return State is a system instruction -- for disassembly only
1543 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1544 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1545 NoItinerary, "srs${amode}\tsp!, $mode",
1546 [/* For disassembly only; pattern left blank */]> {
1547 let Inst{31-28} = 0b1111;
1548 let Inst{22-20} = 0b110; // W = 1
1551 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1552 NoItinerary, "srs${amode}\tsp, $mode",
1553 [/* For disassembly only; pattern left blank */]> {
1554 let Inst{31-28} = 0b1111;
1555 let Inst{22-20} = 0b100; // W = 0
1558 // Return From Exception is a system instruction -- for disassembly only
1559 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1560 NoItinerary, "rfe${amode}\t$base!",
1561 [/* For disassembly only; pattern left blank */]> {
1562 let Inst{31-28} = 0b1111;
1563 let Inst{22-20} = 0b011; // W = 1
1566 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1567 NoItinerary, "rfe${amode}\t$base",
1568 [/* For disassembly only; pattern left blank */]> {
1569 let Inst{31-28} = 0b1111;
1570 let Inst{22-20} = 0b001; // W = 0
1572 } // isCodeGenOnly = 1
1574 //===----------------------------------------------------------------------===//
1575 // Load / store Instructions.
1581 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1582 UnOpFrag<(load node:$Src)>>;
1583 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1584 UnOpFrag<(zextloadi8 node:$Src)>>;
1585 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1586 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1587 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1588 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1590 // Special LDR for loads from non-pc-relative constpools.
1591 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1592 isReMaterializable = 1 in
1593 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1594 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1598 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1599 let Inst{19-16} = 0b1111;
1600 let Inst{15-12} = Rt;
1601 let Inst{11-0} = addr{11-0}; // imm12
1604 // Loads with zero extension
1605 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1606 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1607 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1609 // Loads with sign extension
1610 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1611 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1612 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1614 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1615 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1616 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1618 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1619 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1620 // FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1)
1621 // how to represent that such that tblgen is happy and we don't
1622 // mark this codegen only?
1624 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1625 (ins addrmode3:$addr), LdMiscFrm,
1626 IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
1627 []>, Requires<[IsARM, HasV5TE]>;
1631 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1632 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1633 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1634 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1636 // {13} 1 == Rm, 0 == imm12
1640 let Inst{25} = addr{13};
1641 let Inst{23} = addr{12};
1642 let Inst{19-16} = addr{17-14};
1643 let Inst{11-0} = addr{11-0};
1645 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1646 (ins GPR:$Rn, am2offset:$offset),
1647 IndexModePost, LdFrm, itin,
1648 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1649 // {13} 1 == Rm, 0 == imm12
1654 let Inst{25} = offset{13};
1655 let Inst{23} = offset{12};
1656 let Inst{19-16} = Rn;
1657 let Inst{11-0} = offset{11-0};
1661 let mayLoad = 1, neverHasSideEffects = 1 in {
1662 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1663 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1666 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1667 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1668 (ins addrmode3:$addr), IndexModePre,
1670 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1672 let Inst{23} = addr{8}; // U bit
1673 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1674 let Inst{19-16} = addr{12-9}; // Rn
1675 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1676 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1678 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1679 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1681 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1684 let Inst{23} = offset{8}; // U bit
1685 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1686 let Inst{19-16} = Rn;
1687 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1688 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1692 let mayLoad = 1, neverHasSideEffects = 1 in {
1693 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1694 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1695 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1696 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1697 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1698 } // mayLoad = 1, neverHasSideEffects = 1
1700 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1701 let mayLoad = 1, neverHasSideEffects = 1 in {
1702 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1703 (ins GPR:$base, am2offset:$offset), IndexModePost,
1704 LdFrm, IIC_iLoad_ru,
1705 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1706 let Inst{21} = 1; // overwrite
1708 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1709 (ins GPR:$base, am2offset:$offset), IndexModePost,
1710 LdFrm, IIC_iLoad_bh_ru,
1711 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1712 let Inst{21} = 1; // overwrite
1714 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1715 (ins GPR:$base, am3offset:$offset), IndexModePost,
1716 LdMiscFrm, IIC_iLoad_bh_ru,
1717 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1718 let Inst{21} = 1; // overwrite
1720 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1721 (ins GPR:$base, am3offset:$offset), IndexModePost,
1722 LdMiscFrm, IIC_iLoad_bh_ru,
1723 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1724 let Inst{21} = 1; // overwrite
1726 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1727 (ins GPR:$base, am3offset:$offset), IndexModePost,
1728 LdMiscFrm, IIC_iLoad_bh_ru,
1729 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1730 let Inst{21} = 1; // overwrite
1736 // Stores with truncate
1737 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1738 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1739 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1742 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1743 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1744 def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1745 StMiscFrm, IIC_iStore_d_r,
1746 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1749 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1750 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1751 IndexModePre, StFrm, IIC_iStore_ru,
1752 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1754 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1756 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1757 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1758 IndexModePost, StFrm, IIC_iStore_ru,
1759 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1761 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1763 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1764 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1765 IndexModePre, StFrm, IIC_iStore_bh_ru,
1766 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1767 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1768 GPR:$Rn, am2offset:$offset))]>;
1769 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1770 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1771 IndexModePost, StFrm, IIC_iStore_bh_ru,
1772 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1773 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1774 GPR:$Rn, am2offset:$offset))]>;
1776 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1777 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1778 IndexModePre, StMiscFrm, IIC_iStore_ru,
1779 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1781 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1783 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1784 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1785 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1786 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1787 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1788 GPR:$Rn, am3offset:$offset))]>;
1790 // For disassembly only
1791 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1792 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1793 StMiscFrm, IIC_iStore_d_ru,
1794 "strd", "\t$src1, $src2, [$base, $offset]!",
1795 "$base = $base_wb", []>;
1797 // For disassembly only
1798 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1799 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1800 StMiscFrm, IIC_iStore_d_ru,
1801 "strd", "\t$src1, $src2, [$base], $offset",
1802 "$base = $base_wb", []>;
1804 // STRT, STRBT, and STRHT are for disassembly only.
1806 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1807 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
1808 IndexModePost, StFrm, IIC_iStore_ru,
1809 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1810 [/* For disassembly only; pattern left blank */]> {
1811 let Inst{21} = 1; // overwrite
1814 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1815 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1816 IndexModePost, StFrm, IIC_iStore_bh_ru,
1817 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1818 [/* For disassembly only; pattern left blank */]> {
1819 let Inst{21} = 1; // overwrite
1822 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1823 (ins GPR:$src, GPR:$base,am3offset:$offset),
1824 StMiscFrm, IIC_iStore_bh_ru,
1825 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1826 [/* For disassembly only; pattern left blank */]> {
1827 let Inst{21} = 1; // overwrite
1830 //===----------------------------------------------------------------------===//
1831 // Load / store multiple Instructions.
1834 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1835 InstrItinClass itin, InstrItinClass itin_upd> {
1837 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1838 IndexModeNone, f, itin,
1839 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1840 let Inst{24-23} = 0b01; // Increment After
1841 let Inst{21} = 0; // No writeback
1842 let Inst{20} = L_bit;
1845 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1846 IndexModeUpd, f, itin_upd,
1847 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1848 let Inst{24-23} = 0b01; // Increment After
1849 let Inst{21} = 1; // Writeback
1850 let Inst{20} = L_bit;
1853 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1854 IndexModeNone, f, itin,
1855 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1856 let Inst{24-23} = 0b00; // Decrement After
1857 let Inst{21} = 0; // No writeback
1858 let Inst{20} = L_bit;
1861 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1862 IndexModeUpd, f, itin_upd,
1863 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1864 let Inst{24-23} = 0b00; // Decrement After
1865 let Inst{21} = 1; // Writeback
1866 let Inst{20} = L_bit;
1869 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1870 IndexModeNone, f, itin,
1871 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1872 let Inst{24-23} = 0b10; // Decrement Before
1873 let Inst{21} = 0; // No writeback
1874 let Inst{20} = L_bit;
1877 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1878 IndexModeUpd, f, itin_upd,
1879 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1880 let Inst{24-23} = 0b10; // Decrement Before
1881 let Inst{21} = 1; // Writeback
1882 let Inst{20} = L_bit;
1885 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1886 IndexModeNone, f, itin,
1887 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1888 let Inst{24-23} = 0b11; // Increment Before
1889 let Inst{21} = 0; // No writeback
1890 let Inst{20} = L_bit;
1893 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1894 IndexModeUpd, f, itin_upd,
1895 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1896 let Inst{24-23} = 0b11; // Increment Before
1897 let Inst{21} = 1; // Writeback
1898 let Inst{20} = L_bit;
1902 let neverHasSideEffects = 1 in {
1904 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1905 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1907 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1908 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1910 } // neverHasSideEffects
1912 // Load / Store Multiple Mnemonic Aliases
1913 def : MnemonicAlias<"ldm", "ldmia">;
1914 def : MnemonicAlias<"stm", "stmia">;
1916 // FIXME: remove when we have a way to marking a MI with these properties.
1917 // FIXME: Should pc be an implicit operand like PICADD, etc?
1918 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1919 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1920 def LDMIA_RET : ARMPseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1921 reglist:$regs, variable_ops),
1922 Size4Bytes, IIC_iLoad_mBr, []>,
1923 RegConstraint<"$Rn = $wb">;
1925 //===----------------------------------------------------------------------===//
1926 // Move Instructions.
1929 let neverHasSideEffects = 1 in
1930 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1931 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1935 let Inst{11-4} = 0b00000000;
1938 let Inst{15-12} = Rd;
1941 // A version for the smaller set of tail call registers.
1942 let neverHasSideEffects = 1 in
1943 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1944 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1948 let Inst{11-4} = 0b00000000;
1951 let Inst{15-12} = Rd;
1954 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1955 DPSoRegFrm, IIC_iMOVsr,
1956 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1960 let Inst{15-12} = Rd;
1961 let Inst{11-0} = src;
1965 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1966 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1967 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1971 let Inst{15-12} = Rd;
1972 let Inst{19-16} = 0b0000;
1973 let Inst{11-0} = imm;
1976 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1977 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
1979 "movw", "\t$Rd, $imm",
1980 [(set GPR:$Rd, imm0_65535:$imm)]>,
1981 Requires<[IsARM, HasV6T2]>, UnaryDP {
1984 let Inst{15-12} = Rd;
1985 let Inst{11-0} = imm{11-0};
1986 let Inst{19-16} = imm{15-12};
1991 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
1992 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
1994 let Constraints = "$src = $Rd" in {
1995 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
1997 "movt", "\t$Rd, $imm",
1999 (or (and GPR:$src, 0xffff),
2000 lo16AllZero:$imm))]>, UnaryDP,
2001 Requires<[IsARM, HasV6T2]> {
2004 let Inst{15-12} = Rd;
2005 let Inst{11-0} = imm{11-0};
2006 let Inst{19-16} = imm{15-12};
2011 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2012 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2016 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2017 Requires<[IsARM, HasV6T2]>;
2019 let Uses = [CPSR] in
2020 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2021 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2024 // These aren't really mov instructions, but we have to define them this way
2025 // due to flag operands.
2027 let Defs = [CPSR] in {
2028 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2029 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2031 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2032 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2036 //===----------------------------------------------------------------------===//
2037 // Extend Instructions.
2042 defm SXTB : AI_ext_rrot<0b01101010,
2043 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2044 defm SXTH : AI_ext_rrot<0b01101011,
2045 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2047 defm SXTAB : AI_exta_rrot<0b01101010,
2048 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2049 defm SXTAH : AI_exta_rrot<0b01101011,
2050 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2052 // For disassembly only
2053 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2055 // For disassembly only
2056 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2060 let AddedComplexity = 16 in {
2061 defm UXTB : AI_ext_rrot<0b01101110,
2062 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2063 defm UXTH : AI_ext_rrot<0b01101111,
2064 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2065 defm UXTB16 : AI_ext_rrot<0b01101100,
2066 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2068 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2069 // The transformation should probably be done as a combiner action
2070 // instead so we can include a check for masking back in the upper
2071 // eight bits of the source into the lower eight bits of the result.
2072 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2073 // (UXTB16r_rot GPR:$Src, 24)>;
2074 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2075 (UXTB16r_rot GPR:$Src, 8)>;
2077 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2078 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2079 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2080 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2083 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2084 // For disassembly only
2085 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2088 def SBFX : I<(outs GPR:$Rd),
2089 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2090 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2091 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2092 Requires<[IsARM, HasV6T2]> {
2097 let Inst{27-21} = 0b0111101;
2098 let Inst{6-4} = 0b101;
2099 let Inst{20-16} = width;
2100 let Inst{15-12} = Rd;
2101 let Inst{11-7} = lsb;
2105 def UBFX : I<(outs GPR:$Rd),
2106 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2107 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2108 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2109 Requires<[IsARM, HasV6T2]> {
2114 let Inst{27-21} = 0b0111111;
2115 let Inst{6-4} = 0b101;
2116 let Inst{20-16} = width;
2117 let Inst{15-12} = Rd;
2118 let Inst{11-7} = lsb;
2122 //===----------------------------------------------------------------------===//
2123 // Arithmetic Instructions.
2126 defm ADD : AsI1_bin_irs<0b0100, "add",
2127 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2128 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2129 defm SUB : AsI1_bin_irs<0b0010, "sub",
2130 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2131 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2133 // ADD and SUB with 's' bit set.
2134 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2135 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2136 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2137 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2138 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2139 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2141 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2142 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2143 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2144 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2146 // ADC and SUBC with 's' bit set.
2147 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2148 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2149 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2150 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2152 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2153 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2154 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2159 let Inst{15-12} = Rd;
2160 let Inst{19-16} = Rn;
2161 let Inst{11-0} = imm;
2164 // The reg/reg form is only defined for the disassembler; for codegen it is
2165 // equivalent to SUBrr.
2166 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2167 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2168 [/* For disassembly only; pattern left blank */]> {
2172 let Inst{11-4} = 0b00000000;
2175 let Inst{15-12} = Rd;
2176 let Inst{19-16} = Rn;
2179 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2180 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2181 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2186 let Inst{11-0} = shift;
2187 let Inst{15-12} = Rd;
2188 let Inst{19-16} = Rn;
2191 // RSB with 's' bit set.
2192 let isCodeGenOnly = 1, Defs = [CPSR] in {
2193 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2194 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2195 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2201 let Inst{15-12} = Rd;
2202 let Inst{19-16} = Rn;
2203 let Inst{11-0} = imm;
2205 def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2206 IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
2207 [/* For disassembly only; pattern left blank */]> {
2211 let Inst{11-4} = 0b00000000;
2215 let Inst{15-12} = Rd;
2216 let Inst{19-16} = Rn;
2218 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2219 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2220 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2226 let Inst{11-0} = shift;
2227 let Inst{15-12} = Rd;
2228 let Inst{19-16} = Rn;
2232 let Uses = [CPSR] in {
2233 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2234 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2235 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2241 let Inst{15-12} = Rd;
2242 let Inst{19-16} = Rn;
2243 let Inst{11-0} = imm;
2245 // The reg/reg form is only defined for the disassembler; for codegen it is
2246 // equivalent to SUBrr.
2247 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2248 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2249 [/* For disassembly only; pattern left blank */]> {
2253 let Inst{11-4} = 0b00000000;
2256 let Inst{15-12} = Rd;
2257 let Inst{19-16} = Rn;
2259 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2260 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2261 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2267 let Inst{11-0} = shift;
2268 let Inst{15-12} = Rd;
2269 let Inst{19-16} = Rn;
2273 // FIXME: Allow these to be predicated.
2274 let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
2275 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2276 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2277 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2284 let Inst{15-12} = Rd;
2285 let Inst{19-16} = Rn;
2286 let Inst{11-0} = imm;
2288 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2289 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2290 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2297 let Inst{11-0} = shift;
2298 let Inst{15-12} = Rd;
2299 let Inst{19-16} = Rn;
2303 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2304 // The assume-no-carry-in form uses the negation of the input since add/sub
2305 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2306 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2308 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2309 (SUBri GPR:$src, so_imm_neg:$imm)>;
2310 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2311 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2312 // The with-carry-in form matches bitwise not instead of the negation.
2313 // Effectively, the inverse interpretation of the carry flag already accounts
2314 // for part of the negation.
2315 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2316 (SBCri GPR:$src, so_imm_not:$imm)>;
2318 // Note: These are implemented in C++ code, because they have to generate
2319 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2321 // (mul X, 2^n+1) -> (add (X << n), X)
2322 // (mul X, 2^n-1) -> (rsb X, (X << n))
2324 // ARM Arithmetic Instruction -- for disassembly only
2325 // GPR:$dst = GPR:$a op GPR:$b
2326 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2327 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2328 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2329 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2333 let Inst{27-20} = op27_20;
2334 let Inst{11-4} = op11_4;
2335 let Inst{19-16} = Rn;
2336 let Inst{15-12} = Rd;
2340 // Saturating add/subtract -- for disassembly only
2342 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2343 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2344 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2345 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2346 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2347 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2348 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2350 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2353 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2354 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2355 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2356 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2357 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2358 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2359 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2360 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2361 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2362 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2363 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2364 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2366 // Signed/Unsigned add/subtract -- for disassembly only
2368 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2369 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2370 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2371 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2372 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2373 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2374 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2375 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2376 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2377 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2378 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2379 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2381 // Signed/Unsigned halving add/subtract -- for disassembly only
2383 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2384 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2385 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2386 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2387 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2388 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2389 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2390 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2391 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2392 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2393 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2394 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2396 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2398 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2399 MulFrm /* for convenience */, NoItinerary, "usad8",
2400 "\t$Rd, $Rn, $Rm", []>,
2401 Requires<[IsARM, HasV6]> {
2405 let Inst{27-20} = 0b01111000;
2406 let Inst{15-12} = 0b1111;
2407 let Inst{7-4} = 0b0001;
2408 let Inst{19-16} = Rd;
2409 let Inst{11-8} = Rm;
2412 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2413 MulFrm /* for convenience */, NoItinerary, "usada8",
2414 "\t$Rd, $Rn, $Rm, $Ra", []>,
2415 Requires<[IsARM, HasV6]> {
2420 let Inst{27-20} = 0b01111000;
2421 let Inst{7-4} = 0b0001;
2422 let Inst{19-16} = Rd;
2423 let Inst{15-12} = Ra;
2424 let Inst{11-8} = Rm;
2428 // Signed/Unsigned saturate -- for disassembly only
2430 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2431 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2432 [/* For disassembly only; pattern left blank */]> {
2437 let Inst{27-21} = 0b0110101;
2438 let Inst{5-4} = 0b01;
2439 let Inst{20-16} = sat_imm;
2440 let Inst{15-12} = Rd;
2441 let Inst{11-7} = sh{7-3};
2442 let Inst{6} = sh{0};
2446 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2447 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2448 [/* For disassembly only; pattern left blank */]> {
2452 let Inst{27-20} = 0b01101010;
2453 let Inst{11-4} = 0b11110011;
2454 let Inst{15-12} = Rd;
2455 let Inst{19-16} = sat_imm;
2459 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2460 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2461 [/* For disassembly only; pattern left blank */]> {
2466 let Inst{27-21} = 0b0110111;
2467 let Inst{5-4} = 0b01;
2468 let Inst{15-12} = Rd;
2469 let Inst{11-7} = sh{7-3};
2470 let Inst{6} = sh{0};
2471 let Inst{20-16} = sat_imm;
2475 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2476 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2477 [/* For disassembly only; pattern left blank */]> {
2481 let Inst{27-20} = 0b01101110;
2482 let Inst{11-4} = 0b11110011;
2483 let Inst{15-12} = Rd;
2484 let Inst{19-16} = sat_imm;
2488 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2489 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2491 //===----------------------------------------------------------------------===//
2492 // Bitwise Instructions.
2495 defm AND : AsI1_bin_irs<0b0000, "and",
2496 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2497 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2498 defm ORR : AsI1_bin_irs<0b1100, "orr",
2499 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2500 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2501 defm EOR : AsI1_bin_irs<0b0001, "eor",
2502 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2503 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2504 defm BIC : AsI1_bin_irs<0b1110, "bic",
2505 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2506 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2508 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2509 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2510 "bfc", "\t$Rd, $imm", "$src = $Rd",
2511 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2512 Requires<[IsARM, HasV6T2]> {
2515 let Inst{27-21} = 0b0111110;
2516 let Inst{6-0} = 0b0011111;
2517 let Inst{15-12} = Rd;
2518 let Inst{11-7} = imm{4-0}; // lsb
2519 let Inst{20-16} = imm{9-5}; // width
2522 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2523 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2524 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2525 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2526 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2527 bf_inv_mask_imm:$imm))]>,
2528 Requires<[IsARM, HasV6T2]> {
2532 let Inst{27-21} = 0b0111110;
2533 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2534 let Inst{15-12} = Rd;
2535 let Inst{11-7} = imm{4-0}; // lsb
2536 let Inst{20-16} = imm{9-5}; // width
2540 // GNU as only supports this form of bfi (w/ 4 arguments)
2541 let isAsmParserOnly = 1 in
2542 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2543 lsb_pos_imm:$lsb, width_imm:$width),
2544 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2545 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2546 []>, Requires<[IsARM, HasV6T2]> {
2551 let Inst{27-21} = 0b0111110;
2552 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2553 let Inst{15-12} = Rd;
2554 let Inst{11-7} = lsb;
2555 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2559 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2560 "mvn", "\t$Rd, $Rm",
2561 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2565 let Inst{19-16} = 0b0000;
2566 let Inst{11-4} = 0b00000000;
2567 let Inst{15-12} = Rd;
2570 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2571 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2572 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2576 let Inst{19-16} = 0b0000;
2577 let Inst{15-12} = Rd;
2578 let Inst{11-0} = shift;
2580 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2581 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2582 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2583 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2587 let Inst{19-16} = 0b0000;
2588 let Inst{15-12} = Rd;
2589 let Inst{11-0} = imm;
2592 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2593 (BICri GPR:$src, so_imm_not:$imm)>;
2595 //===----------------------------------------------------------------------===//
2596 // Multiply Instructions.
2598 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2599 string opc, string asm, list<dag> pattern>
2600 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2604 let Inst{19-16} = Rd;
2605 let Inst{11-8} = Rm;
2608 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2609 string opc, string asm, list<dag> pattern>
2610 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2615 let Inst{19-16} = RdHi;
2616 let Inst{15-12} = RdLo;
2617 let Inst{11-8} = Rm;
2621 let isCommutable = 1 in {
2622 let Constraints = "@earlyclobber $Rd" in
2623 def MULv5: ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2624 pred:$p, cc_out:$s),
2625 Size4Bytes, IIC_iMUL32,
2626 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2627 Requires<[IsARM, NoV6]>;
2629 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2630 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2631 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2632 Requires<[IsARM, HasV6]>;
2635 let Constraints = "@earlyclobber $Rd" in
2636 def MLAv5: ARMPseudoInst<(outs GPR:$Rd),
2637 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2638 Size4Bytes, IIC_iMAC32,
2639 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2640 Requires<[IsARM, NoV6]> {
2642 let Inst{15-12} = Ra;
2644 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2645 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2646 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2647 Requires<[IsARM, HasV6]> {
2649 let Inst{15-12} = Ra;
2652 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2653 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2654 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2655 Requires<[IsARM, HasV6T2]> {
2660 let Inst{19-16} = Rd;
2661 let Inst{15-12} = Ra;
2662 let Inst{11-8} = Rm;
2666 // Extra precision multiplies with low / high results
2668 let neverHasSideEffects = 1 in {
2669 let isCommutable = 1 in {
2670 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2671 def SMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2672 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2673 Size4Bytes, IIC_iMUL64, []>,
2674 Requires<[IsARM, NoV6]>;
2676 def UMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2677 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2678 Size4Bytes, IIC_iMUL64, []>,
2679 Requires<[IsARM, NoV6]>;
2682 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2683 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2684 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2685 Requires<[IsARM, HasV6]>;
2687 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2688 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2689 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2690 Requires<[IsARM, HasV6]>;
2693 // Multiply + accumulate
2694 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2695 def SMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2696 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2697 Size4Bytes, IIC_iMAC64, []>,
2698 Requires<[IsARM, NoV6]>;
2699 def UMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2700 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2701 Size4Bytes, IIC_iMAC64, []>,
2702 Requires<[IsARM, NoV6]>;
2703 def UMAALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2704 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2705 Size4Bytes, IIC_iMAC64, []>,
2706 Requires<[IsARM, NoV6]>;
2710 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2711 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2712 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2713 Requires<[IsARM, HasV6]>;
2714 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2715 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2716 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2717 Requires<[IsARM, HasV6]>;
2719 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2720 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2721 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2722 Requires<[IsARM, HasV6]> {
2727 let Inst{19-16} = RdLo;
2728 let Inst{15-12} = RdHi;
2729 let Inst{11-8} = Rm;
2732 } // neverHasSideEffects
2734 // Most significant word multiply
2735 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2736 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2737 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2738 Requires<[IsARM, HasV6]> {
2739 let Inst{15-12} = 0b1111;
2742 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2743 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2744 [/* For disassembly only; pattern left blank */]>,
2745 Requires<[IsARM, HasV6]> {
2746 let Inst{15-12} = 0b1111;
2749 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2750 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2751 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2752 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2753 Requires<[IsARM, HasV6]>;
2755 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2756 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2757 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2758 [/* For disassembly only; pattern left blank */]>,
2759 Requires<[IsARM, HasV6]>;
2761 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2762 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2763 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2764 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2765 Requires<[IsARM, HasV6]>;
2767 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2768 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2769 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2770 [/* For disassembly only; pattern left blank */]>,
2771 Requires<[IsARM, HasV6]>;
2773 multiclass AI_smul<string opc, PatFrag opnode> {
2774 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2775 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2776 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2777 (sext_inreg GPR:$Rm, i16)))]>,
2778 Requires<[IsARM, HasV5TE]>;
2780 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2781 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2782 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2783 (sra GPR:$Rm, (i32 16))))]>,
2784 Requires<[IsARM, HasV5TE]>;
2786 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2787 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2788 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2789 (sext_inreg GPR:$Rm, i16)))]>,
2790 Requires<[IsARM, HasV5TE]>;
2792 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2793 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2794 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2795 (sra GPR:$Rm, (i32 16))))]>,
2796 Requires<[IsARM, HasV5TE]>;
2798 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2799 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2800 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2801 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2802 Requires<[IsARM, HasV5TE]>;
2804 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2805 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2806 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2807 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2808 Requires<[IsARM, HasV5TE]>;
2812 multiclass AI_smla<string opc, PatFrag opnode> {
2813 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2814 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2815 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2816 [(set GPR:$Rd, (add GPR:$Ra,
2817 (opnode (sext_inreg GPR:$Rn, i16),
2818 (sext_inreg GPR:$Rm, i16))))]>,
2819 Requires<[IsARM, HasV5TE]>;
2821 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2822 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2823 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2824 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2825 (sra GPR:$Rm, (i32 16)))))]>,
2826 Requires<[IsARM, HasV5TE]>;
2828 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2829 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2830 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2831 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2832 (sext_inreg GPR:$Rm, i16))))]>,
2833 Requires<[IsARM, HasV5TE]>;
2835 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2836 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2837 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2838 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2839 (sra GPR:$Rm, (i32 16)))))]>,
2840 Requires<[IsARM, HasV5TE]>;
2842 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2843 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2844 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2845 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2846 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2847 Requires<[IsARM, HasV5TE]>;
2849 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2850 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2851 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2852 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2853 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2854 Requires<[IsARM, HasV5TE]>;
2857 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2858 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2860 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2861 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2862 (ins GPR:$Rn, GPR:$Rm),
2863 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2864 [/* For disassembly only; pattern left blank */]>,
2865 Requires<[IsARM, HasV5TE]>;
2867 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2868 (ins GPR:$Rn, GPR:$Rm),
2869 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2870 [/* For disassembly only; pattern left blank */]>,
2871 Requires<[IsARM, HasV5TE]>;
2873 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2874 (ins GPR:$Rn, GPR:$Rm),
2875 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2876 [/* For disassembly only; pattern left blank */]>,
2877 Requires<[IsARM, HasV5TE]>;
2879 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2880 (ins GPR:$Rn, GPR:$Rm),
2881 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2882 [/* For disassembly only; pattern left blank */]>,
2883 Requires<[IsARM, HasV5TE]>;
2885 // Helper class for AI_smld -- for disassembly only
2886 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2887 InstrItinClass itin, string opc, string asm>
2888 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2895 let Inst{21-20} = 0b00;
2896 let Inst{22} = long;
2897 let Inst{27-23} = 0b01110;
2898 let Inst{11-8} = Rm;
2901 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2902 InstrItinClass itin, string opc, string asm>
2903 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2905 let Inst{15-12} = 0b1111;
2906 let Inst{19-16} = Rd;
2908 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2909 InstrItinClass itin, string opc, string asm>
2910 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2912 let Inst{15-12} = Ra;
2914 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2915 InstrItinClass itin, string opc, string asm>
2916 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2919 let Inst{19-16} = RdHi;
2920 let Inst{15-12} = RdLo;
2923 multiclass AI_smld<bit sub, string opc> {
2925 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2926 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2928 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2929 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2931 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2932 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2933 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2935 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2936 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2937 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2941 defm SMLA : AI_smld<0, "smla">;
2942 defm SMLS : AI_smld<1, "smls">;
2944 multiclass AI_sdml<bit sub, string opc> {
2946 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2947 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2948 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2949 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2952 defm SMUA : AI_sdml<0, "smua">;
2953 defm SMUS : AI_sdml<1, "smus">;
2955 //===----------------------------------------------------------------------===//
2956 // Misc. Arithmetic Instructions.
2959 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2960 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2961 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2963 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2964 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2965 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2966 Requires<[IsARM, HasV6T2]>;
2968 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2969 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2970 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2972 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2973 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2975 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2976 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2977 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2978 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2979 Requires<[IsARM, HasV6]>;
2981 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2982 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2985 (or (srl GPR:$Rm, (i32 8)),
2986 (shl GPR:$Rm, (i32 8))), i16))]>,
2987 Requires<[IsARM, HasV6]>;
2989 def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2990 (shl GPR:$Rm, (i32 8))), i16),
2993 // Need the AddedComplexity or else MOVs + REV would be chosen.
2994 let AddedComplexity = 5 in
2995 def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;
2997 def lsl_shift_imm : SDNodeXForm<imm, [{
2998 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2999 return CurDAG->getTargetConstant(Sh, MVT::i32);
3002 def lsl_amt : PatLeaf<(i32 imm), [{
3003 return (N->getZExtValue() < 32);
3006 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3007 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3008 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3009 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3010 (and (shl GPR:$Rm, lsl_amt:$sh),
3012 Requires<[IsARM, HasV6]>;
3014 // Alternate cases for PKHBT where identities eliminate some nodes.
3015 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3016 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3017 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3018 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3020 def asr_shift_imm : SDNodeXForm<imm, [{
3021 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3022 return CurDAG->getTargetConstant(Sh, MVT::i32);
3025 def asr_amt : PatLeaf<(i32 imm), [{
3026 return (N->getZExtValue() <= 32);
3029 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3030 // will match the pattern below.
3031 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3032 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3033 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3034 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3035 (and (sra GPR:$Rm, asr_amt:$sh),
3037 Requires<[IsARM, HasV6]>;
3039 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3040 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3041 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3042 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3043 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3044 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3045 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3047 //===----------------------------------------------------------------------===//
3048 // Comparison Instructions...
3051 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3052 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3053 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3055 // ARMcmpZ can re-use the above instruction definitions.
3056 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3057 (CMPri GPR:$src, so_imm:$imm)>;
3058 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3059 (CMPrr GPR:$src, GPR:$rhs)>;
3060 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3061 (CMPrs GPR:$src, so_reg:$rhs)>;
3063 // FIXME: We have to be careful when using the CMN instruction and comparison
3064 // with 0. One would expect these two pieces of code should give identical
3080 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3081 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3082 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3083 // value of r0 and the carry bit (because the "carry bit" parameter to
3084 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3085 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3086 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3087 // parameter to AddWithCarry is defined as 0).
3089 // When x is 0 and unsigned:
3093 // ~x + 1 = 0x1 0000 0000
3094 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3096 // Therefore, we should disable CMN when comparing against zero, until we can
3097 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3098 // when it's a comparison which doesn't look at the 'carry' flag).
3100 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3102 // This is related to <rdar://problem/7569620>.
3104 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3105 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3107 // Note that TST/TEQ don't set all the same flags that CMP does!
3108 defm TST : AI1_cmp_irs<0b1000, "tst",
3109 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3110 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3111 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3112 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3113 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3115 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3116 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3117 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3119 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3120 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3122 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3123 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3125 // Pseudo i64 compares for some floating point compares.
3126 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3128 def BCCi64 : PseudoInst<(outs),
3129 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3131 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3133 def BCCZi64 : PseudoInst<(outs),
3134 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3135 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3136 } // usesCustomInserter
3139 // Conditional moves
3140 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3141 // a two-value operand where a dag node expects two operands. :(
3142 let neverHasSideEffects = 1 in {
3143 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3144 Size4Bytes, IIC_iCMOVr,
3145 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3146 RegConstraint<"$false = $Rd">;
3147 def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
3148 (ins GPR:$false, so_reg:$shift, pred:$p),
3149 Size4Bytes, IIC_iCMOVsr,
3150 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3151 RegConstraint<"$false = $Rd">;
3153 let isMoveImm = 1 in
3154 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3155 (ins GPR:$false, i32imm_hilo16:$imm, pred:$p),
3156 Size4Bytes, IIC_iMOVi,
3158 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3160 let isMoveImm = 1 in
3161 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3162 (ins GPR:$false, so_imm:$imm, pred:$p),
3163 Size4Bytes, IIC_iCMOVi,
3164 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3165 RegConstraint<"$false = $Rd">;
3167 // Two instruction predicate mov immediate.
3168 let isMoveImm = 1 in
3169 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3170 (ins GPR:$false, i32imm:$src, pred:$p),
3171 Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3173 let isMoveImm = 1 in
3174 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3175 (ins GPR:$false, so_imm:$imm, pred:$p),
3176 Size4Bytes, IIC_iCMOVi,
3177 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3178 RegConstraint<"$false = $Rd">;
3179 } // neverHasSideEffects
3181 //===----------------------------------------------------------------------===//
3182 // Atomic operations intrinsics
3185 def memb_opt : Operand<i32> {
3186 let PrintMethod = "printMemBOption";
3187 let ParserMatchClass = MemBarrierOptOperand;
3190 // memory barriers protect the atomic sequences
3191 let hasSideEffects = 1 in {
3192 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3193 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3194 Requires<[IsARM, HasDB]> {
3196 let Inst{31-4} = 0xf57ff05;
3197 let Inst{3-0} = opt;
3201 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3203 [/* For disassembly only; pattern left blank */]>,
3204 Requires<[IsARM, HasDB]> {
3206 let Inst{31-4} = 0xf57ff04;
3207 let Inst{3-0} = opt;
3210 // ISB has only full system option -- for disassembly only
3211 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3212 Requires<[IsARM, HasDB]> {
3213 let Inst{31-4} = 0xf57ff06;
3214 let Inst{3-0} = 0b1111;
3217 let usesCustomInserter = 1 in {
3218 let Uses = [CPSR] in {
3219 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3220 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3221 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3222 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3223 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3224 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3225 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3226 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3227 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3228 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3229 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3230 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3231 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3232 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3233 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3234 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3235 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3236 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3237 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3238 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3239 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3240 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3241 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3242 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3243 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3244 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3245 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3246 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3247 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3248 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3249 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3250 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3251 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3252 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3253 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3254 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3255 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3256 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3257 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3258 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3259 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3260 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3261 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3262 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3263 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3264 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3265 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3266 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3267 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3268 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3269 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3270 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3271 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3272 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3274 def ATOMIC_SWAP_I8 : PseudoInst<
3275 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3276 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3277 def ATOMIC_SWAP_I16 : PseudoInst<
3278 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3279 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3280 def ATOMIC_SWAP_I32 : PseudoInst<
3281 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3282 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3284 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3285 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3286 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3287 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3288 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3289 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3290 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3291 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3292 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3296 let mayLoad = 1 in {
3297 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3298 "ldrexb", "\t$Rt, [$Rn]",
3300 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3301 "ldrexh", "\t$Rt, [$Rn]",
3303 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3304 "ldrex", "\t$Rt, [$Rn]",
3306 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3308 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3312 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3313 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3315 "strexb", "\t$Rd, $src, [$Rn]",
3317 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3319 "strexh", "\t$Rd, $Rt, [$Rn]",
3321 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3323 "strex", "\t$Rd, $Rt, [$Rn]",
3325 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3326 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3328 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3332 // Clear-Exclusive is for disassembly only.
3333 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3334 [/* For disassembly only; pattern left blank */]>,
3335 Requires<[IsARM, HasV7]> {
3336 let Inst{31-0} = 0b11110101011111111111000000011111;
3339 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3340 let mayLoad = 1 in {
3341 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3342 [/* For disassembly only; pattern left blank */]>;
3343 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3344 [/* For disassembly only; pattern left blank */]>;
3347 //===----------------------------------------------------------------------===//
3348 // Coprocessor Instructions.
3351 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3352 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3353 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3354 [/* For disassembly only; pattern left blank */]> {
3362 let Inst{3-0} = CRm;
3364 let Inst{7-5} = opc2;
3365 let Inst{11-8} = cop;
3366 let Inst{15-12} = CRd;
3367 let Inst{19-16} = CRn;
3368 let Inst{23-20} = opc1;
3371 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3372 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3373 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3374 [/* For disassembly only; pattern left blank */]> {
3375 let Inst{31-28} = 0b1111;
3383 let Inst{3-0} = CRm;
3385 let Inst{7-5} = opc2;
3386 let Inst{11-8} = cop;
3387 let Inst{15-12} = CRd;
3388 let Inst{19-16} = CRn;
3389 let Inst{23-20} = opc1;
3392 class ACI<dag oops, dag iops, string opc, string asm>
3393 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3394 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3395 let Inst{27-25} = 0b110;
3398 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3400 def _OFFSET : ACI<(outs),
3401 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3402 opc, "\tp$cop, cr$CRd, $addr"> {
3403 let Inst{31-28} = op31_28;
3404 let Inst{24} = 1; // P = 1
3405 let Inst{21} = 0; // W = 0
3406 let Inst{22} = 0; // D = 0
3407 let Inst{20} = load;
3410 def _PRE : ACI<(outs),
3411 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3412 opc, "\tp$cop, cr$CRd, $addr!"> {
3413 let Inst{31-28} = op31_28;
3414 let Inst{24} = 1; // P = 1
3415 let Inst{21} = 1; // W = 1
3416 let Inst{22} = 0; // D = 0
3417 let Inst{20} = load;
3420 def _POST : ACI<(outs),
3421 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3422 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3423 let Inst{31-28} = op31_28;
3424 let Inst{24} = 0; // P = 0
3425 let Inst{21} = 1; // W = 1
3426 let Inst{22} = 0; // D = 0
3427 let Inst{20} = load;
3430 def _OPTION : ACI<(outs),
3431 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3432 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3433 let Inst{31-28} = op31_28;
3434 let Inst{24} = 0; // P = 0
3435 let Inst{23} = 1; // U = 1
3436 let Inst{21} = 0; // W = 0
3437 let Inst{22} = 0; // D = 0
3438 let Inst{20} = load;
3441 def L_OFFSET : ACI<(outs),
3442 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3443 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3444 let Inst{31-28} = op31_28;
3445 let Inst{24} = 1; // P = 1
3446 let Inst{21} = 0; // W = 0
3447 let Inst{22} = 1; // D = 1
3448 let Inst{20} = load;
3451 def L_PRE : ACI<(outs),
3452 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3453 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3454 let Inst{31-28} = op31_28;
3455 let Inst{24} = 1; // P = 1
3456 let Inst{21} = 1; // W = 1
3457 let Inst{22} = 1; // D = 1
3458 let Inst{20} = load;
3461 def L_POST : ACI<(outs),
3462 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3463 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3464 let Inst{31-28} = op31_28;
3465 let Inst{24} = 0; // P = 0
3466 let Inst{21} = 1; // W = 1
3467 let Inst{22} = 1; // D = 1
3468 let Inst{20} = load;
3471 def L_OPTION : ACI<(outs),
3472 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3473 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3474 let Inst{31-28} = op31_28;
3475 let Inst{24} = 0; // P = 0
3476 let Inst{23} = 1; // U = 1
3477 let Inst{21} = 0; // W = 0
3478 let Inst{22} = 1; // D = 1
3479 let Inst{20} = load;
3483 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3484 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3485 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3486 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3488 //===----------------------------------------------------------------------===//
3489 // Move between coprocessor and ARM core register -- for disassembly only
3492 class MovRCopro<string opc, bit direction, dag oops, dag iops>
3493 : ABI<0b1110, oops, iops, NoItinerary, opc,
3494 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
3495 [/* For disassembly only; pattern left blank */]> {
3496 let Inst{20} = direction;
3506 let Inst{15-12} = Rt;
3507 let Inst{11-8} = cop;
3508 let Inst{23-21} = opc1;
3509 let Inst{7-5} = opc2;
3510 let Inst{3-0} = CRm;
3511 let Inst{19-16} = CRn;
3514 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3515 (outs), (ins p_imm:$cop, i32imm:$opc1,
3516 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3518 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3519 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3520 c_imm:$CRn, c_imm:$CRm, i32imm:$opc2)>;
3522 class MovRCopro2<string opc, bit direction, dag oops, dag iops>
3523 : ABXI<0b1110, oops, iops, NoItinerary,
3524 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3525 [/* For disassembly only; pattern left blank */]> {
3526 let Inst{31-28} = 0b1111;
3527 let Inst{20} = direction;
3537 let Inst{15-12} = Rt;
3538 let Inst{11-8} = cop;
3539 let Inst{23-21} = opc1;
3540 let Inst{7-5} = opc2;
3541 let Inst{3-0} = CRm;
3542 let Inst{19-16} = CRn;
3545 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3546 (outs), (ins p_imm:$cop, i32imm:$opc1,
3547 GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
3549 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3550 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
3551 c_imm:$CRn, c_imm:$CRm,
3554 class MovRRCopro<string opc, bit direction>
3555 : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3556 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3557 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
3558 [/* For disassembly only; pattern left blank */]> {
3559 let Inst{23-21} = 0b010;
3560 let Inst{20} = direction;
3568 let Inst{15-12} = Rt;
3569 let Inst{19-16} = Rt2;
3570 let Inst{11-8} = cop;
3571 let Inst{7-4} = opc1;
3572 let Inst{3-0} = CRm;
3575 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
3576 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3578 class MovRRCopro2<string opc, bit direction>
3579 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3580 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3581 NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
3582 [/* For disassembly only; pattern left blank */]> {
3583 let Inst{31-28} = 0b1111;
3584 let Inst{23-21} = 0b010;
3585 let Inst{20} = direction;
3593 let Inst{15-12} = Rt;
3594 let Inst{19-16} = Rt2;
3595 let Inst{11-8} = cop;
3596 let Inst{7-4} = opc1;
3597 let Inst{3-0} = CRm;
3600 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */>;
3601 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3603 //===----------------------------------------------------------------------===//
3604 // Move between special register and ARM core register -- for disassembly only
3607 // Move to ARM core register from Special Register
3608 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3609 [/* For disassembly only; pattern left blank */]> {
3611 let Inst{23-16} = 0b00001111;
3612 let Inst{15-12} = Rd;
3613 let Inst{7-4} = 0b0000;
3616 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3617 [/* For disassembly only; pattern left blank */]> {
3619 let Inst{23-16} = 0b01001111;
3620 let Inst{15-12} = Rd;
3621 let Inst{7-4} = 0b0000;
3624 // Move from ARM core register to Special Register
3626 // No need to have both system and application versions, the encodings are the
3627 // same and the assembly parser has no way to distinguish between them. The mask
3628 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3629 // the mask with the fields to be accessed in the special register.
3630 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3631 "msr", "\t$mask, $Rn",
3632 [/* For disassembly only; pattern left blank */]> {
3637 let Inst{22} = mask{4}; // R bit
3638 let Inst{21-20} = 0b10;
3639 let Inst{19-16} = mask{3-0};
3640 let Inst{15-12} = 0b1111;
3641 let Inst{11-4} = 0b00000000;
3645 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3646 "msr", "\t$mask, $a",
3647 [/* For disassembly only; pattern left blank */]> {
3652 let Inst{22} = mask{4}; // R bit
3653 let Inst{21-20} = 0b10;
3654 let Inst{19-16} = mask{3-0};
3655 let Inst{15-12} = 0b1111;
3659 //===----------------------------------------------------------------------===//
3663 // __aeabi_read_tp preserves the registers r1-r3.
3664 // This is a pseudo inst so that we can get the encoding right,
3665 // complete with fixup for the aeabi_read_tp function.
3667 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3668 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3669 [(set R0, ARMthread_pointer)]>;
3672 //===----------------------------------------------------------------------===//
3673 // SJLJ Exception handling intrinsics
3674 // eh_sjlj_setjmp() is an instruction sequence to store the return
3675 // address and save #0 in R0 for the non-longjmp case.
3676 // Since by its nature we may be coming from some other function to get
3677 // here, and we're using the stack frame for the containing function to
3678 // save/restore registers, we can't keep anything live in regs across
3679 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3680 // when we get here from a longjmp(). We force everthing out of registers
3681 // except for our own input by listing the relevant registers in Defs. By
3682 // doing so, we also cause the prologue/epilogue code to actively preserve
3683 // all of the callee-saved resgisters, which is exactly what we want.
3684 // A constant value is passed in $val, and we use the location as a scratch.
3686 // These are pseudo-instructions and are lowered to individual MC-insts, so
3687 // no encoding information is necessary.
3689 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3690 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3691 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3692 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3693 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3695 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3696 Requires<[IsARM, HasVFP2]>;
3700 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3701 hasSideEffects = 1, isBarrier = 1 in {
3702 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3704 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3705 Requires<[IsARM, NoVFP]>;
3708 // FIXME: Non-Darwin version(s)
3709 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3710 Defs = [ R7, LR, SP ] in {
3711 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3713 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3714 Requires<[IsARM, IsDarwin]>;
3717 // eh.sjlj.dispatchsetup pseudo-instruction.
3718 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3719 // handled when the pseudo is expanded (which happens before any passes
3720 // that need the instruction size).
3721 let isBarrier = 1, hasSideEffects = 1 in
3722 def Int_eh_sjlj_dispatchsetup :
3723 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3724 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3725 Requires<[IsDarwin]>;
3727 //===----------------------------------------------------------------------===//
3728 // Non-Instruction Patterns
3731 // Large immediate handling.
3733 // 32-bit immediate using two piece so_imms or movw + movt.
3734 // This is a single pseudo instruction, the benefit is that it can be remat'd
3735 // as a single unit instead of having to handle reg inputs.
3736 // FIXME: Remove this when we can do generalized remat.
3737 let isReMaterializable = 1, isMoveImm = 1 in
3738 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3739 [(set GPR:$dst, (arm_i32imm:$src))]>,
3742 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3743 // It also makes it possible to rematerialize the instructions.
3744 // FIXME: Remove this when we can do generalized remat and when machine licm
3745 // can properly the instructions.
3746 let isReMaterializable = 1 in {
3747 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3749 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3750 Requires<[IsARM, UseMovt]>;
3752 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3754 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3755 Requires<[IsARM, UseMovt]>;
3757 let AddedComplexity = 10 in
3758 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3760 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3761 Requires<[IsARM, UseMovt]>;
3762 } // isReMaterializable
3764 // ConstantPool, GlobalAddress, and JumpTable
3765 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3766 Requires<[IsARM, DontUseMovt]>;
3767 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3768 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3769 Requires<[IsARM, UseMovt]>;
3770 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3771 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3773 // TODO: add,sub,and, 3-instr forms?
3776 def : ARMPat<(ARMtcret tcGPR:$dst),
3777 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3779 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3780 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3782 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3783 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3785 def : ARMPat<(ARMtcret tcGPR:$dst),
3786 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3788 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3789 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3791 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3792 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3795 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3796 Requires<[IsARM, IsNotDarwin]>;
3797 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3798 Requires<[IsARM, IsDarwin]>;
3800 // zextload i1 -> zextload i8
3801 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3802 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3804 // extload -> zextload
3805 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3806 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3807 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3808 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3810 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3812 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3813 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3816 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3817 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3818 (SMULBB GPR:$a, GPR:$b)>;
3819 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3820 (SMULBB GPR:$a, GPR:$b)>;
3821 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3822 (sra GPR:$b, (i32 16))),
3823 (SMULBT GPR:$a, GPR:$b)>;
3824 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3825 (SMULBT GPR:$a, GPR:$b)>;
3826 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3827 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3828 (SMULTB GPR:$a, GPR:$b)>;
3829 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3830 (SMULTB GPR:$a, GPR:$b)>;
3831 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3833 (SMULWB GPR:$a, GPR:$b)>;
3834 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3835 (SMULWB GPR:$a, GPR:$b)>;
3837 def : ARMV5TEPat<(add GPR:$acc,
3838 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3839 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3840 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3841 def : ARMV5TEPat<(add GPR:$acc,
3842 (mul sext_16_node:$a, sext_16_node:$b)),
3843 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3844 def : ARMV5TEPat<(add GPR:$acc,
3845 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3846 (sra GPR:$b, (i32 16)))),
3847 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3848 def : ARMV5TEPat<(add GPR:$acc,
3849 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3850 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3851 def : ARMV5TEPat<(add GPR:$acc,
3852 (mul (sra GPR:$a, (i32 16)),
3853 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3854 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3855 def : ARMV5TEPat<(add GPR:$acc,
3856 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3857 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3858 def : ARMV5TEPat<(add GPR:$acc,
3859 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3861 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3862 def : ARMV5TEPat<(add GPR:$acc,
3863 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3864 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3867 // Pre-v7 uses MCR for synchronization barriers.
3868 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
3869 Requires<[IsARM, HasV6]>;
3872 //===----------------------------------------------------------------------===//
3876 include "ARMInstrThumb.td"
3878 //===----------------------------------------------------------------------===//
3882 include "ARMInstrThumb2.td"
3884 //===----------------------------------------------------------------------===//
3885 // Floating Point Support
3888 include "ARMInstrVFP.td"
3890 //===----------------------------------------------------------------------===//
3891 // Advanced SIMD (NEON) Support
3894 include "ARMInstrNEON.td"