1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
75 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
76 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
77 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
79 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
80 [SDNPHasChain, SDNPOutGlue]>;
81 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
84 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
90 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
91 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
94 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
95 [SDNPHasChain, SDNPOptInGlue]>;
97 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
100 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
101 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
103 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
105 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
108 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
111 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
114 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
115 [SDNPOutGlue, SDNPCommutative]>;
117 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
119 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
120 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
121 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
123 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
124 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
125 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
126 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
127 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
128 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
129 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
132 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
134 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
136 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
137 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
139 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
141 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
145 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
147 //===----------------------------------------------------------------------===//
148 // ARM Instruction Predicate Definitions.
150 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
151 AssemblerPredicate<"HasV4TOps">;
152 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
153 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
154 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
155 AssemblerPredicate<"HasV5TEOps">;
156 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
157 AssemblerPredicate<"HasV6Ops">;
158 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
159 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
160 AssemblerPredicate<"HasV6T2Ops">;
161 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
162 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
163 AssemblerPredicate<"HasV7Ops">;
164 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
165 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
166 AssemblerPredicate<"FeatureVFP2">;
167 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
168 AssemblerPredicate<"FeatureVFP3">;
169 def HasNEON : Predicate<"Subtarget->hasNEON()">,
170 AssemblerPredicate<"FeatureNEON">;
171 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
172 AssemblerPredicate<"FeatureFP16">;
173 def HasDivide : Predicate<"Subtarget->hasDivide()">,
174 AssemblerPredicate<"FeatureHWDiv">;
175 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
176 AssemblerPredicate<"FeatureT2XtPk">;
177 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
178 AssemblerPredicate<"FeatureDSPThumb2">;
179 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
180 AssemblerPredicate<"FeatureDB">;
181 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
182 AssemblerPredicate<"FeatureMP">;
183 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
184 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
185 def IsThumb : Predicate<"Subtarget->isThumb()">,
186 AssemblerPredicate<"ModeThumb">;
187 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
188 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
189 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
190 def IsARM : Predicate<"!Subtarget->isThumb()">,
191 AssemblerPredicate<"!ModeThumb">;
192 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
193 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
195 // FIXME: Eventually this will be just "hasV6T2Ops".
196 def UseMovt : Predicate<"Subtarget->useMovt()">;
197 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
198 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
200 //===----------------------------------------------------------------------===//
201 // ARM Flag Definitions.
203 class RegConstraint<string C> {
204 string Constraints = C;
207 //===----------------------------------------------------------------------===//
208 // ARM specific transformation functions and pattern fragments.
211 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
212 // so_imm_neg def below.
213 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
214 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
217 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
218 // so_imm_not def below.
219 def so_imm_not_XFORM : SDNodeXForm<imm, [{
220 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
223 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
224 def imm1_15 : ImmLeaf<i32, [{
225 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
228 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
229 def imm16_31 : ImmLeaf<i32, [{
230 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
235 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
236 }], so_imm_neg_XFORM>;
240 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
241 }], so_imm_not_XFORM>;
243 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
244 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
245 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
248 /// Split a 32-bit immediate into two 16 bit parts.
249 def hi16 : SDNodeXForm<imm, [{
250 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
253 def lo16AllZero : PatLeaf<(i32 imm), [{
254 // Returns true if all low 16-bits are 0.
255 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
258 /// imm0_65535 - An immediate is in the range [0.65535].
259 def Imm0_65535AsmOperand: AsmOperandClass { let Name = "Imm0_65535"; }
260 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
261 return Imm >= 0 && Imm < 65536;
263 let ParserMatchClass = Imm0_65535AsmOperand;
266 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
267 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
269 /// adde and sube predicates - True based on whether the carry flag output
270 /// will be needed or not.
271 def adde_dead_carry :
272 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
273 [{return !N->hasAnyUseOfValue(1);}]>;
274 def sube_dead_carry :
275 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
276 [{return !N->hasAnyUseOfValue(1);}]>;
277 def adde_live_carry :
278 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
279 [{return N->hasAnyUseOfValue(1);}]>;
280 def sube_live_carry :
281 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
282 [{return N->hasAnyUseOfValue(1);}]>;
284 // An 'and' node with a single use.
285 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
286 return N->hasOneUse();
289 // An 'xor' node with a single use.
290 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
291 return N->hasOneUse();
294 // An 'fmul' node with a single use.
295 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
296 return N->hasOneUse();
299 // An 'fadd' node which checks for single non-hazardous use.
300 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
301 return hasNoVMLxHazardUse(N);
304 // An 'fsub' node which checks for single non-hazardous use.
305 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
306 return hasNoVMLxHazardUse(N);
309 //===----------------------------------------------------------------------===//
310 // Operand Definitions.
314 // FIXME: rename brtarget to t2_brtarget
315 def brtarget : Operand<OtherVT> {
316 let EncoderMethod = "getBranchTargetOpValue";
317 let OperandType = "OPERAND_PCREL";
318 let DecoderMethod = "DecodeT2BROperand";
321 // FIXME: get rid of this one?
322 def uncondbrtarget : Operand<OtherVT> {
323 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
324 let OperandType = "OPERAND_PCREL";
327 // Branch target for ARM. Handles conditional/unconditional
328 def br_target : Operand<OtherVT> {
329 let EncoderMethod = "getARMBranchTargetOpValue";
330 let OperandType = "OPERAND_PCREL";
334 // FIXME: rename bltarget to t2_bl_target?
335 def bltarget : Operand<i32> {
336 // Encoded the same as branch targets.
337 let EncoderMethod = "getBranchTargetOpValue";
338 let OperandType = "OPERAND_PCREL";
341 // Call target for ARM. Handles conditional/unconditional
342 // FIXME: rename bl_target to t2_bltarget?
343 def bl_target : Operand<i32> {
344 // Encoded the same as branch targets.
345 let EncoderMethod = "getARMBranchTargetOpValue";
346 let OperandType = "OPERAND_PCREL";
347 let DecoderMethod = "DecodeBLTargetOperand";
351 // A list of registers separated by comma. Used by load/store multiple.
352 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
353 def reglist : Operand<i32> {
354 let EncoderMethod = "getRegisterListOpValue";
355 let ParserMatchClass = RegListAsmOperand;
356 let PrintMethod = "printRegisterList";
357 let DecoderMethod = "DecodeRegListOperand";
360 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
361 def dpr_reglist : Operand<i32> {
362 let EncoderMethod = "getRegisterListOpValue";
363 let ParserMatchClass = DPRRegListAsmOperand;
364 let PrintMethod = "printRegisterList";
365 let DecoderMethod = "DecodeDPRRegListOperand";
368 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
369 def spr_reglist : Operand<i32> {
370 let EncoderMethod = "getRegisterListOpValue";
371 let ParserMatchClass = SPRRegListAsmOperand;
372 let PrintMethod = "printRegisterList";
373 let DecoderMethod = "DecodeSPRRegListOperand";
376 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
377 def cpinst_operand : Operand<i32> {
378 let PrintMethod = "printCPInstOperand";
382 def pclabel : Operand<i32> {
383 let PrintMethod = "printPCLabel";
386 // ADR instruction labels.
387 def adrlabel : Operand<i32> {
388 let EncoderMethod = "getAdrLabelOpValue";
391 def neon_vcvt_imm32 : Operand<i32> {
392 let EncoderMethod = "getNEONVcvtImm32OpValue";
393 let DecoderMethod = "DecodeVCVTImmOperand";
396 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
397 def rot_imm_XFORM: SDNodeXForm<imm, [{
398 switch (N->getZExtValue()){
400 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
401 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
402 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
403 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
406 def RotImmAsmOperand : AsmOperandClass {
408 let ParserMethod = "parseRotImm";
410 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
411 int32_t v = N->getZExtValue();
412 return v == 8 || v == 16 || v == 24; }],
414 let PrintMethod = "printRotImmOperand";
415 let ParserMatchClass = RotImmAsmOperand;
418 // shift_imm: An integer that encodes a shift amount and the type of shift
419 // (asr or lsl). The 6-bit immediate encodes as:
422 // {4-0} imm5 shift amount.
423 // asr #32 encoded as imm5 == 0.
424 def ShifterImmAsmOperand : AsmOperandClass {
425 let Name = "ShifterImm";
426 let ParserMethod = "parseShifterImm";
428 def shift_imm : Operand<i32> {
429 let PrintMethod = "printShiftImmOperand";
430 let ParserMatchClass = ShifterImmAsmOperand;
433 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
434 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
435 def so_reg_reg : Operand<i32>, // reg reg imm
436 ComplexPattern<i32, 3, "SelectRegShifterOperand",
437 [shl, srl, sra, rotr]> {
438 let EncoderMethod = "getSORegRegOpValue";
439 let PrintMethod = "printSORegRegOperand";
440 let DecoderMethod = "DecodeSORegRegOperand";
441 let ParserMatchClass = ShiftedRegAsmOperand;
442 let MIOperandInfo = (ops GPR, GPR, i32imm);
445 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
446 def so_reg_imm : Operand<i32>, // reg imm
447 ComplexPattern<i32, 2, "SelectImmShifterOperand",
448 [shl, srl, sra, rotr]> {
449 let EncoderMethod = "getSORegImmOpValue";
450 let PrintMethod = "printSORegImmOperand";
451 let DecoderMethod = "DecodeSORegImmOperand";
452 let ParserMatchClass = ShiftedImmAsmOperand;
453 let MIOperandInfo = (ops GPR, i32imm);
456 // FIXME: Does this need to be distinct from so_reg?
457 def shift_so_reg_reg : Operand<i32>, // reg reg imm
458 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
459 [shl,srl,sra,rotr]> {
460 let EncoderMethod = "getSORegRegOpValue";
461 let PrintMethod = "printSORegRegOperand";
462 let DecoderMethod = "DecodeSORegRegOperand";
463 let MIOperandInfo = (ops GPR, GPR, i32imm);
466 // FIXME: Does this need to be distinct from so_reg?
467 def shift_so_reg_imm : Operand<i32>, // reg reg imm
468 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
469 [shl,srl,sra,rotr]> {
470 let EncoderMethod = "getSORegImmOpValue";
471 let PrintMethod = "printSORegImmOperand";
472 let DecoderMethod = "DecodeSORegImmOperand";
473 let MIOperandInfo = (ops GPR, i32imm);
477 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
478 // 8-bit immediate rotated by an arbitrary number of bits.
479 def SOImmAsmOperand: AsmOperandClass { let Name = "ARMSOImm"; }
480 def so_imm : Operand<i32>, ImmLeaf<i32, [{
481 return ARM_AM::getSOImmVal(Imm) != -1;
483 let EncoderMethod = "getSOImmOpValue";
484 let ParserMatchClass = SOImmAsmOperand;
485 let DecoderMethod = "DecodeSOImmOperand";
488 // Break so_imm's up into two pieces. This handles immediates with up to 16
489 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
490 // get the first/second pieces.
491 def so_imm2part : PatLeaf<(imm), [{
492 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
495 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
497 def arm_i32imm : PatLeaf<(imm), [{
498 if (Subtarget->hasV6T2Ops())
500 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
503 /// imm0_7 predicate - Immediate in the range [0,7].
504 def Imm0_7AsmOperand: AsmOperandClass { let Name = "Imm0_7"; }
505 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
506 return Imm >= 0 && Imm < 8;
508 let ParserMatchClass = Imm0_7AsmOperand;
511 /// imm0_15 predicate - Immediate in the range [0,15].
512 def Imm0_15AsmOperand: AsmOperandClass { let Name = "Imm0_15"; }
513 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
514 return Imm >= 0 && Imm < 16;
516 let ParserMatchClass = Imm0_15AsmOperand;
519 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
520 def Imm0_31AsmOperand: AsmOperandClass { let Name = "Imm0_31"; }
521 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
522 return Imm >= 0 && Imm < 32;
524 let ParserMatchClass = Imm0_31AsmOperand;
527 /// imm0_255 predicate - Immediate in the range [0,255].
528 def Imm0_255AsmOperand : AsmOperandClass { let Name = "Imm0_255"; }
529 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
530 let ParserMatchClass = Imm0_255AsmOperand;
533 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
534 // a relocatable expression.
536 // FIXME: This really needs a Thumb version separate from the ARM version.
537 // While the range is the same, and can thus use the same match class,
538 // the encoding is different so it should have a different encoder method.
539 def Imm0_65535ExprAsmOperand: AsmOperandClass { let Name = "Imm0_65535Expr"; }
540 def imm0_65535_expr : Operand<i32> {
541 let EncoderMethod = "getHiLo16ImmOpValue";
542 let ParserMatchClass = Imm0_65535ExprAsmOperand;
545 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
546 def Imm24bitAsmOperand: AsmOperandClass { let Name = "Imm24bit"; }
547 def imm24b : Operand<i32>, ImmLeaf<i32, [{
548 return Imm >= 0 && Imm <= 0xffffff;
550 let ParserMatchClass = Imm24bitAsmOperand;
554 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
556 def BitfieldAsmOperand : AsmOperandClass {
557 let Name = "Bitfield";
558 let ParserMethod = "parseBitfield";
560 def bf_inv_mask_imm : Operand<i32>,
562 return ARM::isBitFieldInvertedMask(N->getZExtValue());
564 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
565 let PrintMethod = "printBitfieldInvMaskImmOperand";
566 let DecoderMethod = "DecodeBitfieldMaskOperand";
567 let ParserMatchClass = BitfieldAsmOperand;
570 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
571 def lsb_pos_imm : Operand<i32>, ImmLeaf<i32, [{
572 return isInt<5>(Imm);
575 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
576 def width_imm : Operand<i32>, ImmLeaf<i32, [{
577 return Imm > 0 && Imm <= 32;
579 let EncoderMethod = "getMsbOpValue";
582 def imm1_32_XFORM: SDNodeXForm<imm, [{
583 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
585 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
586 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 32; }],
588 let PrintMethod = "printImmPlusOneOperand";
589 let ParserMatchClass = Imm1_32AsmOperand;
592 def imm1_16_XFORM: SDNodeXForm<imm, [{
593 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
595 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
596 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
598 let PrintMethod = "printImmPlusOneOperand";
599 let ParserMatchClass = Imm1_16AsmOperand;
602 // Define ARM specific addressing modes.
603 // addrmode_imm12 := reg +/- imm12
605 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
606 def addrmode_imm12 : Operand<i32>,
607 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
608 // 12-bit immediate operand. Note that instructions using this encode
609 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
610 // immediate values are as normal.
612 let EncoderMethod = "getAddrModeImm12OpValue";
613 let PrintMethod = "printAddrModeImm12Operand";
614 let DecoderMethod = "DecodeAddrModeImm12Operand";
615 let ParserMatchClass = MemImm12OffsetAsmOperand;
616 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
618 // ldst_so_reg := reg +/- reg shop imm
620 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
621 def ldst_so_reg : Operand<i32>,
622 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
623 let EncoderMethod = "getLdStSORegOpValue";
624 // FIXME: Simplify the printer
625 let PrintMethod = "printAddrMode2Operand";
626 let DecoderMethod = "DecodeSORegMemOperand";
627 let ParserMatchClass = MemRegOffsetAsmOperand;
628 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$shift);
631 // postidx_imm8 := +/- [0,255]
634 // {8} 1 is imm8 is non-negative. 0 otherwise.
635 // {7-0} [0,255] imm8 value.
636 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
637 def postidx_imm8 : Operand<i32> {
638 let PrintMethod = "printPostIdxImm8Operand";
639 let ParserMatchClass = PostIdxImm8AsmOperand;
640 let MIOperandInfo = (ops i32imm);
643 // postidx_imm8s4 := +/- [0,1020]
646 // {8} 1 is imm8 is non-negative. 0 otherwise.
647 // {7-0} [0,255] imm8 value, scaled by 4.
648 def postidx_imm8s4 : Operand<i32> {
649 let PrintMethod = "printPostIdxImm8s4Operand";
650 let MIOperandInfo = (ops i32imm);
654 // postidx_reg := +/- reg
656 def PostIdxRegAsmOperand : AsmOperandClass {
657 let Name = "PostIdxReg";
658 let ParserMethod = "parsePostIdxReg";
660 def postidx_reg : Operand<i32> {
661 let EncoderMethod = "getPostIdxRegOpValue";
662 let DecoderMethod = "DecodePostIdxReg";
663 let PrintMethod = "printPostIdxRegOperand";
664 let ParserMatchClass = PostIdxRegAsmOperand;
665 let MIOperandInfo = (ops GPR, i32imm);
669 // addrmode2 := reg +/- imm12
670 // := reg +/- reg shop imm
672 // FIXME: addrmode2 should be refactored the rest of the way to always
673 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
674 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
675 def addrmode2 : Operand<i32>,
676 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
677 let EncoderMethod = "getAddrMode2OpValue";
678 let PrintMethod = "printAddrMode2Operand";
679 let ParserMatchClass = AddrMode2AsmOperand;
680 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
683 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
684 let Name = "PostIdxRegShifted";
685 let ParserMethod = "parsePostIdxReg";
687 def am2offset_reg : Operand<i32>,
688 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
689 [], [SDNPWantRoot]> {
690 let EncoderMethod = "getAddrMode2OffsetOpValue";
691 let PrintMethod = "printAddrMode2OffsetOperand";
692 // When using this for assembly, it's always as a post-index offset.
693 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
694 let MIOperandInfo = (ops GPR, i32imm);
697 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
698 // the GPR is purely vestigal at this point.
699 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
700 def am2offset_imm : Operand<i32>,
701 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
702 [], [SDNPWantRoot]> {
703 let EncoderMethod = "getAddrMode2OffsetOpValue";
704 let PrintMethod = "printAddrMode2OffsetOperand";
705 let ParserMatchClass = AM2OffsetImmAsmOperand;
706 let MIOperandInfo = (ops GPR, i32imm);
710 // addrmode3 := reg +/- reg
711 // addrmode3 := reg +/- imm8
713 //def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
714 def addrmode3 : Operand<i32>,
715 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
716 let EncoderMethod = "getAddrMode3OpValue";
717 let PrintMethod = "printAddrMode3Operand";
718 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
721 def am3offset : Operand<i32>,
722 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
723 [], [SDNPWantRoot]> {
724 let EncoderMethod = "getAddrMode3OffsetOpValue";
725 let DecoderMethod = "DecodeAddrMode3Offset";
726 let PrintMethod = "printAddrMode3OffsetOperand";
727 let MIOperandInfo = (ops GPR, i32imm);
730 // ldstm_mode := {ia, ib, da, db}
732 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
733 let EncoderMethod = "getLdStmModeOpValue";
734 let PrintMethod = "printLdStmModeOperand";
737 // addrmode5 := reg +/- imm8*4
739 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
740 def addrmode5 : Operand<i32>,
741 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
742 let PrintMethod = "printAddrMode5Operand";
743 let EncoderMethod = "getAddrMode5OpValue";
744 let DecoderMethod = "DecodeAddrMode5Operand";
745 let ParserMatchClass = AddrMode5AsmOperand;
746 let MIOperandInfo = (ops GPR:$base, i32imm);
749 // addrmode6 := reg with optional alignment
751 def addrmode6 : Operand<i32>,
752 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
753 let PrintMethod = "printAddrMode6Operand";
754 let MIOperandInfo = (ops GPR:$addr, i32imm);
755 let EncoderMethod = "getAddrMode6AddressOpValue";
756 let DecoderMethod = "DecodeAddrMode6Operand";
759 def am6offset : Operand<i32>,
760 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
761 [], [SDNPWantRoot]> {
762 let PrintMethod = "printAddrMode6OffsetOperand";
763 let MIOperandInfo = (ops GPR);
764 let EncoderMethod = "getAddrMode6OffsetOpValue";
765 let DecoderMethod = "DecodeGPRRegisterClass";
768 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
769 // (single element from one lane) for size 32.
770 def addrmode6oneL32 : Operand<i32>,
771 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
772 let PrintMethod = "printAddrMode6Operand";
773 let MIOperandInfo = (ops GPR:$addr, i32imm);
774 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
777 // Special version of addrmode6 to handle alignment encoding for VLD-dup
778 // instructions, specifically VLD4-dup.
779 def addrmode6dup : Operand<i32>,
780 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
781 let PrintMethod = "printAddrMode6Operand";
782 let MIOperandInfo = (ops GPR:$addr, i32imm);
783 let EncoderMethod = "getAddrMode6DupAddressOpValue";
786 // addrmodepc := pc + reg
788 def addrmodepc : Operand<i32>,
789 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
790 let PrintMethod = "printAddrModePCOperand";
791 let MIOperandInfo = (ops GPR, i32imm);
794 // addr_offset_none := reg
796 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
797 def addr_offset_none : Operand<i32>,
798 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
799 let PrintMethod = "printAddrMode7Operand";
800 let DecoderMethod = "DecodeAddrMode7Operand";
801 let ParserMatchClass = MemNoOffsetAsmOperand;
802 let MIOperandInfo = (ops GPR:$base);
805 def nohash_imm : Operand<i32> {
806 let PrintMethod = "printNoHashImmediate";
809 def CoprocNumAsmOperand : AsmOperandClass {
810 let Name = "CoprocNum";
811 let ParserMethod = "parseCoprocNumOperand";
813 def p_imm : Operand<i32> {
814 let PrintMethod = "printPImmediate";
815 let ParserMatchClass = CoprocNumAsmOperand;
816 let DecoderMethod = "DecodeCoprocessor";
819 def CoprocRegAsmOperand : AsmOperandClass {
820 let Name = "CoprocReg";
821 let ParserMethod = "parseCoprocRegOperand";
823 def c_imm : Operand<i32> {
824 let PrintMethod = "printCImmediate";
825 let ParserMatchClass = CoprocRegAsmOperand;
828 //===----------------------------------------------------------------------===//
830 include "ARMInstrFormats.td"
832 //===----------------------------------------------------------------------===//
833 // Multiclass helpers...
836 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
837 /// binop that produces a value.
838 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
839 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
840 PatFrag opnode, string baseOpc, bit Commutable = 0> {
841 // The register-immediate version is re-materializable. This is useful
842 // in particular for taking the address of a local.
843 let isReMaterializable = 1 in {
844 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
845 iii, opc, "\t$Rd, $Rn, $imm",
846 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
851 let Inst{19-16} = Rn;
852 let Inst{15-12} = Rd;
853 let Inst{11-0} = imm;
856 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
857 iir, opc, "\t$Rd, $Rn, $Rm",
858 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
863 let isCommutable = Commutable;
864 let Inst{19-16} = Rn;
865 let Inst{15-12} = Rd;
866 let Inst{11-4} = 0b00000000;
870 def rsi : AsI1<opcod, (outs GPR:$Rd),
871 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
872 iis, opc, "\t$Rd, $Rn, $shift",
873 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
878 let Inst{19-16} = Rn;
879 let Inst{15-12} = Rd;
880 let Inst{11-5} = shift{11-5};
882 let Inst{3-0} = shift{3-0};
885 def rsr : AsI1<opcod, (outs GPR:$Rd),
886 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
887 iis, opc, "\t$Rd, $Rn, $shift",
888 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
893 let Inst{19-16} = Rn;
894 let Inst{15-12} = Rd;
895 let Inst{11-8} = shift{11-8};
897 let Inst{6-5} = shift{6-5};
899 let Inst{3-0} = shift{3-0};
902 // Assembly aliases for optional destination operand when it's the same
903 // as the source operand.
904 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
905 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
906 so_imm:$imm, pred:$p,
909 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
910 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
914 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
915 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
916 so_reg_imm:$shift, pred:$p,
919 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
920 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
921 so_reg_reg:$shift, pred:$p,
927 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
928 /// instruction modifies the CPSR register.
929 let isCodeGenOnly = 1, Defs = [CPSR] in {
930 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
931 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
932 PatFrag opnode, bit Commutable = 0> {
933 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
934 iii, opc, "\t$Rd, $Rn, $imm",
935 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
941 let Inst{19-16} = Rn;
942 let Inst{15-12} = Rd;
943 let Inst{11-0} = imm;
945 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
946 iir, opc, "\t$Rd, $Rn, $Rm",
947 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
951 let isCommutable = Commutable;
954 let Inst{19-16} = Rn;
955 let Inst{15-12} = Rd;
956 let Inst{11-4} = 0b00000000;
959 def rsi : AI1<opcod, (outs GPR:$Rd),
960 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
961 iis, opc, "\t$Rd, $Rn, $shift",
962 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
968 let Inst{19-16} = Rn;
969 let Inst{15-12} = Rd;
970 let Inst{11-5} = shift{11-5};
972 let Inst{3-0} = shift{3-0};
975 def rsr : AI1<opcod, (outs GPR:$Rd),
976 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
977 iis, opc, "\t$Rd, $Rn, $shift",
978 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
984 let Inst{19-16} = Rn;
985 let Inst{15-12} = Rd;
986 let Inst{11-8} = shift{11-8};
988 let Inst{6-5} = shift{6-5};
990 let Inst{3-0} = shift{3-0};
995 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
996 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
997 /// a explicit result, only implicitly set CPSR.
998 let isCompare = 1, Defs = [CPSR] in {
999 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1000 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1001 PatFrag opnode, bit Commutable = 0> {
1002 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1004 [(opnode GPR:$Rn, so_imm:$imm)]> {
1009 let Inst{19-16} = Rn;
1010 let Inst{15-12} = 0b0000;
1011 let Inst{11-0} = imm;
1013 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1015 [(opnode GPR:$Rn, GPR:$Rm)]> {
1018 let isCommutable = Commutable;
1021 let Inst{19-16} = Rn;
1022 let Inst{15-12} = 0b0000;
1023 let Inst{11-4} = 0b00000000;
1026 def rsi : AI1<opcod, (outs),
1027 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1028 opc, "\t$Rn, $shift",
1029 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1034 let Inst{19-16} = Rn;
1035 let Inst{15-12} = 0b0000;
1036 let Inst{11-5} = shift{11-5};
1038 let Inst{3-0} = shift{3-0};
1040 def rsr : AI1<opcod, (outs),
1041 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1042 opc, "\t$Rn, $shift",
1043 [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
1048 let Inst{19-16} = Rn;
1049 let Inst{15-12} = 0b0000;
1050 let Inst{11-8} = shift{11-8};
1052 let Inst{6-5} = shift{6-5};
1054 let Inst{3-0} = shift{3-0};
1060 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1061 /// register and one whose operand is a register rotated by 8/16/24.
1062 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1063 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1064 : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
1065 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1066 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
1067 Requires<[IsARM, HasV6]> {
1071 let Inst{19-16} = 0b1111;
1072 let Inst{15-12} = Rd;
1073 let Inst{11-10} = rot;
1077 class AI_ext_rrot_np<bits<8> opcod, string opc>
1078 : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
1079 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1080 Requires<[IsARM, HasV6]> {
1082 let Inst{19-16} = 0b1111;
1083 let Inst{11-10} = rot;
1086 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1087 /// register and one whose operand is a register rotated by 8/16/24.
1088 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1089 : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, rot_imm:$rot),
1090 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1091 [(set GPR:$Rd, (opnode GPR:$Rn, (rotr GPR:$Rm, rot_imm:$rot)))]>,
1092 Requires<[IsARM, HasV6]> {
1097 let Inst{19-16} = Rn;
1098 let Inst{15-12} = Rd;
1099 let Inst{11-10} = rot;
1100 let Inst{9-4} = 0b000111;
1104 class AI_exta_rrot_np<bits<8> opcod, string opc>
1105 : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, rot_imm:$rot),
1106 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1107 Requires<[IsARM, HasV6]> {
1110 let Inst{19-16} = Rn;
1111 let Inst{11-10} = rot;
1114 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1115 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1116 string baseOpc, bit Commutable = 0> {
1117 let Uses = [CPSR] in {
1118 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1119 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1120 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1126 let Inst{15-12} = Rd;
1127 let Inst{19-16} = Rn;
1128 let Inst{11-0} = imm;
1130 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1131 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1132 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1137 let Inst{11-4} = 0b00000000;
1139 let isCommutable = Commutable;
1141 let Inst{15-12} = Rd;
1142 let Inst{19-16} = Rn;
1144 def rsi : AsI1<opcod, (outs GPR:$Rd),
1145 (ins GPR:$Rn, so_reg_imm:$shift),
1146 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1147 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1153 let Inst{19-16} = Rn;
1154 let Inst{15-12} = Rd;
1155 let Inst{11-5} = shift{11-5};
1157 let Inst{3-0} = shift{3-0};
1159 def rsr : AsI1<opcod, (outs GPR:$Rd),
1160 (ins GPR:$Rn, so_reg_reg:$shift),
1161 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1162 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1168 let Inst{19-16} = Rn;
1169 let Inst{15-12} = Rd;
1170 let Inst{11-8} = shift{11-8};
1172 let Inst{6-5} = shift{6-5};
1174 let Inst{3-0} = shift{3-0};
1177 // Assembly aliases for optional destination operand when it's the same
1178 // as the source operand.
1179 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1180 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1181 so_imm:$imm, pred:$p,
1184 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1185 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1189 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1190 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1191 so_reg_imm:$shift, pred:$p,
1194 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1195 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1196 so_reg_reg:$shift, pred:$p,
1201 // Carry setting variants
1202 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
1203 let usesCustomInserter = 1 in {
1204 multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
1205 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1207 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>;
1208 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1210 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
1211 let isCommutable = Commutable;
1213 def rsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1215 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>;
1216 def rsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1218 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>;
1222 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1223 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1224 InstrItinClass iir, PatFrag opnode> {
1225 // Note: We use the complex addrmode_imm12 rather than just an input
1226 // GPR and a constrained immediate so that we can use this to match
1227 // frame index references and avoid matching constant pool references.
1228 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1229 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1230 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1233 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1234 let Inst{19-16} = addr{16-13}; // Rn
1235 let Inst{15-12} = Rt;
1236 let Inst{11-0} = addr{11-0}; // imm12
1238 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1239 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1240 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1243 let shift{4} = 0; // Inst{4} = 0
1244 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1245 let Inst{19-16} = shift{16-13}; // Rn
1246 let Inst{15-12} = Rt;
1247 let Inst{11-0} = shift{11-0};
1252 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1253 InstrItinClass iir, PatFrag opnode> {
1254 // Note: We use the complex addrmode_imm12 rather than just an input
1255 // GPR and a constrained immediate so that we can use this to match
1256 // frame index references and avoid matching constant pool references.
1257 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1258 (ins GPR:$Rt, addrmode_imm12:$addr),
1259 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1260 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1263 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1264 let Inst{19-16} = addr{16-13}; // Rn
1265 let Inst{15-12} = Rt;
1266 let Inst{11-0} = addr{11-0}; // imm12
1268 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1269 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1270 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1273 let shift{4} = 0; // Inst{4} = 0
1274 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1275 let Inst{19-16} = shift{16-13}; // Rn
1276 let Inst{15-12} = Rt;
1277 let Inst{11-0} = shift{11-0};
1280 //===----------------------------------------------------------------------===//
1282 //===----------------------------------------------------------------------===//
1284 //===----------------------------------------------------------------------===//
1285 // Miscellaneous Instructions.
1288 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1289 /// the function. The first operand is the ID# for this instruction, the second
1290 /// is the index into the MachineConstantPool that this is, the third is the
1291 /// size in bytes of this constant pool entry.
1292 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1293 def CONSTPOOL_ENTRY :
1294 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1295 i32imm:$size), NoItinerary, []>;
1297 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1298 // from removing one half of the matched pairs. That breaks PEI, which assumes
1299 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1300 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1301 def ADJCALLSTACKUP :
1302 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1303 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1305 def ADJCALLSTACKDOWN :
1306 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1307 [(ARMcallseq_start timm:$amt)]>;
1310 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1311 [/* For disassembly only; pattern left blank */]>,
1312 Requires<[IsARM, HasV6T2]> {
1313 let Inst{27-16} = 0b001100100000;
1314 let Inst{15-8} = 0b11110000;
1315 let Inst{7-0} = 0b00000000;
1318 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1319 [/* For disassembly only; pattern left blank */]>,
1320 Requires<[IsARM, HasV6T2]> {
1321 let Inst{27-16} = 0b001100100000;
1322 let Inst{15-8} = 0b11110000;
1323 let Inst{7-0} = 0b00000001;
1326 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1327 [/* For disassembly only; pattern left blank */]>,
1328 Requires<[IsARM, HasV6T2]> {
1329 let Inst{27-16} = 0b001100100000;
1330 let Inst{15-8} = 0b11110000;
1331 let Inst{7-0} = 0b00000010;
1334 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1335 [/* For disassembly only; pattern left blank */]>,
1336 Requires<[IsARM, HasV6T2]> {
1337 let Inst{27-16} = 0b001100100000;
1338 let Inst{15-8} = 0b11110000;
1339 let Inst{7-0} = 0b00000011;
1342 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1343 "\t$dst, $a, $b", []>, Requires<[IsARM, HasV6]> {
1348 let Inst{15-12} = Rd;
1349 let Inst{19-16} = Rn;
1350 let Inst{27-20} = 0b01101000;
1351 let Inst{7-4} = 0b1011;
1352 let Inst{11-8} = 0b1111;
1355 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1356 []>, Requires<[IsARM, HasV6T2]> {
1357 let Inst{27-16} = 0b001100100000;
1358 let Inst{15-8} = 0b11110000;
1359 let Inst{7-0} = 0b00000100;
1362 // The i32imm operand $val can be used by a debugger to store more information
1363 // about the breakpoint.
1364 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1365 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1367 let Inst{3-0} = val{3-0};
1368 let Inst{19-8} = val{15-4};
1369 let Inst{27-20} = 0b00010010;
1370 let Inst{7-4} = 0b0111;
1373 // Change Processor State
1374 // FIXME: We should use InstAlias to handle the optional operands.
1375 class CPS<dag iops, string asm_ops>
1376 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1377 []>, Requires<[IsARM]> {
1383 let Inst{31-28} = 0b1111;
1384 let Inst{27-20} = 0b00010000;
1385 let Inst{19-18} = imod;
1386 let Inst{17} = M; // Enabled if mode is set;
1388 let Inst{8-6} = iflags;
1390 let Inst{4-0} = mode;
1394 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1395 "$imod\t$iflags, $mode">;
1396 let mode = 0, M = 0 in
1397 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1399 let imod = 0, iflags = 0, M = 1 in
1400 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1402 // Preload signals the memory system of possible future data/instruction access.
1403 // These are for disassembly only.
1404 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1406 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1407 !strconcat(opc, "\t$addr"),
1408 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1411 let Inst{31-26} = 0b111101;
1412 let Inst{25} = 0; // 0 for immediate form
1413 let Inst{24} = data;
1414 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1415 let Inst{22} = read;
1416 let Inst{21-20} = 0b01;
1417 let Inst{19-16} = addr{16-13}; // Rn
1418 let Inst{15-12} = 0b1111;
1419 let Inst{11-0} = addr{11-0}; // imm12
1422 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1423 !strconcat(opc, "\t$shift"),
1424 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1426 let Inst{31-26} = 0b111101;
1427 let Inst{25} = 1; // 1 for register form
1428 let Inst{24} = data;
1429 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1430 let Inst{22} = read;
1431 let Inst{21-20} = 0b01;
1432 let Inst{19-16} = shift{16-13}; // Rn
1433 let Inst{15-12} = 0b1111;
1434 let Inst{11-0} = shift{11-0};
1438 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1439 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1440 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1442 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1443 "setend\t$end", []>, Requires<[IsARM]> {
1445 let Inst{31-10} = 0b1111000100000001000000;
1450 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1451 []>, Requires<[IsARM, HasV7]> {
1453 let Inst{27-4} = 0b001100100000111100001111;
1454 let Inst{3-0} = opt;
1457 // A5.4 Permanently UNDEFINED instructions.
1458 let isBarrier = 1, isTerminator = 1 in
1459 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1462 let Inst = 0xe7ffdefe;
1465 // Address computation and loads and stores in PIC mode.
1466 let isNotDuplicable = 1 in {
1467 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1469 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1471 let AddedComplexity = 10 in {
1472 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1474 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1476 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1478 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1480 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1482 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1484 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1486 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1488 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1490 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1492 let AddedComplexity = 10 in {
1493 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1494 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1496 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1497 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1498 addrmodepc:$addr)]>;
1500 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1501 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1503 } // isNotDuplicable = 1
1506 // LEApcrel - Load a pc-relative address into a register without offending the
1508 let neverHasSideEffects = 1, isReMaterializable = 1 in
1509 // The 'adr' mnemonic encodes differently if the label is before or after
1510 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1511 // know until then which form of the instruction will be used.
1512 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1513 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1516 let Inst{27-25} = 0b001;
1518 let Inst{19-16} = 0b1111;
1519 let Inst{15-12} = Rd;
1520 let Inst{11-0} = label;
1522 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1525 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1526 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1529 //===----------------------------------------------------------------------===//
1530 // Control Flow Instructions.
1533 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1535 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1536 "bx", "\tlr", [(ARMretflag)]>,
1537 Requires<[IsARM, HasV4T]> {
1538 let Inst{27-0} = 0b0001001011111111111100011110;
1542 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1543 "mov", "\tpc, lr", [(ARMretflag)]>,
1544 Requires<[IsARM, NoV4T]> {
1545 let Inst{27-0} = 0b0001101000001111000000001110;
1549 // Indirect branches
1550 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1552 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1553 [(brind GPR:$dst)]>,
1554 Requires<[IsARM, HasV4T]> {
1556 let Inst{31-4} = 0b1110000100101111111111110001;
1557 let Inst{3-0} = dst;
1560 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1561 "bx", "\t$dst", [/* pattern left blank */]>,
1562 Requires<[IsARM, HasV4T]> {
1564 let Inst{27-4} = 0b000100101111111111110001;
1565 let Inst{3-0} = dst;
1569 // All calls clobber the non-callee saved registers. SP is marked as
1570 // a use to prevent stack-pointer assignments that appear immediately
1571 // before calls from potentially appearing dead.
1573 // On non-Darwin platforms R9 is callee-saved.
1574 // FIXME: Do we really need a non-predicated version? If so, it should
1575 // at least be a pseudo instruction expanding to the predicated version
1576 // at MC lowering time.
1577 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1579 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1580 IIC_Br, "bl\t$func",
1581 [(ARMcall tglobaladdr:$func)]>,
1582 Requires<[IsARM, IsNotDarwin]> {
1583 let Inst{31-28} = 0b1110;
1585 let Inst{23-0} = func;
1588 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1589 IIC_Br, "bl", "\t$func",
1590 [(ARMcall_pred tglobaladdr:$func)]>,
1591 Requires<[IsARM, IsNotDarwin]> {
1593 let Inst{23-0} = func;
1597 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1598 IIC_Br, "blx\t$func",
1599 [(ARMcall GPR:$func)]>,
1600 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1602 let Inst{31-4} = 0b1110000100101111111111110011;
1603 let Inst{3-0} = func;
1606 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1607 IIC_Br, "blx", "\t$func",
1608 [(ARMcall_pred GPR:$func)]>,
1609 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1611 let Inst{27-4} = 0b000100101111111111110011;
1612 let Inst{3-0} = func;
1616 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1617 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1618 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1619 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1622 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1623 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1624 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1628 // On Darwin R9 is call-clobbered.
1629 // R7 is marked as a use to prevent frame-pointer assignments from being
1630 // moved above / below calls.
1631 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1632 Uses = [R7, SP] in {
1633 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1635 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1636 Requires<[IsARM, IsDarwin]>;
1638 def BLr9_pred : ARMPseudoExpand<(outs),
1639 (ins bl_target:$func, pred:$p, variable_ops),
1641 [(ARMcall_pred tglobaladdr:$func)],
1642 (BL_pred bl_target:$func, pred:$p)>,
1643 Requires<[IsARM, IsDarwin]>;
1646 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1648 [(ARMcall GPR:$func)],
1650 Requires<[IsARM, HasV5T, IsDarwin]>;
1652 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1654 [(ARMcall_pred GPR:$func)],
1655 (BLX_pred GPR:$func, pred:$p)>,
1656 Requires<[IsARM, HasV5T, IsDarwin]>;
1659 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1660 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1661 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1662 Requires<[IsARM, HasV4T, IsDarwin]>;
1665 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1666 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1667 Requires<[IsARM, NoV4T, IsDarwin]>;
1670 let isBranch = 1, isTerminator = 1 in {
1671 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1672 // a two-value operand where a dag node expects two operands. :(
1673 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1674 IIC_Br, "b", "\t$target",
1675 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1677 let Inst{23-0} = target;
1678 let DecoderMethod = "DecodeBranchImmInstruction";
1681 let isBarrier = 1 in {
1682 // B is "predicable" since it's just a Bcc with an 'always' condition.
1683 let isPredicable = 1 in
1684 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1685 // should be sufficient.
1686 // FIXME: Is B really a Barrier? That doesn't seem right.
1687 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1688 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1690 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1691 def BR_JTr : ARMPseudoInst<(outs),
1692 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1694 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1695 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1696 // into i12 and rs suffixed versions.
1697 def BR_JTm : ARMPseudoInst<(outs),
1698 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1700 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1702 def BR_JTadd : ARMPseudoInst<(outs),
1703 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1705 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1707 } // isNotDuplicable = 1, isIndirectBranch = 1
1713 def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
1714 "blx\t$target", []>,
1715 Requires<[IsARM, HasV5T]> {
1716 let Inst{31-25} = 0b1111101;
1718 let Inst{23-0} = target{24-1};
1719 let Inst{24} = target{0};
1722 // Branch and Exchange Jazelle
1723 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1724 [/* pattern left blank */]> {
1726 let Inst{23-20} = 0b0010;
1727 let Inst{19-8} = 0xfff;
1728 let Inst{7-4} = 0b0010;
1729 let Inst{3-0} = func;
1734 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1736 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1738 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1739 IIC_Br, []>, Requires<[IsDarwin]>;
1741 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1742 IIC_Br, []>, Requires<[IsDarwin]>;
1744 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
1746 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1747 Requires<[IsARM, IsDarwin]>;
1749 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
1752 Requires<[IsARM, IsDarwin]>;
1756 // Non-Darwin versions (the difference is R9).
1757 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1759 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1760 IIC_Br, []>, Requires<[IsNotDarwin]>;
1762 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1763 IIC_Br, []>, Requires<[IsNotDarwin]>;
1765 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
1767 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1768 Requires<[IsARM, IsNotDarwin]>;
1770 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
1773 Requires<[IsARM, IsNotDarwin]>;
1781 // Secure Monitor Call is a system instruction -- for disassembly only
1782 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
1785 let Inst{23-4} = 0b01100000000000000111;
1786 let Inst{3-0} = opt;
1789 // Supervisor Call (Software Interrupt)
1790 let isCall = 1, Uses = [SP] in {
1791 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
1793 let Inst{23-0} = svc;
1797 // Store Return State
1798 class SRSI<bit wb, string asm>
1799 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
1800 NoItinerary, asm, "", []> {
1802 let Inst{31-28} = 0b1111;
1803 let Inst{27-25} = 0b100;
1807 let Inst{19-16} = 0b1101; // SP
1808 let Inst{15-5} = 0b00000101000;
1809 let Inst{4-0} = mode;
1812 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
1813 let Inst{24-23} = 0;
1815 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
1816 let Inst{24-23} = 0;
1818 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
1819 let Inst{24-23} = 0b10;
1821 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
1822 let Inst{24-23} = 0b10;
1824 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
1825 let Inst{24-23} = 0b01;
1827 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
1828 let Inst{24-23} = 0b01;
1830 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
1831 let Inst{24-23} = 0b11;
1833 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
1834 let Inst{24-23} = 0b11;
1837 // Return From Exception
1838 class RFEI<bit wb, string asm>
1839 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
1840 NoItinerary, asm, "", []> {
1842 let Inst{31-28} = 0b1111;
1843 let Inst{27-25} = 0b100;
1847 let Inst{19-16} = Rn;
1848 let Inst{15-0} = 0xa00;
1851 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
1852 let Inst{24-23} = 0;
1854 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
1855 let Inst{24-23} = 0;
1857 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
1858 let Inst{24-23} = 0b10;
1860 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
1861 let Inst{24-23} = 0b10;
1863 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
1864 let Inst{24-23} = 0b01;
1866 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
1867 let Inst{24-23} = 0b01;
1869 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
1870 let Inst{24-23} = 0b11;
1872 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
1873 let Inst{24-23} = 0b11;
1876 //===----------------------------------------------------------------------===//
1877 // Load / store Instructions.
1883 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1884 UnOpFrag<(load node:$Src)>>;
1885 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1886 UnOpFrag<(zextloadi8 node:$Src)>>;
1887 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1888 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1889 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1890 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1892 // Special LDR for loads from non-pc-relative constpools.
1893 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1894 isReMaterializable = 1, isCodeGenOnly = 1 in
1895 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1896 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1900 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1901 let Inst{19-16} = 0b1111;
1902 let Inst{15-12} = Rt;
1903 let Inst{11-0} = addr{11-0}; // imm12
1906 // Loads with zero extension
1907 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1908 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1909 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1911 // Loads with sign extension
1912 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1913 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1914 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1916 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1917 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1918 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1920 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1922 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1923 (ins addrmode3:$addr), LdMiscFrm,
1924 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
1925 []>, Requires<[IsARM, HasV5TE]>;
1929 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1930 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1931 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1932 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1938 let Inst{25} = addr{13};
1939 let Inst{23} = addr{12};
1940 let Inst{19-16} = addr{17-14};
1941 let Inst{11-0} = addr{11-0};
1942 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
1943 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
1946 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1947 (ins addr_offset_none:$addr, am2offset_reg:$offset),
1948 IndexModePost, LdFrm, itin,
1949 opc, "\t$Rt, $addr, $offset",
1950 "$addr.base = $Rn_wb", []> {
1956 let Inst{23} = offset{12};
1957 let Inst{19-16} = addr;
1958 let Inst{11-0} = offset{11-0};
1960 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
1963 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1964 (ins addr_offset_none:$addr, am2offset_imm:$offset),
1965 IndexModePost, LdFrm, itin,
1966 opc, "\t$Rt, $addr, $offset",
1967 "$addr.base = $Rn_wb", []> {
1973 let Inst{23} = offset{12};
1974 let Inst{19-16} = addr;
1975 let Inst{11-0} = offset{11-0};
1977 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
1982 let mayLoad = 1, neverHasSideEffects = 1 in {
1983 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1984 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1987 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1988 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1989 (ins addrmode3:$addr), IndexModePre,
1991 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1993 let Inst{23} = addr{8}; // U bit
1994 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1995 let Inst{19-16} = addr{12-9}; // Rn
1996 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1997 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1999 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2000 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
2002 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
2005 let Inst{23} = offset{8}; // U bit
2006 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2007 let Inst{19-16} = Rn;
2008 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2009 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2013 let mayLoad = 1, neverHasSideEffects = 1 in {
2014 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
2015 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
2016 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
2017 let hasExtraDefRegAllocReq = 1 in {
2018 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2019 (ins addrmode3:$addr), IndexModePre,
2020 LdMiscFrm, IIC_iLoad_d_ru,
2021 "ldrd", "\t$Rt, $Rt2, $addr!",
2022 "$addr.base = $Rn_wb", []> {
2024 let Inst{23} = addr{8}; // U bit
2025 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2026 let Inst{19-16} = addr{12-9}; // Rn
2027 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2028 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2029 let DecoderMethod = "DecodeAddrMode3Instruction";
2031 def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2032 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
2033 LdMiscFrm, IIC_iLoad_d_ru,
2034 "ldrd", "\t$Rt, $Rt2, [$Rn], $offset",
2035 "$Rn = $Rn_wb", []> {
2038 let Inst{23} = offset{8}; // U bit
2039 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2040 let Inst{19-16} = Rn;
2041 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2042 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2043 let DecoderMethod = "DecodeAddrMode3Instruction";
2045 } // hasExtraDefRegAllocReq = 1
2046 } // mayLoad = 1, neverHasSideEffects = 1
2048 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
2049 let mayLoad = 1, neverHasSideEffects = 1 in {
2050 def LDRTr : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
2051 (ins ldst_so_reg:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
2052 "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
2054 // {13} 1 == Rm, 0 == imm12
2059 let Inst{23} = addr{12};
2060 let Inst{21} = 1; // overwrite
2061 let Inst{19-16} = addr{17-14};
2062 let Inst{11-5} = addr{11-5};
2064 let Inst{3-0} = addr{3-0};
2065 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2066 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2068 def LDRTi : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
2069 (ins addrmode_imm12:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
2070 "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
2072 // {13} 1 == Rm, 0 == imm12
2077 let Inst{23} = addr{12};
2078 let Inst{21} = 1; // overwrite
2079 let Inst{19-16} = addr{17-14};
2080 let Inst{11-0} = addr{11-0};
2081 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2082 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2085 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2086 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2087 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2088 "ldrbt", "\t$Rt, $addr, $offset",
2089 "$addr.base = $Rn_wb", []> {
2095 let Inst{23} = offset{12};
2096 let Inst{21} = 1; // overwrite
2097 let Inst{19-16} = addr;
2098 let Inst{11-0} = offset{11-0};
2099 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2102 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2103 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2104 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2105 "ldrbt", "\t$Rt, $addr, $offset",
2106 "$addr.base = $Rn_wb", []> {
2112 let Inst{23} = offset{12};
2113 let Inst{21} = 1; // overwrite
2114 let Inst{19-16} = addr;
2115 let Inst{11-0} = offset{11-0};
2116 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2119 multiclass AI3ldrT<bits<4> op, string opc> {
2120 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2121 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2122 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2123 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2125 let Inst{23} = offset{8};
2127 let Inst{11-8} = offset{7-4};
2128 let Inst{3-0} = offset{3-0};
2129 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2131 def r : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2132 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2133 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2134 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2136 let Inst{23} = Rm{4};
2139 let Inst{3-0} = Rm{3-0};
2140 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2144 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2145 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2146 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2151 // Stores with truncate
2152 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2153 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2154 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2157 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2158 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2159 StMiscFrm, IIC_iStore_d_r,
2160 "strd", "\t$Rt, $src2, $addr", []>,
2161 Requires<[IsARM, HasV5TE]> {
2166 multiclass AI2_stridx<bit isByte, string opc, InstrItinClass itin> {
2167 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2168 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2170 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2173 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2174 let Inst{19-16} = addr{16-13}; // Rn
2175 let Inst{11-0} = addr{11-0}; // imm12
2176 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2179 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2180 (ins GPR:$Rt, addrmode2:$addr), IndexModePre, StFrm, itin,
2181 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2184 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2185 let Inst{19-16} = addr{16-13}; // Rn
2186 let Inst{11-0} = addr{11-0};
2187 let Inst{4} = 0; // Inst{4} = 0
2188 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2190 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2191 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2192 IndexModePost, StFrm, itin,
2193 opc, "\t$Rt, $addr, $offset",
2194 "$addr.base = $Rn_wb", []> {
2200 let Inst{23} = offset{12};
2201 let Inst{19-16} = addr;
2202 let Inst{11-0} = offset{11-0};
2204 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2207 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2208 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2209 IndexModePost, StFrm, itin,
2210 opc, "\t$Rt, $addr, $offset",
2211 "$addr.base = $Rn_wb", []> {
2217 let Inst{23} = offset{12};
2218 let Inst{19-16} = addr;
2219 let Inst{11-0} = offset{11-0};
2221 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2225 let mayStore = 1, neverHasSideEffects = 1 in {
2226 defm STR : AI2_stridx<0, "str", IIC_iStore_ru>;
2227 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_ru>;
2230 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2231 am2offset_reg:$offset),
2232 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2233 am2offset_reg:$offset)>;
2234 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2235 am2offset_imm:$offset),
2236 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2237 am2offset_imm:$offset)>;
2238 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2239 am2offset_reg:$offset),
2240 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2241 am2offset_reg:$offset)>;
2242 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2243 am2offset_imm:$offset),
2244 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2245 am2offset_imm:$offset)>;
2247 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2248 // put the patterns on the instruction definitions directly as ISel wants
2249 // the address base and offset to be separate operands, not a single
2250 // complex operand like we represent the instructions themselves. The
2251 // pseudos map between the two.
2252 let usesCustomInserter = 1,
2253 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2254 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2255 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2258 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2259 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2260 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2263 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2264 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2265 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2268 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2269 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2270 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2273 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2276 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2277 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
2278 IndexModePre, StMiscFrm, IIC_iStore_ru,
2279 "strh", "\t$Rt, [$Rn, $offset]!",
2280 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2282 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2284 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2285 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
2286 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2287 "strh", "\t$Rt, [$Rn], $offset",
2288 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
2289 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2290 GPR:$Rn, am3offset:$offset))]>;
2292 // For disassembly only
2293 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2294 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
2295 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
2296 StMiscFrm, IIC_iStore_d_ru,
2297 "strd", "\t$src1, $src2, [$base, $offset]!",
2298 "$base = $base_wb", []> {
2302 let Inst{23} = offset{8}; // U bit
2303 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2304 let Inst{19-16} = base;
2305 let Inst{15-12} = src1;
2306 let Inst{11-8} = offset{7-4};
2307 let Inst{3-0} = offset{3-0};
2309 let DecoderMethod = "DecodeAddrMode3Instruction";
2312 // For disassembly only
2313 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
2314 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
2315 StMiscFrm, IIC_iStore_d_ru,
2316 "strd", "\t$src1, $src2, [$base], $offset",
2317 "$base = $base_wb", []> {
2321 let Inst{23} = offset{8}; // U bit
2322 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2323 let Inst{19-16} = base;
2324 let Inst{15-12} = src1;
2325 let Inst{11-8} = offset{7-4};
2326 let Inst{3-0} = offset{3-0};
2328 let DecoderMethod = "DecodeAddrMode3Instruction";
2330 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2332 // STRT, STRBT, and STRHT
2334 def STRTr : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
2335 (ins GPR:$Rt, ldst_so_reg:$addr),
2336 IndexModePost, StFrm, IIC_iStore_ru,
2337 "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
2338 [/* For disassembly only; pattern left blank */]> {
2340 let Inst{21} = 1; // overwrite
2342 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2343 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2346 def STRTi : AI2stridxT<0, 0, (outs GPR:$Rn_wb),
2347 (ins GPR:$Rt, addrmode_imm12:$addr),
2348 IndexModePost, StFrm, IIC_iStore_ru,
2349 "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
2350 [/* For disassembly only; pattern left blank */]> {
2352 let Inst{21} = 1; // overwrite
2353 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2354 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2358 def STRBTr : AI2stridxT<1, 0, (outs GPR:$Rn_wb),
2359 (ins GPR:$Rt, ldst_so_reg:$addr),
2360 IndexModePost, StFrm, IIC_iStore_bh_ru,
2361 "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
2362 [/* For disassembly only; pattern left blank */]> {
2364 let Inst{21} = 1; // overwrite
2366 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2367 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2370 def STRBTi : AI2stridxT<1, 0, (outs GPR:$Rn_wb),
2371 (ins GPR:$Rt, addrmode_imm12:$addr),
2372 IndexModePost, StFrm, IIC_iStore_bh_ru,
2373 "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
2374 [/* For disassembly only; pattern left blank */]> {
2376 let Inst{21} = 1; // overwrite
2377 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2378 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2381 multiclass AI3strT<bits<4> op, string opc> {
2382 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2383 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2384 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2385 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2387 let Inst{23} = offset{8};
2389 let Inst{11-8} = offset{7-4};
2390 let Inst{3-0} = offset{3-0};
2391 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2393 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2394 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2395 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2396 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2398 let Inst{23} = Rm{4};
2401 let Inst{3-0} = Rm{3-0};
2402 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2407 defm STRHT : AI3strT<0b1011, "strht">;
2410 //===----------------------------------------------------------------------===//
2411 // Load / store multiple Instructions.
2414 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
2415 InstrItinClass itin, InstrItinClass itin_upd> {
2416 // IA is the default, so no need for an explicit suffix on the
2417 // mnemonic here. Without it is the cannonical spelling.
2419 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2420 IndexModeNone, f, itin,
2421 !strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
2422 let Inst{24-23} = 0b01; // Increment After
2423 let Inst{21} = 0; // No writeback
2424 let Inst{20} = L_bit;
2427 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2428 IndexModeUpd, f, itin_upd,
2429 !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2430 let Inst{24-23} = 0b01; // Increment After
2431 let Inst{21} = 1; // Writeback
2432 let Inst{20} = L_bit;
2434 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2437 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2438 IndexModeNone, f, itin,
2439 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
2440 let Inst{24-23} = 0b00; // Decrement After
2441 let Inst{21} = 0; // No writeback
2442 let Inst{20} = L_bit;
2445 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2446 IndexModeUpd, f, itin_upd,
2447 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2448 let Inst{24-23} = 0b00; // Decrement After
2449 let Inst{21} = 1; // Writeback
2450 let Inst{20} = L_bit;
2452 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2455 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2456 IndexModeNone, f, itin,
2457 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
2458 let Inst{24-23} = 0b10; // Decrement Before
2459 let Inst{21} = 0; // No writeback
2460 let Inst{20} = L_bit;
2463 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2464 IndexModeUpd, f, itin_upd,
2465 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2466 let Inst{24-23} = 0b10; // Decrement Before
2467 let Inst{21} = 1; // Writeback
2468 let Inst{20} = L_bit;
2470 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2473 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2474 IndexModeNone, f, itin,
2475 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
2476 let Inst{24-23} = 0b11; // Increment Before
2477 let Inst{21} = 0; // No writeback
2478 let Inst{20} = L_bit;
2481 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2482 IndexModeUpd, f, itin_upd,
2483 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2484 let Inst{24-23} = 0b11; // Increment Before
2485 let Inst{21} = 1; // Writeback
2486 let Inst{20} = L_bit;
2488 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2492 let neverHasSideEffects = 1 in {
2494 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2495 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
2497 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2498 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
2500 } // neverHasSideEffects
2502 // FIXME: remove when we have a way to marking a MI with these properties.
2503 // FIXME: Should pc be an implicit operand like PICADD, etc?
2504 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2505 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2506 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2507 reglist:$regs, variable_ops),
2508 4, IIC_iLoad_mBr, [],
2509 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2510 RegConstraint<"$Rn = $wb">;
2512 //===----------------------------------------------------------------------===//
2513 // Move Instructions.
2516 let neverHasSideEffects = 1 in
2517 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2518 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2522 let Inst{19-16} = 0b0000;
2523 let Inst{11-4} = 0b00000000;
2526 let Inst{15-12} = Rd;
2529 // A version for the smaller set of tail call registers.
2530 let neverHasSideEffects = 1 in
2531 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2532 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2536 let Inst{11-4} = 0b00000000;
2539 let Inst{15-12} = Rd;
2542 def MOVsr : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_reg:$src),
2543 DPSoRegRegFrm, IIC_iMOVsr,
2544 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_reg:$src)]>,
2548 let Inst{15-12} = Rd;
2549 let Inst{19-16} = 0b0000;
2550 let Inst{11-8} = src{11-8};
2552 let Inst{6-5} = src{6-5};
2554 let Inst{3-0} = src{3-0};
2558 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2559 DPSoRegImmFrm, IIC_iMOVsr,
2560 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2564 let Inst{15-12} = Rd;
2565 let Inst{19-16} = 0b0000;
2566 let Inst{11-5} = src{11-5};
2568 let Inst{3-0} = src{3-0};
2572 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2573 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2574 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2578 let Inst{15-12} = Rd;
2579 let Inst{19-16} = 0b0000;
2580 let Inst{11-0} = imm;
2583 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2584 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2586 "movw", "\t$Rd, $imm",
2587 [(set GPR:$Rd, imm0_65535:$imm)]>,
2588 Requires<[IsARM, HasV6T2]>, UnaryDP {
2591 let Inst{15-12} = Rd;
2592 let Inst{11-0} = imm{11-0};
2593 let Inst{19-16} = imm{15-12};
2598 def : InstAlias<"mov${p} $Rd, $imm",
2599 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2602 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2603 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2605 let Constraints = "$src = $Rd" in {
2606 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, imm0_65535_expr:$imm),
2608 "movt", "\t$Rd, $imm",
2610 (or (and GPR:$src, 0xffff),
2611 lo16AllZero:$imm))]>, UnaryDP,
2612 Requires<[IsARM, HasV6T2]> {
2615 let Inst{15-12} = Rd;
2616 let Inst{11-0} = imm{11-0};
2617 let Inst{19-16} = imm{15-12};
2622 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2623 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2627 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2628 Requires<[IsARM, HasV6T2]>;
2630 let Uses = [CPSR] in
2631 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2632 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2635 // These aren't really mov instructions, but we have to define them this way
2636 // due to flag operands.
2638 let Defs = [CPSR] in {
2639 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2640 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2642 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2643 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2647 //===----------------------------------------------------------------------===//
2648 // Extend Instructions.
2653 def SXTB : AI_ext_rrot<0b01101010,
2654 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2655 def SXTH : AI_ext_rrot<0b01101011,
2656 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2658 def SXTAB : AI_exta_rrot<0b01101010,
2659 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2660 def SXTAH : AI_exta_rrot<0b01101011,
2661 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2663 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2665 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2669 let AddedComplexity = 16 in {
2670 def UXTB : AI_ext_rrot<0b01101110,
2671 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2672 def UXTH : AI_ext_rrot<0b01101111,
2673 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2674 def UXTB16 : AI_ext_rrot<0b01101100,
2675 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2677 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2678 // The transformation should probably be done as a combiner action
2679 // instead so we can include a check for masking back in the upper
2680 // eight bits of the source into the lower eight bits of the result.
2681 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2682 // (UXTB16r_rot GPR:$Src, 3)>;
2683 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2684 (UXTB16 GPR:$Src, 1)>;
2686 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2687 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2688 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2689 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2692 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2693 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2696 def SBFX : I<(outs GPR:$Rd),
2697 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
2698 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2699 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2700 Requires<[IsARM, HasV6T2]> {
2705 let Inst{27-21} = 0b0111101;
2706 let Inst{6-4} = 0b101;
2707 let Inst{20-16} = width;
2708 let Inst{15-12} = Rd;
2709 let Inst{11-7} = lsb;
2713 def UBFX : I<(outs GPR:$Rd),
2714 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
2715 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
2716 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2717 Requires<[IsARM, HasV6T2]> {
2722 let Inst{27-21} = 0b0111111;
2723 let Inst{6-4} = 0b101;
2724 let Inst{20-16} = width;
2725 let Inst{15-12} = Rd;
2726 let Inst{11-7} = lsb;
2730 //===----------------------------------------------------------------------===//
2731 // Arithmetic Instructions.
2734 defm ADD : AsI1_bin_irs<0b0100, "add",
2735 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2736 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
2737 defm SUB : AsI1_bin_irs<0b0010, "sub",
2738 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2739 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
2741 // ADD and SUB with 's' bit set.
2742 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2743 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2744 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2745 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2746 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2747 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2749 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2750 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>,
2752 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2753 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>,
2756 // ADC and SUBC with 's' bit set.
2757 let usesCustomInserter = 1 in {
2758 defm ADCS : AI1_adde_sube_s_irs<
2759 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2760 defm SBCS : AI1_adde_sube_s_irs<
2761 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2764 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2765 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2766 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2771 let Inst{15-12} = Rd;
2772 let Inst{19-16} = Rn;
2773 let Inst{11-0} = imm;
2776 // The reg/reg form is only defined for the disassembler; for codegen it is
2777 // equivalent to SUBrr.
2778 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2779 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2780 [/* For disassembly only; pattern left blank */]> {
2784 let Inst{11-4} = 0b00000000;
2787 let Inst{15-12} = Rd;
2788 let Inst{19-16} = Rn;
2791 def RSBrsi : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
2792 DPSoRegImmFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2793 [(set GPR:$Rd, (sub so_reg_imm:$shift, GPR:$Rn))]> {
2798 let Inst{19-16} = Rn;
2799 let Inst{15-12} = Rd;
2800 let Inst{11-5} = shift{11-5};
2802 let Inst{3-0} = shift{3-0};
2805 def RSBrsr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2806 DPSoRegRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2807 [(set GPR:$Rd, (sub so_reg_reg:$shift, GPR:$Rn))]> {
2812 let Inst{19-16} = Rn;
2813 let Inst{15-12} = Rd;
2814 let Inst{11-8} = shift{11-8};
2816 let Inst{6-5} = shift{6-5};
2818 let Inst{3-0} = shift{3-0};
2821 // RSB with 's' bit set.
2822 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2823 let usesCustomInserter = 1 in {
2824 def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2826 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
2827 def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2829 [/* For disassembly only; pattern left blank */]>;
2830 def RSBSrsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
2832 [(set GPR:$Rd, (subc so_reg_imm:$shift, GPR:$Rn))]>;
2833 def RSBSrsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2835 [(set GPR:$Rd, (subc so_reg_reg:$shift, GPR:$Rn))]>;
2838 let Uses = [CPSR] in {
2839 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2840 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2841 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2847 let Inst{15-12} = Rd;
2848 let Inst{19-16} = Rn;
2849 let Inst{11-0} = imm;
2851 // The reg/reg form is only defined for the disassembler; for codegen it is
2852 // equivalent to SUBrr.
2853 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2854 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2855 [/* For disassembly only; pattern left blank */]> {
2859 let Inst{11-4} = 0b00000000;
2862 let Inst{15-12} = Rd;
2863 let Inst{19-16} = Rn;
2865 def RSCrsi : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
2866 DPSoRegImmFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2867 [(set GPR:$Rd, (sube_dead_carry so_reg_imm:$shift, GPR:$Rn))]>,
2873 let Inst{19-16} = Rn;
2874 let Inst{15-12} = Rd;
2875 let Inst{11-5} = shift{11-5};
2877 let Inst{3-0} = shift{3-0};
2879 def RSCrsr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2880 DPSoRegRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2881 [(set GPR:$Rd, (sube_dead_carry so_reg_reg:$shift, GPR:$Rn))]>,
2887 let Inst{19-16} = Rn;
2888 let Inst{15-12} = Rd;
2889 let Inst{11-8} = shift{11-8};
2891 let Inst{6-5} = shift{6-5};
2893 let Inst{3-0} = shift{3-0};
2898 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2899 let usesCustomInserter = 1, Uses = [CPSR] in {
2900 def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2902 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>;
2903 def RSCSrsi : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
2905 [(set GPR:$Rd, (sube_dead_carry so_reg_imm:$shift, GPR:$Rn))]>;
2906 def RSCSrsr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2908 [(set GPR:$Rd, (sube_dead_carry so_reg_reg:$shift, GPR:$Rn))]>;
2911 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2912 // The assume-no-carry-in form uses the negation of the input since add/sub
2913 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2914 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2916 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2917 (SUBri GPR:$src, so_imm_neg:$imm)>;
2918 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2919 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2920 // The with-carry-in form matches bitwise not instead of the negation.
2921 // Effectively, the inverse interpretation of the carry flag already accounts
2922 // for part of the negation.
2923 def : ARMPat<(adde_dead_carry GPR:$src, so_imm_not:$imm),
2924 (SBCri GPR:$src, so_imm_not:$imm)>;
2925 def : ARMPat<(adde_live_carry GPR:$src, so_imm_not:$imm),
2926 (SBCSri GPR:$src, so_imm_not:$imm)>;
2928 // Note: These are implemented in C++ code, because they have to generate
2929 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2931 // (mul X, 2^n+1) -> (add (X << n), X)
2932 // (mul X, 2^n-1) -> (rsb X, (X << n))
2934 // ARM Arithmetic Instruction
2935 // GPR:$dst = GPR:$a op GPR:$b
2936 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2937 list<dag> pattern = [],
2938 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2939 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2943 let Inst{27-20} = op27_20;
2944 let Inst{11-4} = op11_4;
2945 let Inst{19-16} = Rn;
2946 let Inst{15-12} = Rd;
2950 // Saturating add/subtract
2952 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2953 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2954 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2955 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2956 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2957 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2958 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2960 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2963 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2964 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2965 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2966 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2967 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2968 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2969 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2970 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2971 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2972 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2973 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2974 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2976 // Signed/Unsigned add/subtract
2978 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2979 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2980 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2981 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2982 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2983 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2984 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2985 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2986 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2987 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2988 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2989 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2991 // Signed/Unsigned halving add/subtract
2993 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2994 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2995 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2996 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2997 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2998 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2999 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3000 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3001 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3002 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3003 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3004 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3006 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
3008 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3009 MulFrm /* for convenience */, NoItinerary, "usad8",
3010 "\t$Rd, $Rn, $Rm", []>,
3011 Requires<[IsARM, HasV6]> {
3015 let Inst{27-20} = 0b01111000;
3016 let Inst{15-12} = 0b1111;
3017 let Inst{7-4} = 0b0001;
3018 let Inst{19-16} = Rd;
3019 let Inst{11-8} = Rm;
3022 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3023 MulFrm /* for convenience */, NoItinerary, "usada8",
3024 "\t$Rd, $Rn, $Rm, $Ra", []>,
3025 Requires<[IsARM, HasV6]> {
3030 let Inst{27-20} = 0b01111000;
3031 let Inst{7-4} = 0b0001;
3032 let Inst{19-16} = Rd;
3033 let Inst{15-12} = Ra;
3034 let Inst{11-8} = Rm;
3038 // Signed/Unsigned saturate -- for disassembly only
3040 def SSAT : AI<(outs GPR:$Rd), (ins imm1_32:$sat_imm, GPR:$Rn, shift_imm:$sh),
3041 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3046 let Inst{27-21} = 0b0110101;
3047 let Inst{5-4} = 0b01;
3048 let Inst{20-16} = sat_imm;
3049 let Inst{15-12} = Rd;
3050 let Inst{11-7} = sh{4-0};
3051 let Inst{6} = sh{5};
3055 def SSAT16 : AI<(outs GPR:$Rd), (ins imm1_16:$sat_imm, GPR:$Rn), SatFrm,
3056 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3060 let Inst{27-20} = 0b01101010;
3061 let Inst{11-4} = 0b11110011;
3062 let Inst{15-12} = Rd;
3063 let Inst{19-16} = sat_imm;
3067 def USAT : AI<(outs GPR:$Rd), (ins imm0_31:$sat_imm, GPR:$Rn, shift_imm:$sh),
3068 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3073 let Inst{27-21} = 0b0110111;
3074 let Inst{5-4} = 0b01;
3075 let Inst{15-12} = Rd;
3076 let Inst{11-7} = sh{4-0};
3077 let Inst{6} = sh{5};
3078 let Inst{20-16} = sat_imm;
3082 def USAT16 : AI<(outs GPR:$Rd), (ins imm0_15:$sat_imm, GPR:$a), SatFrm,
3083 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
3084 [/* For disassembly only; pattern left blank */]> {
3088 let Inst{27-20} = 0b01101110;
3089 let Inst{11-4} = 0b11110011;
3090 let Inst{15-12} = Rd;
3091 let Inst{19-16} = sat_imm;
3095 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
3096 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
3098 //===----------------------------------------------------------------------===//
3099 // Bitwise Instructions.
3102 defm AND : AsI1_bin_irs<0b0000, "and",
3103 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3104 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3105 defm ORR : AsI1_bin_irs<0b1100, "orr",
3106 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3107 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3108 defm EOR : AsI1_bin_irs<0b0001, "eor",
3109 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3110 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3111 defm BIC : AsI1_bin_irs<0b1110, "bic",
3112 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3113 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3115 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3116 // like in the actual instruction encoding. The complexity of mapping the mask
3117 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3118 // instruction description.
3119 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3120 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3121 "bfc", "\t$Rd, $imm", "$src = $Rd",
3122 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3123 Requires<[IsARM, HasV6T2]> {
3126 let Inst{27-21} = 0b0111110;
3127 let Inst{6-0} = 0b0011111;
3128 let Inst{15-12} = Rd;
3129 let Inst{11-7} = imm{4-0}; // lsb
3130 let Inst{20-16} = imm{9-5}; // msb
3133 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3134 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3135 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3136 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3137 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
3138 bf_inv_mask_imm:$imm))]>,
3139 Requires<[IsARM, HasV6T2]> {
3143 let Inst{27-21} = 0b0111110;
3144 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3145 let Inst{15-12} = Rd;
3146 let Inst{11-7} = imm{4-0}; // lsb
3147 let Inst{20-16} = imm{9-5}; // width
3151 // GNU as only supports this form of bfi (w/ 4 arguments)
3152 let isAsmParserOnly = 1 in
3153 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
3154 lsb_pos_imm:$lsb, width_imm:$width),
3155 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3156 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
3157 []>, Requires<[IsARM, HasV6T2]> {
3162 let Inst{27-21} = 0b0111110;
3163 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3164 let Inst{15-12} = Rd;
3165 let Inst{11-7} = lsb;
3166 let Inst{20-16} = width; // Custom encoder => lsb+width-1
3170 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3171 "mvn", "\t$Rd, $Rm",
3172 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3176 let Inst{19-16} = 0b0000;
3177 let Inst{11-4} = 0b00000000;
3178 let Inst{15-12} = Rd;
3181 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3182 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3183 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3187 let Inst{19-16} = 0b0000;
3188 let Inst{15-12} = Rd;
3189 let Inst{11-5} = shift{11-5};
3191 let Inst{3-0} = shift{3-0};
3193 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3194 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3195 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3199 let Inst{19-16} = 0b0000;
3200 let Inst{15-12} = Rd;
3201 let Inst{11-8} = shift{11-8};
3203 let Inst{6-5} = shift{6-5};
3205 let Inst{3-0} = shift{3-0};
3207 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3208 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3209 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3210 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3214 let Inst{19-16} = 0b0000;
3215 let Inst{15-12} = Rd;
3216 let Inst{11-0} = imm;
3219 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3220 (BICri GPR:$src, so_imm_not:$imm)>;
3222 //===----------------------------------------------------------------------===//
3223 // Multiply Instructions.
3225 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3226 string opc, string asm, list<dag> pattern>
3227 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3231 let Inst{19-16} = Rd;
3232 let Inst{11-8} = Rm;
3235 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3236 string opc, string asm, list<dag> pattern>
3237 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3242 let Inst{19-16} = RdHi;
3243 let Inst{15-12} = RdLo;
3244 let Inst{11-8} = Rm;
3248 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3249 // property. Remove them when it's possible to add those properties
3250 // on an individual MachineInstr, not just an instuction description.
3251 let isCommutable = 1 in {
3252 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3253 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3254 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
3255 Requires<[IsARM, HasV6]> {
3256 let Inst{15-12} = 0b0000;
3259 let Constraints = "@earlyclobber $Rd" in
3260 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
3261 pred:$p, cc_out:$s),
3263 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
3264 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3265 Requires<[IsARM, NoV6]>;
3268 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3269 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3270 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3271 Requires<[IsARM, HasV6]> {
3273 let Inst{15-12} = Ra;
3276 let Constraints = "@earlyclobber $Rd" in
3277 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3278 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3280 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3281 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3282 Requires<[IsARM, NoV6]>;
3284 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3285 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3286 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3287 Requires<[IsARM, HasV6T2]> {
3292 let Inst{19-16} = Rd;
3293 let Inst{15-12} = Ra;
3294 let Inst{11-8} = Rm;
3298 // Extra precision multiplies with low / high results
3299 let neverHasSideEffects = 1 in {
3300 let isCommutable = 1 in {
3301 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3302 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3303 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3304 Requires<[IsARM, HasV6]>;
3306 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3307 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3308 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3309 Requires<[IsARM, HasV6]>;
3311 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3312 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3313 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3315 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3316 Requires<[IsARM, NoV6]>;
3318 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3319 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3321 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3322 Requires<[IsARM, NoV6]>;
3326 // Multiply + accumulate
3327 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3328 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3329 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3330 Requires<[IsARM, HasV6]>;
3331 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3332 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3333 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3334 Requires<[IsARM, HasV6]>;
3336 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3337 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3338 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3339 Requires<[IsARM, HasV6]> {
3344 let Inst{19-16} = RdLo;
3345 let Inst{15-12} = RdHi;
3346 let Inst{11-8} = Rm;
3350 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3351 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3352 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3354 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3355 Requires<[IsARM, NoV6]>;
3356 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3357 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3359 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3360 Requires<[IsARM, NoV6]>;
3361 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3362 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3364 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3365 Requires<[IsARM, NoV6]>;
3368 } // neverHasSideEffects
3370 // Most significant word multiply
3371 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3372 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3373 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3374 Requires<[IsARM, HasV6]> {
3375 let Inst{15-12} = 0b1111;
3378 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3379 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
3380 [/* For disassembly only; pattern left blank */]>,
3381 Requires<[IsARM, HasV6]> {
3382 let Inst{15-12} = 0b1111;
3385 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3386 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3387 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3388 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3389 Requires<[IsARM, HasV6]>;
3391 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3392 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3393 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
3394 [/* For disassembly only; pattern left blank */]>,
3395 Requires<[IsARM, HasV6]>;
3397 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3398 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3399 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3400 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3401 Requires<[IsARM, HasV6]>;
3403 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3404 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3405 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
3406 [/* For disassembly only; pattern left blank */]>,
3407 Requires<[IsARM, HasV6]>;
3409 multiclass AI_smul<string opc, PatFrag opnode> {
3410 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3411 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3412 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3413 (sext_inreg GPR:$Rm, i16)))]>,
3414 Requires<[IsARM, HasV5TE]>;
3416 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3417 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3418 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3419 (sra GPR:$Rm, (i32 16))))]>,
3420 Requires<[IsARM, HasV5TE]>;
3422 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3423 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3424 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3425 (sext_inreg GPR:$Rm, i16)))]>,
3426 Requires<[IsARM, HasV5TE]>;
3428 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3429 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3430 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3431 (sra GPR:$Rm, (i32 16))))]>,
3432 Requires<[IsARM, HasV5TE]>;
3434 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3435 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3436 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3437 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3438 Requires<[IsARM, HasV5TE]>;
3440 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3441 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3442 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3443 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3444 Requires<[IsARM, HasV5TE]>;
3448 multiclass AI_smla<string opc, PatFrag opnode> {
3449 let DecoderMethod = "DecodeSMLAInstruction" in {
3450 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
3451 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3452 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3453 [(set GPR:$Rd, (add GPR:$Ra,
3454 (opnode (sext_inreg GPR:$Rn, i16),
3455 (sext_inreg GPR:$Rm, i16))))]>,
3456 Requires<[IsARM, HasV5TE]>;
3458 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
3459 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3460 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3461 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
3462 (sra GPR:$Rm, (i32 16)))))]>,
3463 Requires<[IsARM, HasV5TE]>;
3465 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
3466 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3467 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3468 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
3469 (sext_inreg GPR:$Rm, i16))))]>,
3470 Requires<[IsARM, HasV5TE]>;
3472 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
3473 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3474 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3475 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
3476 (sra GPR:$Rm, (i32 16)))))]>,
3477 Requires<[IsARM, HasV5TE]>;
3479 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
3480 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3481 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3482 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
3483 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
3484 Requires<[IsARM, HasV5TE]>;
3486 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
3487 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3488 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3489 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
3490 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
3491 Requires<[IsARM, HasV5TE]>;
3495 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3496 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3498 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
3499 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
3500 (ins GPR:$Rn, GPR:$Rm),
3501 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
3502 [/* For disassembly only; pattern left blank */]>,
3503 Requires<[IsARM, HasV5TE]>;
3505 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
3506 (ins GPR:$Rn, GPR:$Rm),
3507 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
3508 [/* For disassembly only; pattern left blank */]>,
3509 Requires<[IsARM, HasV5TE]>;
3511 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
3512 (ins GPR:$Rn, GPR:$Rm),
3513 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
3514 [/* For disassembly only; pattern left blank */]>,
3515 Requires<[IsARM, HasV5TE]>;
3517 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
3518 (ins GPR:$Rn, GPR:$Rm),
3519 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
3520 [/* For disassembly only; pattern left blank */]>,
3521 Requires<[IsARM, HasV5TE]>;
3523 // Helper class for AI_smld -- for disassembly only
3524 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3525 InstrItinClass itin, string opc, string asm>
3526 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3529 let Inst{27-23} = 0b01110;
3530 let Inst{22} = long;
3531 let Inst{21-20} = 0b00;
3532 let Inst{11-8} = Rm;
3539 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3540 InstrItinClass itin, string opc, string asm>
3541 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3543 let Inst{15-12} = 0b1111;
3544 let Inst{19-16} = Rd;
3546 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3547 InstrItinClass itin, string opc, string asm>
3548 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3551 let Inst{19-16} = Rd;
3552 let Inst{15-12} = Ra;
3554 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3555 InstrItinClass itin, string opc, string asm>
3556 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3559 let Inst{19-16} = RdHi;
3560 let Inst{15-12} = RdLo;
3563 multiclass AI_smld<bit sub, string opc> {
3565 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3566 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3568 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3569 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3571 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
3572 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
3573 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3575 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
3576 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
3577 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3581 defm SMLA : AI_smld<0, "smla">;
3582 defm SMLS : AI_smld<1, "smls">;
3584 multiclass AI_sdml<bit sub, string opc> {
3586 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3587 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3588 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3589 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3592 defm SMUA : AI_sdml<0, "smua">;
3593 defm SMUS : AI_sdml<1, "smus">;
3595 //===----------------------------------------------------------------------===//
3596 // Misc. Arithmetic Instructions.
3599 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3600 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3601 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3603 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3604 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3605 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3606 Requires<[IsARM, HasV6T2]>;
3608 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3609 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3610 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3612 let AddedComplexity = 5 in
3613 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3614 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3615 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3616 Requires<[IsARM, HasV6]>;
3618 let AddedComplexity = 5 in
3619 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3620 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3621 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3622 Requires<[IsARM, HasV6]>;
3624 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3625 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3628 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3629 (ins GPR:$Rn, GPR:$Rm, pkh_lsl_amt:$sh),
3630 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3631 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3632 (and (shl GPR:$Rm, pkh_lsl_amt:$sh),
3634 Requires<[IsARM, HasV6]>;
3636 // Alternate cases for PKHBT where identities eliminate some nodes.
3637 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3638 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3639 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3640 (PKHBT GPR:$Rn, GPR:$Rm, imm16_31:$sh)>;
3642 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3643 // will match the pattern below.
3644 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3645 (ins GPR:$Rn, GPR:$Rm, pkh_asr_amt:$sh),
3646 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3647 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3648 (and (sra GPR:$Rm, pkh_asr_amt:$sh),
3650 Requires<[IsARM, HasV6]>;
3652 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3653 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3654 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3655 (PKHTB GPR:$src1, GPR:$src2, imm16_31:$sh)>;
3656 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3657 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3658 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$sh)>;
3660 //===----------------------------------------------------------------------===//
3661 // Comparison Instructions...
3664 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3665 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3666 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3668 // ARMcmpZ can re-use the above instruction definitions.
3669 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3670 (CMPri GPR:$src, so_imm:$imm)>;
3671 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3672 (CMPrr GPR:$src, GPR:$rhs)>;
3673 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3674 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3675 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3676 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3678 // FIXME: We have to be careful when using the CMN instruction and comparison
3679 // with 0. One would expect these two pieces of code should give identical
3695 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3696 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3697 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3698 // value of r0 and the carry bit (because the "carry bit" parameter to
3699 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3700 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3701 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3702 // parameter to AddWithCarry is defined as 0).
3704 // When x is 0 and unsigned:
3708 // ~x + 1 = 0x1 0000 0000
3709 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3711 // Therefore, we should disable CMN when comparing against zero, until we can
3712 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3713 // when it's a comparison which doesn't look at the 'carry' flag).
3715 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3717 // This is related to <rdar://problem/7569620>.
3719 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3720 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3722 // Note that TST/TEQ don't set all the same flags that CMP does!
3723 defm TST : AI1_cmp_irs<0b1000, "tst",
3724 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3725 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3726 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3727 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3728 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3730 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3731 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3732 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3734 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3735 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3737 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3738 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3740 // Pseudo i64 compares for some floating point compares.
3741 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3743 def BCCi64 : PseudoInst<(outs),
3744 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3746 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3748 def BCCZi64 : PseudoInst<(outs),
3749 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3750 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3751 } // usesCustomInserter
3754 // Conditional moves
3755 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3756 // a two-value operand where a dag node expects two operands. :(
3757 let neverHasSideEffects = 1 in {
3758 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3760 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3761 RegConstraint<"$false = $Rd">;
3762 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3763 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3765 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
3766 imm:$cc, CCR:$ccr))*/]>,
3767 RegConstraint<"$false = $Rd">;
3768 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3769 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3771 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
3772 imm:$cc, CCR:$ccr))*/]>,
3773 RegConstraint<"$false = $Rd">;
3776 let isMoveImm = 1 in
3777 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3778 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3781 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3783 let isMoveImm = 1 in
3784 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3785 (ins GPR:$false, so_imm:$imm, pred:$p),
3787 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3788 RegConstraint<"$false = $Rd">;
3790 // Two instruction predicate mov immediate.
3791 let isMoveImm = 1 in
3792 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3793 (ins GPR:$false, i32imm:$src, pred:$p),
3794 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3796 let isMoveImm = 1 in
3797 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3798 (ins GPR:$false, so_imm:$imm, pred:$p),
3800 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3801 RegConstraint<"$false = $Rd">;
3802 } // neverHasSideEffects
3804 //===----------------------------------------------------------------------===//
3805 // Atomic operations intrinsics
3808 def MemBarrierOptOperand : AsmOperandClass {
3809 let Name = "MemBarrierOpt";
3810 let ParserMethod = "parseMemBarrierOptOperand";
3812 def memb_opt : Operand<i32> {
3813 let PrintMethod = "printMemBOption";
3814 let ParserMatchClass = MemBarrierOptOperand;
3817 // memory barriers protect the atomic sequences
3818 let hasSideEffects = 1 in {
3819 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3820 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3821 Requires<[IsARM, HasDB]> {
3823 let Inst{31-4} = 0xf57ff05;
3824 let Inst{3-0} = opt;
3828 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3829 "dsb", "\t$opt", []>,
3830 Requires<[IsARM, HasDB]> {
3832 let Inst{31-4} = 0xf57ff04;
3833 let Inst{3-0} = opt;
3836 // ISB has only full system option
3837 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3838 "isb", "\t$opt", []>,
3839 Requires<[IsARM, HasDB]> {
3841 let Inst{31-4} = 0xf57ff06;
3842 let Inst{3-0} = opt;
3845 let usesCustomInserter = 1 in {
3846 let Uses = [CPSR] in {
3847 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3848 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3849 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3850 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3851 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3852 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3853 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3854 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3855 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3856 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3857 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3858 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3859 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3860 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3861 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3862 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3863 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3864 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3865 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
3866 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3867 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3868 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
3869 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3870 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3871 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
3872 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3873 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3874 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
3875 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3876 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3877 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3878 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3879 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3880 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3881 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3882 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3883 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3884 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3885 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3886 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3887 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3888 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3889 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3890 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3891 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3892 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3893 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3894 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3895 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
3896 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3897 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3898 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
3899 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3900 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3901 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
3902 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3903 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3904 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
3905 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3906 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3907 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3908 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3909 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3910 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3911 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3912 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3913 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3914 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3915 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3916 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3917 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3918 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3919 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3920 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3921 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3922 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3923 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3924 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3925 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
3926 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3927 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3928 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
3929 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3930 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3931 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
3932 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3933 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3934 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
3935 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3936 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3938 def ATOMIC_SWAP_I8 : PseudoInst<
3939 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3940 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3941 def ATOMIC_SWAP_I16 : PseudoInst<
3942 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3943 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3944 def ATOMIC_SWAP_I32 : PseudoInst<
3945 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3946 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3948 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3949 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3950 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3951 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3952 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3953 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3954 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3955 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3956 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3960 let mayLoad = 1 in {
3961 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
3963 "ldrexb", "\t$Rt, $addr", []>;
3964 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
3965 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
3966 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
3967 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
3968 let hasExtraDefRegAllocReq = 1 in
3969 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
3970 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3973 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3974 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
3975 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3976 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
3977 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3978 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
3979 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3982 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
3983 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3984 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
3985 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3987 // Clear-Exclusive is for disassembly only.
3988 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3989 [/* For disassembly only; pattern left blank */]>,
3990 Requires<[IsARM, HasV7]> {
3991 let Inst{31-0} = 0b11110101011111111111000000011111;
3994 // SWP/SWPB are deprecated in V6/V7.
3995 let mayLoad = 1, mayStore = 1 in {
3996 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
3998 def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4002 //===----------------------------------------------------------------------===//
4003 // Coprocessor Instructions.
4006 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4007 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4008 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4009 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4010 imm:$CRm, imm:$opc2)]> {
4018 let Inst{3-0} = CRm;
4020 let Inst{7-5} = opc2;
4021 let Inst{11-8} = cop;
4022 let Inst{15-12} = CRd;
4023 let Inst{19-16} = CRn;
4024 let Inst{23-20} = opc1;
4027 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4028 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4029 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4030 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4031 imm:$CRm, imm:$opc2)]> {
4032 let Inst{31-28} = 0b1111;
4040 let Inst{3-0} = CRm;
4042 let Inst{7-5} = opc2;
4043 let Inst{11-8} = cop;
4044 let Inst{15-12} = CRd;
4045 let Inst{19-16} = CRn;
4046 let Inst{23-20} = opc1;
4049 class ACI<dag oops, dag iops, string opc, string asm,
4050 IndexMode im = IndexModeNone>
4051 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4053 let Inst{27-25} = 0b110;
4056 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
4057 let DecoderNamespace = "Common" in {
4058 def _OFFSET : ACI<(outs),
4059 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4060 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
4061 let Inst{31-28} = op31_28;
4062 let Inst{24} = 1; // P = 1
4063 let Inst{21} = 0; // W = 0
4064 let Inst{22} = 0; // D = 0
4065 let Inst{20} = load;
4066 let DecoderMethod = "DecodeCopMemInstruction";
4069 def _PRE : ACI<(outs),
4070 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4071 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
4072 let Inst{31-28} = op31_28;
4073 let Inst{24} = 1; // P = 1
4074 let Inst{21} = 1; // W = 1
4075 let Inst{22} = 0; // D = 0
4076 let Inst{20} = load;
4077 let DecoderMethod = "DecodeCopMemInstruction";
4080 def _POST : ACI<(outs),
4081 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4082 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
4083 let Inst{31-28} = op31_28;
4084 let Inst{24} = 0; // P = 0
4085 let Inst{21} = 1; // W = 1
4086 let Inst{22} = 0; // D = 0
4087 let Inst{20} = load;
4088 let DecoderMethod = "DecodeCopMemInstruction";
4091 def _OPTION : ACI<(outs),
4092 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
4094 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
4095 let Inst{31-28} = op31_28;
4096 let Inst{24} = 0; // P = 0
4097 let Inst{23} = 1; // U = 1
4098 let Inst{21} = 0; // W = 0
4099 let Inst{22} = 0; // D = 0
4100 let Inst{20} = load;
4101 let DecoderMethod = "DecodeCopMemInstruction";
4104 def L_OFFSET : ACI<(outs),
4105 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4106 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
4107 let Inst{31-28} = op31_28;
4108 let Inst{24} = 1; // P = 1
4109 let Inst{21} = 0; // W = 0
4110 let Inst{22} = 1; // D = 1
4111 let Inst{20} = load;
4112 let DecoderMethod = "DecodeCopMemInstruction";
4115 def L_PRE : ACI<(outs),
4116 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4117 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
4119 let Inst{31-28} = op31_28;
4120 let Inst{24} = 1; // P = 1
4121 let Inst{21} = 1; // W = 1
4122 let Inst{22} = 1; // D = 1
4123 let Inst{20} = load;
4124 let DecoderMethod = "DecodeCopMemInstruction";
4127 def L_POST : ACI<(outs),
4128 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
4129 postidx_imm8s4:$offset), ops),
4130 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr, $offset",
4132 let Inst{31-28} = op31_28;
4133 let Inst{24} = 0; // P = 0
4134 let Inst{21} = 1; // W = 1
4135 let Inst{22} = 1; // D = 1
4136 let Inst{20} = load;
4137 let DecoderMethod = "DecodeCopMemInstruction";
4140 def L_OPTION : ACI<(outs),
4141 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
4143 !strconcat(!strconcat(opc, "l"), cond),
4144 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
4145 let Inst{31-28} = op31_28;
4146 let Inst{24} = 0; // P = 0
4147 let Inst{23} = 1; // U = 1
4148 let Inst{21} = 0; // W = 0
4149 let Inst{22} = 1; // D = 1
4150 let Inst{20} = load;
4151 let DecoderMethod = "DecodeCopMemInstruction";
4156 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
4157 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
4158 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
4159 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
4161 //===----------------------------------------------------------------------===//
4162 // Move between coprocessor and ARM core register -- for disassembly only
4165 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4167 : ABI<0b1110, oops, iops, NoItinerary, opc,
4168 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4169 let Inst{20} = direction;
4179 let Inst{15-12} = Rt;
4180 let Inst{11-8} = cop;
4181 let Inst{23-21} = opc1;
4182 let Inst{7-5} = opc2;
4183 let Inst{3-0} = CRm;
4184 let Inst{19-16} = CRn;
4187 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4189 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4190 c_imm:$CRm, imm0_7:$opc2),
4191 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4192 imm:$CRm, imm:$opc2)]>;
4193 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4195 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4198 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4199 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4201 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4203 : ABXI<0b1110, oops, iops, NoItinerary,
4204 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4205 let Inst{31-28} = 0b1111;
4206 let Inst{20} = direction;
4216 let Inst{15-12} = Rt;
4217 let Inst{11-8} = cop;
4218 let Inst{23-21} = opc1;
4219 let Inst{7-5} = opc2;
4220 let Inst{3-0} = CRm;
4221 let Inst{19-16} = CRn;
4224 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4226 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4227 c_imm:$CRm, imm0_7:$opc2),
4228 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4229 imm:$CRm, imm:$opc2)]>;
4230 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4232 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4235 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4236 imm:$CRm, imm:$opc2),
4237 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4239 class MovRRCopro<string opc, bit direction,
4240 list<dag> pattern = [/* For disassembly only */]>
4241 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4242 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4243 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4244 let Inst{23-21} = 0b010;
4245 let Inst{20} = direction;
4253 let Inst{15-12} = Rt;
4254 let Inst{19-16} = Rt2;
4255 let Inst{11-8} = cop;
4256 let Inst{7-4} = opc1;
4257 let Inst{3-0} = CRm;
4260 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4261 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4263 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4265 class MovRRCopro2<string opc, bit direction,
4266 list<dag> pattern = [/* For disassembly only */]>
4267 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4268 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
4269 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4270 let Inst{31-28} = 0b1111;
4271 let Inst{23-21} = 0b010;
4272 let Inst{20} = direction;
4280 let Inst{15-12} = Rt;
4281 let Inst{19-16} = Rt2;
4282 let Inst{11-8} = cop;
4283 let Inst{7-4} = opc1;
4284 let Inst{3-0} = CRm;
4287 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4288 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4290 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4292 //===----------------------------------------------------------------------===//
4293 // Move between special register and ARM core register
4296 // Move to ARM core register from Special Register
4297 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4298 "mrs", "\t$Rd, apsr", []> {
4300 let Inst{23-16} = 0b00001111;
4301 let Inst{15-12} = Rd;
4302 let Inst{7-4} = 0b0000;
4305 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
4307 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4308 "mrs", "\t$Rd, spsr", []> {
4310 let Inst{23-16} = 0b01001111;
4311 let Inst{15-12} = Rd;
4312 let Inst{7-4} = 0b0000;
4315 // Move from ARM core register to Special Register
4317 // No need to have both system and application versions, the encodings are the
4318 // same and the assembly parser has no way to distinguish between them. The mask
4319 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4320 // the mask with the fields to be accessed in the special register.
4321 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4322 "msr", "\t$mask, $Rn", []> {
4327 let Inst{22} = mask{4}; // R bit
4328 let Inst{21-20} = 0b10;
4329 let Inst{19-16} = mask{3-0};
4330 let Inst{15-12} = 0b1111;
4331 let Inst{11-4} = 0b00000000;
4335 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4336 "msr", "\t$mask, $a", []> {
4341 let Inst{22} = mask{4}; // R bit
4342 let Inst{21-20} = 0b10;
4343 let Inst{19-16} = mask{3-0};
4344 let Inst{15-12} = 0b1111;
4348 //===----------------------------------------------------------------------===//
4352 // __aeabi_read_tp preserves the registers r1-r3.
4353 // This is a pseudo inst so that we can get the encoding right,
4354 // complete with fixup for the aeabi_read_tp function.
4356 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4357 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4358 [(set R0, ARMthread_pointer)]>;
4361 //===----------------------------------------------------------------------===//
4362 // SJLJ Exception handling intrinsics
4363 // eh_sjlj_setjmp() is an instruction sequence to store the return
4364 // address and save #0 in R0 for the non-longjmp case.
4365 // Since by its nature we may be coming from some other function to get
4366 // here, and we're using the stack frame for the containing function to
4367 // save/restore registers, we can't keep anything live in regs across
4368 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4369 // when we get here from a longjmp(). We force everything out of registers
4370 // except for our own input by listing the relevant registers in Defs. By
4371 // doing so, we also cause the prologue/epilogue code to actively preserve
4372 // all of the callee-saved resgisters, which is exactly what we want.
4373 // A constant value is passed in $val, and we use the location as a scratch.
4375 // These are pseudo-instructions and are lowered to individual MC-insts, so
4376 // no encoding information is necessary.
4378 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4379 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1 in {
4380 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4382 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4383 Requires<[IsARM, HasVFP2]>;
4387 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4388 hasSideEffects = 1, isBarrier = 1 in {
4389 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4391 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4392 Requires<[IsARM, NoVFP]>;
4395 // FIXME: Non-Darwin version(s)
4396 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4397 Defs = [ R7, LR, SP ] in {
4398 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4400 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4401 Requires<[IsARM, IsDarwin]>;
4404 // eh.sjlj.dispatchsetup pseudo-instruction.
4405 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
4406 // handled when the pseudo is expanded (which happens before any passes
4407 // that need the instruction size).
4408 let isBarrier = 1, hasSideEffects = 1 in
4409 def Int_eh_sjlj_dispatchsetup :
4410 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
4411 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
4412 Requires<[IsDarwin]>;
4414 //===----------------------------------------------------------------------===//
4415 // Non-Instruction Patterns
4418 // ARMv4 indirect branch using (MOVr PC, dst)
4419 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4420 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4421 4, IIC_Br, [(brind GPR:$dst)],
4422 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4423 Requires<[IsARM, NoV4T]>;
4425 // Large immediate handling.
4427 // 32-bit immediate using two piece so_imms or movw + movt.
4428 // This is a single pseudo instruction, the benefit is that it can be remat'd
4429 // as a single unit instead of having to handle reg inputs.
4430 // FIXME: Remove this when we can do generalized remat.
4431 let isReMaterializable = 1, isMoveImm = 1 in
4432 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4433 [(set GPR:$dst, (arm_i32imm:$src))]>,
4436 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4437 // It also makes it possible to rematerialize the instructions.
4438 // FIXME: Remove this when we can do generalized remat and when machine licm
4439 // can properly the instructions.
4440 let isReMaterializable = 1 in {
4441 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4443 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4444 Requires<[IsARM, UseMovt]>;
4446 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4448 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4449 Requires<[IsARM, UseMovt]>;
4451 let AddedComplexity = 10 in
4452 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4454 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4455 Requires<[IsARM, UseMovt]>;
4456 } // isReMaterializable
4458 // ConstantPool, GlobalAddress, and JumpTable
4459 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4460 Requires<[IsARM, DontUseMovt]>;
4461 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4462 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4463 Requires<[IsARM, UseMovt]>;
4464 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4465 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4467 // TODO: add,sub,and, 3-instr forms?
4470 def : ARMPat<(ARMtcret tcGPR:$dst),
4471 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
4473 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4474 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4476 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4477 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4479 def : ARMPat<(ARMtcret tcGPR:$dst),
4480 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
4482 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4483 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4485 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4486 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4489 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
4490 Requires<[IsARM, IsNotDarwin]>;
4491 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
4492 Requires<[IsARM, IsDarwin]>;
4494 // zextload i1 -> zextload i8
4495 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4496 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4498 // extload -> zextload
4499 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4500 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4501 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4502 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4504 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4506 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4507 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4510 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4511 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4512 (SMULBB GPR:$a, GPR:$b)>;
4513 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4514 (SMULBB GPR:$a, GPR:$b)>;
4515 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4516 (sra GPR:$b, (i32 16))),
4517 (SMULBT GPR:$a, GPR:$b)>;
4518 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4519 (SMULBT GPR:$a, GPR:$b)>;
4520 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4521 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4522 (SMULTB GPR:$a, GPR:$b)>;
4523 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4524 (SMULTB GPR:$a, GPR:$b)>;
4525 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4527 (SMULWB GPR:$a, GPR:$b)>;
4528 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4529 (SMULWB GPR:$a, GPR:$b)>;
4531 def : ARMV5TEPat<(add GPR:$acc,
4532 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4533 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4534 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4535 def : ARMV5TEPat<(add GPR:$acc,
4536 (mul sext_16_node:$a, sext_16_node:$b)),
4537 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4538 def : ARMV5TEPat<(add GPR:$acc,
4539 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4540 (sra GPR:$b, (i32 16)))),
4541 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4542 def : ARMV5TEPat<(add GPR:$acc,
4543 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4544 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4545 def : ARMV5TEPat<(add GPR:$acc,
4546 (mul (sra GPR:$a, (i32 16)),
4547 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4548 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4549 def : ARMV5TEPat<(add GPR:$acc,
4550 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4551 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4552 def : ARMV5TEPat<(add GPR:$acc,
4553 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4555 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4556 def : ARMV5TEPat<(add GPR:$acc,
4557 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4558 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4561 // Pre-v7 uses MCR for synchronization barriers.
4562 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4563 Requires<[IsARM, HasV6]>;
4565 // SXT/UXT with no rotate
4566 let AddedComplexity = 16 in {
4567 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4568 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4569 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4570 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4571 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4572 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4573 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4576 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4577 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4579 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPR:$Rm, i8)),
4580 (SXTAB GPR:$Rn, GPR:$Rm, 0)>;
4581 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPR:$Rm, i16)),
4582 (SXTAH GPR:$Rn, GPR:$Rm, 0)>;
4584 //===----------------------------------------------------------------------===//
4588 include "ARMInstrThumb.td"
4590 //===----------------------------------------------------------------------===//
4594 include "ARMInstrThumb2.td"
4596 //===----------------------------------------------------------------------===//
4597 // Floating Point Support
4600 include "ARMInstrVFP.td"
4602 //===----------------------------------------------------------------------===//
4603 // Advanced SIMD (NEON) Support
4606 include "ARMInstrNEON.td"
4608 //===----------------------------------------------------------------------===//
4609 // Assembler aliases
4613 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4614 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4615 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4617 // System instructions
4618 def : MnemonicAlias<"swi", "svc">;
4620 // Load / Store Multiple
4621 def : MnemonicAlias<"ldmfd", "ldm">;
4622 def : MnemonicAlias<"ldmia", "ldm">;
4623 def : MnemonicAlias<"stmfd", "stmdb">;
4624 def : MnemonicAlias<"stmia", "stm">;
4625 def : MnemonicAlias<"stmea", "stm">;
4627 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4628 // shift amount is zero (i.e., unspecified).
4629 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4630 (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4631 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4632 (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4634 // PUSH/POP aliases for STM/LDM
4635 def : InstAlias<"push${p} $regs",
4636 (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4637 def : InstAlias<"pop${p} $regs",
4638 (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4640 // RSB two-operand forms (optional explicit destination operand)
4641 def : InstAlias<"rsb${s}${p} $Rdn, $imm",
4642 (RSBri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>,
4644 def : InstAlias<"rsb${s}${p} $Rdn, $Rm",
4645 (RSBrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>,
4647 def : InstAlias<"rsb${s}${p} $Rdn, $shift",
4648 (RSBrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p,
4649 cc_out:$s)>, Requires<[IsARM]>;
4650 def : InstAlias<"rsb${s}${p} $Rdn, $shift",
4651 (RSBrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p,
4652 cc_out:$s)>, Requires<[IsARM]>;
4653 // RSC two-operand forms (optional explicit destination operand)
4654 def : InstAlias<"rsc${s}${p} $Rdn, $imm",
4655 (RSCri GPR:$Rdn, GPR:$Rdn, so_imm:$imm, pred:$p, cc_out:$s)>,
4657 def : InstAlias<"rsc${s}${p} $Rdn, $Rm",
4658 (RSCrr GPR:$Rdn, GPR:$Rdn, GPR:$Rm, pred:$p, cc_out:$s)>,
4660 def : InstAlias<"rsc${s}${p} $Rdn, $shift",
4661 (RSCrsi GPR:$Rdn, GPR:$Rdn, so_reg_imm:$shift, pred:$p,
4662 cc_out:$s)>, Requires<[IsARM]>;
4663 def : InstAlias<"rsc${s}${p} $Rdn, $shift",
4664 (RSCrsr GPR:$Rdn, GPR:$Rdn, so_reg_reg:$shift, pred:$p,
4665 cc_out:$s)>, Requires<[IsARM]>;
4667 // SSAT/USAT optional shift operand.
4668 def : InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4669 (SSAT GPR:$Rd, imm1_32:$sat_imm, GPR:$Rn, 0, pred:$p)>;
4670 def : InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4671 (USAT GPR:$Rd, imm0_31:$sat_imm, GPR:$Rn, 0, pred:$p)>;
4674 // Extend instruction optional rotate operand.
4675 def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4676 (SXTAB GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4677 def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4678 (SXTAH GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4679 def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4680 (SXTAB16 GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4681 def : InstAlias<"sxtb${p} $Rd, $Rm", (SXTB GPR:$Rd, GPR:$Rm, 0, pred:$p)>;
4682 def : InstAlias<"sxtb16${p} $Rd, $Rm", (SXTB16 GPR:$Rd, GPR:$Rm, 0, pred:$p)>;
4683 def : InstAlias<"sxth${p} $Rd, $Rm", (SXTH GPR:$Rd, GPR:$Rm, 0, pred:$p)>;
4685 def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4686 (UXTAB GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4687 def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4688 (UXTAH GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4689 def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4690 (UXTAB16 GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>;
4691 def : InstAlias<"uxtb${p} $Rd, $Rm", (UXTB GPR:$Rd, GPR:$Rm, 0, pred:$p)>;
4692 def : InstAlias<"uxtb16${p} $Rd, $Rm", (UXTB16 GPR:$Rd, GPR:$Rm, 0, pred:$p)>;
4693 def : InstAlias<"uxth${p} $Rd, $Rm", (UXTH GPR:$Rd, GPR:$Rm, 0, pred:$p)>;
4697 def : MnemonicAlias<"rfefa", "rfeda">;
4698 def : MnemonicAlias<"rfeea", "rfedb">;
4699 def : MnemonicAlias<"rfefd", "rfeia">;
4700 def : MnemonicAlias<"rfeed", "rfeib">;
4701 def : MnemonicAlias<"rfe", "rfeia">;
4704 def : MnemonicAlias<"srsfa", "srsda">;
4705 def : MnemonicAlias<"srsea", "srsdb">;
4706 def : MnemonicAlias<"srsfd", "srsia">;
4707 def : MnemonicAlias<"srsed", "srsib">;
4708 def : MnemonicAlias<"srs", "srsia">;
4710 // LDRSBT/LDRHT/LDRSHT post-index offset if optional.
4711 // Note that the write-back output register is a dummy operand for MC (it's
4712 // only meaningful for codegen), so we just pass zero here.
4713 // FIXME: tblgen not cooperating with argument conversions.
4714 //def : InstAlias<"ldrsbt${p} $Rt, $addr",
4715 // (LDRSBTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0,pred:$p)>;
4716 //def : InstAlias<"ldrht${p} $Rt, $addr",
4717 // (LDRHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>;
4718 //def : InstAlias<"ldrsht${p} $Rt, $addr",
4719 // (LDRSHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>;