1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // ARM specific DAG Nodes.
20 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
39 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
42 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
45 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
46 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
48 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
49 [SDNPHasChain, SDNPOutFlag]>;
50 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
51 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
53 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
54 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
55 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
57 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
58 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
61 [SDNPHasChain, SDNPOptInFlag]>;
63 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
65 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
68 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
69 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
71 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
74 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
77 def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
80 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
82 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
83 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
84 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
86 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
88 //===----------------------------------------------------------------------===//
89 // ARM Instruction Predicate Definitions.
91 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
92 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
93 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
94 def IsThumb : Predicate<"Subtarget->isThumb()">;
95 def IsARM : Predicate<"!Subtarget->isThumb()">;
97 //===----------------------------------------------------------------------===//
98 // ARM Flag Definitions.
100 class RegConstraint<string C> {
101 string Constraints = C;
104 //===----------------------------------------------------------------------===//
105 // ARM specific transformation functions and pattern fragments.
108 // so_imm_XFORM - Return a so_imm value packed into the format described for
110 def so_imm_XFORM : SDNodeXForm<imm, [{
111 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getValue()),
115 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
116 // so_imm_neg def below.
117 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
118 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getValue()),
122 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
123 // so_imm_not def below.
124 def so_imm_not_XFORM : SDNodeXForm<imm, [{
125 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getValue()),
129 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
130 def rot_imm : PatLeaf<(i32 imm), [{
131 int32_t v = (int32_t)N->getValue();
132 return v == 8 || v == 16 || v == 24;
135 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
136 def imm1_15 : PatLeaf<(i32 imm), [{
137 return (int32_t)N->getValue() >= 1 && (int32_t)N->getValue() < 16;
140 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
141 def imm16_31 : PatLeaf<(i32 imm), [{
142 return (int32_t)N->getValue() >= 16 && (int32_t)N->getValue() < 32;
146 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }],
150 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }],
153 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
154 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
155 return CurDAG->ComputeNumSignBits(SDOperand(N,0)) >= 17;
160 //===----------------------------------------------------------------------===//
161 // Operand Definitions.
165 def brtarget : Operand<OtherVT>;
167 // A list of registers separated by comma. Used by load/store multiple.
168 def reglist : Operand<i32> {
169 let PrintMethod = "printRegisterList";
172 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
173 def cpinst_operand : Operand<i32> {
174 let PrintMethod = "printCPInstOperand";
177 def jtblock_operand : Operand<i32> {
178 let PrintMethod = "printJTBlockOperand";
182 def pclabel : Operand<i32> {
183 let PrintMethod = "printPCLabel";
186 // shifter_operand operands: so_reg and so_imm.
187 def so_reg : Operand<i32>, // reg reg imm
188 ComplexPattern<i32, 3, "SelectShifterOperandReg",
189 [shl,srl,sra,rotr]> {
190 let PrintMethod = "printSORegOperand";
191 let MIOperandInfo = (ops GPR, GPR, i32imm);
194 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
195 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
196 // represented in the imm field in the same 12-bit form that they are encoded
197 // into so_imm instructions: the 8-bit immediate is the least significant bits
198 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
199 def so_imm : Operand<i32>,
201 [{ return ARM_AM::getSOImmVal(N->getValue()) != -1; }],
203 let PrintMethod = "printSOImmOperand";
206 // Break so_imm's up into two pieces. This handles immediates with up to 16
207 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
208 // get the first/second pieces.
209 def so_imm2part : Operand<i32>,
211 [{ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getValue()); }]> {
212 let PrintMethod = "printSOImm2PartOperand";
215 def so_imm2part_1 : SDNodeXForm<imm, [{
216 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getValue());
217 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
220 def so_imm2part_2 : SDNodeXForm<imm, [{
221 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getValue());
222 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
226 // Define ARM specific addressing modes.
228 // addrmode2 := reg +/- reg shop imm
229 // addrmode2 := reg +/- imm12
231 def addrmode2 : Operand<i32>,
232 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
233 let PrintMethod = "printAddrMode2Operand";
234 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
237 def am2offset : Operand<i32>,
238 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
239 let PrintMethod = "printAddrMode2OffsetOperand";
240 let MIOperandInfo = (ops GPR, i32imm);
243 // addrmode3 := reg +/- reg
244 // addrmode3 := reg +/- imm8
246 def addrmode3 : Operand<i32>,
247 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
248 let PrintMethod = "printAddrMode3Operand";
249 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
252 def am3offset : Operand<i32>,
253 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
254 let PrintMethod = "printAddrMode3OffsetOperand";
255 let MIOperandInfo = (ops GPR, i32imm);
258 // addrmode4 := reg, <mode|W>
260 def addrmode4 : Operand<i32>,
261 ComplexPattern<i32, 2, "", []> {
262 let PrintMethod = "printAddrMode4Operand";
263 let MIOperandInfo = (ops GPR, i32imm);
266 // addrmode5 := reg +/- imm8*4
268 def addrmode5 : Operand<i32>,
269 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
270 let PrintMethod = "printAddrMode5Operand";
271 let MIOperandInfo = (ops GPR, i32imm);
274 // addrmodepc := pc + reg
276 def addrmodepc : Operand<i32>,
277 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
278 let PrintMethod = "printAddrModePCOperand";
279 let MIOperandInfo = (ops GPR, i32imm);
282 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
283 // register whose default is 0 (no register).
284 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
285 (ops (i32 14), (i32 zero_reg))> {
286 let PrintMethod = "printPredicateOperand";
289 // Conditional code operand for conditional branches and conditional moves.
290 // No AlwaysVal value.
291 def ccop : PredicateOperand<OtherVT, (ops i32imm, CCR), (ops)> {
292 let PrintMethod = "printPredicateOperand";
295 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
297 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
298 let PrintMethod = "printSBitModifierOperand";
301 //===----------------------------------------------------------------------===//
302 // ARM Instruction flags. These need to match ARMInstrInfo.h.
306 class AddrMode<bits<4> val> {
309 def AddrModeNone : AddrMode<0>;
310 def AddrMode1 : AddrMode<1>;
311 def AddrMode2 : AddrMode<2>;
312 def AddrMode3 : AddrMode<3>;
313 def AddrMode4 : AddrMode<4>;
314 def AddrMode5 : AddrMode<5>;
315 def AddrModeT1 : AddrMode<6>;
316 def AddrModeT2 : AddrMode<7>;
317 def AddrModeT4 : AddrMode<8>;
318 def AddrModeTs : AddrMode<9>;
321 class SizeFlagVal<bits<3> val> {
324 def SizeInvalid : SizeFlagVal<0>; // Unset.
325 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
326 def Size8Bytes : SizeFlagVal<2>;
327 def Size4Bytes : SizeFlagVal<3>;
328 def Size2Bytes : SizeFlagVal<4>;
330 // Load / store index mode.
331 class IndexMode<bits<2> val> {
334 def IndexModeNone : IndexMode<0>;
335 def IndexModePre : IndexMode<1>;
336 def IndexModePost : IndexMode<2>;
338 //===----------------------------------------------------------------------===//
339 // ARM Instruction templates.
342 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
343 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
344 list<Predicate> Predicates = [IsARM];
346 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
347 list<Predicate> Predicates = [IsARM, HasV5TE];
349 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
350 list<Predicate> Predicates = [IsARM, HasV6];
353 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
356 let Namespace = "ARM";
358 bits<4> Opcode = opcod;
360 bits<4> AddrModeBits = AM.Value;
363 bits<3> SizeFlag = SZ.Value;
366 bits<2> IndexModeBits = IM.Value;
368 let Constraints = cstr;
371 class PseudoInst<dag ops, string asm, list<dag> pattern>
372 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, ""> {
373 let OperandList = ops;
375 let Pattern = pattern;
378 // Almost all ARM instructions are predicable.
379 class I<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im,
380 string opc, string asm, string cstr, list<dag> pattern>
381 // FIXME: Set all opcodes to 0 for now.
382 : InstARM<0, am, sz, im, cstr> {
383 let OperandList = !con(oprnds, (ops pred:$p));
384 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
385 let Pattern = pattern;
386 list<Predicate> Predicates = [IsARM];
389 class AI<dag ops, string opc, string asm, list<dag> pattern>
390 : I<ops, AddrModeNone, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
391 class AI1<dag ops, string opc, string asm, list<dag> pattern>
392 : I<ops, AddrMode1, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
393 class AI2<dag ops, string opc, string asm, list<dag> pattern>
394 : I<ops, AddrMode2, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
395 class AI3<dag ops, string opc, string asm, list<dag> pattern>
396 : I<ops, AddrMode3, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
397 class AI4<dag ops, string opc, string asm, list<dag> pattern>
398 : I<ops, AddrMode4, Size4Bytes, IndexModeNone, opc, asm, "", pattern>;
399 class AI1x2<dag ops, string opc, string asm, list<dag> pattern>
400 : I<ops, AddrMode1, Size8Bytes, IndexModeNone, opc, asm, "", pattern>;
403 class AI2pr<dag ops, string opc, string asm, string cstr, list<dag> pattern>
404 : I<ops, AddrMode2, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>;
405 class AI3pr<dag ops, string opc, string asm, string cstr, list<dag> pattern>
406 : I<ops, AddrMode3, Size4Bytes, IndexModePre, opc, asm, cstr, pattern>;
409 class AI2po<dag ops, string opc, string asm, string cstr, list<dag> pattern>
410 : I<ops, AddrMode2, Size4Bytes, IndexModePost, opc, asm, cstr, pattern>;
411 class AI3po<dag ops, string opc, string asm, string cstr, list<dag> pattern>
412 : I<ops, AddrMode3, Size4Bytes, IndexModePost, opc, asm, cstr, pattern>;
415 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
416 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
419 /// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
420 /// binop that produces a value.
421 multiclass AI1_bin_irs<string opc, PatFrag opnode> {
422 def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
423 opc, " $dst, $a, $b",
424 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
425 def rr : AI1<(ops GPR:$dst, GPR:$a, GPR:$b),
426 opc, " $dst, $a, $b",
427 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
428 def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
429 opc, " $dst, $a, $b",
430 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
433 /// AI1_bin_s_irs - Similar to AI1_bin_irs except it sets the 's' bit so the
434 /// instruction modifies the CSPR register.
435 multiclass AI1_bin_s_irs<string opc, PatFrag opnode> {
436 def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
437 opc, "s $dst, $a, $b",
438 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[], [CPSR]>;
439 def rr : AI1<(ops GPR:$dst, GPR:$a, GPR:$b),
440 opc, "s $dst, $a, $b",
441 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[], [CPSR]>;
442 def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
443 opc, "s $dst, $a, $b",
444 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[], [CPSR]>;
447 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
448 /// patterns. Similar to AI1_bin_irs except the instruction does not produce
449 /// a explicit result, only implicitly set CPSR.
450 multiclass AI1_cmp_irs<string opc, PatFrag opnode> {
451 def ri : AI1<(ops GPR:$a, so_imm:$b),
453 [(opnode GPR:$a, so_imm:$b)]>, Imp<[], [CPSR]>;
454 def rr : AI1<(ops GPR:$a, GPR:$b),
456 [(opnode GPR:$a, GPR:$b)]>, Imp<[], [CPSR]>;
457 def rs : AI1<(ops GPR:$a, so_reg:$b),
459 [(opnode GPR:$a, so_reg:$b)]>, Imp<[], [CPSR]>;
462 /// AI1_bin_is - Defines a set of (op r, {so_imm|so_reg}) patterns for a binop.
463 multiclass AI1_bin_is<string opc, PatFrag opnode> {
464 def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
465 opc, " $dst, $a, $b",
466 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
467 def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
468 opc, " $dst, $a, $b",
469 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
472 /// AI1_unary_irs - Defines a set of (op {so_imm|r|so_reg}) patterns for unary
474 multiclass AI1_unary_irs<string opc, PatFrag opnode> {
475 def i : AI1<(ops GPR:$dst, so_imm:$a),
477 [(set GPR:$dst, (opnode so_imm:$a))]>;
478 def r : AI1<(ops GPR:$dst, GPR:$a),
480 [(set GPR:$dst, (opnode GPR:$a))]>;
481 def s : AI1<(ops GPR:$dst, so_reg:$a),
483 [(set GPR:$dst, (opnode so_reg:$a))]>;
486 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
487 /// register and one whose operand is a register rotated by 8/16/24.
488 multiclass AI_unary_rrot<string opc, PatFrag opnode> {
489 def r : AI<(ops GPR:$dst, GPR:$Src),
491 [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
492 def r_rot : AI<(ops GPR:$dst, GPR:$Src, i32imm:$rot),
493 opc, " $dst, $Src, ror $rot",
494 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
495 Requires<[IsARM, HasV6]>;
498 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
499 /// register and one whose operand is a register rotated by 8/16/24.
500 multiclass AI_bin_rrot<string opc, PatFrag opnode> {
501 def rr : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS),
502 opc, " $dst, $LHS, $RHS",
503 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
504 Requires<[IsARM, HasV6]>;
505 def rr_rot : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS, i32imm:$rot),
506 opc, " $dst, $LHS, $RHS, ror $rot",
507 [(set GPR:$dst, (opnode GPR:$LHS,
508 (rotr GPR:$RHS, rot_imm:$rot)))]>,
509 Requires<[IsARM, HasV6]>;
513 class XI<dag oprnds, AddrMode am, SizeFlagVal sz, IndexMode im,
514 string asm, string cstr, list<dag> pattern>
515 // FIXME: Set all opcodes to 0 for now.
516 : InstARM<0, am, sz, im, cstr> {
517 let OperandList = oprnds;
519 let Pattern = pattern;
520 list<Predicate> Predicates = [IsARM];
523 class AXI<dag ops, string asm, list<dag> pattern>
524 : XI<ops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern>;
525 class AXI1<dag ops, string asm, list<dag> pattern>
526 : XI<ops, AddrMode1, Size4Bytes, IndexModeNone, asm, "", pattern>;
527 class AXI2<dag ops, string asm, list<dag> pattern>
528 : XI<ops, AddrMode2, Size4Bytes, IndexModeNone, asm, "", pattern>;
529 class AXI3<dag ops, string asm, list<dag> pattern>
530 : XI<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
531 class AXI4<dag ops, string asm, list<dag> pattern>
532 : XI<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
534 class AXIx2<dag ops, string asm, list<dag> pattern>
535 : XI<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
537 // BR_JT instructions
538 class JTI<dag ops, string asm, list<dag> pattern>
539 : XI<ops, AddrModeNone, SizeSpecial, IndexModeNone, asm, "", pattern>;
540 class JTI1<dag ops, string asm, list<dag> pattern>
541 : XI<ops, AddrMode1, SizeSpecial, IndexModeNone, asm, "", pattern>;
542 class JTI2<dag ops, string asm, list<dag> pattern>
543 : XI<ops, AddrMode2, SizeSpecial, IndexModeNone, asm, "", pattern>;
545 /// AXI1_bin_c_irs - Same as AI1_bin_irs but without the predicate operand and
546 /// setting carry bit.
547 multiclass AXI1_bin_c_irs<string opc, PatFrag opnode> {
548 def ri : AXI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
549 !strconcat(opc, " $dst, $a, $b"),
550 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>, Imp<[CPSR], []>;
551 def rr : AXI1<(ops GPR:$dst, GPR:$a, GPR:$b),
552 !strconcat(opc, " $dst, $a, $b"),
553 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>, Imp<[CPSR], []>;
554 def rs : AXI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
555 !strconcat(opc, " $dst, $a, $b"),
556 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>, Imp<[CPSR], []>;
559 //===----------------------------------------------------------------------===//
561 //===----------------------------------------------------------------------===//
563 //===----------------------------------------------------------------------===//
564 // Miscellaneous Instructions.
566 def IMPLICIT_DEF_GPR :
567 PseudoInst<(ops GPR:$rD, pred:$p),
568 "@ IMPLICIT_DEF_GPR $rD",
569 [(set GPR:$rD, (undef))]>;
572 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
573 /// the function. The first operand is the ID# for this instruction, the second
574 /// is the index into the MachineConstantPool that this is, the third is the
575 /// size in bytes of this constant pool entry.
576 let isNotDuplicable = 1 in
577 def CONSTPOOL_ENTRY :
578 PseudoInst<(ops cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size),
579 "${instid:label} ${cpidx:cpentry}", []>;
582 PseudoInst<(ops i32imm:$amt, pred:$p),
583 "@ ADJCALLSTACKUP $amt",
584 [(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>;
586 def ADJCALLSTACKDOWN :
587 PseudoInst<(ops i32imm:$amt, pred:$p),
588 "@ ADJCALLSTACKDOWN $amt",
589 [(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>;
592 PseudoInst<(ops i32imm:$line, i32imm:$col, i32imm:$file),
593 ".loc $file, $line, $col",
594 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
596 let isNotDuplicable = 1 in {
597 def PICADD : AXI1<(ops GPR:$dst, GPR:$a, pclabel:$cp, pred:$p),
598 "$cp:\n\tadd$p $dst, pc, $a",
599 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
601 let isLoad = 1, AddedComplexity = 10 in {
602 def PICLD : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
603 "${addr:label}:\n\tldr$p $dst, $addr",
604 [(set GPR:$dst, (load addrmodepc:$addr))]>;
606 def PICLDZH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
607 "${addr:label}:\n\tldr${p}h $dst, $addr",
608 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
610 def PICLDZB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
611 "${addr:label}:\n\tldr${p}b $dst, $addr",
612 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
614 def PICLDH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
615 "${addr:label}:\n\tldr${p}h $dst, $addr",
616 [(set GPR:$dst, (extloadi16 addrmodepc:$addr))]>;
618 def PICLDB : AXI2<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
619 "${addr:label}:\n\tldr${p}b $dst, $addr",
620 [(set GPR:$dst, (extloadi8 addrmodepc:$addr))]>;
622 def PICLDSH : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
623 "${addr:label}:\n\tldr${p}sh $dst, $addr",
624 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
626 def PICLDSB : AXI3<(ops GPR:$dst, addrmodepc:$addr, pred:$p),
627 "${addr:label}:\n\tldr${p}sb $dst, $addr",
628 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
630 let isStore = 1, AddedComplexity = 10 in {
631 def PICSTR : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p),
632 "${addr:label}:\n\tstr$p $src, $addr",
633 [(store GPR:$src, addrmodepc:$addr)]>;
635 def PICSTRH : AXI3<(ops GPR:$src, addrmodepc:$addr, pred:$p),
636 "${addr:label}:\n\tstr${p}h $src, $addr",
637 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
639 def PICSTRB : AXI2<(ops GPR:$src, addrmodepc:$addr, pred:$p),
640 "${addr:label}:\n\tstr${p}b $src, $addr",
641 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
645 //===----------------------------------------------------------------------===//
646 // Control Flow Instructions.
649 let isReturn = 1, isTerminator = 1 in
650 def BX_RET : AI<(ops), "bx", " lr", [(ARMretflag)]>;
652 // FIXME: remove when we have a way to marking a MI with these properties.
653 let isLoad = 1, isReturn = 1, isTerminator = 1 in
654 def LDM_RET : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
655 "ldm${p}${addr:submode} $addr, $dst1",
658 let isCall = 1, noResults = 1, clobbersPred = 1,
659 Defs = [R0, R1, R2, R3, R12, LR,
660 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
661 def BL : AXI<(ops i32imm:$func, variable_ops),
663 [(ARMcall tglobaladdr:$func)]>;
665 def BL_pred : AI<(ops i32imm:$func, variable_ops),
666 "bl", " ${func:call}",
667 [(ARMcall_pred tglobaladdr:$func)]>;
670 def BLX : AXI<(ops GPR:$dst, variable_ops),
672 [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
675 def BX : AXIx2<(ops GPR:$dst, variable_ops),
676 "mov lr, pc\n\tbx $dst",
677 [(ARMcall_nolink GPR:$dst)]>;
681 let isBranch = 1, isTerminator = 1, noResults = 1 in {
682 // B is "predicable" since it can be xformed into a Bcc.
683 let isBarrier = 1 in {
684 let isPredicable = 1 in
685 def B : AXI<(ops brtarget:$dst), "b $dst",
688 let isNotDuplicable = 1 in {
689 def BR_JTr : JTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
690 "mov pc, $dst \n$jt",
691 [(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>;
692 def BR_JTm : JTI2<(ops addrmode2:$dst, jtblock_operand:$jt, i32imm:$id),
693 "ldr pc, $dst \n$jt",
694 [(ARMbrjt (i32 (load addrmode2:$dst)), tjumptable:$jt,
696 def BR_JTadd : JTI1<(ops GPR:$dst, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
697 "add pc, $dst, $idx \n$jt",
698 [(ARMbrjt (add GPR:$dst, GPR:$idx), tjumptable:$jt,
703 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
704 // a two-value operand where a dag node expects two operands. :(
705 def Bcc : AXI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst",
706 [/*(ARMbrcond bb:$dst, imm:$cc, CCR:$ccr)*/]>;
709 //===----------------------------------------------------------------------===//
710 // Load / store Instructions.
715 def LDR : AI2<(ops GPR:$dst, addrmode2:$addr),
716 "ldr", " $dst, $addr",
717 [(set GPR:$dst, (load addrmode2:$addr))]>;
719 // Special LDR for loads from non-pc-relative constpools.
720 let isReMaterializable = 1 in
721 def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr),
722 "ldr", " $dst, $addr", []>;
724 // Loads with zero extension
725 def LDRH : AI3<(ops GPR:$dst, addrmode3:$addr),
726 "ldr", "h $dst, $addr",
727 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
729 def LDRB : AI2<(ops GPR:$dst, addrmode2:$addr),
730 "ldr", "b $dst, $addr",
731 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
733 // Loads with sign extension
734 def LDRSH : AI3<(ops GPR:$dst, addrmode3:$addr),
735 "ldr", "sh $dst, $addr",
736 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
738 def LDRSB : AI3<(ops GPR:$dst, addrmode3:$addr),
739 "ldr", "sb $dst, $addr",
740 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
743 def LDRD : AI3<(ops GPR:$dst, addrmode3:$addr),
744 "ldr", "d $dst, $addr",
745 []>, Requires<[IsARM, HasV5T]>;
748 def LDR_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr),
749 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
751 def LDR_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base, am2offset:$offset),
752 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
754 def LDRH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
755 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
757 def LDRH_POST : AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
758 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
760 def LDRB_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr),
761 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
763 def LDRB_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am2offset:$offset),
764 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
766 def LDRSH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
767 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
769 def LDRSH_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
770 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
772 def LDRSB_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
773 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
775 def LDRSB_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
776 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
781 def STR : AI2<(ops GPR:$src, addrmode2:$addr),
782 "str", " $src, $addr",
783 [(store GPR:$src, addrmode2:$addr)]>;
785 // Stores with truncate
786 def STRH : AI3<(ops GPR:$src, addrmode3:$addr),
787 "str", "h $src, $addr",
788 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
790 def STRB : AI2<(ops GPR:$src, addrmode2:$addr),
791 "str", "b $src, $addr",
792 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
795 def STRD : AI3<(ops GPR:$src, addrmode3:$addr),
796 "str", "d $src, $addr",
797 []>, Requires<[IsARM, HasV5T]>;
800 def STR_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base, am2offset:$offset),
801 "str", " $src, [$base, $offset]!", "$base = $base_wb",
803 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
805 def STR_POST : AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
806 "str", " $src, [$base], $offset", "$base = $base_wb",
808 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
810 def STRH_PRE : AI3pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset),
811 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
813 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
815 def STRH_POST: AI3po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset),
816 "str", "h $src, [$base], $offset", "$base = $base_wb",
817 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
818 GPR:$base, am3offset:$offset))]>;
820 def STRB_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
821 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
822 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
823 GPR:$base, am2offset:$offset))]>;
825 def STRB_POST: AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
826 "str", "b $src, [$base], $offset", "$base = $base_wb",
827 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
828 GPR:$base, am2offset:$offset))]>;
831 //===----------------------------------------------------------------------===//
832 // Load / store multiple Instructions.
836 def LDM : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
837 "ldm${p}${addr:submode} $addr, $dst1",
841 def STM : AXI4<(ops addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
842 "stm${p}${addr:submode} $addr, $src1",
845 //===----------------------------------------------------------------------===//
846 // Move Instructions.
849 def MOVr : AI1<(ops GPR:$dst, GPR:$src),
850 "mov", " $dst, $src", []>;
851 def MOVs : AI1<(ops GPR:$dst, so_reg:$src),
852 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
854 let isReMaterializable = 1 in
855 def MOVi : AI1<(ops GPR:$dst, so_imm:$src),
856 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
858 // These aren't really mov instructions, but we have to define them this way
859 // due to flag operands.
861 let clobbersPred = 1 in {
862 def MOVsrl_flag : AI1<(ops GPR:$dst, GPR:$src),
863 "mov", "s $dst, $src, lsr #1",
864 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, Imp<[], [CPSR]>;
865 def MOVsra_flag : AI1<(ops GPR:$dst, GPR:$src),
866 "mov", "s $dst, $src, asr #1",
867 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, Imp<[], [CPSR]>;
869 def MOVrx : AI1<(ops GPR:$dst, GPR:$src),
870 "mov", " $dst, $src, rrx",
871 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
873 //===----------------------------------------------------------------------===//
874 // Extend Instructions.
879 defm SXTB : AI_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
880 defm SXTH : AI_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
882 defm SXTAB : AI_bin_rrot<"sxtab",
883 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
884 defm SXTAH : AI_bin_rrot<"sxtah",
885 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
887 // TODO: SXT(A){B|H}16
891 let AddedComplexity = 16 in {
892 defm UXTB : AI_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
893 defm UXTH : AI_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
894 defm UXTB16 : AI_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
896 def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
897 (UXTB16r_rot GPR:$Src, 24)>;
898 def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
899 (UXTB16r_rot GPR:$Src, 8)>;
901 defm UXTAB : AI_bin_rrot<"uxtab",
902 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
903 defm UXTAH : AI_bin_rrot<"uxtah",
904 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
907 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
908 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
910 // TODO: UXT(A){B|H}16
912 //===----------------------------------------------------------------------===//
913 // Arithmetic Instructions.
916 defm ADD : AI1_bin_irs<"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
917 defm SUB : AI1_bin_irs<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
919 // ADD and SUB with 's' bit set.
920 let clobbersPred = 1 in {
921 defm ADDS : AI1_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
922 defm SUBS : AI1_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
925 // FIXME: Do not allow ADC / SBC to be predicated for now.
926 defm ADC : AXI1_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
927 defm SBC : AXI1_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
929 // These don't define reg/reg forms, because they are handled above.
930 defm RSB : AI1_bin_is <"rsb", BinOpFrag<(sub node:$RHS, node:$LHS)>>;
932 // RSB with 's' bit set.
933 let clobbersPred = 1 in {
934 def RSBSri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
935 "rsb", "s $dst, $a, $b",
936 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>, Imp<[], [CPSR]>;
937 def RSBSrs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
938 "rsb", "s $dst, $a, $b",
939 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>, Imp<[], [CPSR]>;
942 // FIXME: Do not allow RSC to be predicated for now.
943 def RSCri : AXI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
945 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>, Imp<[CPSR], []>;
946 def RSCrs : AXI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
948 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>, Imp<[CPSR], []>;
950 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
951 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
952 (SUBri GPR:$src, so_imm_neg:$imm)>;
954 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
955 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
956 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
957 // (SBCri GPR:$src, so_imm_neg:$imm)>;
959 // Note: These are implemented in C++ code, because they have to generate
960 // ADD/SUBrs instructions, which use a complex pattern that a xform function
962 // (mul X, 2^n+1) -> (add (X << n), X)
963 // (mul X, 2^n-1) -> (rsb X, (X << n))
966 //===----------------------------------------------------------------------===//
967 // Bitwise Instructions.
970 defm AND : AI1_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
971 defm ORR : AI1_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
972 defm EOR : AI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
973 defm BIC : AI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
975 def MVNr : AI<(ops GPR:$dst, GPR:$src),
976 "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
977 def MVNs : AI<(ops GPR:$dst, so_reg:$src),
978 "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
979 let isReMaterializable = 1 in
980 def MVNi : AI<(ops GPR:$dst, so_imm:$imm),
981 "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
983 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
984 (BICri GPR:$src, so_imm_not:$imm)>;
986 //===----------------------------------------------------------------------===//
987 // Multiply Instructions.
990 // AI_orr - Defines a (op r, r) pattern.
991 class AI_orr<string opc, SDNode opnode>
992 : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
993 opc, " $dst, $a, $b",
994 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
996 // AI_oorr - Defines a (op (op r, r), r) pattern.
997 class AI_oorr<string opc, SDNode opnode1, SDNode opnode2>
998 : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
999 opc, " $dst, $a, $b, $c",
1000 [(set GPR:$dst, (opnode1 (opnode2 GPR:$a, GPR:$b), GPR:$c))]>;
1002 def MUL : AI_orr<"mul", mul>;
1003 def MLA : AI_oorr<"mla", add, mul>;
1005 // Extra precision multiplies with low / high results
1006 def SMULL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
1007 "smull", " $ldst, $hdst, $a, $b",
1010 def UMULL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
1011 "umull", " $ldst, $hdst, $a, $b",
1014 // Multiply + accumulate
1015 def SMLAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
1016 "smlal", " $ldst, $hdst, $a, $b",
1019 def UMLAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
1020 "umlal", " $ldst, $hdst, $a, $b",
1023 def UMAAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
1024 "umaal", " $ldst, $hdst, $a, $b",
1025 []>, Requires<[IsARM, HasV6]>;
1027 // Most significant word multiply
1028 def SMMUL : AI_orr<"smmul", mulhs>, Requires<[IsARM, HasV6]>;
1029 def SMMLA : AI_oorr<"smmla", add, mulhs>, Requires<[IsARM, HasV6]>;
1032 def SMMLS : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
1033 "smmls", " $dst, $a, $b, $c",
1034 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1035 Requires<[IsARM, HasV6]>;
1037 multiclass AI_smul<string opc, PatFrag opnode> {
1038 def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
1039 !strconcat(opc, "bb"), " $dst, $a, $b",
1040 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1041 (sext_inreg GPR:$b, i16)))]>,
1042 Requires<[IsARM, HasV5TE]>;
1043 def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
1044 !strconcat(opc, "bt"), " $dst, $a, $b",
1045 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1046 (sra GPR:$b, 16)))]>,
1047 Requires<[IsARM, HasV5TE]>;
1048 def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
1049 !strconcat(opc, "tb"), " $dst, $a, $b",
1050 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1051 (sext_inreg GPR:$b, i16)))]>,
1052 Requires<[IsARM, HasV5TE]>;
1053 def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
1054 !strconcat(opc, "tt"), " $dst, $a, $b",
1055 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
1056 (sra GPR:$b, 16)))]>,
1057 Requires<[IsARM, HasV5TE]>;
1058 def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
1059 !strconcat(opc, "wb"), " $dst, $a, $b",
1060 [(set GPR:$dst, (sra (opnode GPR:$a,
1061 (sext_inreg GPR:$b, i16)), 16))]>,
1062 Requires<[IsARM, HasV5TE]>;
1063 def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
1064 !strconcat(opc, "wt"), " $dst, $a, $b",
1065 [(set GPR:$dst, (sra (opnode GPR:$a,
1066 (sra GPR:$b, 16)), 16))]>,
1067 Requires<[IsARM, HasV5TE]>;
1070 multiclass AI_smla<string opc, PatFrag opnode> {
1071 def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
1072 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1073 [(set GPR:$dst, (add GPR:$acc,
1074 (opnode (sext_inreg GPR:$a, i16),
1075 (sext_inreg GPR:$b, i16))))]>,
1076 Requires<[IsARM, HasV5TE]>;
1077 def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
1078 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1079 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1080 (sra GPR:$b, 16))))]>,
1081 Requires<[IsARM, HasV5TE]>;
1082 def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
1083 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1084 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1085 (sext_inreg GPR:$b, i16))))]>,
1086 Requires<[IsARM, HasV5TE]>;
1087 def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
1088 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1089 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
1090 (sra GPR:$b, 16))))]>,
1091 Requires<[IsARM, HasV5TE]>;
1093 def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
1094 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1095 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1096 (sext_inreg GPR:$b, i16)), 16)))]>,
1097 Requires<[IsARM, HasV5TE]>;
1098 def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
1099 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1100 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1101 (sra GPR:$b, 16)), 16)))]>,
1102 Requires<[IsARM, HasV5TE]>;
1105 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1106 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1108 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1109 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1111 //===----------------------------------------------------------------------===//
1112 // Misc. Arithmetic Instructions.
1115 def CLZ : AI<(ops GPR:$dst, GPR:$src),
1116 "clz", " $dst, $src",
1117 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
1119 def REV : AI<(ops GPR:$dst, GPR:$src),
1120 "rev", " $dst, $src",
1121 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
1123 def REV16 : AI<(ops GPR:$dst, GPR:$src),
1124 "rev16", " $dst, $src",
1126 (or (and (srl GPR:$src, 8), 0xFF),
1127 (or (and (shl GPR:$src, 8), 0xFF00),
1128 (or (and (srl GPR:$src, 8), 0xFF0000),
1129 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
1130 Requires<[IsARM, HasV6]>;
1132 def REVSH : AI<(ops GPR:$dst, GPR:$src),
1133 "revsh", " $dst, $src",
1136 (or (srl (and GPR:$src, 0xFF00), 8),
1137 (shl GPR:$src, 8)), i16))]>,
1138 Requires<[IsARM, HasV6]>;
1140 def PKHBT : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt),
1141 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1142 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1143 (and (shl GPR:$src2, (i32 imm:$shamt)),
1145 Requires<[IsARM, HasV6]>;
1147 // Alternate cases for PKHBT where identities eliminate some nodes.
1148 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1149 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1150 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1151 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1154 def PKHTB : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt),
1155 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1156 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1157 (and (sra GPR:$src2, imm16_31:$shamt),
1158 0xFFFF)))]>, Requires<[IsARM, HasV6]>;
1160 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1161 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1162 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)),
1163 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1164 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1165 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1166 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1169 //===----------------------------------------------------------------------===//
1170 // Comparison Instructions...
1173 let clobbersPred = 1 in {
1174 defm CMP : AI1_cmp_irs<"cmp", BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1175 defm CMN : AI1_cmp_irs<"cmn", BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1177 // Note that TST/TEQ don't set all the same flags that CMP does!
1178 defm TST : AI1_cmp_irs<"tst", BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
1179 defm TEQ : AI1_cmp_irs<"teq", BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
1181 defm CMPnz : AI1_cmp_irs<"cmp", BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
1182 defm CMNnz : AI1_cmp_irs<"cmn", BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
1185 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1186 (CMNri GPR:$src, so_imm_neg:$imm)>;
1188 def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1189 (CMNri GPR:$src, so_imm_neg:$imm)>;
1192 // Conditional moves
1193 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1194 // a two-value operand where a dag node expects two operands. :(
1195 def MOVCCr : AXI<(ops GPR:$dst, GPR:$false, GPR:$true, ccop:$cc),
1196 "mov$cc $dst, $true",
1197 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1198 RegConstraint<"$false = $dst">;
1200 def MOVCCs : AXI<(ops GPR:$dst, GPR:$false, so_reg:$true, ccop:$cc),
1201 "mov$cc $dst, $true",
1202 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1203 RegConstraint<"$false = $dst">;
1205 def MOVCCi : AXI<(ops GPR:$dst, GPR:$false, so_imm:$true, ccop:$cc),
1206 "mov$cc $dst, $true",
1207 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1208 RegConstraint<"$false = $dst">;
1211 // LEApcrel - Load a pc-relative address into a register without offending the
1213 def LEApcrel : AXI1<(ops GPR:$dst, i32imm:$label, pred:$p),
1214 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
1215 "${:private}PCRELL${:uid}+8))\n"),
1216 !strconcat("${:private}PCRELL${:uid}:\n\t",
1217 "add$p $dst, pc, #PCRELV${:uid}")),
1220 def LEApcrelJT : AXI1<(ops GPR:$dst, i32imm:$label, i32imm:$id, pred:$p),
1221 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
1222 "${:private}PCRELL${:uid}+8))\n"),
1223 !strconcat("${:private}PCRELL${:uid}:\n\t",
1224 "add$p $dst, pc, #PCRELV${:uid}")),
1227 //===----------------------------------------------------------------------===//
1231 // __aeabi_read_tp preserves the registers r1-r3.
1232 let isCall = 1, clobbersPred = 1,
1233 Defs = [R0, R12, LR] in {
1234 def TPsoft : AXI<(ops),
1235 "bl __aeabi_read_tp",
1236 [(set R0, ARMthread_pointer)]>;
1239 //===----------------------------------------------------------------------===//
1240 // Non-Instruction Patterns
1243 // ConstantPool, GlobalAddress, and JumpTable
1244 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1245 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1246 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1247 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1249 // Large immediate handling.
1251 // Two piece so_imms.
1252 let isReMaterializable = 1 in
1253 def MOVi2pieces : AI1x2<(ops GPR:$dst, so_imm2part:$src),
1254 "mov", " $dst, $src",
1255 [(set GPR:$dst, so_imm2part:$src)]>;
1257 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1258 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1259 (so_imm2part_2 imm:$RHS))>;
1260 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1261 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1262 (so_imm2part_2 imm:$RHS))>;
1264 // TODO: add,sub,and, 3-instr forms?
1268 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
1270 // zextload i1 -> zextload i8
1271 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1273 // extload -> zextload
1274 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1275 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1276 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1278 // truncstore i1 -> truncstore i8
1279 def : ARMPat<(truncstorei1 GPR:$src, addrmode2:$dst),
1280 (STRB GPR:$src, addrmode2:$dst)>;
1281 def : ARMPat<(pre_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
1282 (STRB_PRE GPR:$src, GPR:$base, am2offset:$offset)>;
1283 def : ARMPat<(post_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
1284 (STRB_POST GPR:$src, GPR:$base, am2offset:$offset)>;
1287 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
1288 (SMULBB GPR:$a, GPR:$b)>;
1289 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1290 (SMULBB GPR:$a, GPR:$b)>;
1291 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)),
1292 (SMULBT GPR:$a, GPR:$b)>;
1293 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)),
1294 (SMULBT GPR:$a, GPR:$b)>;
1295 def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)),
1296 (SMULTB GPR:$a, GPR:$b)>;
1297 def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b),
1298 (SMULTB GPR:$a, GPR:$b)>;
1299 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16),
1300 (SMULWB GPR:$a, GPR:$b)>;
1301 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16),
1302 (SMULWB GPR:$a, GPR:$b)>;
1304 def : ARMV5TEPat<(add GPR:$acc,
1305 (mul (sra (shl GPR:$a, 16), 16),
1306 (sra (shl GPR:$b, 16), 16))),
1307 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1308 def : ARMV5TEPat<(add GPR:$acc,
1309 (mul sext_16_node:$a, sext_16_node:$b)),
1310 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1311 def : ARMV5TEPat<(add GPR:$acc,
1312 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))),
1313 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1314 def : ARMV5TEPat<(add GPR:$acc,
1315 (mul sext_16_node:$a, (sra GPR:$b, 16))),
1316 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1317 def : ARMV5TEPat<(add GPR:$acc,
1318 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))),
1319 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1320 def : ARMV5TEPat<(add GPR:$acc,
1321 (mul (sra GPR:$a, 16), sext_16_node:$b)),
1322 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1323 def : ARMV5TEPat<(add GPR:$acc,
1324 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)),
1325 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1326 def : ARMV5TEPat<(add GPR:$acc,
1327 (sra (mul GPR:$a, sext_16_node:$b), 16)),
1328 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1330 //===----------------------------------------------------------------------===//
1334 include "ARMInstrThumb.td"
1336 //===----------------------------------------------------------------------===//
1337 // Floating Point Support
1340 include "ARMInstrVFP.td"