1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
75 def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
77 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
80 SDTCisInt<0>, SDTCisVT<1, i32>]>;
82 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
83 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
90 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
91 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
92 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
93 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
94 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
97 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
98 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
99 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
100 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
102 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
103 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
104 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
105 [SDNPHasChain, SDNPSideEffect,
106 SDNPOptInGlue, SDNPOutGlue]>;
107 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
109 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
110 SDNPMayStore, SDNPMayLoad]>;
112 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
115 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
118 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
119 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
122 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
123 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
125 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
128 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
129 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
131 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
133 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
136 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
139 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
142 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
145 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
146 [SDNPOutGlue, SDNPCommutative]>;
148 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
150 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
151 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
152 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
154 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
156 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
157 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
158 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
160 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
161 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
162 SDT_ARMEH_SJLJ_Setjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
164 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
165 SDT_ARMEH_SJLJ_Longjmp,
166 [SDNPHasChain, SDNPSideEffect]>;
168 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
169 [SDNPHasChain, SDNPSideEffect]>;
170 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
171 [SDNPHasChain, SDNPSideEffect]>;
172 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
173 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
175 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
177 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
178 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
180 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
182 def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
183 def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
185 //===----------------------------------------------------------------------===//
186 // ARM Instruction Predicate Definitions.
188 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
189 AssemblerPredicate<"HasV4TOps", "armv4t">;
190 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
191 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
192 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
193 AssemblerPredicate<"HasV5TEOps", "armv5te">;
194 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
195 AssemblerPredicate<"HasV6Ops", "armv6">;
196 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
197 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
198 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
199 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
200 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
201 AssemblerPredicate<"HasV7Ops", "armv7">;
202 def HasV8 : Predicate<"Subtarget->hasV8Ops()">,
203 AssemblerPredicate<"HasV8Ops", "armv8">;
204 def PreV8 : Predicate<"!Subtarget->hasV8Ops()">,
205 AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">;
206 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
207 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
208 AssemblerPredicate<"FeatureVFP2", "VFP2">;
209 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
210 AssemblerPredicate<"FeatureVFP3", "VFP3">;
211 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
212 AssemblerPredicate<"FeatureVFP4", "VFP4">;
213 def HasV8FP : Predicate<"Subtarget->hasV8FP()">,
214 AssemblerPredicate<"FeatureV8FP", "V8FP">;
215 def HasNEON : Predicate<"Subtarget->hasNEON()">,
216 AssemblerPredicate<"FeatureNEON", "NEON">;
217 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
218 AssemblerPredicate<"FeatureFP16","half-float">;
219 def HasDivide : Predicate<"Subtarget->hasDivide()">,
220 AssemblerPredicate<"FeatureHWDiv", "divide">;
221 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
222 AssemblerPredicate<"FeatureHWDivARM">;
223 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
224 AssemblerPredicate<"FeatureT2XtPk",
226 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
227 AssemblerPredicate<"FeatureDSPThumb2",
229 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
230 AssemblerPredicate<"FeatureDB",
232 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
233 AssemblerPredicate<"FeatureMP",
235 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
236 AssemblerPredicate<"FeatureTrustZone",
238 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
239 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
240 def IsThumb : Predicate<"Subtarget->isThumb()">,
241 AssemblerPredicate<"ModeThumb", "thumb">;
242 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
243 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
244 AssemblerPredicate<"ModeThumb,FeatureThumb2",
246 def IsMClass : Predicate<"Subtarget->isMClass()">,
247 AssemblerPredicate<"FeatureMClass", "armv7m">;
248 def IsARClass : Predicate<"!Subtarget->isMClass()">,
249 AssemblerPredicate<"!FeatureMClass",
251 def IsARM : Predicate<"!Subtarget->isThumb()">,
252 AssemblerPredicate<"!ModeThumb", "arm-mode">;
253 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
254 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
255 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
256 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
257 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
258 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
260 // FIXME: Eventually this will be just "hasV6T2Ops".
261 def UseMovt : Predicate<"Subtarget->useMovt()">;
262 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
263 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
264 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
266 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
267 // But only select them if more precision in FP computation is allowed.
268 // Do not use them for Darwin platforms.
269 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
270 " FPOpFusion::Fast) && "
271 "!Subtarget->isTargetDarwin()">;
272 def DontUseFusedMAC : Predicate<"!(TM.Options.AllowFPOpFusion =="
273 " FPOpFusion::Fast &&"
274 " Subtarget->hasVFP4()) || "
275 "Subtarget->isTargetDarwin()">;
277 // VGETLNi32 is microcoded on Swift - prefer VMOV.
278 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
279 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
281 // VDUP.32 is microcoded on Swift - prefer VMOV.
282 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
283 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
285 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
286 // this allows more effective execution domain optimization. See
287 // setExecutionDomain().
288 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
289 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
291 def IsLE : Predicate<"getTargetLowering()->isLittleEndian()">;
292 def IsBE : Predicate<"getTargetLowering()->isBigEndian()">;
294 //===----------------------------------------------------------------------===//
295 // ARM Flag Definitions.
297 class RegConstraint<string C> {
298 string Constraints = C;
301 //===----------------------------------------------------------------------===//
302 // ARM specific transformation functions and pattern fragments.
305 // imm_neg_XFORM - Return the negation of an i32 immediate value.
306 def imm_neg_XFORM : SDNodeXForm<imm, [{
307 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
310 // imm_not_XFORM - Return the complement of a i32 immediate value.
311 def imm_not_XFORM : SDNodeXForm<imm, [{
312 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
315 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
316 def imm16_31 : ImmLeaf<i32, [{
317 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
320 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
321 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
322 unsigned Value = -(unsigned)N->getZExtValue();
323 return Value && ARM_AM::getSOImmVal(Value) != -1;
325 let ParserMatchClass = so_imm_neg_asmoperand;
328 // Note: this pattern doesn't require an encoder method and such, as it's
329 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
330 // is handled by the destination instructions, which use so_imm.
331 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
332 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
333 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
335 let ParserMatchClass = so_imm_not_asmoperand;
338 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
339 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
340 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
343 /// Split a 32-bit immediate into two 16 bit parts.
344 def hi16 : SDNodeXForm<imm, [{
345 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
348 def lo16AllZero : PatLeaf<(i32 imm), [{
349 // Returns true if all low 16-bits are 0.
350 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
353 class BinOpWithFlagFrag<dag res> :
354 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
355 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
356 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
358 // An 'and' node with a single use.
359 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
360 return N->hasOneUse();
363 // An 'xor' node with a single use.
364 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
365 return N->hasOneUse();
368 // An 'fmul' node with a single use.
369 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
370 return N->hasOneUse();
373 // An 'fadd' node which checks for single non-hazardous use.
374 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
375 return hasNoVMLxHazardUse(N);
378 // An 'fsub' node which checks for single non-hazardous use.
379 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
380 return hasNoVMLxHazardUse(N);
383 //===----------------------------------------------------------------------===//
384 // Operand Definitions.
387 // Immediate operands with a shared generic asm render method.
388 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
391 // FIXME: rename brtarget to t2_brtarget
392 def brtarget : Operand<OtherVT> {
393 let EncoderMethod = "getBranchTargetOpValue";
394 let OperandType = "OPERAND_PCREL";
395 let DecoderMethod = "DecodeT2BROperand";
398 // FIXME: get rid of this one?
399 def uncondbrtarget : Operand<OtherVT> {
400 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
401 let OperandType = "OPERAND_PCREL";
404 // Branch target for ARM. Handles conditional/unconditional
405 def br_target : Operand<OtherVT> {
406 let EncoderMethod = "getARMBranchTargetOpValue";
407 let OperandType = "OPERAND_PCREL";
411 // FIXME: rename bltarget to t2_bl_target?
412 def bltarget : Operand<i32> {
413 // Encoded the same as branch targets.
414 let EncoderMethod = "getBranchTargetOpValue";
415 let OperandType = "OPERAND_PCREL";
418 // Call target for ARM. Handles conditional/unconditional
419 // FIXME: rename bl_target to t2_bltarget?
420 def bl_target : Operand<i32> {
421 let EncoderMethod = "getARMBLTargetOpValue";
422 let OperandType = "OPERAND_PCREL";
425 def blx_target : Operand<i32> {
426 let EncoderMethod = "getARMBLXTargetOpValue";
427 let OperandType = "OPERAND_PCREL";
430 // A list of registers separated by comma. Used by load/store multiple.
431 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
432 def reglist : Operand<i32> {
433 let EncoderMethod = "getRegisterListOpValue";
434 let ParserMatchClass = RegListAsmOperand;
435 let PrintMethod = "printRegisterList";
436 let DecoderMethod = "DecodeRegListOperand";
439 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
441 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
442 def dpr_reglist : Operand<i32> {
443 let EncoderMethod = "getRegisterListOpValue";
444 let ParserMatchClass = DPRRegListAsmOperand;
445 let PrintMethod = "printRegisterList";
446 let DecoderMethod = "DecodeDPRRegListOperand";
449 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
450 def spr_reglist : Operand<i32> {
451 let EncoderMethod = "getRegisterListOpValue";
452 let ParserMatchClass = SPRRegListAsmOperand;
453 let PrintMethod = "printRegisterList";
454 let DecoderMethod = "DecodeSPRRegListOperand";
457 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
458 def cpinst_operand : Operand<i32> {
459 let PrintMethod = "printCPInstOperand";
463 def pclabel : Operand<i32> {
464 let PrintMethod = "printPCLabel";
467 // ADR instruction labels.
468 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
469 def adrlabel : Operand<i32> {
470 let EncoderMethod = "getAdrLabelOpValue";
471 let ParserMatchClass = AdrLabelAsmOperand;
472 let PrintMethod = "printAdrLabelOperand<0>";
475 def neon_vcvt_imm32 : Operand<i32> {
476 let EncoderMethod = "getNEONVcvtImm32OpValue";
477 let DecoderMethod = "DecodeVCVTImmOperand";
480 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
481 def rot_imm_XFORM: SDNodeXForm<imm, [{
482 switch (N->getZExtValue()){
484 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
485 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
486 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
487 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
490 def RotImmAsmOperand : AsmOperandClass {
492 let ParserMethod = "parseRotImm";
494 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
495 int32_t v = N->getZExtValue();
496 return v == 8 || v == 16 || v == 24; }],
498 let PrintMethod = "printRotImmOperand";
499 let ParserMatchClass = RotImmAsmOperand;
502 // shift_imm: An integer that encodes a shift amount and the type of shift
503 // (asr or lsl). The 6-bit immediate encodes as:
506 // {4-0} imm5 shift amount.
507 // asr #32 encoded as imm5 == 0.
508 def ShifterImmAsmOperand : AsmOperandClass {
509 let Name = "ShifterImm";
510 let ParserMethod = "parseShifterImm";
512 def shift_imm : Operand<i32> {
513 let PrintMethod = "printShiftImmOperand";
514 let ParserMatchClass = ShifterImmAsmOperand;
517 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
518 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
519 def so_reg_reg : Operand<i32>, // reg reg imm
520 ComplexPattern<i32, 3, "SelectRegShifterOperand",
521 [shl, srl, sra, rotr]> {
522 let EncoderMethod = "getSORegRegOpValue";
523 let PrintMethod = "printSORegRegOperand";
524 let DecoderMethod = "DecodeSORegRegOperand";
525 let ParserMatchClass = ShiftedRegAsmOperand;
526 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
529 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
530 def so_reg_imm : Operand<i32>, // reg imm
531 ComplexPattern<i32, 2, "SelectImmShifterOperand",
532 [shl, srl, sra, rotr]> {
533 let EncoderMethod = "getSORegImmOpValue";
534 let PrintMethod = "printSORegImmOperand";
535 let DecoderMethod = "DecodeSORegImmOperand";
536 let ParserMatchClass = ShiftedImmAsmOperand;
537 let MIOperandInfo = (ops GPR, i32imm);
540 // FIXME: Does this need to be distinct from so_reg?
541 def shift_so_reg_reg : Operand<i32>, // reg reg imm
542 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
543 [shl,srl,sra,rotr]> {
544 let EncoderMethod = "getSORegRegOpValue";
545 let PrintMethod = "printSORegRegOperand";
546 let DecoderMethod = "DecodeSORegRegOperand";
547 let ParserMatchClass = ShiftedRegAsmOperand;
548 let MIOperandInfo = (ops GPR, GPR, i32imm);
551 // FIXME: Does this need to be distinct from so_reg?
552 def shift_so_reg_imm : Operand<i32>, // reg reg imm
553 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
554 [shl,srl,sra,rotr]> {
555 let EncoderMethod = "getSORegImmOpValue";
556 let PrintMethod = "printSORegImmOperand";
557 let DecoderMethod = "DecodeSORegImmOperand";
558 let ParserMatchClass = ShiftedImmAsmOperand;
559 let MIOperandInfo = (ops GPR, i32imm);
563 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
564 // 8-bit immediate rotated by an arbitrary number of bits.
565 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
566 def so_imm : Operand<i32>, ImmLeaf<i32, [{
567 return ARM_AM::getSOImmVal(Imm) != -1;
569 let EncoderMethod = "getSOImmOpValue";
570 let ParserMatchClass = SOImmAsmOperand;
571 let DecoderMethod = "DecodeSOImmOperand";
574 // Break so_imm's up into two pieces. This handles immediates with up to 16
575 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
576 // get the first/second pieces.
577 def so_imm2part : PatLeaf<(imm), [{
578 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
581 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
583 def arm_i32imm : PatLeaf<(imm), [{
584 if (Subtarget->hasV6T2Ops())
586 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
589 /// imm0_1 predicate - Immediate in the range [0,1].
590 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
591 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
593 /// imm0_3 predicate - Immediate in the range [0,3].
594 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
595 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
597 /// imm0_4 predicate - Immediate in the range [0,4].
598 def Imm0_4AsmOperand : ImmAsmOperand
601 let DiagnosticType = "ImmRange0_4";
603 def imm0_4 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 5; }]> {
604 let ParserMatchClass = Imm0_4AsmOperand;
605 let DecoderMethod = "DecodeImm0_4";
608 /// imm0_7 predicate - Immediate in the range [0,7].
609 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
610 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
611 return Imm >= 0 && Imm < 8;
613 let ParserMatchClass = Imm0_7AsmOperand;
616 /// imm8 predicate - Immediate is exactly 8.
617 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
618 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
619 let ParserMatchClass = Imm8AsmOperand;
622 /// imm16 predicate - Immediate is exactly 16.
623 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
624 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
625 let ParserMatchClass = Imm16AsmOperand;
628 /// imm32 predicate - Immediate is exactly 32.
629 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
630 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
631 let ParserMatchClass = Imm32AsmOperand;
634 /// imm1_7 predicate - Immediate in the range [1,7].
635 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
636 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
637 let ParserMatchClass = Imm1_7AsmOperand;
640 /// imm1_15 predicate - Immediate in the range [1,15].
641 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
642 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
643 let ParserMatchClass = Imm1_15AsmOperand;
646 /// imm1_31 predicate - Immediate in the range [1,31].
647 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
648 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
649 let ParserMatchClass = Imm1_31AsmOperand;
652 /// imm0_15 predicate - Immediate in the range [0,15].
653 def Imm0_15AsmOperand: ImmAsmOperand {
654 let Name = "Imm0_15";
655 let DiagnosticType = "ImmRange0_15";
657 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
658 return Imm >= 0 && Imm < 16;
660 let ParserMatchClass = Imm0_15AsmOperand;
663 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
664 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
665 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
666 return Imm >= 0 && Imm < 32;
668 let ParserMatchClass = Imm0_31AsmOperand;
671 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
672 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
673 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
674 return Imm >= 0 && Imm < 32;
676 let ParserMatchClass = Imm0_32AsmOperand;
679 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
680 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
681 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
682 return Imm >= 0 && Imm < 64;
684 let ParserMatchClass = Imm0_63AsmOperand;
687 /// imm0_255 predicate - Immediate in the range [0,255].
688 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
689 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
690 let ParserMatchClass = Imm0_255AsmOperand;
693 /// imm0_65535 - An immediate is in the range [0.65535].
694 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
695 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
696 return Imm >= 0 && Imm < 65536;
698 let ParserMatchClass = Imm0_65535AsmOperand;
701 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
702 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
703 return -Imm >= 0 && -Imm < 65536;
706 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
707 // a relocatable expression.
709 // FIXME: This really needs a Thumb version separate from the ARM version.
710 // While the range is the same, and can thus use the same match class,
711 // the encoding is different so it should have a different encoder method.
712 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
713 def imm0_65535_expr : Operand<i32> {
714 let EncoderMethod = "getHiLo16ImmOpValue";
715 let ParserMatchClass = Imm0_65535ExprAsmOperand;
718 def Imm256_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm256_65535Expr"; }
719 def imm256_65535_expr : Operand<i32> {
720 let ParserMatchClass = Imm256_65535ExprAsmOperand;
723 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
724 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
725 def imm24b : Operand<i32>, ImmLeaf<i32, [{
726 return Imm >= 0 && Imm <= 0xffffff;
728 let ParserMatchClass = Imm24bitAsmOperand;
732 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
734 def BitfieldAsmOperand : AsmOperandClass {
735 let Name = "Bitfield";
736 let ParserMethod = "parseBitfield";
739 def bf_inv_mask_imm : Operand<i32>,
741 return ARM::isBitFieldInvertedMask(N->getZExtValue());
743 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
744 let PrintMethod = "printBitfieldInvMaskImmOperand";
745 let DecoderMethod = "DecodeBitfieldMaskOperand";
746 let ParserMatchClass = BitfieldAsmOperand;
749 def imm1_32_XFORM: SDNodeXForm<imm, [{
750 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
752 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
753 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
754 uint64_t Imm = N->getZExtValue();
755 return Imm > 0 && Imm <= 32;
758 let PrintMethod = "printImmPlusOneOperand";
759 let ParserMatchClass = Imm1_32AsmOperand;
762 def imm1_16_XFORM: SDNodeXForm<imm, [{
763 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
765 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
766 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
768 let PrintMethod = "printImmPlusOneOperand";
769 let ParserMatchClass = Imm1_16AsmOperand;
772 // Define ARM specific addressing modes.
773 // addrmode_imm12 := reg +/- imm12
775 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
776 class AddrMode_Imm12 : Operand<i32>,
777 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
778 // 12-bit immediate operand. Note that instructions using this encode
779 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
780 // immediate values are as normal.
782 let EncoderMethod = "getAddrModeImm12OpValue";
783 let DecoderMethod = "DecodeAddrModeImm12Operand";
784 let ParserMatchClass = MemImm12OffsetAsmOperand;
785 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
788 def addrmode_imm12 : AddrMode_Imm12 {
789 let PrintMethod = "printAddrModeImm12Operand<false>";
792 def addrmode_imm12_pre : AddrMode_Imm12 {
793 let PrintMethod = "printAddrModeImm12Operand<true>";
796 // ldst_so_reg := reg +/- reg shop imm
798 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
799 def ldst_so_reg : Operand<i32>,
800 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
801 let EncoderMethod = "getLdStSORegOpValue";
802 // FIXME: Simplify the printer
803 let PrintMethod = "printAddrMode2Operand";
804 let DecoderMethod = "DecodeSORegMemOperand";
805 let ParserMatchClass = MemRegOffsetAsmOperand;
806 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
809 // postidx_imm8 := +/- [0,255]
812 // {8} 1 is imm8 is non-negative. 0 otherwise.
813 // {7-0} [0,255] imm8 value.
814 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
815 def postidx_imm8 : Operand<i32> {
816 let PrintMethod = "printPostIdxImm8Operand";
817 let ParserMatchClass = PostIdxImm8AsmOperand;
818 let MIOperandInfo = (ops i32imm);
821 // postidx_imm8s4 := +/- [0,1020]
824 // {8} 1 is imm8 is non-negative. 0 otherwise.
825 // {7-0} [0,255] imm8 value, scaled by 4.
826 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
827 def postidx_imm8s4 : Operand<i32> {
828 let PrintMethod = "printPostIdxImm8s4Operand";
829 let ParserMatchClass = PostIdxImm8s4AsmOperand;
830 let MIOperandInfo = (ops i32imm);
834 // postidx_reg := +/- reg
836 def PostIdxRegAsmOperand : AsmOperandClass {
837 let Name = "PostIdxReg";
838 let ParserMethod = "parsePostIdxReg";
840 def postidx_reg : Operand<i32> {
841 let EncoderMethod = "getPostIdxRegOpValue";
842 let DecoderMethod = "DecodePostIdxReg";
843 let PrintMethod = "printPostIdxRegOperand";
844 let ParserMatchClass = PostIdxRegAsmOperand;
845 let MIOperandInfo = (ops GPRnopc, i32imm);
849 // addrmode2 := reg +/- imm12
850 // := reg +/- reg shop imm
852 // FIXME: addrmode2 should be refactored the rest of the way to always
853 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
854 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
855 def addrmode2 : Operand<i32>,
856 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
857 let EncoderMethod = "getAddrMode2OpValue";
858 let PrintMethod = "printAddrMode2Operand";
859 let ParserMatchClass = AddrMode2AsmOperand;
860 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
863 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
864 let Name = "PostIdxRegShifted";
865 let ParserMethod = "parsePostIdxReg";
867 def am2offset_reg : Operand<i32>,
868 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
869 [], [SDNPWantRoot]> {
870 let EncoderMethod = "getAddrMode2OffsetOpValue";
871 let PrintMethod = "printAddrMode2OffsetOperand";
872 // When using this for assembly, it's always as a post-index offset.
873 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
874 let MIOperandInfo = (ops GPRnopc, i32imm);
877 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
878 // the GPR is purely vestigal at this point.
879 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
880 def am2offset_imm : Operand<i32>,
881 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
882 [], [SDNPWantRoot]> {
883 let EncoderMethod = "getAddrMode2OffsetOpValue";
884 let PrintMethod = "printAddrMode2OffsetOperand";
885 let ParserMatchClass = AM2OffsetImmAsmOperand;
886 let MIOperandInfo = (ops GPRnopc, i32imm);
890 // addrmode3 := reg +/- reg
891 // addrmode3 := reg +/- imm8
893 // FIXME: split into imm vs. reg versions.
894 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
895 class AddrMode3 : Operand<i32>,
896 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
897 let EncoderMethod = "getAddrMode3OpValue";
898 let ParserMatchClass = AddrMode3AsmOperand;
899 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
902 def addrmode3 : AddrMode3
904 let PrintMethod = "printAddrMode3Operand<false>";
907 def addrmode3_pre : AddrMode3
909 let PrintMethod = "printAddrMode3Operand<true>";
912 // FIXME: split into imm vs. reg versions.
913 // FIXME: parser method to handle +/- register.
914 def AM3OffsetAsmOperand : AsmOperandClass {
915 let Name = "AM3Offset";
916 let ParserMethod = "parseAM3Offset";
918 def am3offset : Operand<i32>,
919 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
920 [], [SDNPWantRoot]> {
921 let EncoderMethod = "getAddrMode3OffsetOpValue";
922 let PrintMethod = "printAddrMode3OffsetOperand";
923 let ParserMatchClass = AM3OffsetAsmOperand;
924 let MIOperandInfo = (ops GPR, i32imm);
927 // ldstm_mode := {ia, ib, da, db}
929 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
930 let EncoderMethod = "getLdStmModeOpValue";
931 let PrintMethod = "printLdStmModeOperand";
934 // addrmode5 := reg +/- imm8*4
936 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
937 class AddrMode5 : Operand<i32>,
938 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
939 let EncoderMethod = "getAddrMode5OpValue";
940 let DecoderMethod = "DecodeAddrMode5Operand";
941 let ParserMatchClass = AddrMode5AsmOperand;
942 let MIOperandInfo = (ops GPR:$base, i32imm);
945 def addrmode5 : AddrMode5 {
946 let PrintMethod = "printAddrMode5Operand<false>";
949 def addrmode5_pre : AddrMode5 {
950 let PrintMethod = "printAddrMode5Operand<true>";
953 // addrmode6 := reg with optional alignment
955 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
956 def addrmode6 : Operand<i32>,
957 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
958 let PrintMethod = "printAddrMode6Operand";
959 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
960 let EncoderMethod = "getAddrMode6AddressOpValue";
961 let DecoderMethod = "DecodeAddrMode6Operand";
962 let ParserMatchClass = AddrMode6AsmOperand;
965 def am6offset : Operand<i32>,
966 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
967 [], [SDNPWantRoot]> {
968 let PrintMethod = "printAddrMode6OffsetOperand";
969 let MIOperandInfo = (ops GPR);
970 let EncoderMethod = "getAddrMode6OffsetOpValue";
971 let DecoderMethod = "DecodeGPRRegisterClass";
974 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
975 // (single element from one lane) for size 32.
976 def addrmode6oneL32 : Operand<i32>,
977 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
978 let PrintMethod = "printAddrMode6Operand";
979 let MIOperandInfo = (ops GPR:$addr, i32imm);
980 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
983 // Special version of addrmode6 to handle alignment encoding for VLD-dup
984 // instructions, specifically VLD4-dup.
985 def addrmode6dup : Operand<i32>,
986 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
987 let PrintMethod = "printAddrMode6Operand";
988 let MIOperandInfo = (ops GPR:$addr, i32imm);
989 let EncoderMethod = "getAddrMode6DupAddressOpValue";
990 // FIXME: This is close, but not quite right. The alignment specifier is
992 let ParserMatchClass = AddrMode6AsmOperand;
995 // addrmodepc := pc + reg
997 def addrmodepc : Operand<i32>,
998 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
999 let PrintMethod = "printAddrModePCOperand";
1000 let MIOperandInfo = (ops GPR, i32imm);
1003 // addr_offset_none := reg
1005 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
1006 def addr_offset_none : Operand<i32>,
1007 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
1008 let PrintMethod = "printAddrMode7Operand";
1009 let DecoderMethod = "DecodeAddrMode7Operand";
1010 let ParserMatchClass = MemNoOffsetAsmOperand;
1011 let MIOperandInfo = (ops GPR:$base);
1014 def nohash_imm : Operand<i32> {
1015 let PrintMethod = "printNoHashImmediate";
1018 def CoprocNumAsmOperand : AsmOperandClass {
1019 let Name = "CoprocNum";
1020 let ParserMethod = "parseCoprocNumOperand";
1022 def p_imm : Operand<i32> {
1023 let PrintMethod = "printPImmediate";
1024 let ParserMatchClass = CoprocNumAsmOperand;
1025 let DecoderMethod = "DecodeCoprocessor";
1028 def CoprocRegAsmOperand : AsmOperandClass {
1029 let Name = "CoprocReg";
1030 let ParserMethod = "parseCoprocRegOperand";
1032 def c_imm : Operand<i32> {
1033 let PrintMethod = "printCImmediate";
1034 let ParserMatchClass = CoprocRegAsmOperand;
1036 def CoprocOptionAsmOperand : AsmOperandClass {
1037 let Name = "CoprocOption";
1038 let ParserMethod = "parseCoprocOptionOperand";
1040 def coproc_option_imm : Operand<i32> {
1041 let PrintMethod = "printCoprocOptionImm";
1042 let ParserMatchClass = CoprocOptionAsmOperand;
1045 //===----------------------------------------------------------------------===//
1047 include "ARMInstrFormats.td"
1049 //===----------------------------------------------------------------------===//
1050 // Multiclass helpers...
1053 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1054 /// binop that produces a value.
1055 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1056 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1057 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1058 PatFrag opnode, bit Commutable = 0> {
1059 // The register-immediate version is re-materializable. This is useful
1060 // in particular for taking the address of a local.
1061 let isReMaterializable = 1 in {
1062 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1063 iii, opc, "\t$Rd, $Rn, $imm",
1064 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1065 Sched<[WriteALU, ReadALU]> {
1070 let Inst{19-16} = Rn;
1071 let Inst{15-12} = Rd;
1072 let Inst{11-0} = imm;
1075 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1076 iir, opc, "\t$Rd, $Rn, $Rm",
1077 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1078 Sched<[WriteALU, ReadALU, ReadALU]> {
1083 let isCommutable = Commutable;
1084 let Inst{19-16} = Rn;
1085 let Inst{15-12} = Rd;
1086 let Inst{11-4} = 0b00000000;
1090 def rsi : AsI1<opcod, (outs GPR:$Rd),
1091 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1092 iis, opc, "\t$Rd, $Rn, $shift",
1093 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1094 Sched<[WriteALUsi, ReadALU]> {
1099 let Inst{19-16} = Rn;
1100 let Inst{15-12} = Rd;
1101 let Inst{11-5} = shift{11-5};
1103 let Inst{3-0} = shift{3-0};
1106 def rsr : AsI1<opcod, (outs GPR:$Rd),
1107 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1108 iis, opc, "\t$Rd, $Rn, $shift",
1109 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1110 Sched<[WriteALUsr, ReadALUsr]> {
1115 let Inst{19-16} = Rn;
1116 let Inst{15-12} = Rd;
1117 let Inst{11-8} = shift{11-8};
1119 let Inst{6-5} = shift{6-5};
1121 let Inst{3-0} = shift{3-0};
1125 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1126 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1127 /// it is equivalent to the AsI1_bin_irs counterpart.
1128 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1129 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1130 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1131 PatFrag opnode, bit Commutable = 0> {
1132 // The register-immediate version is re-materializable. This is useful
1133 // in particular for taking the address of a local.
1134 let isReMaterializable = 1 in {
1135 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1136 iii, opc, "\t$Rd, $Rn, $imm",
1137 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1138 Sched<[WriteALU, ReadALU]> {
1143 let Inst{19-16} = Rn;
1144 let Inst{15-12} = Rd;
1145 let Inst{11-0} = imm;
1148 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1149 iir, opc, "\t$Rd, $Rn, $Rm",
1150 [/* pattern left blank */]>,
1151 Sched<[WriteALU, ReadALU, ReadALU]> {
1155 let Inst{11-4} = 0b00000000;
1158 let Inst{15-12} = Rd;
1159 let Inst{19-16} = Rn;
1162 def rsi : AsI1<opcod, (outs GPR:$Rd),
1163 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1164 iis, opc, "\t$Rd, $Rn, $shift",
1165 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1166 Sched<[WriteALUsi, ReadALU]> {
1171 let Inst{19-16} = Rn;
1172 let Inst{15-12} = Rd;
1173 let Inst{11-5} = shift{11-5};
1175 let Inst{3-0} = shift{3-0};
1178 def rsr : AsI1<opcod, (outs GPR:$Rd),
1179 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1180 iis, opc, "\t$Rd, $Rn, $shift",
1181 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1182 Sched<[WriteALUsr, ReadALUsr]> {
1187 let Inst{19-16} = Rn;
1188 let Inst{15-12} = Rd;
1189 let Inst{11-8} = shift{11-8};
1191 let Inst{6-5} = shift{6-5};
1193 let Inst{3-0} = shift{3-0};
1197 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1199 /// These opcodes will be converted to the real non-S opcodes by
1200 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1201 let hasPostISelHook = 1, Defs = [CPSR] in {
1202 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1203 InstrItinClass iis, PatFrag opnode,
1204 bit Commutable = 0> {
1205 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1207 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1208 Sched<[WriteALU, ReadALU]>;
1210 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1212 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1213 Sched<[WriteALU, ReadALU, ReadALU]> {
1214 let isCommutable = Commutable;
1216 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1217 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1219 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1220 so_reg_imm:$shift))]>,
1221 Sched<[WriteALUsi, ReadALU]>;
1223 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1224 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1226 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1227 so_reg_reg:$shift))]>,
1228 Sched<[WriteALUSsr, ReadALUsr]>;
1232 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1233 /// operands are reversed.
1234 let hasPostISelHook = 1, Defs = [CPSR] in {
1235 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1236 InstrItinClass iis, PatFrag opnode,
1237 bit Commutable = 0> {
1238 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1240 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1241 Sched<[WriteALU, ReadALU]>;
1243 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1244 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1246 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1248 Sched<[WriteALUsi, ReadALU]>;
1250 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1251 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1253 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1255 Sched<[WriteALUSsr, ReadALUsr]>;
1259 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1260 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1261 /// a explicit result, only implicitly set CPSR.
1262 let isCompare = 1, Defs = [CPSR] in {
1263 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1264 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1265 PatFrag opnode, bit Commutable = 0> {
1266 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1268 [(opnode GPR:$Rn, so_imm:$imm)]>,
1269 Sched<[WriteCMP, ReadALU]> {
1274 let Inst{19-16} = Rn;
1275 let Inst{15-12} = 0b0000;
1276 let Inst{11-0} = imm;
1278 let Unpredictable{15-12} = 0b1111;
1280 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1282 [(opnode GPR:$Rn, GPR:$Rm)]>,
1283 Sched<[WriteCMP, ReadALU, ReadALU]> {
1286 let isCommutable = Commutable;
1289 let Inst{19-16} = Rn;
1290 let Inst{15-12} = 0b0000;
1291 let Inst{11-4} = 0b00000000;
1294 let Unpredictable{15-12} = 0b1111;
1296 def rsi : AI1<opcod, (outs),
1297 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1298 opc, "\t$Rn, $shift",
1299 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1300 Sched<[WriteCMPsi, ReadALU]> {
1305 let Inst{19-16} = Rn;
1306 let Inst{15-12} = 0b0000;
1307 let Inst{11-5} = shift{11-5};
1309 let Inst{3-0} = shift{3-0};
1311 let Unpredictable{15-12} = 0b1111;
1313 def rsr : AI1<opcod, (outs),
1314 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1315 opc, "\t$Rn, $shift",
1316 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1317 Sched<[WriteCMPsr, ReadALU]> {
1322 let Inst{19-16} = Rn;
1323 let Inst{15-12} = 0b0000;
1324 let Inst{11-8} = shift{11-8};
1326 let Inst{6-5} = shift{6-5};
1328 let Inst{3-0} = shift{3-0};
1330 let Unpredictable{15-12} = 0b1111;
1336 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1337 /// register and one whose operand is a register rotated by 8/16/24.
1338 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1339 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1340 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1341 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1342 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1343 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1347 let Inst{19-16} = 0b1111;
1348 let Inst{15-12} = Rd;
1349 let Inst{11-10} = rot;
1353 class AI_ext_rrot_np<bits<8> opcod, string opc>
1354 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1355 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1356 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1358 let Inst{19-16} = 0b1111;
1359 let Inst{11-10} = rot;
1362 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1363 /// register and one whose operand is a register rotated by 8/16/24.
1364 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1365 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1366 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1367 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1368 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1369 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1374 let Inst{19-16} = Rn;
1375 let Inst{15-12} = Rd;
1376 let Inst{11-10} = rot;
1377 let Inst{9-4} = 0b000111;
1381 class AI_exta_rrot_np<bits<8> opcod, string opc>
1382 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1383 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1384 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1387 let Inst{19-16} = Rn;
1388 let Inst{11-10} = rot;
1391 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1392 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1393 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1394 bit Commutable = 0> {
1395 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1396 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1397 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1398 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1400 Sched<[WriteALU, ReadALU]> {
1405 let Inst{15-12} = Rd;
1406 let Inst{19-16} = Rn;
1407 let Inst{11-0} = imm;
1409 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1410 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1411 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1413 Sched<[WriteALU, ReadALU, ReadALU]> {
1417 let Inst{11-4} = 0b00000000;
1419 let isCommutable = Commutable;
1421 let Inst{15-12} = Rd;
1422 let Inst{19-16} = Rn;
1424 def rsi : AsI1<opcod, (outs GPR:$Rd),
1425 (ins GPR:$Rn, so_reg_imm:$shift),
1426 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1427 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1429 Sched<[WriteALUsi, ReadALU]> {
1434 let Inst{19-16} = Rn;
1435 let Inst{15-12} = Rd;
1436 let Inst{11-5} = shift{11-5};
1438 let Inst{3-0} = shift{3-0};
1440 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1441 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1442 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1443 [(set GPRnopc:$Rd, CPSR,
1444 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1446 Sched<[WriteALUsr, ReadALUsr]> {
1451 let Inst{19-16} = Rn;
1452 let Inst{15-12} = Rd;
1453 let Inst{11-8} = shift{11-8};
1455 let Inst{6-5} = shift{6-5};
1457 let Inst{3-0} = shift{3-0};
1462 /// AI1_rsc_irs - Define instructions and patterns for rsc
1463 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1464 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1465 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1466 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1467 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1468 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1470 Sched<[WriteALU, ReadALU]> {
1475 let Inst{15-12} = Rd;
1476 let Inst{19-16} = Rn;
1477 let Inst{11-0} = imm;
1479 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1480 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1481 [/* pattern left blank */]>,
1482 Sched<[WriteALU, ReadALU, ReadALU]> {
1486 let Inst{11-4} = 0b00000000;
1489 let Inst{15-12} = Rd;
1490 let Inst{19-16} = Rn;
1492 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1493 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1494 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1496 Sched<[WriteALUsi, ReadALU]> {
1501 let Inst{19-16} = Rn;
1502 let Inst{15-12} = Rd;
1503 let Inst{11-5} = shift{11-5};
1505 let Inst{3-0} = shift{3-0};
1507 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1508 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1509 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1511 Sched<[WriteALUsr, ReadALUsr]> {
1516 let Inst{19-16} = Rn;
1517 let Inst{15-12} = Rd;
1518 let Inst{11-8} = shift{11-8};
1520 let Inst{6-5} = shift{6-5};
1522 let Inst{3-0} = shift{3-0};
1527 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1528 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1529 InstrItinClass iir, PatFrag opnode> {
1530 // Note: We use the complex addrmode_imm12 rather than just an input
1531 // GPR and a constrained immediate so that we can use this to match
1532 // frame index references and avoid matching constant pool references.
1533 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1534 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1535 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1538 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1539 let Inst{19-16} = addr{16-13}; // Rn
1540 let Inst{15-12} = Rt;
1541 let Inst{11-0} = addr{11-0}; // imm12
1543 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1544 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1545 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1548 let shift{4} = 0; // Inst{4} = 0
1549 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1550 let Inst{19-16} = shift{16-13}; // Rn
1551 let Inst{15-12} = Rt;
1552 let Inst{11-0} = shift{11-0};
1557 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1558 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1559 InstrItinClass iir, PatFrag opnode> {
1560 // Note: We use the complex addrmode_imm12 rather than just an input
1561 // GPR and a constrained immediate so that we can use this to match
1562 // frame index references and avoid matching constant pool references.
1563 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1564 (ins addrmode_imm12:$addr),
1565 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1566 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1569 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1570 let Inst{19-16} = addr{16-13}; // Rn
1571 let Inst{15-12} = Rt;
1572 let Inst{11-0} = addr{11-0}; // imm12
1574 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1575 (ins ldst_so_reg:$shift),
1576 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1577 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1580 let shift{4} = 0; // Inst{4} = 0
1581 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1582 let Inst{19-16} = shift{16-13}; // Rn
1583 let Inst{15-12} = Rt;
1584 let Inst{11-0} = shift{11-0};
1590 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1591 InstrItinClass iir, PatFrag opnode> {
1592 // Note: We use the complex addrmode_imm12 rather than just an input
1593 // GPR and a constrained immediate so that we can use this to match
1594 // frame index references and avoid matching constant pool references.
1595 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1596 (ins GPR:$Rt, addrmode_imm12:$addr),
1597 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1598 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1601 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1602 let Inst{19-16} = addr{16-13}; // Rn
1603 let Inst{15-12} = Rt;
1604 let Inst{11-0} = addr{11-0}; // imm12
1606 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1607 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1608 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1611 let shift{4} = 0; // Inst{4} = 0
1612 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1613 let Inst{19-16} = shift{16-13}; // Rn
1614 let Inst{15-12} = Rt;
1615 let Inst{11-0} = shift{11-0};
1619 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1620 InstrItinClass iir, PatFrag opnode> {
1621 // Note: We use the complex addrmode_imm12 rather than just an input
1622 // GPR and a constrained immediate so that we can use this to match
1623 // frame index references and avoid matching constant pool references.
1624 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1625 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1626 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1627 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1630 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1631 let Inst{19-16} = addr{16-13}; // Rn
1632 let Inst{15-12} = Rt;
1633 let Inst{11-0} = addr{11-0}; // imm12
1635 def rs : AI2ldst<0b011, 0, isByte, (outs),
1636 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1637 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1638 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1641 let shift{4} = 0; // Inst{4} = 0
1642 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1643 let Inst{19-16} = shift{16-13}; // Rn
1644 let Inst{15-12} = Rt;
1645 let Inst{11-0} = shift{11-0};
1650 //===----------------------------------------------------------------------===//
1652 //===----------------------------------------------------------------------===//
1654 //===----------------------------------------------------------------------===//
1655 // Miscellaneous Instructions.
1658 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1659 /// the function. The first operand is the ID# for this instruction, the second
1660 /// is the index into the MachineConstantPool that this is, the third is the
1661 /// size in bytes of this constant pool entry.
1662 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1663 def CONSTPOOL_ENTRY :
1664 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1665 i32imm:$size), NoItinerary, []>;
1667 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1668 // from removing one half of the matched pairs. That breaks PEI, which assumes
1669 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1670 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1671 def ADJCALLSTACKUP :
1672 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1673 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1675 def ADJCALLSTACKDOWN :
1676 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1677 [(ARMcallseq_start timm:$amt)]>;
1680 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1681 // (These pseudos use a hand-written selection code).
1682 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1683 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1684 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1686 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1687 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1689 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1690 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1692 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1693 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1695 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1696 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1698 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1699 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1701 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1702 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1704 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1705 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1706 GPR:$set1, GPR:$set2),
1708 def ATOMMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1709 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1711 def ATOMUMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1712 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1714 def ATOMMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1715 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1717 def ATOMUMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1718 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1722 def HINT : AI<(outs), (ins imm0_4:$imm), MiscFrm, NoItinerary,
1723 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1725 let Inst{27-3} = 0b0011001000001111000000000;
1726 let Inst{2-0} = imm;
1729 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1730 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1731 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1732 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1733 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1735 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1736 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1741 let Inst{15-12} = Rd;
1742 let Inst{19-16} = Rn;
1743 let Inst{27-20} = 0b01101000;
1744 let Inst{7-4} = 0b1011;
1745 let Inst{11-8} = 0b1111;
1746 let Unpredictable{11-8} = 0b1111;
1749 // The 16-bit operand $val can be used by a debugger to store more information
1750 // about the breakpoint.
1751 def BKPT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1752 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1754 let Inst{3-0} = val{3-0};
1755 let Inst{19-8} = val{15-4};
1756 let Inst{27-20} = 0b00010010;
1757 let Inst{31-28} = 0xe; // AL
1758 let Inst{7-4} = 0b0111;
1761 def HLT : AInoP<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1762 "hlt", "\t$val", []>, Requires<[IsARM, HasV8]> {
1764 let Inst{3-0} = val{3-0};
1765 let Inst{19-8} = val{15-4};
1766 let Inst{27-20} = 0b00010000;
1767 let Inst{31-28} = 0xe; // AL
1768 let Inst{7-4} = 0b0111;
1771 // Change Processor State
1772 // FIXME: We should use InstAlias to handle the optional operands.
1773 class CPS<dag iops, string asm_ops>
1774 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1775 []>, Requires<[IsARM]> {
1781 let Inst{31-28} = 0b1111;
1782 let Inst{27-20} = 0b00010000;
1783 let Inst{19-18} = imod;
1784 let Inst{17} = M; // Enabled if mode is set;
1785 let Inst{16-9} = 0b00000000;
1786 let Inst{8-6} = iflags;
1788 let Inst{4-0} = mode;
1791 let DecoderMethod = "DecodeCPSInstruction" in {
1793 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1794 "$imod\t$iflags, $mode">;
1795 let mode = 0, M = 0 in
1796 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1798 let imod = 0, iflags = 0, M = 1 in
1799 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1802 // Preload signals the memory system of possible future data/instruction access.
1803 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1805 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1806 !strconcat(opc, "\t$addr"),
1807 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1808 Sched<[WritePreLd]> {
1811 let Inst{31-26} = 0b111101;
1812 let Inst{25} = 0; // 0 for immediate form
1813 let Inst{24} = data;
1814 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1815 let Inst{22} = read;
1816 let Inst{21-20} = 0b01;
1817 let Inst{19-16} = addr{16-13}; // Rn
1818 let Inst{15-12} = 0b1111;
1819 let Inst{11-0} = addr{11-0}; // imm12
1822 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1823 !strconcat(opc, "\t$shift"),
1824 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1825 Sched<[WritePreLd]> {
1827 let Inst{31-26} = 0b111101;
1828 let Inst{25} = 1; // 1 for register form
1829 let Inst{24} = data;
1830 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1831 let Inst{22} = read;
1832 let Inst{21-20} = 0b01;
1833 let Inst{19-16} = shift{16-13}; // Rn
1834 let Inst{15-12} = 0b1111;
1835 let Inst{11-0} = shift{11-0};
1840 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1841 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1842 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1844 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1845 "setend\t$end", []>, Requires<[IsARM]> {
1847 let Inst{31-10} = 0b1111000100000001000000;
1852 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1853 []>, Requires<[IsARM, HasV7]> {
1855 let Inst{27-4} = 0b001100100000111100001111;
1856 let Inst{3-0} = opt;
1860 * A5.4 Permanently UNDEFINED instructions.
1862 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1863 * Other UDF encodings generate SIGILL.
1865 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1867 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1869 * 1101 1110 iiii iiii
1870 * It uses the following encoding:
1871 * 1110 0111 1111 1110 1101 1110 1111 0000
1872 * - In ARM: UDF #60896;
1873 * - In Thumb: UDF #254 followed by a branch-to-self.
1875 let isBarrier = 1, isTerminator = 1 in
1876 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
1878 Requires<[IsARM,UseNaClTrap]> {
1879 let Inst = 0xe7fedef0;
1881 let isBarrier = 1, isTerminator = 1 in
1882 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1884 Requires<[IsARM,DontUseNaClTrap]> {
1885 let Inst = 0xe7ffdefe;
1888 // Address computation and loads and stores in PIC mode.
1889 let isNotDuplicable = 1 in {
1890 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1892 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
1893 Sched<[WriteALU, ReadALU]>;
1895 let AddedComplexity = 10 in {
1896 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1898 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1900 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1902 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1904 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1906 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1908 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1910 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1912 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1914 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1916 let AddedComplexity = 10 in {
1917 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1918 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1920 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1921 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1922 addrmodepc:$addr)]>;
1924 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1925 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1927 } // isNotDuplicable = 1
1930 // LEApcrel - Load a pc-relative address into a register without offending the
1932 let neverHasSideEffects = 1, isReMaterializable = 1 in
1933 // The 'adr' mnemonic encodes differently if the label is before or after
1934 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1935 // know until then which form of the instruction will be used.
1936 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1937 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
1938 Sched<[WriteALU, ReadALU]> {
1941 let Inst{27-25} = 0b001;
1943 let Inst{23-22} = label{13-12};
1946 let Inst{19-16} = 0b1111;
1947 let Inst{15-12} = Rd;
1948 let Inst{11-0} = label{11-0};
1951 let hasSideEffects = 1 in {
1952 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1953 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1955 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1956 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1957 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1960 //===----------------------------------------------------------------------===//
1961 // Control Flow Instructions.
1964 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1966 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1967 "bx", "\tlr", [(ARMretflag)]>,
1968 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1969 let Inst{27-0} = 0b0001001011111111111100011110;
1973 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1974 "mov", "\tpc, lr", [(ARMretflag)]>,
1975 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]> {
1976 let Inst{27-0} = 0b0001101000001111000000001110;
1980 // Indirect branches
1981 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1983 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1984 [(brind GPR:$dst)]>,
1985 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1987 let Inst{31-4} = 0b1110000100101111111111110001;
1988 let Inst{3-0} = dst;
1991 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1992 "bx", "\t$dst", [/* pattern left blank */]>,
1993 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]> {
1995 let Inst{27-4} = 0b000100101111111111110001;
1996 let Inst{3-0} = dst;
2000 // SP is marked as a use to prevent stack-pointer assignments that appear
2001 // immediately before calls from potentially appearing dead.
2003 // FIXME: Do we really need a non-predicated version? If so, it should
2004 // at least be a pseudo instruction expanding to the predicated version
2005 // at MC lowering time.
2006 Defs = [LR], Uses = [SP] in {
2007 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
2008 IIC_Br, "bl\t$func",
2009 [(ARMcall tglobaladdr:$func)]>,
2010 Requires<[IsARM]>, Sched<[WriteBrL]> {
2011 let Inst{31-28} = 0b1110;
2013 let Inst{23-0} = func;
2014 let DecoderMethod = "DecodeBranchImmInstruction";
2017 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
2018 IIC_Br, "bl", "\t$func",
2019 [(ARMcall_pred tglobaladdr:$func)]>,
2020 Requires<[IsARM]>, Sched<[WriteBrL]> {
2022 let Inst{23-0} = func;
2023 let DecoderMethod = "DecodeBranchImmInstruction";
2027 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2028 IIC_Br, "blx\t$func",
2029 [(ARMcall GPR:$func)]>,
2030 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2032 let Inst{31-4} = 0b1110000100101111111111110011;
2033 let Inst{3-0} = func;
2036 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2037 IIC_Br, "blx", "\t$func",
2038 [(ARMcall_pred GPR:$func)]>,
2039 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2041 let Inst{27-4} = 0b000100101111111111110011;
2042 let Inst{3-0} = func;
2046 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2047 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2048 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2049 Requires<[IsARM, HasV4T]>, Sched<[WriteBr]>;
2052 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2053 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2054 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
2056 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2057 // return stack predictor.
2058 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2059 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2060 Requires<[IsARM]>, Sched<[WriteBr]>;
2063 let isBranch = 1, isTerminator = 1 in {
2064 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2065 // a two-value operand where a dag node expects two operands. :(
2066 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2067 IIC_Br, "b", "\t$target",
2068 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>,
2071 let Inst{23-0} = target;
2072 let DecoderMethod = "DecodeBranchImmInstruction";
2075 let isBarrier = 1 in {
2076 // B is "predicable" since it's just a Bcc with an 'always' condition.
2077 let isPredicable = 1 in
2078 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2079 // should be sufficient.
2080 // FIXME: Is B really a Barrier? That doesn't seem right.
2081 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2082 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>,
2085 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2086 def BR_JTr : ARMPseudoInst<(outs),
2087 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2089 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>,
2091 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2092 // into i12 and rs suffixed versions.
2093 def BR_JTm : ARMPseudoInst<(outs),
2094 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2096 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2097 imm:$id)]>, Sched<[WriteBrTbl]>;
2098 def BR_JTadd : ARMPseudoInst<(outs),
2099 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2101 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2102 imm:$id)]>, Sched<[WriteBrTbl]>;
2103 } // isNotDuplicable = 1, isIndirectBranch = 1
2109 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2110 "blx\t$target", []>,
2111 Requires<[IsARM, HasV5T]>, Sched<[WriteBrL]> {
2112 let Inst{31-25} = 0b1111101;
2114 let Inst{23-0} = target{24-1};
2115 let Inst{24} = target{0};
2118 // Branch and Exchange Jazelle
2119 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2120 [/* pattern left blank */]>, Sched<[WriteBr]> {
2122 let Inst{23-20} = 0b0010;
2123 let Inst{19-8} = 0xfff;
2124 let Inst{7-4} = 0b0010;
2125 let Inst{3-0} = func;
2130 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2131 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>,
2134 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>,
2137 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2139 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2140 Requires<[IsARM]>, Sched<[WriteBr]>;
2142 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2144 (BX GPR:$dst)>, Sched<[WriteBr]>,
2148 // Secure Monitor Call is a system instruction.
2149 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2150 []>, Requires<[IsARM, HasTrustZone]> {
2152 let Inst{23-4} = 0b01100000000000000111;
2153 let Inst{3-0} = opt;
2156 // Supervisor Call (Software Interrupt)
2157 let isCall = 1, Uses = [SP] in {
2158 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []>,
2161 let Inst{23-0} = svc;
2165 // Store Return State
2166 class SRSI<bit wb, string asm>
2167 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2168 NoItinerary, asm, "", []> {
2170 let Inst{31-28} = 0b1111;
2171 let Inst{27-25} = 0b100;
2175 let Inst{19-16} = 0b1101; // SP
2176 let Inst{15-5} = 0b00000101000;
2177 let Inst{4-0} = mode;
2180 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2181 let Inst{24-23} = 0;
2183 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2184 let Inst{24-23} = 0;
2186 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2187 let Inst{24-23} = 0b10;
2189 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2190 let Inst{24-23} = 0b10;
2192 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2193 let Inst{24-23} = 0b01;
2195 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2196 let Inst{24-23} = 0b01;
2198 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2199 let Inst{24-23} = 0b11;
2201 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2202 let Inst{24-23} = 0b11;
2205 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2206 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2208 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2209 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2211 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2212 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2214 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2215 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2217 // Return From Exception
2218 class RFEI<bit wb, string asm>
2219 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2220 NoItinerary, asm, "", []> {
2222 let Inst{31-28} = 0b1111;
2223 let Inst{27-25} = 0b100;
2227 let Inst{19-16} = Rn;
2228 let Inst{15-0} = 0xa00;
2231 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2232 let Inst{24-23} = 0;
2234 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2235 let Inst{24-23} = 0;
2237 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2238 let Inst{24-23} = 0b10;
2240 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2241 let Inst{24-23} = 0b10;
2243 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2244 let Inst{24-23} = 0b01;
2246 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2247 let Inst{24-23} = 0b01;
2249 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2250 let Inst{24-23} = 0b11;
2252 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2253 let Inst{24-23} = 0b11;
2256 //===----------------------------------------------------------------------===//
2257 // Load / Store Instructions.
2263 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2264 UnOpFrag<(load node:$Src)>>;
2265 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2266 UnOpFrag<(zextloadi8 node:$Src)>>;
2267 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2268 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2269 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2270 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2272 // Special LDR for loads from non-pc-relative constpools.
2273 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2274 isReMaterializable = 1, isCodeGenOnly = 1 in
2275 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2276 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2280 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2281 let Inst{19-16} = 0b1111;
2282 let Inst{15-12} = Rt;
2283 let Inst{11-0} = addr{11-0}; // imm12
2286 // Loads with zero extension
2287 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2288 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2289 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2291 // Loads with sign extension
2292 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2293 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2294 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2296 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2297 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2298 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2300 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2302 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2303 (ins addrmode3:$addr), LdMiscFrm,
2304 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2305 []>, Requires<[IsARM, HasV5TE]>;
2308 def LDA : AIldracq<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2309 NoItinerary, "lda", "\t$Rt, $addr", []>;
2310 def LDAB : AIldracq<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2311 NoItinerary, "ldab", "\t$Rt, $addr", []>;
2312 def LDAH : AIldracq<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
2313 NoItinerary, "ldah", "\t$Rt, $addr", []>;
2316 multiclass AI2_ldridx<bit isByte, string opc,
2317 InstrItinClass iii, InstrItinClass iir> {
2318 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2319 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2320 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2323 let Inst{23} = addr{12};
2324 let Inst{19-16} = addr{16-13};
2325 let Inst{11-0} = addr{11-0};
2326 let DecoderMethod = "DecodeLDRPreImm";
2329 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2330 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2331 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2334 let Inst{23} = addr{12};
2335 let Inst{19-16} = addr{16-13};
2336 let Inst{11-0} = addr{11-0};
2338 let DecoderMethod = "DecodeLDRPreReg";
2341 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2342 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2343 IndexModePost, LdFrm, iir,
2344 opc, "\t$Rt, $addr, $offset",
2345 "$addr.base = $Rn_wb", []> {
2351 let Inst{23} = offset{12};
2352 let Inst{19-16} = addr;
2353 let Inst{11-0} = offset{11-0};
2356 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2359 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2360 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2361 IndexModePost, LdFrm, iii,
2362 opc, "\t$Rt, $addr, $offset",
2363 "$addr.base = $Rn_wb", []> {
2369 let Inst{23} = offset{12};
2370 let Inst{19-16} = addr;
2371 let Inst{11-0} = offset{11-0};
2373 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2378 let mayLoad = 1, neverHasSideEffects = 1 in {
2379 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2380 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2381 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2382 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2385 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2386 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2387 (ins addrmode3_pre:$addr), IndexModePre,
2389 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2391 let Inst{23} = addr{8}; // U bit
2392 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2393 let Inst{19-16} = addr{12-9}; // Rn
2394 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2395 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2396 let DecoderMethod = "DecodeAddrMode3Instruction";
2398 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2399 (ins addr_offset_none:$addr, am3offset:$offset),
2400 IndexModePost, LdMiscFrm, itin,
2401 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2405 let Inst{23} = offset{8}; // U bit
2406 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2407 let Inst{19-16} = addr;
2408 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2409 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2410 let DecoderMethod = "DecodeAddrMode3Instruction";
2414 let mayLoad = 1, neverHasSideEffects = 1 in {
2415 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2416 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2417 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2418 let hasExtraDefRegAllocReq = 1 in {
2419 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2420 (ins addrmode3_pre:$addr), IndexModePre,
2421 LdMiscFrm, IIC_iLoad_d_ru,
2422 "ldrd", "\t$Rt, $Rt2, $addr!",
2423 "$addr.base = $Rn_wb", []> {
2425 let Inst{23} = addr{8}; // U bit
2426 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2427 let Inst{19-16} = addr{12-9}; // Rn
2428 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2429 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2430 let DecoderMethod = "DecodeAddrMode3Instruction";
2432 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2433 (ins addr_offset_none:$addr, am3offset:$offset),
2434 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2435 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2436 "$addr.base = $Rn_wb", []> {
2439 let Inst{23} = offset{8}; // U bit
2440 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2441 let Inst{19-16} = addr;
2442 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2443 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2444 let DecoderMethod = "DecodeAddrMode3Instruction";
2446 } // hasExtraDefRegAllocReq = 1
2447 } // mayLoad = 1, neverHasSideEffects = 1
2449 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2450 let mayLoad = 1, neverHasSideEffects = 1 in {
2451 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2452 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2453 IndexModePost, LdFrm, IIC_iLoad_ru,
2454 "ldrt", "\t$Rt, $addr, $offset",
2455 "$addr.base = $Rn_wb", []> {
2461 let Inst{23} = offset{12};
2462 let Inst{21} = 1; // overwrite
2463 let Inst{19-16} = addr;
2464 let Inst{11-5} = offset{11-5};
2466 let Inst{3-0} = offset{3-0};
2467 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2470 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2471 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2472 IndexModePost, LdFrm, IIC_iLoad_ru,
2473 "ldrt", "\t$Rt, $addr, $offset",
2474 "$addr.base = $Rn_wb", []> {
2480 let Inst{23} = offset{12};
2481 let Inst{21} = 1; // overwrite
2482 let Inst{19-16} = addr;
2483 let Inst{11-0} = offset{11-0};
2484 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2487 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2488 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2489 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2490 "ldrbt", "\t$Rt, $addr, $offset",
2491 "$addr.base = $Rn_wb", []> {
2497 let Inst{23} = offset{12};
2498 let Inst{21} = 1; // overwrite
2499 let Inst{19-16} = addr;
2500 let Inst{11-5} = offset{11-5};
2502 let Inst{3-0} = offset{3-0};
2503 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2506 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2507 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2508 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2509 "ldrbt", "\t$Rt, $addr, $offset",
2510 "$addr.base = $Rn_wb", []> {
2516 let Inst{23} = offset{12};
2517 let Inst{21} = 1; // overwrite
2518 let Inst{19-16} = addr;
2519 let Inst{11-0} = offset{11-0};
2520 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2523 multiclass AI3ldrT<bits<4> op, string opc> {
2524 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2525 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2526 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2527 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2529 let Inst{23} = offset{8};
2531 let Inst{11-8} = offset{7-4};
2532 let Inst{3-0} = offset{3-0};
2534 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2535 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2536 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2537 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2539 let Inst{23} = Rm{4};
2542 let Unpredictable{11-8} = 0b1111;
2543 let Inst{3-0} = Rm{3-0};
2544 let DecoderMethod = "DecodeLDR";
2548 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2549 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2550 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2555 // Stores with truncate
2556 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2557 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2558 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2561 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2562 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2563 StMiscFrm, IIC_iStore_d_r,
2564 "strd", "\t$Rt, $src2, $addr", []>,
2565 Requires<[IsARM, HasV5TE]> {
2570 multiclass AI2_stridx<bit isByte, string opc,
2571 InstrItinClass iii, InstrItinClass iir> {
2572 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2573 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2575 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2578 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2579 let Inst{19-16} = addr{16-13}; // Rn
2580 let Inst{11-0} = addr{11-0}; // imm12
2581 let DecoderMethod = "DecodeSTRPreImm";
2584 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2585 (ins GPR:$Rt, ldst_so_reg:$addr),
2586 IndexModePre, StFrm, iir,
2587 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2590 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2591 let Inst{19-16} = addr{16-13}; // Rn
2592 let Inst{11-0} = addr{11-0};
2593 let Inst{4} = 0; // Inst{4} = 0
2594 let DecoderMethod = "DecodeSTRPreReg";
2596 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2597 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2598 IndexModePost, StFrm, iir,
2599 opc, "\t$Rt, $addr, $offset",
2600 "$addr.base = $Rn_wb", []> {
2606 let Inst{23} = offset{12};
2607 let Inst{19-16} = addr;
2608 let Inst{11-0} = offset{11-0};
2611 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2614 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2615 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2616 IndexModePost, StFrm, iii,
2617 opc, "\t$Rt, $addr, $offset",
2618 "$addr.base = $Rn_wb", []> {
2624 let Inst{23} = offset{12};
2625 let Inst{19-16} = addr;
2626 let Inst{11-0} = offset{11-0};
2628 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2632 let mayStore = 1, neverHasSideEffects = 1 in {
2633 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2634 // IIC_iStore_siu depending on whether it the offset register is shifted.
2635 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2636 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2639 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2640 am2offset_reg:$offset),
2641 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2642 am2offset_reg:$offset)>;
2643 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2644 am2offset_imm:$offset),
2645 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2646 am2offset_imm:$offset)>;
2647 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2648 am2offset_reg:$offset),
2649 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2650 am2offset_reg:$offset)>;
2651 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2652 am2offset_imm:$offset),
2653 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2654 am2offset_imm:$offset)>;
2656 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2657 // put the patterns on the instruction definitions directly as ISel wants
2658 // the address base and offset to be separate operands, not a single
2659 // complex operand like we represent the instructions themselves. The
2660 // pseudos map between the two.
2661 let usesCustomInserter = 1,
2662 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2663 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2664 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2667 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2668 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2669 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2672 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2673 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2674 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2677 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2678 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2679 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2682 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2683 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2684 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2687 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2692 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2693 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2694 StMiscFrm, IIC_iStore_bh_ru,
2695 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2697 let Inst{23} = addr{8}; // U bit
2698 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2699 let Inst{19-16} = addr{12-9}; // Rn
2700 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2701 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2702 let DecoderMethod = "DecodeAddrMode3Instruction";
2705 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2706 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2707 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2708 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2709 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2710 addr_offset_none:$addr,
2711 am3offset:$offset))]> {
2714 let Inst{23} = offset{8}; // U bit
2715 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2716 let Inst{19-16} = addr;
2717 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2718 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2719 let DecoderMethod = "DecodeAddrMode3Instruction";
2722 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2723 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2724 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2725 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2726 "strd", "\t$Rt, $Rt2, $addr!",
2727 "$addr.base = $Rn_wb", []> {
2729 let Inst{23} = addr{8}; // U bit
2730 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2731 let Inst{19-16} = addr{12-9}; // Rn
2732 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2733 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2734 let DecoderMethod = "DecodeAddrMode3Instruction";
2737 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2738 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2740 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2741 "strd", "\t$Rt, $Rt2, $addr, $offset",
2742 "$addr.base = $Rn_wb", []> {
2745 let Inst{23} = offset{8}; // U bit
2746 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2747 let Inst{19-16} = addr;
2748 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2749 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2750 let DecoderMethod = "DecodeAddrMode3Instruction";
2752 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2754 // STRT, STRBT, and STRHT
2756 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2757 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2758 IndexModePost, StFrm, IIC_iStore_bh_ru,
2759 "strbt", "\t$Rt, $addr, $offset",
2760 "$addr.base = $Rn_wb", []> {
2766 let Inst{23} = offset{12};
2767 let Inst{21} = 1; // overwrite
2768 let Inst{19-16} = addr;
2769 let Inst{11-5} = offset{11-5};
2771 let Inst{3-0} = offset{3-0};
2772 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2775 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2776 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2777 IndexModePost, StFrm, IIC_iStore_bh_ru,
2778 "strbt", "\t$Rt, $addr, $offset",
2779 "$addr.base = $Rn_wb", []> {
2785 let Inst{23} = offset{12};
2786 let Inst{21} = 1; // overwrite
2787 let Inst{19-16} = addr;
2788 let Inst{11-0} = offset{11-0};
2789 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2792 let mayStore = 1, neverHasSideEffects = 1 in {
2793 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2794 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2795 IndexModePost, StFrm, IIC_iStore_ru,
2796 "strt", "\t$Rt, $addr, $offset",
2797 "$addr.base = $Rn_wb", []> {
2803 let Inst{23} = offset{12};
2804 let Inst{21} = 1; // overwrite
2805 let Inst{19-16} = addr;
2806 let Inst{11-5} = offset{11-5};
2808 let Inst{3-0} = offset{3-0};
2809 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2812 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2813 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2814 IndexModePost, StFrm, IIC_iStore_ru,
2815 "strt", "\t$Rt, $addr, $offset",
2816 "$addr.base = $Rn_wb", []> {
2822 let Inst{23} = offset{12};
2823 let Inst{21} = 1; // overwrite
2824 let Inst{19-16} = addr;
2825 let Inst{11-0} = offset{11-0};
2826 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2831 multiclass AI3strT<bits<4> op, string opc> {
2832 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2833 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2834 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2835 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2837 let Inst{23} = offset{8};
2839 let Inst{11-8} = offset{7-4};
2840 let Inst{3-0} = offset{3-0};
2842 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2843 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2844 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2845 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2847 let Inst{23} = Rm{4};
2850 let Inst{3-0} = Rm{3-0};
2855 defm STRHT : AI3strT<0b1011, "strht">;
2857 def STL : AIstrrel<0b00, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2858 NoItinerary, "stl", "\t$Rt, $addr", []>;
2859 def STLB : AIstrrel<0b10, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2860 NoItinerary, "stlb", "\t$Rt, $addr", []>;
2861 def STLH : AIstrrel<0b11, (outs), (ins GPR:$Rt, addr_offset_none:$addr),
2862 NoItinerary, "stlh", "\t$Rt, $addr", []>;
2864 //===----------------------------------------------------------------------===//
2865 // Load / store multiple Instructions.
2868 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2869 InstrItinClass itin, InstrItinClass itin_upd> {
2870 // IA is the default, so no need for an explicit suffix on the
2871 // mnemonic here. Without it is the canonical spelling.
2873 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2874 IndexModeNone, f, itin,
2875 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2876 let Inst{24-23} = 0b01; // Increment After
2877 let Inst{22} = P_bit;
2878 let Inst{21} = 0; // No writeback
2879 let Inst{20} = L_bit;
2882 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2883 IndexModeUpd, f, itin_upd,
2884 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2885 let Inst{24-23} = 0b01; // Increment After
2886 let Inst{22} = P_bit;
2887 let Inst{21} = 1; // Writeback
2888 let Inst{20} = L_bit;
2890 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2893 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2894 IndexModeNone, f, itin,
2895 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2896 let Inst{24-23} = 0b00; // Decrement After
2897 let Inst{22} = P_bit;
2898 let Inst{21} = 0; // No writeback
2899 let Inst{20} = L_bit;
2902 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2903 IndexModeUpd, f, itin_upd,
2904 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2905 let Inst{24-23} = 0b00; // Decrement After
2906 let Inst{22} = P_bit;
2907 let Inst{21} = 1; // Writeback
2908 let Inst{20} = L_bit;
2910 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2913 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2914 IndexModeNone, f, itin,
2915 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2916 let Inst{24-23} = 0b10; // Decrement Before
2917 let Inst{22} = P_bit;
2918 let Inst{21} = 0; // No writeback
2919 let Inst{20} = L_bit;
2922 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2923 IndexModeUpd, f, itin_upd,
2924 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2925 let Inst{24-23} = 0b10; // Decrement Before
2926 let Inst{22} = P_bit;
2927 let Inst{21} = 1; // Writeback
2928 let Inst{20} = L_bit;
2930 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2933 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2934 IndexModeNone, f, itin,
2935 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2936 let Inst{24-23} = 0b11; // Increment Before
2937 let Inst{22} = P_bit;
2938 let Inst{21} = 0; // No writeback
2939 let Inst{20} = L_bit;
2942 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2943 IndexModeUpd, f, itin_upd,
2944 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2945 let Inst{24-23} = 0b11; // Increment Before
2946 let Inst{22} = P_bit;
2947 let Inst{21} = 1; // Writeback
2948 let Inst{20} = L_bit;
2950 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2954 let neverHasSideEffects = 1 in {
2956 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2957 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2960 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2961 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2964 } // neverHasSideEffects
2966 // FIXME: remove when we have a way to marking a MI with these properties.
2967 // FIXME: Should pc be an implicit operand like PICADD, etc?
2968 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2969 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2970 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2971 reglist:$regs, variable_ops),
2972 4, IIC_iLoad_mBr, [],
2973 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2974 RegConstraint<"$Rn = $wb">;
2976 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2977 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2980 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2981 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2986 //===----------------------------------------------------------------------===//
2987 // Move Instructions.
2990 let neverHasSideEffects = 1 in
2991 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2992 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2996 let Inst{19-16} = 0b0000;
2997 let Inst{11-4} = 0b00000000;
3000 let Inst{15-12} = Rd;
3003 // A version for the smaller set of tail call registers.
3004 let neverHasSideEffects = 1 in
3005 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
3006 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
3010 let Inst{11-4} = 0b00000000;
3013 let Inst{15-12} = Rd;
3016 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
3017 DPSoRegRegFrm, IIC_iMOVsr,
3018 "mov", "\t$Rd, $src",
3019 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
3023 let Inst{15-12} = Rd;
3024 let Inst{19-16} = 0b0000;
3025 let Inst{11-8} = src{11-8};
3027 let Inst{6-5} = src{6-5};
3029 let Inst{3-0} = src{3-0};
3033 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3034 DPSoRegImmFrm, IIC_iMOVsr,
3035 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3036 UnaryDP, Sched<[WriteALU]> {
3039 let Inst{15-12} = Rd;
3040 let Inst{19-16} = 0b0000;
3041 let Inst{11-5} = src{11-5};
3043 let Inst{3-0} = src{3-0};
3047 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3048 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3049 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
3054 let Inst{15-12} = Rd;
3055 let Inst{19-16} = 0b0000;
3056 let Inst{11-0} = imm;
3059 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3060 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3062 "movw", "\t$Rd, $imm",
3063 [(set GPR:$Rd, imm0_65535:$imm)]>,
3064 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3067 let Inst{15-12} = Rd;
3068 let Inst{11-0} = imm{11-0};
3069 let Inst{19-16} = imm{15-12};
3072 let DecoderMethod = "DecodeArmMOVTWInstruction";
3075 def : InstAlias<"mov${p} $Rd, $imm",
3076 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3079 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3080 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3083 let Constraints = "$src = $Rd" in {
3084 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3085 (ins GPR:$src, imm0_65535_expr:$imm),
3087 "movt", "\t$Rd, $imm",
3089 (or (and GPR:$src, 0xffff),
3090 lo16AllZero:$imm))]>, UnaryDP,
3091 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3094 let Inst{15-12} = Rd;
3095 let Inst{11-0} = imm{11-0};
3096 let Inst{19-16} = imm{15-12};
3099 let DecoderMethod = "DecodeArmMOVTWInstruction";
3102 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3103 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3108 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3109 Requires<[IsARM, HasV6T2]>;
3111 let Uses = [CPSR] in
3112 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3113 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3114 Requires<[IsARM]>, Sched<[WriteALU]>;
3116 // These aren't really mov instructions, but we have to define them this way
3117 // due to flag operands.
3119 let Defs = [CPSR] in {
3120 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3121 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3122 Sched<[WriteALU]>, Requires<[IsARM]>;
3123 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3124 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3125 Sched<[WriteALU]>, Requires<[IsARM]>;
3128 //===----------------------------------------------------------------------===//
3129 // Extend Instructions.
3134 def SXTB : AI_ext_rrot<0b01101010,
3135 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3136 def SXTH : AI_ext_rrot<0b01101011,
3137 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3139 def SXTAB : AI_exta_rrot<0b01101010,
3140 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3141 def SXTAH : AI_exta_rrot<0b01101011,
3142 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3144 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3146 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3150 let AddedComplexity = 16 in {
3151 def UXTB : AI_ext_rrot<0b01101110,
3152 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3153 def UXTH : AI_ext_rrot<0b01101111,
3154 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3155 def UXTB16 : AI_ext_rrot<0b01101100,
3156 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3158 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3159 // The transformation should probably be done as a combiner action
3160 // instead so we can include a check for masking back in the upper
3161 // eight bits of the source into the lower eight bits of the result.
3162 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3163 // (UXTB16r_rot GPR:$Src, 3)>;
3164 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3165 (UXTB16 GPR:$Src, 1)>;
3167 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3168 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3169 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3170 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3173 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3174 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3177 def SBFX : I<(outs GPRnopc:$Rd),
3178 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3179 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3180 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3181 Requires<[IsARM, HasV6T2]> {
3186 let Inst{27-21} = 0b0111101;
3187 let Inst{6-4} = 0b101;
3188 let Inst{20-16} = width;
3189 let Inst{15-12} = Rd;
3190 let Inst{11-7} = lsb;
3194 def UBFX : I<(outs GPR:$Rd),
3195 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3196 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3197 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3198 Requires<[IsARM, HasV6T2]> {
3203 let Inst{27-21} = 0b0111111;
3204 let Inst{6-4} = 0b101;
3205 let Inst{20-16} = width;
3206 let Inst{15-12} = Rd;
3207 let Inst{11-7} = lsb;
3211 //===----------------------------------------------------------------------===//
3212 // Arithmetic Instructions.
3215 defm ADD : AsI1_bin_irs<0b0100, "add",
3216 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3217 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3218 defm SUB : AsI1_bin_irs<0b0010, "sub",
3219 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3220 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3222 // ADD and SUB with 's' bit set.
3224 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3225 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3226 // AdjustInstrPostInstrSelection where we determine whether or not to
3227 // set the "s" bit based on CPSR liveness.
3229 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3230 // support for an optional CPSR definition that corresponds to the DAG
3231 // node's second value. We can then eliminate the implicit def of CPSR.
3232 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3233 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3234 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3235 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3237 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3238 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3239 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3240 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3242 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3243 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3244 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3246 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3247 // CPSR and the implicit def of CPSR is not needed.
3248 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3249 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3251 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3252 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3254 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3255 // The assume-no-carry-in form uses the negation of the input since add/sub
3256 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3257 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3259 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3260 (SUBri GPR:$src, so_imm_neg:$imm)>;
3261 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3262 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3264 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3265 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3266 Requires<[IsARM, HasV6T2]>;
3267 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3268 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3269 Requires<[IsARM, HasV6T2]>;
3271 // The with-carry-in form matches bitwise not instead of the negation.
3272 // Effectively, the inverse interpretation of the carry flag already accounts
3273 // for part of the negation.
3274 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3275 (SBCri GPR:$src, so_imm_not:$imm)>;
3276 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3277 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3279 // Note: These are implemented in C++ code, because they have to generate
3280 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3282 // (mul X, 2^n+1) -> (add (X << n), X)
3283 // (mul X, 2^n-1) -> (rsb X, (X << n))
3285 // ARM Arithmetic Instruction
3286 // GPR:$dst = GPR:$a op GPR:$b
3287 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3288 list<dag> pattern = [],
3289 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3290 string asm = "\t$Rd, $Rn, $Rm">
3291 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3292 Sched<[WriteALU, ReadALU, ReadALU]> {
3296 let Inst{27-20} = op27_20;
3297 let Inst{11-4} = op11_4;
3298 let Inst{19-16} = Rn;
3299 let Inst{15-12} = Rd;
3302 let Unpredictable{11-8} = 0b1111;
3305 // Saturating add/subtract
3307 let DecoderMethod = "DecodeQADDInstruction" in
3308 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3309 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3310 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3312 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3313 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3314 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3315 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3316 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3318 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3319 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3322 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3323 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3324 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3325 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3326 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3327 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3328 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3329 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3330 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3331 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3332 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3333 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3335 // Signed/Unsigned add/subtract
3337 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3338 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3339 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3340 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3341 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3342 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3343 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3344 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3345 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3346 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3347 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3348 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3350 // Signed/Unsigned halving add/subtract
3352 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3353 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3354 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3355 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3356 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3357 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3358 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3359 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3360 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3361 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3362 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3363 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3365 // Unsigned Sum of Absolute Differences [and Accumulate].
3367 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3368 MulFrm /* for convenience */, NoItinerary, "usad8",
3369 "\t$Rd, $Rn, $Rm", []>,
3370 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3374 let Inst{27-20} = 0b01111000;
3375 let Inst{15-12} = 0b1111;
3376 let Inst{7-4} = 0b0001;
3377 let Inst{19-16} = Rd;
3378 let Inst{11-8} = Rm;
3381 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3382 MulFrm /* for convenience */, NoItinerary, "usada8",
3383 "\t$Rd, $Rn, $Rm, $Ra", []>,
3384 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3389 let Inst{27-20} = 0b01111000;
3390 let Inst{7-4} = 0b0001;
3391 let Inst{19-16} = Rd;
3392 let Inst{15-12} = Ra;
3393 let Inst{11-8} = Rm;
3397 // Signed/Unsigned saturate
3399 def SSAT : AI<(outs GPRnopc:$Rd),
3400 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3401 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3406 let Inst{27-21} = 0b0110101;
3407 let Inst{5-4} = 0b01;
3408 let Inst{20-16} = sat_imm;
3409 let Inst{15-12} = Rd;
3410 let Inst{11-7} = sh{4-0};
3411 let Inst{6} = sh{5};
3415 def SSAT16 : AI<(outs GPRnopc:$Rd),
3416 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3417 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3421 let Inst{27-20} = 0b01101010;
3422 let Inst{11-4} = 0b11110011;
3423 let Inst{15-12} = Rd;
3424 let Inst{19-16} = sat_imm;
3428 def USAT : AI<(outs GPRnopc:$Rd),
3429 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3430 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3435 let Inst{27-21} = 0b0110111;
3436 let Inst{5-4} = 0b01;
3437 let Inst{15-12} = Rd;
3438 let Inst{11-7} = sh{4-0};
3439 let Inst{6} = sh{5};
3440 let Inst{20-16} = sat_imm;
3444 def USAT16 : AI<(outs GPRnopc:$Rd),
3445 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3446 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3450 let Inst{27-20} = 0b01101110;
3451 let Inst{11-4} = 0b11110011;
3452 let Inst{15-12} = Rd;
3453 let Inst{19-16} = sat_imm;
3457 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3458 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3459 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3460 (USAT imm:$pos, GPRnopc:$a, 0)>;
3462 //===----------------------------------------------------------------------===//
3463 // Bitwise Instructions.
3466 defm AND : AsI1_bin_irs<0b0000, "and",
3467 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3468 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3469 defm ORR : AsI1_bin_irs<0b1100, "orr",
3470 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3471 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3472 defm EOR : AsI1_bin_irs<0b0001, "eor",
3473 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3474 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3475 defm BIC : AsI1_bin_irs<0b1110, "bic",
3476 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3477 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3479 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3480 // like in the actual instruction encoding. The complexity of mapping the mask
3481 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3482 // instruction description.
3483 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3484 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3485 "bfc", "\t$Rd, $imm", "$src = $Rd",
3486 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3487 Requires<[IsARM, HasV6T2]> {
3490 let Inst{27-21} = 0b0111110;
3491 let Inst{6-0} = 0b0011111;
3492 let Inst{15-12} = Rd;
3493 let Inst{11-7} = imm{4-0}; // lsb
3494 let Inst{20-16} = imm{9-5}; // msb
3497 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3498 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3499 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3500 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3501 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3502 bf_inv_mask_imm:$imm))]>,
3503 Requires<[IsARM, HasV6T2]> {
3507 let Inst{27-21} = 0b0111110;
3508 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3509 let Inst{15-12} = Rd;
3510 let Inst{11-7} = imm{4-0}; // lsb
3511 let Inst{20-16} = imm{9-5}; // width
3515 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3516 "mvn", "\t$Rd, $Rm",
3517 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3521 let Inst{19-16} = 0b0000;
3522 let Inst{11-4} = 0b00000000;
3523 let Inst{15-12} = Rd;
3526 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3527 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3528 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3533 let Inst{19-16} = 0b0000;
3534 let Inst{15-12} = Rd;
3535 let Inst{11-5} = shift{11-5};
3537 let Inst{3-0} = shift{3-0};
3539 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3540 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3541 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3546 let Inst{19-16} = 0b0000;
3547 let Inst{15-12} = Rd;
3548 let Inst{11-8} = shift{11-8};
3550 let Inst{6-5} = shift{6-5};
3552 let Inst{3-0} = shift{3-0};
3554 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3555 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3556 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3557 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3561 let Inst{19-16} = 0b0000;
3562 let Inst{15-12} = Rd;
3563 let Inst{11-0} = imm;
3566 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3567 (BICri GPR:$src, so_imm_not:$imm)>;
3569 //===----------------------------------------------------------------------===//
3570 // Multiply Instructions.
3572 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3573 string opc, string asm, list<dag> pattern>
3574 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3578 let Inst{19-16} = Rd;
3579 let Inst{11-8} = Rm;
3582 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3583 string opc, string asm, list<dag> pattern>
3584 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3589 let Inst{19-16} = RdHi;
3590 let Inst{15-12} = RdLo;
3591 let Inst{11-8} = Rm;
3594 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3595 string opc, string asm, list<dag> pattern>
3596 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3601 let Inst{19-16} = RdHi;
3602 let Inst{15-12} = RdLo;
3603 let Inst{11-8} = Rm;
3607 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3608 // property. Remove them when it's possible to add those properties
3609 // on an individual MachineInstr, not just an instruction description.
3610 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3611 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3612 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3613 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3614 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3615 Requires<[IsARM, HasV6]> {
3616 let Inst{15-12} = 0b0000;
3617 let Unpredictable{15-12} = 0b1111;
3620 let Constraints = "@earlyclobber $Rd" in
3621 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3622 pred:$p, cc_out:$s),
3624 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3625 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3626 Requires<[IsARM, NoV6, UseMulOps]>;
3629 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3630 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3631 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3632 Requires<[IsARM, HasV6, UseMulOps]> {
3634 let Inst{15-12} = Ra;
3637 let Constraints = "@earlyclobber $Rd" in
3638 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3639 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3641 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3642 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3643 Requires<[IsARM, NoV6]>;
3645 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3646 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3647 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3648 Requires<[IsARM, HasV6T2, UseMulOps]> {
3653 let Inst{19-16} = Rd;
3654 let Inst{15-12} = Ra;
3655 let Inst{11-8} = Rm;
3659 // Extra precision multiplies with low / high results
3660 let neverHasSideEffects = 1 in {
3661 let isCommutable = 1 in {
3662 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3663 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3664 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3665 Requires<[IsARM, HasV6]>;
3667 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3668 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3669 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3670 Requires<[IsARM, HasV6]>;
3672 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3673 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3674 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3676 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3677 Requires<[IsARM, NoV6]>;
3679 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3680 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3682 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3683 Requires<[IsARM, NoV6]>;
3687 // Multiply + accumulate
3688 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3689 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3690 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3691 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3692 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3693 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3694 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3695 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3697 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3698 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3699 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3700 Requires<[IsARM, HasV6]> {
3705 let Inst{19-16} = RdHi;
3706 let Inst{15-12} = RdLo;
3707 let Inst{11-8} = Rm;
3711 let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
3712 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3713 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3715 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3716 pred:$p, cc_out:$s)>,
3717 Requires<[IsARM, NoV6]>;
3718 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3719 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3721 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3722 pred:$p, cc_out:$s)>,
3723 Requires<[IsARM, NoV6]>;
3726 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3727 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3728 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3730 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3731 Requires<[IsARM, NoV6]>;
3734 } // neverHasSideEffects
3736 // Most significant word multiply
3737 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3738 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3739 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3740 Requires<[IsARM, HasV6]> {
3741 let Inst{15-12} = 0b1111;
3744 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3745 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3746 Requires<[IsARM, HasV6]> {
3747 let Inst{15-12} = 0b1111;
3750 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3751 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3752 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3753 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3754 Requires<[IsARM, HasV6, UseMulOps]>;
3756 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3757 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3758 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3759 Requires<[IsARM, HasV6]>;
3761 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3762 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3763 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3764 Requires<[IsARM, HasV6, UseMulOps]>;
3766 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3767 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3768 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3769 Requires<[IsARM, HasV6]>;
3771 multiclass AI_smul<string opc, PatFrag opnode> {
3772 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3773 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3774 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3775 (sext_inreg GPR:$Rm, i16)))]>,
3776 Requires<[IsARM, HasV5TE]>;
3778 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3779 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3780 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3781 (sra GPR:$Rm, (i32 16))))]>,
3782 Requires<[IsARM, HasV5TE]>;
3784 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3785 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3786 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3787 (sext_inreg GPR:$Rm, i16)))]>,
3788 Requires<[IsARM, HasV5TE]>;
3790 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3791 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3792 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3793 (sra GPR:$Rm, (i32 16))))]>,
3794 Requires<[IsARM, HasV5TE]>;
3796 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3797 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3798 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3799 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3800 Requires<[IsARM, HasV5TE]>;
3802 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3803 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3804 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3805 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3806 Requires<[IsARM, HasV5TE]>;
3810 multiclass AI_smla<string opc, PatFrag opnode> {
3811 let DecoderMethod = "DecodeSMLAInstruction" in {
3812 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3813 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3814 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3815 [(set GPRnopc:$Rd, (add GPR:$Ra,
3816 (opnode (sext_inreg GPRnopc:$Rn, i16),
3817 (sext_inreg GPRnopc:$Rm, i16))))]>,
3818 Requires<[IsARM, HasV5TE, UseMulOps]>;
3820 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3821 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3822 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3824 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3825 (sra GPRnopc:$Rm, (i32 16)))))]>,
3826 Requires<[IsARM, HasV5TE, UseMulOps]>;
3828 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3829 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3830 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3832 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3833 (sext_inreg GPRnopc:$Rm, i16))))]>,
3834 Requires<[IsARM, HasV5TE, UseMulOps]>;
3836 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3837 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3838 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3840 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3841 (sra GPRnopc:$Rm, (i32 16)))))]>,
3842 Requires<[IsARM, HasV5TE, UseMulOps]>;
3844 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3845 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3846 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3848 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3849 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3850 Requires<[IsARM, HasV5TE, UseMulOps]>;
3852 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3853 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3854 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3856 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3857 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3858 Requires<[IsARM, HasV5TE, UseMulOps]>;
3862 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3863 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3865 // Halfword multiply accumulate long: SMLAL<x><y>.
3866 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3867 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3868 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3869 Requires<[IsARM, HasV5TE]>;
3871 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3872 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3873 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3874 Requires<[IsARM, HasV5TE]>;
3876 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3877 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3878 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3879 Requires<[IsARM, HasV5TE]>;
3881 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3882 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3883 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3884 Requires<[IsARM, HasV5TE]>;
3886 // Helper class for AI_smld.
3887 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3888 InstrItinClass itin, string opc, string asm>
3889 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3892 let Inst{27-23} = 0b01110;
3893 let Inst{22} = long;
3894 let Inst{21-20} = 0b00;
3895 let Inst{11-8} = Rm;
3902 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3903 InstrItinClass itin, string opc, string asm>
3904 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3906 let Inst{15-12} = 0b1111;
3907 let Inst{19-16} = Rd;
3909 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3910 InstrItinClass itin, string opc, string asm>
3911 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3914 let Inst{19-16} = Rd;
3915 let Inst{15-12} = Ra;
3917 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3918 InstrItinClass itin, string opc, string asm>
3919 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3922 let Inst{19-16} = RdHi;
3923 let Inst{15-12} = RdLo;
3926 multiclass AI_smld<bit sub, string opc> {
3928 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3929 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3930 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3932 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3933 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3934 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3936 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3937 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3938 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3940 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3941 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3942 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3946 defm SMLA : AI_smld<0, "smla">;
3947 defm SMLS : AI_smld<1, "smls">;
3949 multiclass AI_sdml<bit sub, string opc> {
3951 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3952 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3953 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3954 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3957 defm SMUA : AI_sdml<0, "smua">;
3958 defm SMUS : AI_sdml<1, "smus">;
3960 //===----------------------------------------------------------------------===//
3961 // Division Instructions (ARMv7-A with virtualization extension)
3963 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3964 "sdiv", "\t$Rd, $Rn, $Rm",
3965 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3966 Requires<[IsARM, HasDivideInARM]>;
3968 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3969 "udiv", "\t$Rd, $Rn, $Rm",
3970 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3971 Requires<[IsARM, HasDivideInARM]>;
3973 //===----------------------------------------------------------------------===//
3974 // Misc. Arithmetic Instructions.
3977 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3978 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3979 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
3982 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3983 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3984 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3985 Requires<[IsARM, HasV6T2]>,
3988 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3989 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3990 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
3993 let AddedComplexity = 5 in
3994 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3995 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3996 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3997 Requires<[IsARM, HasV6]>,
4000 let AddedComplexity = 5 in
4001 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
4002 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
4003 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
4004 Requires<[IsARM, HasV6]>,
4007 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
4008 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
4011 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
4012 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4013 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4014 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4015 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
4017 Requires<[IsARM, HasV6]>,
4018 Sched<[WriteALUsi, ReadALU]>;
4020 // Alternate cases for PKHBT where identities eliminate some nodes.
4021 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4022 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4023 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4024 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4026 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
4027 // will match the pattern below.
4028 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
4029 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4030 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4031 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4032 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4034 Requires<[IsARM, HasV6]>,
4035 Sched<[WriteALUsi, ReadALU]>;
4037 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4038 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4039 // We also can not replace a srl (17..31) by an arithmetic shift we would use in
4040 // pkhtb src1, src2, asr (17..31).
4041 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4042 (srl GPRnopc:$src2, imm16:$sh)),
4043 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16:$sh)>;
4044 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4045 (sra GPRnopc:$src2, imm16_31:$sh)),
4046 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4047 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4048 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4049 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4051 //===----------------------------------------------------------------------===//
4052 // Comparison Instructions...
4055 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4056 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4057 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4059 // ARMcmpZ can re-use the above instruction definitions.
4060 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
4061 (CMPri GPR:$src, so_imm:$imm)>;
4062 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4063 (CMPrr GPR:$src, GPR:$rhs)>;
4064 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4065 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4066 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4067 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4069 // CMN register-integer
4070 let isCompare = 1, Defs = [CPSR] in {
4071 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
4072 "cmn", "\t$Rn, $imm",
4073 [(ARMcmn GPR:$Rn, so_imm:$imm)]>,
4074 Sched<[WriteCMP, ReadALU]> {
4079 let Inst{19-16} = Rn;
4080 let Inst{15-12} = 0b0000;
4081 let Inst{11-0} = imm;
4083 let Unpredictable{15-12} = 0b1111;
4086 // CMN register-register/shift
4087 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4088 "cmn", "\t$Rn, $Rm",
4089 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4090 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4093 let isCommutable = 1;
4096 let Inst{19-16} = Rn;
4097 let Inst{15-12} = 0b0000;
4098 let Inst{11-4} = 0b00000000;
4101 let Unpredictable{15-12} = 0b1111;
4104 def CMNzrsi : AI1<0b1011, (outs),
4105 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4106 "cmn", "\t$Rn, $shift",
4107 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4108 GPR:$Rn, so_reg_imm:$shift)]>,
4109 Sched<[WriteCMPsi, ReadALU]> {
4114 let Inst{19-16} = Rn;
4115 let Inst{15-12} = 0b0000;
4116 let Inst{11-5} = shift{11-5};
4118 let Inst{3-0} = shift{3-0};
4120 let Unpredictable{15-12} = 0b1111;
4123 def CMNzrsr : AI1<0b1011, (outs),
4124 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4125 "cmn", "\t$Rn, $shift",
4126 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4127 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4128 Sched<[WriteCMPsr, ReadALU]> {
4133 let Inst{19-16} = Rn;
4134 let Inst{15-12} = 0b0000;
4135 let Inst{11-8} = shift{11-8};
4137 let Inst{6-5} = shift{6-5};
4139 let Inst{3-0} = shift{3-0};
4141 let Unpredictable{15-12} = 0b1111;
4146 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4147 (CMNri GPR:$src, so_imm_neg:$imm)>;
4149 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4150 (CMNri GPR:$src, so_imm_neg:$imm)>;
4152 // Note that TST/TEQ don't set all the same flags that CMP does!
4153 defm TST : AI1_cmp_irs<0b1000, "tst",
4154 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4155 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4156 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4157 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4158 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4160 // Pseudo i64 compares for some floating point compares.
4161 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4163 def BCCi64 : PseudoInst<(outs),
4164 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4166 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>,
4169 def BCCZi64 : PseudoInst<(outs),
4170 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4171 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>,
4173 } // usesCustomInserter
4176 // Conditional moves
4177 let neverHasSideEffects = 1 in {
4179 let isCommutable = 1, isSelect = 1 in
4180 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd),
4181 (ins GPR:$false, GPR:$Rm, cmovpred:$p),
4183 [(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm,
4185 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4187 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4188 (ins GPR:$false, so_reg_imm:$shift, cmovpred:$p),
4191 (ARMcmov GPR:$false, so_reg_imm:$shift,
4193 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4194 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4195 (ins GPR:$false, so_reg_reg:$shift, cmovpred:$p),
4197 [(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4199 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4202 let isMoveImm = 1 in
4204 : ARMPseudoInst<(outs GPR:$Rd),
4205 (ins GPR:$false, imm0_65535_expr:$imm, cmovpred:$p),
4207 [(set GPR:$Rd, (ARMcmov GPR:$false, imm0_65535:$imm,
4209 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4212 let isMoveImm = 1 in
4213 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4214 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4216 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm,
4218 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4220 // Two instruction predicate mov immediate.
4221 let isMoveImm = 1 in
4223 : ARMPseudoInst<(outs GPR:$Rd),
4224 (ins GPR:$false, i32imm:$src, cmovpred:$p),
4226 [(set GPR:$Rd, (ARMcmov GPR:$false, imm:$src,
4228 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4230 let isMoveImm = 1 in
4231 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4232 (ins GPR:$false, so_imm:$imm, cmovpred:$p),
4234 [(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm,
4236 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4238 } // neverHasSideEffects
4241 //===----------------------------------------------------------------------===//
4242 // Atomic operations intrinsics
4245 def MemBarrierOptOperand : AsmOperandClass {
4246 let Name = "MemBarrierOpt";
4247 let ParserMethod = "parseMemBarrierOptOperand";
4249 def memb_opt : Operand<i32> {
4250 let PrintMethod = "printMemBOption";
4251 let ParserMatchClass = MemBarrierOptOperand;
4252 let DecoderMethod = "DecodeMemBarrierOption";
4255 def InstSyncBarrierOptOperand : AsmOperandClass {
4256 let Name = "InstSyncBarrierOpt";
4257 let ParserMethod = "parseInstSyncBarrierOptOperand";
4259 def instsyncb_opt : Operand<i32> {
4260 let PrintMethod = "printInstSyncBOption";
4261 let ParserMatchClass = InstSyncBarrierOptOperand;
4262 let DecoderMethod = "DecodeInstSyncBarrierOption";
4265 // memory barriers protect the atomic sequences
4266 let hasSideEffects = 1 in {
4267 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4268 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4269 Requires<[IsARM, HasDB]> {
4271 let Inst{31-4} = 0xf57ff05;
4272 let Inst{3-0} = opt;
4276 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4277 "dsb", "\t$opt", []>,
4278 Requires<[IsARM, HasDB]> {
4280 let Inst{31-4} = 0xf57ff04;
4281 let Inst{3-0} = opt;
4284 // ISB has only full system option
4285 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
4286 "isb", "\t$opt", []>,
4287 Requires<[IsARM, HasDB]> {
4289 let Inst{31-4} = 0xf57ff06;
4290 let Inst{3-0} = opt;
4293 // Pseudo instruction that combines movs + predicated rsbmi
4294 // to implement integer ABS
4295 let usesCustomInserter = 1, Defs = [CPSR] in
4296 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4298 let usesCustomInserter = 1 in {
4299 let Defs = [CPSR] in {
4300 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4301 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4302 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4303 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4304 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4305 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4306 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4307 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4308 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4309 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4310 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4311 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4312 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4313 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4314 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4315 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4316 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4317 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4318 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4319 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4320 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4321 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4322 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4323 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4324 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4325 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4326 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4327 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4328 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4329 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4330 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4331 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4332 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4333 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4334 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4335 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4336 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4337 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4338 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4339 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4340 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4341 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4342 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4343 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4344 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4345 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4346 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4347 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4348 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4349 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4350 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4351 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4352 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4353 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4354 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4355 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4356 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4357 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4358 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4359 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4360 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4361 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4362 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4363 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4364 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4365 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4366 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4367 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4368 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4369 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4370 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4371 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4372 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4373 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4374 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4375 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4376 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4377 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4378 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4379 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4380 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4381 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4382 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4383 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4384 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4385 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4386 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4387 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4388 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4389 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4391 def ATOMIC_SWAP_I8 : PseudoInst<
4392 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4393 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4394 def ATOMIC_SWAP_I16 : PseudoInst<
4395 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4396 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4397 def ATOMIC_SWAP_I32 : PseudoInst<
4398 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4399 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4401 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4402 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4403 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4404 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4405 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4406 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4407 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4408 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4409 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4413 let usesCustomInserter = 1 in {
4414 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4415 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4417 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4420 def ldrex_1 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4421 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4424 def ldrex_2 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4425 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4428 def ldrex_4 : PatFrag<(ops node:$ptr), (int_arm_ldrex node:$ptr), [{
4429 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4432 def strex_1 : PatFrag<(ops node:$val, node:$ptr),
4433 (int_arm_strex node:$val, node:$ptr), [{
4434 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
4437 def strex_2 : PatFrag<(ops node:$val, node:$ptr),
4438 (int_arm_strex node:$val, node:$ptr), [{
4439 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
4442 def strex_4 : PatFrag<(ops node:$val, node:$ptr),
4443 (int_arm_strex node:$val, node:$ptr), [{
4444 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
4447 let mayLoad = 1 in {
4448 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4449 NoItinerary, "ldrexb", "\t$Rt, $addr",
4450 [(set GPR:$Rt, (ldrex_1 addr_offset_none:$addr))]>;
4451 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4452 NoItinerary, "ldrexh", "\t$Rt, $addr",
4453 [(set GPR:$Rt, (ldrex_2 addr_offset_none:$addr))]>;
4454 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4455 NoItinerary, "ldrex", "\t$Rt, $addr",
4456 [(set GPR:$Rt, (ldrex_4 addr_offset_none:$addr))]>;
4457 let hasExtraDefRegAllocReq = 1 in
4458 def LDREXD : AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4459 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4460 let DecoderMethod = "DecodeDoubleRegLoad";
4463 def LDAEXB : AIldaex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4464 NoItinerary, "ldaexb", "\t$Rt, $addr", []>;
4465 def LDAEXH : AIldaex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4466 NoItinerary, "ldaexh", "\t$Rt, $addr", []>;
4467 def LDAEX : AIldaex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4468 NoItinerary, "ldaex", "\t$Rt, $addr", []>;
4469 let hasExtraDefRegAllocReq = 1 in
4470 def LDAEXD : AIldaex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4471 NoItinerary, "ldaexd", "\t$Rt, $addr", []> {
4472 let DecoderMethod = "DecodeDoubleRegLoad";
4476 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4477 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4478 NoItinerary, "strexb", "\t$Rd, $Rt, $addr",
4479 [(set GPR:$Rd, (strex_1 GPR:$Rt, addr_offset_none:$addr))]>;
4480 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4481 NoItinerary, "strexh", "\t$Rd, $Rt, $addr",
4482 [(set GPR:$Rd, (strex_2 GPR:$Rt, addr_offset_none:$addr))]>;
4483 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4484 NoItinerary, "strex", "\t$Rd, $Rt, $addr",
4485 [(set GPR:$Rd, (strex_4 GPR:$Rt, addr_offset_none:$addr))]>;
4486 let hasExtraSrcRegAllocReq = 1 in
4487 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4488 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4489 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4490 let DecoderMethod = "DecodeDoubleRegStore";
4492 def STLEXB: AIstlex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4493 NoItinerary, "stlexb", "\t$Rd, $Rt, $addr",
4495 def STLEXH: AIstlex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4496 NoItinerary, "stlexh", "\t$Rd, $Rt, $addr",
4498 def STLEX : AIstlex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4499 NoItinerary, "stlex", "\t$Rd, $Rt, $addr",
4501 let hasExtraSrcRegAllocReq = 1 in
4502 def STLEXD : AIstlex<0b01, (outs GPR:$Rd),
4503 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4504 NoItinerary, "stlexd", "\t$Rd, $Rt, $addr", []> {
4505 let DecoderMethod = "DecodeDoubleRegStore";
4509 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
4511 Requires<[IsARM, HasV7]> {
4512 let Inst{31-0} = 0b11110101011111111111000000011111;
4515 def : ARMPat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
4516 (LDREXB addr_offset_none:$addr)>;
4517 def : ARMPat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
4518 (LDREXH addr_offset_none:$addr)>;
4519 def : ARMPat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
4520 (STREXB GPR:$Rt, addr_offset_none:$addr)>;
4521 def : ARMPat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
4522 (STREXH GPR:$Rt, addr_offset_none:$addr)>;
4524 // SWP/SWPB are deprecated in V6/V7.
4525 let mayLoad = 1, mayStore = 1 in {
4526 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4527 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>,
4529 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4530 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>,
4534 //===----------------------------------------------------------------------===//
4535 // Coprocessor Instructions.
4538 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4539 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4540 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4541 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4542 imm:$CRm, imm:$opc2)]> {
4550 let Inst{3-0} = CRm;
4552 let Inst{7-5} = opc2;
4553 let Inst{11-8} = cop;
4554 let Inst{15-12} = CRd;
4555 let Inst{19-16} = CRn;
4556 let Inst{23-20} = opc1;
4559 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4560 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4561 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4562 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4563 imm:$CRm, imm:$opc2)]> {
4564 let Inst{31-28} = 0b1111;
4572 let Inst{3-0} = CRm;
4574 let Inst{7-5} = opc2;
4575 let Inst{11-8} = cop;
4576 let Inst{15-12} = CRd;
4577 let Inst{19-16} = CRn;
4578 let Inst{23-20} = opc1;
4581 class ACI<dag oops, dag iops, string opc, string asm,
4582 IndexMode im = IndexModeNone>
4583 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4585 let Inst{27-25} = 0b110;
4587 class ACInoP<dag oops, dag iops, string opc, string asm,
4588 IndexMode im = IndexModeNone>
4589 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4591 let Inst{31-28} = 0b1111;
4592 let Inst{27-25} = 0b110;
4594 multiclass LdStCop<bit load, bit Dbit, string asm> {
4595 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4596 asm, "\t$cop, $CRd, $addr"> {
4600 let Inst{24} = 1; // P = 1
4601 let Inst{23} = addr{8};
4602 let Inst{22} = Dbit;
4603 let Inst{21} = 0; // W = 0
4604 let Inst{20} = load;
4605 let Inst{19-16} = addr{12-9};
4606 let Inst{15-12} = CRd;
4607 let Inst{11-8} = cop;
4608 let Inst{7-0} = addr{7-0};
4609 let DecoderMethod = "DecodeCopMemInstruction";
4611 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4612 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4616 let Inst{24} = 1; // P = 1
4617 let Inst{23} = addr{8};
4618 let Inst{22} = Dbit;
4619 let Inst{21} = 1; // W = 1
4620 let Inst{20} = load;
4621 let Inst{19-16} = addr{12-9};
4622 let Inst{15-12} = CRd;
4623 let Inst{11-8} = cop;
4624 let Inst{7-0} = addr{7-0};
4625 let DecoderMethod = "DecodeCopMemInstruction";
4627 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4628 postidx_imm8s4:$offset),
4629 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4634 let Inst{24} = 0; // P = 0
4635 let Inst{23} = offset{8};
4636 let Inst{22} = Dbit;
4637 let Inst{21} = 1; // W = 1
4638 let Inst{20} = load;
4639 let Inst{19-16} = addr;
4640 let Inst{15-12} = CRd;
4641 let Inst{11-8} = cop;
4642 let Inst{7-0} = offset{7-0};
4643 let DecoderMethod = "DecodeCopMemInstruction";
4645 def _OPTION : ACI<(outs),
4646 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4647 coproc_option_imm:$option),
4648 asm, "\t$cop, $CRd, $addr, $option"> {
4653 let Inst{24} = 0; // P = 0
4654 let Inst{23} = 1; // U = 1
4655 let Inst{22} = Dbit;
4656 let Inst{21} = 0; // W = 0
4657 let Inst{20} = load;
4658 let Inst{19-16} = addr;
4659 let Inst{15-12} = CRd;
4660 let Inst{11-8} = cop;
4661 let Inst{7-0} = option;
4662 let DecoderMethod = "DecodeCopMemInstruction";
4665 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4666 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4667 asm, "\t$cop, $CRd, $addr"> {
4671 let Inst{24} = 1; // P = 1
4672 let Inst{23} = addr{8};
4673 let Inst{22} = Dbit;
4674 let Inst{21} = 0; // W = 0
4675 let Inst{20} = load;
4676 let Inst{19-16} = addr{12-9};
4677 let Inst{15-12} = CRd;
4678 let Inst{11-8} = cop;
4679 let Inst{7-0} = addr{7-0};
4680 let DecoderMethod = "DecodeCopMemInstruction";
4682 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4683 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4687 let Inst{24} = 1; // P = 1
4688 let Inst{23} = addr{8};
4689 let Inst{22} = Dbit;
4690 let Inst{21} = 1; // W = 1
4691 let Inst{20} = load;
4692 let Inst{19-16} = addr{12-9};
4693 let Inst{15-12} = CRd;
4694 let Inst{11-8} = cop;
4695 let Inst{7-0} = addr{7-0};
4696 let DecoderMethod = "DecodeCopMemInstruction";
4698 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4699 postidx_imm8s4:$offset),
4700 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4705 let Inst{24} = 0; // P = 0
4706 let Inst{23} = offset{8};
4707 let Inst{22} = Dbit;
4708 let Inst{21} = 1; // W = 1
4709 let Inst{20} = load;
4710 let Inst{19-16} = addr;
4711 let Inst{15-12} = CRd;
4712 let Inst{11-8} = cop;
4713 let Inst{7-0} = offset{7-0};
4714 let DecoderMethod = "DecodeCopMemInstruction";
4716 def _OPTION : ACInoP<(outs),
4717 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4718 coproc_option_imm:$option),
4719 asm, "\t$cop, $CRd, $addr, $option"> {
4724 let Inst{24} = 0; // P = 0
4725 let Inst{23} = 1; // U = 1
4726 let Inst{22} = Dbit;
4727 let Inst{21} = 0; // W = 0
4728 let Inst{20} = load;
4729 let Inst{19-16} = addr;
4730 let Inst{15-12} = CRd;
4731 let Inst{11-8} = cop;
4732 let Inst{7-0} = option;
4733 let DecoderMethod = "DecodeCopMemInstruction";
4737 defm LDC : LdStCop <1, 0, "ldc">;
4738 defm LDCL : LdStCop <1, 1, "ldcl">;
4739 defm STC : LdStCop <0, 0, "stc">;
4740 defm STCL : LdStCop <0, 1, "stcl">;
4741 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4742 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4743 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4744 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4746 //===----------------------------------------------------------------------===//
4747 // Move between coprocessor and ARM core register.
4750 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4752 : ABI<0b1110, oops, iops, NoItinerary, opc,
4753 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4754 let Inst{20} = direction;
4764 let Inst{15-12} = Rt;
4765 let Inst{11-8} = cop;
4766 let Inst{23-21} = opc1;
4767 let Inst{7-5} = opc2;
4768 let Inst{3-0} = CRm;
4769 let Inst{19-16} = CRn;
4772 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4774 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4775 c_imm:$CRm, imm0_7:$opc2),
4776 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4777 imm:$CRm, imm:$opc2)]>;
4778 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4779 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4780 c_imm:$CRm, 0, pred:$p)>;
4781 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4782 (outs GPRwithAPSR:$Rt),
4783 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4785 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4786 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4787 c_imm:$CRm, 0, pred:$p)>;
4789 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4790 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4792 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4794 : ABXI<0b1110, oops, iops, NoItinerary,
4795 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4796 let Inst{31-24} = 0b11111110;
4797 let Inst{20} = direction;
4807 let Inst{15-12} = Rt;
4808 let Inst{11-8} = cop;
4809 let Inst{23-21} = opc1;
4810 let Inst{7-5} = opc2;
4811 let Inst{3-0} = CRm;
4812 let Inst{19-16} = CRn;
4815 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4817 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4818 c_imm:$CRm, imm0_7:$opc2),
4819 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4820 imm:$CRm, imm:$opc2)]>;
4821 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4822 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4824 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4825 (outs GPRwithAPSR:$Rt),
4826 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4828 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4829 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4832 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4833 imm:$CRm, imm:$opc2),
4834 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4836 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4837 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4838 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4839 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4840 let Inst{23-21} = 0b010;
4841 let Inst{20} = direction;
4849 let Inst{15-12} = Rt;
4850 let Inst{19-16} = Rt2;
4851 let Inst{11-8} = cop;
4852 let Inst{7-4} = opc1;
4853 let Inst{3-0} = CRm;
4856 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4857 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4858 GPRnopc:$Rt2, imm:$CRm)]>;
4859 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4861 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4862 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4863 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4864 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4865 let Inst{31-28} = 0b1111;
4866 let Inst{23-21} = 0b010;
4867 let Inst{20} = direction;
4875 let Inst{15-12} = Rt;
4876 let Inst{19-16} = Rt2;
4877 let Inst{11-8} = cop;
4878 let Inst{7-4} = opc1;
4879 let Inst{3-0} = CRm;
4881 let DecoderMethod = "DecodeMRRC2";
4884 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4885 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4886 GPRnopc:$Rt2, imm:$CRm)]>;
4887 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4889 //===----------------------------------------------------------------------===//
4890 // Move between special register and ARM core register
4893 // Move to ARM core register from Special Register
4894 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4895 "mrs", "\t$Rd, apsr", []> {
4897 let Inst{23-16} = 0b00001111;
4898 let Unpredictable{19-17} = 0b111;
4900 let Inst{15-12} = Rd;
4902 let Inst{11-0} = 0b000000000000;
4903 let Unpredictable{11-0} = 0b110100001111;
4906 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4909 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4910 // section B9.3.9, with the R bit set to 1.
4911 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4912 "mrs", "\t$Rd, spsr", []> {
4914 let Inst{23-16} = 0b01001111;
4915 let Unpredictable{19-16} = 0b1111;
4917 let Inst{15-12} = Rd;
4919 let Inst{11-0} = 0b000000000000;
4920 let Unpredictable{11-0} = 0b110100001111;
4923 // Move from ARM core register to Special Register
4925 // No need to have both system and application versions, the encodings are the
4926 // same and the assembly parser has no way to distinguish between them. The mask
4927 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4928 // the mask with the fields to be accessed in the special register.
4929 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4930 "msr", "\t$mask, $Rn", []> {
4935 let Inst{22} = mask{4}; // R bit
4936 let Inst{21-20} = 0b10;
4937 let Inst{19-16} = mask{3-0};
4938 let Inst{15-12} = 0b1111;
4939 let Inst{11-4} = 0b00000000;
4943 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4944 "msr", "\t$mask, $a", []> {
4949 let Inst{22} = mask{4}; // R bit
4950 let Inst{21-20} = 0b10;
4951 let Inst{19-16} = mask{3-0};
4952 let Inst{15-12} = 0b1111;
4956 //===----------------------------------------------------------------------===//
4960 // __aeabi_read_tp preserves the registers r1-r3.
4961 // This is a pseudo inst so that we can get the encoding right,
4962 // complete with fixup for the aeabi_read_tp function.
4964 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4965 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4966 [(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
4969 //===----------------------------------------------------------------------===//
4970 // SJLJ Exception handling intrinsics
4971 // eh_sjlj_setjmp() is an instruction sequence to store the return
4972 // address and save #0 in R0 for the non-longjmp case.
4973 // Since by its nature we may be coming from some other function to get
4974 // here, and we're using the stack frame for the containing function to
4975 // save/restore registers, we can't keep anything live in regs across
4976 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4977 // when we get here from a longjmp(). We force everything out of registers
4978 // except for our own input by listing the relevant registers in Defs. By
4979 // doing so, we also cause the prologue/epilogue code to actively preserve
4980 // all of the callee-saved resgisters, which is exactly what we want.
4981 // A constant value is passed in $val, and we use the location as a scratch.
4983 // These are pseudo-instructions and are lowered to individual MC-insts, so
4984 // no encoding information is necessary.
4986 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4987 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4988 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4989 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4991 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4992 Requires<[IsARM, HasVFP2]>;
4996 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4997 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4998 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
5000 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
5001 Requires<[IsARM, NoVFP]>;
5004 // FIXME: Non-IOS version(s)
5005 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
5006 Defs = [ R7, LR, SP ] in {
5007 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
5009 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
5010 Requires<[IsARM, IsIOS]>;
5013 // eh.sjlj.dispatchsetup pseudo-instruction.
5014 // This pseudo is used for both ARM and Thumb. Any differences are handled when
5015 // the pseudo is expanded (which happens before any passes that need the
5016 // instruction size).
5017 let isBarrier = 1 in
5018 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
5021 //===----------------------------------------------------------------------===//
5022 // Non-Instruction Patterns
5025 // ARMv4 indirect branch using (MOVr PC, dst)
5026 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
5027 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
5028 4, IIC_Br, [(brind GPR:$dst)],
5029 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
5030 Requires<[IsARM, NoV4T]>, Sched<[WriteBr]>;
5032 // Large immediate handling.
5034 // 32-bit immediate using two piece so_imms or movw + movt.
5035 // This is a single pseudo instruction, the benefit is that it can be remat'd
5036 // as a single unit instead of having to handle reg inputs.
5037 // FIXME: Remove this when we can do generalized remat.
5038 let isReMaterializable = 1, isMoveImm = 1 in
5039 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
5040 [(set GPR:$dst, (arm_i32imm:$src))]>,
5043 // Pseudo instruction that combines movw + movt + add pc (if PIC).
5044 // It also makes it possible to rematerialize the instructions.
5045 // FIXME: Remove this when we can do generalized remat and when machine licm
5046 // can properly the instructions.
5047 let isReMaterializable = 1 in {
5048 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5050 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
5051 Requires<[IsARM, UseMovt]>;
5053 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5055 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
5056 Requires<[IsARM, UseMovt]>;
5058 let AddedComplexity = 10 in
5059 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
5061 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
5062 Requires<[IsARM, UseMovt]>;
5063 } // isReMaterializable
5065 // ConstantPool, GlobalAddress, and JumpTable
5066 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
5067 Requires<[IsARM, DontUseMovt]>;
5068 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
5069 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
5070 Requires<[IsARM, UseMovt]>;
5071 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
5072 (LEApcrelJT tjumptable:$dst, imm:$id)>;
5074 // TODO: add,sub,and, 3-instr forms?
5076 // Tail calls. These patterns also apply to Thumb mode.
5077 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
5078 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
5079 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
5082 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
5083 def : ARMPat<(ARMcall_nolink texternalsym:$func),
5084 (BMOVPCB_CALL texternalsym:$func)>;
5086 // zextload i1 -> zextload i8
5087 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5088 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5090 // extload -> zextload
5091 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5092 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5093 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
5094 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
5096 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
5098 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
5099 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
5102 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5103 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5104 (SMULBB GPR:$a, GPR:$b)>;
5105 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5106 (SMULBB GPR:$a, GPR:$b)>;
5107 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5108 (sra GPR:$b, (i32 16))),
5109 (SMULBT GPR:$a, GPR:$b)>;
5110 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5111 (SMULBT GPR:$a, GPR:$b)>;
5112 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
5113 (sra (shl GPR:$b, (i32 16)), (i32 16))),
5114 (SMULTB GPR:$a, GPR:$b)>;
5115 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5116 (SMULTB GPR:$a, GPR:$b)>;
5117 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5119 (SMULWB GPR:$a, GPR:$b)>;
5120 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
5121 (SMULWB GPR:$a, GPR:$b)>;
5123 def : ARMV5MOPat<(add GPR:$acc,
5124 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5125 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5126 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5127 def : ARMV5MOPat<(add GPR:$acc,
5128 (mul sext_16_node:$a, sext_16_node:$b)),
5129 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5130 def : ARMV5MOPat<(add GPR:$acc,
5131 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5132 (sra GPR:$b, (i32 16)))),
5133 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5134 def : ARMV5MOPat<(add GPR:$acc,
5135 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5136 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5137 def : ARMV5MOPat<(add GPR:$acc,
5138 (mul (sra GPR:$a, (i32 16)),
5139 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5140 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5141 def : ARMV5MOPat<(add GPR:$acc,
5142 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5143 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5144 def : ARMV5MOPat<(add GPR:$acc,
5145 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5147 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5148 def : ARMV5MOPat<(add GPR:$acc,
5149 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
5150 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5153 // Pre-v7 uses MCR for synchronization barriers.
5154 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5155 Requires<[IsARM, HasV6]>;
5157 // SXT/UXT with no rotate
5158 let AddedComplexity = 16 in {
5159 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5160 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5161 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5162 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5163 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5164 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5165 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5168 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5169 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5171 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5172 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5173 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5174 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5176 // Atomic load/store patterns
5177 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5178 (LDRBrs ldst_so_reg:$src)>;
5179 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5180 (LDRBi12 addrmode_imm12:$src)>;
5181 def : ARMPat<(atomic_load_16 addrmode3:$src),
5182 (LDRH addrmode3:$src)>;
5183 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5184 (LDRrs ldst_so_reg:$src)>;
5185 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5186 (LDRi12 addrmode_imm12:$src)>;
5187 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5188 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5189 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5190 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5191 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5192 (STRH GPR:$val, addrmode3:$ptr)>;
5193 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5194 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5195 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5196 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5199 //===----------------------------------------------------------------------===//
5203 include "ARMInstrThumb.td"
5205 //===----------------------------------------------------------------------===//
5209 include "ARMInstrThumb2.td"
5211 //===----------------------------------------------------------------------===//
5212 // Floating Point Support
5215 include "ARMInstrVFP.td"
5217 //===----------------------------------------------------------------------===//
5218 // Advanced SIMD (NEON) Support
5221 include "ARMInstrNEON.td"
5223 //===----------------------------------------------------------------------===//
5224 // Assembler aliases
5228 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5229 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5230 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5232 // System instructions
5233 def : MnemonicAlias<"swi", "svc">;
5235 // Load / Store Multiple
5236 def : MnemonicAlias<"ldmfd", "ldm">;
5237 def : MnemonicAlias<"ldmia", "ldm">;
5238 def : MnemonicAlias<"ldmea", "ldmdb">;
5239 def : MnemonicAlias<"stmfd", "stmdb">;
5240 def : MnemonicAlias<"stmia", "stm">;
5241 def : MnemonicAlias<"stmea", "stm">;
5243 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5244 // shift amount is zero (i.e., unspecified).
5245 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5246 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5247 Requires<[IsARM, HasV6]>;
5248 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5249 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5250 Requires<[IsARM, HasV6]>;
5252 // PUSH/POP aliases for STM/LDM
5253 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5254 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5256 // SSAT/USAT optional shift operand.
5257 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5258 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5259 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5260 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5263 // Extend instruction optional rotate operand.
5264 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5265 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5266 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5267 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5268 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5269 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5270 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5271 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5272 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5273 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5274 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5275 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5277 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5278 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5279 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5280 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5281 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5282 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5283 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5284 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5285 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5286 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5287 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5288 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5292 def : MnemonicAlias<"rfefa", "rfeda">;
5293 def : MnemonicAlias<"rfeea", "rfedb">;
5294 def : MnemonicAlias<"rfefd", "rfeia">;
5295 def : MnemonicAlias<"rfeed", "rfeib">;
5296 def : MnemonicAlias<"rfe", "rfeia">;
5299 def : MnemonicAlias<"srsfa", "srsib">;
5300 def : MnemonicAlias<"srsea", "srsia">;
5301 def : MnemonicAlias<"srsfd", "srsdb">;
5302 def : MnemonicAlias<"srsed", "srsda">;
5303 def : MnemonicAlias<"srs", "srsia">;
5306 def : MnemonicAlias<"qsubaddx", "qsax">;
5308 def : MnemonicAlias<"saddsubx", "sasx">;
5309 // SHASX == SHADDSUBX
5310 def : MnemonicAlias<"shaddsubx", "shasx">;
5311 // SHSAX == SHSUBADDX
5312 def : MnemonicAlias<"shsubaddx", "shsax">;
5314 def : MnemonicAlias<"ssubaddx", "ssax">;
5316 def : MnemonicAlias<"uaddsubx", "uasx">;
5317 // UHASX == UHADDSUBX
5318 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5319 // UHSAX == UHSUBADDX
5320 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5321 // UQASX == UQADDSUBX
5322 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5323 // UQSAX == UQSUBADDX
5324 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5326 def : MnemonicAlias<"usubaddx", "usax">;
5328 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5330 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5331 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5332 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5333 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5334 // Same for AND <--> BIC
5335 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5336 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5337 pred:$p, cc_out:$s)>;
5338 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5339 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5340 pred:$p, cc_out:$s)>;
5341 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5342 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5343 pred:$p, cc_out:$s)>;
5344 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5345 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5346 pred:$p, cc_out:$s)>;
5348 // Likewise, "add Rd, so_imm_neg" -> sub
5349 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5350 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5351 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5352 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5353 // Same for CMP <--> CMN via so_imm_neg
5354 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5355 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5356 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5357 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5359 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5360 // LSR, ROR, and RRX instructions.
5361 // FIXME: We need C++ parser hooks to map the alias to the MOV
5362 // encoding. It seems we should be able to do that sort of thing
5363 // in tblgen, but it could get ugly.
5364 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5365 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5366 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5368 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5369 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5371 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5372 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5374 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5375 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5378 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5379 (ins GPR:$Rd, GPR:$Rm, pred:$p, cc_out:$s)>;
5380 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5381 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5382 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5384 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5385 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5387 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5388 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5390 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5391 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5395 // "neg" is and alias for "rsb rd, rn, #0"
5396 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5397 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5399 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5400 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5401 Requires<[IsARM, NoV6]>;
5403 // UMULL/SMULL are available on all arches, but the instruction definitions
5404 // need difference constraints pre-v6. Use these aliases for the assembly
5405 // parsing on pre-v6.
5406 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5407 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5408 Requires<[IsARM, NoV6]>;
5409 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5410 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5411 Requires<[IsARM, NoV6]>;
5413 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5415 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;