1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
39 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
42 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
43 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
46 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
47 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
49 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
50 [SDNPHasChain, SDNPOutFlag]>;
51 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
52 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
54 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
55 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
56 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
57 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
61 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
62 [SDNPHasChain, SDNPOptInFlag]>;
64 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
66 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
69 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
70 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
72 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
75 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
78 def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
81 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
83 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
84 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
85 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
87 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
88 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
90 //===----------------------------------------------------------------------===//
91 // ARM Instruction Predicate Definitions.
93 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
94 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
95 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
96 def IsThumb : Predicate<"Subtarget->isThumb()">;
97 def HasThumb2 : Predicate<"Subtarget->hasThumb2()">;
98 def IsARM : Predicate<"!Subtarget->isThumb()">;
99 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
100 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
102 //===----------------------------------------------------------------------===//
103 // ARM Flag Definitions.
105 class RegConstraint<string C> {
106 string Constraints = C;
109 //===----------------------------------------------------------------------===//
110 // ARM specific transformation functions and pattern fragments.
113 // so_imm_XFORM - Return a so_imm value packed into the format described for
115 def so_imm_XFORM : SDNodeXForm<imm, [{
116 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getZExtValue()),
120 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
121 // so_imm_neg def below.
122 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
123 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getZExtValue()),
127 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
128 // so_imm_not def below.
129 def so_imm_not_XFORM : SDNodeXForm<imm, [{
130 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getZExtValue()),
134 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
135 def rot_imm : PatLeaf<(i32 imm), [{
136 int32_t v = (int32_t)N->getZExtValue();
137 return v == 8 || v == 16 || v == 24;
140 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
141 def imm1_15 : PatLeaf<(i32 imm), [{
142 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
145 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
146 def imm16_31 : PatLeaf<(i32 imm), [{
147 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
152 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
153 }], so_imm_neg_XFORM>;
157 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
158 }], so_imm_not_XFORM>;
160 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
161 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
162 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
165 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
166 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
168 //===----------------------------------------------------------------------===//
169 // Operand Definitions.
173 def brtarget : Operand<OtherVT>;
175 // A list of registers separated by comma. Used by load/store multiple.
176 def reglist : Operand<i32> {
177 let PrintMethod = "printRegisterList";
180 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
181 def cpinst_operand : Operand<i32> {
182 let PrintMethod = "printCPInstOperand";
185 def jtblock_operand : Operand<i32> {
186 let PrintMethod = "printJTBlockOperand";
190 def pclabel : Operand<i32> {
191 let PrintMethod = "printPCLabel";
194 // shifter_operand operands: so_reg and so_imm.
195 def so_reg : Operand<i32>, // reg reg imm
196 ComplexPattern<i32, 3, "SelectShifterOperandReg",
197 [shl,srl,sra,rotr]> {
198 let PrintMethod = "printSORegOperand";
199 let MIOperandInfo = (ops GPR, GPR, i32imm);
202 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
203 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
204 // represented in the imm field in the same 12-bit form that they are encoded
205 // into so_imm instructions: the 8-bit immediate is the least significant bits
206 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
207 def so_imm : Operand<i32>,
209 [{ return ARM_AM::getSOImmVal(N->getZExtValue()) != -1; }],
211 let PrintMethod = "printSOImmOperand";
214 // Break so_imm's up into two pieces. This handles immediates with up to 16
215 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
216 // get the first/second pieces.
217 def so_imm2part : Operand<i32>,
219 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
221 let PrintMethod = "printSOImm2PartOperand";
224 def so_imm2part_1 : SDNodeXForm<imm, [{
225 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
226 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
229 def so_imm2part_2 : SDNodeXForm<imm, [{
230 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
231 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
235 // Define ARM specific addressing modes.
237 // addrmode2 := reg +/- reg shop imm
238 // addrmode2 := reg +/- imm12
240 def addrmode2 : Operand<i32>,
241 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
242 let PrintMethod = "printAddrMode2Operand";
243 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
246 def am2offset : Operand<i32>,
247 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
248 let PrintMethod = "printAddrMode2OffsetOperand";
249 let MIOperandInfo = (ops GPR, i32imm);
252 // addrmode3 := reg +/- reg
253 // addrmode3 := reg +/- imm8
255 def addrmode3 : Operand<i32>,
256 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
257 let PrintMethod = "printAddrMode3Operand";
258 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
261 def am3offset : Operand<i32>,
262 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
263 let PrintMethod = "printAddrMode3OffsetOperand";
264 let MIOperandInfo = (ops GPR, i32imm);
267 // addrmode4 := reg, <mode|W>
269 def addrmode4 : Operand<i32>,
270 ComplexPattern<i32, 2, "", []> {
271 let PrintMethod = "printAddrMode4Operand";
272 let MIOperandInfo = (ops GPR, i32imm);
275 // addrmode5 := reg +/- imm8*4
277 def addrmode5 : Operand<i32>,
278 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
279 let PrintMethod = "printAddrMode5Operand";
280 let MIOperandInfo = (ops GPR, i32imm);
283 // addrmodepc := pc + reg
285 def addrmodepc : Operand<i32>,
286 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
287 let PrintMethod = "printAddrModePCOperand";
288 let MIOperandInfo = (ops GPR, i32imm);
291 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
292 // register whose default is 0 (no register).
293 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
294 (ops (i32 14), (i32 zero_reg))> {
295 let PrintMethod = "printPredicateOperand";
298 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
300 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
301 let PrintMethod = "printSBitModifierOperand";
304 //===----------------------------------------------------------------------===//
305 // ARM Instruction flags. These need to match ARMInstrInfo.h.
309 class AddrMode<bits<4> val> {
312 def AddrModeNone : AddrMode<0>;
313 def AddrMode1 : AddrMode<1>;
314 def AddrMode2 : AddrMode<2>;
315 def AddrMode3 : AddrMode<3>;
316 def AddrMode4 : AddrMode<4>;
317 def AddrMode5 : AddrMode<5>;
318 def AddrModeT1 : AddrMode<6>;
319 def AddrModeT2 : AddrMode<7>;
320 def AddrModeT4 : AddrMode<8>;
321 def AddrModeTs : AddrMode<9>;
324 class SizeFlagVal<bits<3> val> {
327 def SizeInvalid : SizeFlagVal<0>; // Unset.
328 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
329 def Size8Bytes : SizeFlagVal<2>;
330 def Size4Bytes : SizeFlagVal<3>;
331 def Size2Bytes : SizeFlagVal<4>;
333 // Load / store index mode.
334 class IndexMode<bits<2> val> {
337 def IndexModeNone : IndexMode<0>;
338 def IndexModePre : IndexMode<1>;
339 def IndexModePost : IndexMode<2>;
341 //===----------------------------------------------------------------------===//
343 include "ARMInstrFormats.td"
345 //===----------------------------------------------------------------------===//
346 // Multiclass helpers...
349 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
350 /// binop that produces a value.
351 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
352 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
353 opc, " $dst, $a, $b",
354 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
355 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
356 opc, " $dst, $a, $b",
357 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
358 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
359 opc, " $dst, $a, $b",
360 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
363 /// ASI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
364 /// instruction modifies the CSPR register.
365 let Defs = [CPSR] in {
366 multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
367 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
368 opc, "s $dst, $a, $b",
369 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
370 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
371 opc, "s $dst, $a, $b",
372 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
373 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
374 opc, "s $dst, $a, $b",
375 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
379 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
380 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
381 /// a explicit result, only implicitly set CPSR.
382 let Defs = [CPSR] in {
383 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
384 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm,
386 [(opnode GPR:$a, so_imm:$b)]>;
387 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm,
389 [(opnode GPR:$a, GPR:$b)]>;
390 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
392 [(opnode GPR:$a, so_reg:$b)]>;
396 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
397 /// register and one whose operand is a register rotated by 8/16/24.
398 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
399 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
400 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src),
402 [(set GPR:$dst, (opnode GPR:$Src))]>,
403 Requires<[IsARM, HasV6]> {
404 let Inst{19-16} = 0b1111;
406 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot),
407 opc, " $dst, $Src, ror $rot",
408 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
409 Requires<[IsARM, HasV6]> {
410 let Inst{19-16} = 0b1111;
414 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
415 /// register and one whose operand is a register rotated by 8/16/24.
416 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
417 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
418 opc, " $dst, $LHS, $RHS",
419 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
420 Requires<[IsARM, HasV6]>;
421 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
422 opc, " $dst, $LHS, $RHS, ror $rot",
423 [(set GPR:$dst, (opnode GPR:$LHS,
424 (rotr GPR:$RHS, rot_imm:$rot)))]>,
425 Requires<[IsARM, HasV6]>;
428 /// AsXI1_bin_c_irs - Same as AsI1_bin_irs but without the predicate operand and
429 /// setting carry bit. But it can optionally set CPSR.
430 let Uses = [CPSR] in {
431 multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
432 def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
433 DPFrm, !strconcat(opc, "${s} $dst, $a, $b"),
434 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
435 def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
436 DPFrm, !strconcat(opc, "${s} $dst, $a, $b"),
437 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
438 def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
439 DPSoRegFrm, !strconcat(opc, "${s} $dst, $a, $b"),
440 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
444 //===----------------------------------------------------------------------===//
446 //===----------------------------------------------------------------------===//
448 //===----------------------------------------------------------------------===//
449 // Miscellaneous Instructions.
452 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
453 /// the function. The first operand is the ID# for this instruction, the second
454 /// is the index into the MachineConstantPool that this is, the third is the
455 /// size in bytes of this constant pool entry.
456 let neverHasSideEffects = 1, isNotDuplicable = 1 in
457 def CONSTPOOL_ENTRY :
458 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
460 "${instid:label} ${cpidx:cpentry}", []>;
462 let Defs = [SP], Uses = [SP] in {
464 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p),
465 "@ ADJCALLSTACKUP $amt1",
466 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
468 def ADJCALLSTACKDOWN :
469 PseudoInst<(outs), (ins i32imm:$amt, pred:$p),
470 "@ ADJCALLSTACKDOWN $amt",
471 [(ARMcallseq_start timm:$amt)]>;
475 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
476 ".loc $file, $line, $col",
477 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
480 // Address computation and loads and stores in PIC mode.
481 let isNotDuplicable = 1 in {
482 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
483 Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
484 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
486 let AddedComplexity = 10 in {
487 let canFoldAsLoad = 1 in
488 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
489 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
490 [(set GPR:$dst, (load addrmodepc:$addr))]>;
492 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
493 Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
494 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
496 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
497 Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
498 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
500 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
501 Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
502 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
504 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
505 Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
506 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
508 let AddedComplexity = 10 in {
509 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
510 Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
511 [(store GPR:$src, addrmodepc:$addr)]>;
513 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
514 Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
515 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
517 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
518 Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
519 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
521 } // isNotDuplicable = 1
523 //===----------------------------------------------------------------------===//
524 // Control Flow Instructions.
527 let isReturn = 1, isTerminator = 1 in
528 def BX_RET : AI<(outs), (ins), BrMiscFrm, "bx", " lr", [(ARMretflag)]> {
529 let Inst{7-4} = 0b0001;
530 let Inst{19-8} = 0b111111111111;
531 let Inst{27-20} = 0b00010010;
534 // FIXME: remove when we have a way to marking a MI with these properties.
535 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
537 // FIXME: Should pc be an implicit operand like PICADD, etc?
538 let isReturn = 1, isTerminator = 1 in
539 def LDM_RET : AXI4ld<(outs),
540 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
541 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
544 // On non-Darwin platforms R9 is callee-saved.
545 let isCall = 1, Itinerary = IIC_Br,
546 Defs = [R0, R1, R2, R3, R12, LR,
547 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
548 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
550 [(ARMcall tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
552 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
553 "bl", " ${func:call}",
554 [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsNotDarwin]>;
557 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
559 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsNotDarwin]> {
560 let Inst{7-4} = 0b0011;
561 let Inst{19-8} = 0b111111111111;
562 let Inst{27-20} = 0b00010010;
567 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
568 "mov lr, pc\n\tbx $func",
569 [(ARMcall_nolink GPR:$func)]>, Requires<[IsNotDarwin]>;
573 // On Darwin R9 is call-clobbered.
574 let isCall = 1, Itinerary = IIC_Br,
575 Defs = [R0, R1, R2, R3, R9, R12, LR,
576 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
577 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
579 [(ARMcall tglobaladdr:$func)]>, Requires<[IsDarwin]>;
581 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
582 "bl", " ${func:call}",
583 [(ARMcall_pred tglobaladdr:$func)]>, Requires<[IsDarwin]>;
586 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
588 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
589 let Inst{7-4} = 0b0011;
590 let Inst{19-8} = 0b111111111111;
591 let Inst{27-20} = 0b00010010;
596 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
597 "mov lr, pc\n\tbx $func",
598 [(ARMcall_nolink GPR:$func)]>, Requires<[IsDarwin]>;
602 let isBranch = 1, isTerminator = 1, Itinerary = IIC_Br in {
603 // B is "predicable" since it can be xformed into a Bcc.
604 let isBarrier = 1 in {
605 let isPredicable = 1 in
606 def B : ABXI<0b1010, (outs), (ins brtarget:$target), "b $target",
609 let isNotDuplicable = 1, isIndirectBranch = 1 in {
610 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
611 "mov pc, $target \n$jt",
612 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
613 let Inst{20} = 0; // S Bit
614 let Inst{24-21} = 0b1101;
615 let Inst{27-26} = {0,0};
617 def BR_JTm : JTI<(outs),
618 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
619 "ldr pc, $target \n$jt",
620 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
622 let Inst{20} = 1; // L bit
623 let Inst{21} = 0; // W bit
624 let Inst{22} = 0; // B bit
625 let Inst{24} = 1; // P bit
626 let Inst{27-26} = {0,1};
628 def BR_JTadd : JTI<(outs),
629 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
630 "add pc, $target, $idx \n$jt",
631 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
633 let Inst{20} = 0; // S bit
634 let Inst{24-21} = 0b0100;
635 let Inst{27-26} = {0,0};
637 } // isNotDuplicable = 1, isIndirectBranch = 1
640 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
641 // a two-value operand where a dag node expects two operands. :(
642 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
644 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
647 //===----------------------------------------------------------------------===//
648 // Load / store Instructions.
652 let canFoldAsLoad = 1 in
653 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
654 "ldr", " $dst, $addr",
655 [(set GPR:$dst, (load addrmode2:$addr))]>;
657 // Special LDR for loads from non-pc-relative constpools.
658 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
659 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
660 "ldr", " $dst, $addr", []>;
662 // Loads with zero extension
663 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
664 "ldr", "h $dst, $addr",
665 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
667 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
668 "ldr", "b $dst, $addr",
669 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
671 // Loads with sign extension
672 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
673 "ldr", "sh $dst, $addr",
674 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
676 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
677 "ldr", "sb $dst, $addr",
678 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
682 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
683 "ldr", "d $dst1, $addr", []>, Requires<[IsARM, HasV5T]>;
686 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
687 (ins addrmode2:$addr), LdFrm,
688 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
690 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
691 (ins GPR:$base, am2offset:$offset), LdFrm,
692 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
694 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
695 (ins addrmode3:$addr), LdMiscFrm,
696 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
698 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
699 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
700 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
702 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
703 (ins addrmode2:$addr), LdFrm,
704 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
706 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
707 (ins GPR:$base,am2offset:$offset), LdFrm,
708 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
710 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
711 (ins addrmode3:$addr), LdMiscFrm,
712 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
714 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
715 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
716 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
718 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
719 (ins addrmode3:$addr), LdMiscFrm,
720 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
722 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
723 (ins GPR:$base,am3offset:$offset), LdMiscFrm,
724 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
728 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
729 "str", " $src, $addr",
730 [(store GPR:$src, addrmode2:$addr)]>;
732 // Stores with truncate
733 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
734 "str", "h $src, $addr",
735 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
737 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
738 "str", "b $src, $addr",
739 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
743 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),StMiscFrm,
744 "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5T]>;
747 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
748 (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
749 "str", " $src, [$base, $offset]!", "$base = $base_wb",
751 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
753 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
754 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
755 "str", " $src, [$base], $offset", "$base = $base_wb",
757 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
759 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
760 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
761 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
763 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
765 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
766 (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
767 "str", "h $src, [$base], $offset", "$base = $base_wb",
768 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
769 GPR:$base, am3offset:$offset))]>;
771 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
772 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
773 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
774 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
775 GPR:$base, am2offset:$offset))]>;
777 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
778 (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
779 "str", "b $src, [$base], $offset", "$base = $base_wb",
780 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
781 GPR:$base, am2offset:$offset))]>;
783 //===----------------------------------------------------------------------===//
784 // Load / store multiple Instructions.
787 // FIXME: $dst1 should be a def.
789 def LDM : AXI4ld<(outs),
790 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
791 LdStMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
795 def STM : AXI4st<(outs),
796 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
797 LdStMulFrm, "stm${p}${addr:submode} $addr, $src1",
800 //===----------------------------------------------------------------------===//
801 // Move Instructions.
804 let neverHasSideEffects = 1 in
805 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm,
806 "mov", " $dst, $src", []>, UnaryDP;
807 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
808 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP;
810 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
811 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm,
812 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP;
814 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
815 "mov", " $dst, $src, rrx",
816 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
818 // These aren't really mov instructions, but we have to define them this way
819 // due to flag operands.
821 let Defs = [CPSR] in {
822 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
823 "mov", "s $dst, $src, lsr #1",
824 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
825 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
826 "mov", "s $dst, $src, asr #1",
827 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
830 //===----------------------------------------------------------------------===//
831 // Extend Instructions.
836 defm SXTB : AI_unary_rrot<0b01101010,
837 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
838 defm SXTH : AI_unary_rrot<0b01101011,
839 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
841 defm SXTAB : AI_bin_rrot<0b01101010,
842 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
843 defm SXTAH : AI_bin_rrot<0b01101011,
844 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
846 // TODO: SXT(A){B|H}16
850 let AddedComplexity = 16 in {
851 defm UXTB : AI_unary_rrot<0b01101110,
852 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
853 defm UXTH : AI_unary_rrot<0b01101111,
854 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
855 defm UXTB16 : AI_unary_rrot<0b01101100,
856 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
858 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
859 (UXTB16r_rot GPR:$Src, 24)>;
860 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
861 (UXTB16r_rot GPR:$Src, 8)>;
863 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
864 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
865 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
866 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
869 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
870 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
872 // TODO: UXT(A){B|H}16
874 //===----------------------------------------------------------------------===//
875 // Arithmetic Instructions.
878 defm ADD : AsI1_bin_irs<0b0100, "add",
879 BinOpFrag<(add node:$LHS, node:$RHS)>>;
880 defm SUB : AsI1_bin_irs<0b0010, "sub",
881 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
883 // ADD and SUB with 's' bit set.
884 defm ADDS : ASI1_bin_s_irs<0b0100, "add",
885 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
886 defm SUBS : ASI1_bin_s_irs<0b0010, "sub",
887 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
889 // FIXME: Do not allow ADC / SBC to be predicated for now.
890 defm ADC : AsXI1_bin_c_irs<0b0101, "adc",
891 BinOpFrag<(adde node:$LHS, node:$RHS)>>;
892 defm SBC : AsXI1_bin_c_irs<0b0110, "sbc",
893 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
895 // These don't define reg/reg forms, because they are handled above.
896 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
897 "rsb", " $dst, $a, $b",
898 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
900 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
901 "rsb", " $dst, $a, $b",
902 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
904 // RSB with 's' bit set.
905 let Defs = [CPSR] in {
906 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
907 "rsb", "s $dst, $a, $b",
908 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
909 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
910 "rsb", "s $dst, $a, $b",
911 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
914 // FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
915 let Uses = [CPSR] in {
916 def RSCri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
917 DPFrm, "rsc${s} $dst, $a, $b",
918 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
919 def RSCrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
920 DPSoRegFrm, "rsc${s} $dst, $a, $b",
921 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
924 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
925 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
926 (SUBri GPR:$src, so_imm_neg:$imm)>;
928 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
929 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
930 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
931 // (SBCri GPR:$src, so_imm_neg:$imm)>;
933 // Note: These are implemented in C++ code, because they have to generate
934 // ADD/SUBrs instructions, which use a complex pattern that a xform function
936 // (mul X, 2^n+1) -> (add (X << n), X)
937 // (mul X, 2^n-1) -> (rsb X, (X << n))
940 //===----------------------------------------------------------------------===//
941 // Bitwise Instructions.
944 defm AND : AsI1_bin_irs<0b0000, "and",
945 BinOpFrag<(and node:$LHS, node:$RHS)>>;
946 defm ORR : AsI1_bin_irs<0b1100, "orr",
947 BinOpFrag<(or node:$LHS, node:$RHS)>>;
948 defm EOR : AsI1_bin_irs<0b0001, "eor",
949 BinOpFrag<(xor node:$LHS, node:$RHS)>>;
950 defm BIC : AsI1_bin_irs<0b1110, "bic",
951 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
953 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm,
954 "mvn", " $dst, $src",
955 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP;
956 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
957 "mvn", " $dst, $src",
958 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
959 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
960 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
961 "mvn", " $dst, $imm",
962 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP;
964 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
965 (BICri GPR:$src, so_imm_not:$imm)>;
967 //===----------------------------------------------------------------------===//
968 // Multiply Instructions.
971 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
972 "mul", " $dst, $a, $b",
973 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
975 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
976 "mla", " $dst, $a, $b, $c",
977 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
979 // Extra precision multiplies with low / high results
980 let neverHasSideEffects = 1 in {
981 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
982 (ins GPR:$a, GPR:$b),
983 "smull", " $ldst, $hdst, $a, $b", []>;
985 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
986 (ins GPR:$a, GPR:$b),
987 "umull", " $ldst, $hdst, $a, $b", []>;
989 // Multiply + accumulate
990 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
991 (ins GPR:$a, GPR:$b),
992 "smlal", " $ldst, $hdst, $a, $b", []>;
994 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
995 (ins GPR:$a, GPR:$b),
996 "umlal", " $ldst, $hdst, $a, $b", []>;
998 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
999 (ins GPR:$a, GPR:$b),
1000 "umaal", " $ldst, $hdst, $a, $b", []>,
1001 Requires<[IsARM, HasV6]>;
1002 } // neverHasSideEffects
1004 // Most significant word multiply
1005 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1006 "smmul", " $dst, $a, $b",
1007 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1008 Requires<[IsARM, HasV6]> {
1009 let Inst{7-4} = 0b0001;
1010 let Inst{15-12} = 0b1111;
1013 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1014 "smmla", " $dst, $a, $b, $c",
1015 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1016 Requires<[IsARM, HasV6]> {
1017 let Inst{7-4} = 0b0001;
1021 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1022 "smmls", " $dst, $a, $b, $c",
1023 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1024 Requires<[IsARM, HasV6]> {
1025 let Inst{7-4} = 0b1101;
1028 multiclass AI_smul<string opc, PatFrag opnode> {
1029 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1030 !strconcat(opc, "bb"), " $dst, $a, $b",
1031 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1032 (sext_inreg GPR:$b, i16)))]>,
1033 Requires<[IsARM, HasV5TE]> {
1038 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1039 !strconcat(opc, "bt"), " $dst, $a, $b",
1040 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1041 (sra GPR:$b, (i32 16))))]>,
1042 Requires<[IsARM, HasV5TE]> {
1047 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1048 !strconcat(opc, "tb"), " $dst, $a, $b",
1049 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1050 (sext_inreg GPR:$b, i16)))]>,
1051 Requires<[IsARM, HasV5TE]> {
1056 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1057 !strconcat(opc, "tt"), " $dst, $a, $b",
1058 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1059 (sra GPR:$b, (i32 16))))]>,
1060 Requires<[IsARM, HasV5TE]> {
1065 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1066 !strconcat(opc, "wb"), " $dst, $a, $b",
1067 [(set GPR:$dst, (sra (opnode GPR:$a,
1068 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1069 Requires<[IsARM, HasV5TE]> {
1074 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1075 !strconcat(opc, "wt"), " $dst, $a, $b",
1076 [(set GPR:$dst, (sra (opnode GPR:$a,
1077 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1078 Requires<[IsARM, HasV5TE]> {
1085 multiclass AI_smla<string opc, PatFrag opnode> {
1086 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1087 !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1088 [(set GPR:$dst, (add GPR:$acc,
1089 (opnode (sext_inreg GPR:$a, i16),
1090 (sext_inreg GPR:$b, i16))))]>,
1091 Requires<[IsARM, HasV5TE]> {
1096 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1097 !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1098 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1099 (sra GPR:$b, (i32 16)))))]>,
1100 Requires<[IsARM, HasV5TE]> {
1105 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1106 !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1107 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1108 (sext_inreg GPR:$b, i16))))]>,
1109 Requires<[IsARM, HasV5TE]> {
1114 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1115 !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1116 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1117 (sra GPR:$b, (i32 16)))))]>,
1118 Requires<[IsARM, HasV5TE]> {
1123 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1124 !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1125 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1126 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1127 Requires<[IsARM, HasV5TE]> {
1132 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1133 !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1134 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1135 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1136 Requires<[IsARM, HasV5TE]> {
1142 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1143 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1145 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1146 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1148 //===----------------------------------------------------------------------===//
1149 // Misc. Arithmetic Instructions.
1152 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src),
1153 "clz", " $dst, $src",
1154 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1155 let Inst{7-4} = 0b0001;
1156 let Inst{11-8} = 0b1111;
1157 let Inst{19-16} = 0b1111;
1160 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
1161 "rev", " $dst, $src",
1162 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1163 let Inst{7-4} = 0b0011;
1164 let Inst{11-8} = 0b1111;
1165 let Inst{19-16} = 0b1111;
1168 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src),
1169 "rev16", " $dst, $src",
1171 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1172 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1173 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1174 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1175 Requires<[IsARM, HasV6]> {
1176 let Inst{7-4} = 0b1011;
1177 let Inst{11-8} = 0b1111;
1178 let Inst{19-16} = 0b1111;
1181 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src),
1182 "revsh", " $dst, $src",
1185 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1186 (shl GPR:$src, (i32 8))), i16))]>,
1187 Requires<[IsARM, HasV6]> {
1188 let Inst{7-4} = 0b1011;
1189 let Inst{11-8} = 0b1111;
1190 let Inst{19-16} = 0b1111;
1193 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1194 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1195 "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1196 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1197 (and (shl GPR:$src2, (i32 imm:$shamt)),
1199 Requires<[IsARM, HasV6]> {
1200 let Inst{6-4} = 0b001;
1203 // Alternate cases for PKHBT where identities eliminate some nodes.
1204 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1205 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1206 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1207 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1210 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1211 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1212 "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1213 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1214 (and (sra GPR:$src2, imm16_31:$shamt),
1215 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1216 let Inst{6-4} = 0b101;
1219 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1220 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1221 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1222 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1223 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1224 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1225 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1227 //===----------------------------------------------------------------------===//
1228 // Comparison Instructions...
1231 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1232 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1233 defm CMN : AI1_cmp_irs<0b1011, "cmn",
1234 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1236 // Note that TST/TEQ don't set all the same flags that CMP does!
1237 defm TST : AI1_cmp_irs<0b1000, "tst",
1238 BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
1239 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1240 BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
1242 defm CMPnz : AI1_cmp_irs<0b1010, "cmp",
1243 BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
1244 defm CMNnz : AI1_cmp_irs<0b1011, "cmn",
1245 BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
1247 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1248 (CMNri GPR:$src, so_imm_neg:$imm)>;
1250 def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1251 (CMNri GPR:$src, so_imm_neg:$imm)>;
1254 // Conditional moves
1255 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1256 // a two-value operand where a dag node expects two operands. :(
1257 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1258 "mov", " $dst, $true",
1259 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1260 RegConstraint<"$false = $dst">, UnaryDP;
1262 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1263 (ins GPR:$false, so_reg:$true), DPSoRegFrm,
1264 "mov", " $dst, $true",
1265 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1266 RegConstraint<"$false = $dst">, UnaryDP;
1268 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1269 (ins GPR:$false, so_imm:$true), DPFrm,
1270 "mov", " $dst, $true",
1271 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1272 RegConstraint<"$false = $dst">, UnaryDP;
1275 // LEApcrel - Load a pc-relative address into a register without offending the
1277 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo,
1278 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
1279 "${:private}PCRELL${:uid}+8))\n"),
1280 !strconcat("${:private}PCRELL${:uid}:\n\t",
1281 "add$p $dst, pc, #PCRELV${:uid}")),
1284 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred:$p),
1286 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
1287 "${:private}PCRELL${:uid}+8))\n"),
1288 !strconcat("${:private}PCRELL${:uid}:\n\t",
1289 "add$p $dst, pc, #PCRELV${:uid}")),
1292 //===----------------------------------------------------------------------===//
1296 // __aeabi_read_tp preserves the registers r1-r3.
1298 Defs = [R0, R12, LR, CPSR] in {
1299 def TPsoft : ABXI<0b1011, (outs), (ins),
1300 "bl __aeabi_read_tp",
1301 [(set R0, ARMthread_pointer)]>;
1304 //===----------------------------------------------------------------------===//
1305 // SJLJ Exception handling intrinsics
1306 // eh_sjlj_setjmp() is a three instruction sequence to store the return
1307 // address and save #0 in R0 for the non-longjmp case.
1308 // Since by its nature we may be coming from some other function to get
1309 // here, and we're using the stack frame for the containing function to
1310 // save/restore registers, we can't keep anything live in regs across
1311 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1312 // when we get here from a longjmp(). We force everthing out of registers
1313 // except for our own input by listing the relevant registers in Defs. By
1314 // doing so, we also cause the prologue/epilogue code to actively preserve
1315 // all of the callee-saved resgisters, which is exactly what we want.
1317 [ R0, R1, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR,
1318 D0, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 ] in {
1319 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1320 AddrModeNone, SizeSpecial, IndexModeNone, Pseudo,
1321 "add r0, pc, #4\n\t"
1322 "str r0, [$src, #+4]\n\t"
1323 "mov r0, #0 @ eh_setjmp", "",
1324 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1327 //===----------------------------------------------------------------------===//
1328 // Non-Instruction Patterns
1331 // ConstantPool, GlobalAddress, and JumpTable
1332 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1333 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1334 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1335 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1337 // Large immediate handling.
1339 // Two piece so_imms.
1340 let isReMaterializable = 1 in
1341 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), Pseudo,
1342 "mov", " $dst, $src",
1343 [(set GPR:$dst, so_imm2part:$src)]>;
1345 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1346 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1347 (so_imm2part_2 imm:$RHS))>;
1348 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1349 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1350 (so_imm2part_2 imm:$RHS))>;
1352 // TODO: add,sub,and, 3-instr forms?
1356 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1357 Requires<[IsNotDarwin]>;
1358 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1359 Requires<[IsDarwin]>;
1361 // zextload i1 -> zextload i8
1362 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1364 // extload -> zextload
1365 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1366 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1367 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1369 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1370 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1373 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1374 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1375 (SMULBB GPR:$a, GPR:$b)>;
1376 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1377 (SMULBB GPR:$a, GPR:$b)>;
1378 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1379 (sra GPR:$b, (i32 16))),
1380 (SMULBT GPR:$a, GPR:$b)>;
1381 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1382 (SMULBT GPR:$a, GPR:$b)>;
1383 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1384 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1385 (SMULTB GPR:$a, GPR:$b)>;
1386 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1387 (SMULTB GPR:$a, GPR:$b)>;
1388 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1390 (SMULWB GPR:$a, GPR:$b)>;
1391 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1392 (SMULWB GPR:$a, GPR:$b)>;
1394 def : ARMV5TEPat<(add GPR:$acc,
1395 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1396 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1397 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1398 def : ARMV5TEPat<(add GPR:$acc,
1399 (mul sext_16_node:$a, sext_16_node:$b)),
1400 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1401 def : ARMV5TEPat<(add GPR:$acc,
1402 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1403 (sra GPR:$b, (i32 16)))),
1404 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1405 def : ARMV5TEPat<(add GPR:$acc,
1406 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1407 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1408 def : ARMV5TEPat<(add GPR:$acc,
1409 (mul (sra GPR:$a, (i32 16)),
1410 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1411 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1412 def : ARMV5TEPat<(add GPR:$acc,
1413 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1414 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1415 def : ARMV5TEPat<(add GPR:$acc,
1416 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1418 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1419 def : ARMV5TEPat<(add GPR:$acc,
1420 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1421 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1423 //===----------------------------------------------------------------------===//
1427 include "ARMInstrThumb.td"
1429 //===----------------------------------------------------------------------===//
1433 include "ARMInstrThumb2.td"
1435 //===----------------------------------------------------------------------===//
1436 // Floating Point Support
1439 include "ARMInstrVFP.td"