1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
77 SDTCisInt<0>, SDTCisVT<1, i32>]>;
79 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
80 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
87 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
88 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
89 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
90 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
91 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
94 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
95 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
96 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
97 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
99 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
100 [SDNPHasChain, SDNPOutGlue]>;
101 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
102 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
103 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
105 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
106 SDNPMayStore, SDNPMayLoad]>;
108 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
109 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
111 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
112 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
114 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
118 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
119 [SDNPHasChain, SDNPOptInGlue]>;
121 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
124 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
125 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
127 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
129 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
132 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
135 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
138 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
141 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
142 [SDNPOutGlue, SDNPCommutative]>;
144 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
146 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
147 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
148 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
150 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
152 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
153 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
154 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
156 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
157 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
158 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
159 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
160 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
162 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
164 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
166 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
167 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
169 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
171 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
172 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
175 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
177 //===----------------------------------------------------------------------===//
178 // ARM Instruction Predicate Definitions.
180 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
181 AssemblerPredicate<"HasV4TOps", "armv4t">;
182 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
183 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
184 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
185 AssemblerPredicate<"HasV5TEOps", "armv5te">;
186 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
187 AssemblerPredicate<"HasV6Ops", "armv6">;
188 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
189 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
190 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
191 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
192 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
193 AssemblerPredicate<"HasV7Ops", "armv7">;
194 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
195 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
196 AssemblerPredicate<"FeatureVFP2", "VFP2">;
197 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
198 AssemblerPredicate<"FeatureVFP3", "VFP3">;
199 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
200 AssemblerPredicate<"FeatureVFP4", "VFP4">;
201 def HasNEON : Predicate<"Subtarget->hasNEON()">,
202 AssemblerPredicate<"FeatureNEON", "NEON">;
203 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
204 AssemblerPredicate<"FeatureFP16","half-float">;
205 def HasDivide : Predicate<"Subtarget->hasDivide()">,
206 AssemblerPredicate<"FeatureHWDiv", "divide">;
207 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
208 AssemblerPredicate<"FeatureT2XtPk",
210 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
211 AssemblerPredicate<"FeatureDSPThumb2",
213 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
214 AssemblerPredicate<"FeatureDB",
216 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
217 AssemblerPredicate<"FeatureMP",
219 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
220 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
221 def IsThumb : Predicate<"Subtarget->isThumb()">,
222 AssemblerPredicate<"ModeThumb", "thumb">;
223 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
224 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
225 AssemblerPredicate<"ModeThumb,FeatureThumb2",
227 def IsMClass : Predicate<"Subtarget->isMClass()">,
228 AssemblerPredicate<"FeatureMClass", "armv7m">;
229 def IsARClass : Predicate<"!Subtarget->isMClass()">,
230 AssemblerPredicate<"!FeatureMClass",
232 def IsARM : Predicate<"!Subtarget->isThumb()">,
233 AssemblerPredicate<"!ModeThumb", "arm-mode">;
234 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
235 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
236 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
238 // FIXME: Eventually this will be just "hasV6T2Ops".
239 def UseMovt : Predicate<"Subtarget->useMovt()">;
240 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
241 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
243 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
244 // But only select them if more precision in FP computation is allowed.
245 // Do not use them for Darwin platforms.
246 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
247 " FPOpFusion::Fast) && "
248 "!Subtarget->isTargetDarwin()">;
249 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
250 "Subtarget->isTargetDarwin()">;
252 //===----------------------------------------------------------------------===//
253 // ARM Flag Definitions.
255 class RegConstraint<string C> {
256 string Constraints = C;
259 //===----------------------------------------------------------------------===//
260 // ARM specific transformation functions and pattern fragments.
263 // imm_neg_XFORM - Return a imm value packed into the format described for
264 // imm_neg defs below.
265 def imm_neg_XFORM : SDNodeXForm<imm, [{
266 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
269 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
270 // so_imm_not def below.
271 def so_imm_not_XFORM : SDNodeXForm<imm, [{
272 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
275 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
276 def imm16_31 : ImmLeaf<i32, [{
277 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
280 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
281 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
282 int64_t Value = -(int)N->getZExtValue();
283 return Value && ARM_AM::getSOImmVal(Value) != -1;
285 let ParserMatchClass = so_imm_neg_asmoperand;
288 // Note: this pattern doesn't require an encoder method and such, as it's
289 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
290 // is handled by the destination instructions, which use so_imm.
291 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
292 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
293 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
294 }], so_imm_not_XFORM> {
295 let ParserMatchClass = so_imm_not_asmoperand;
298 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
299 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
300 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
303 /// Split a 32-bit immediate into two 16 bit parts.
304 def hi16 : SDNodeXForm<imm, [{
305 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
308 def lo16AllZero : PatLeaf<(i32 imm), [{
309 // Returns true if all low 16-bits are 0.
310 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
313 class BinOpWithFlagFrag<dag res> :
314 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
315 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
316 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
318 // An 'and' node with a single use.
319 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
320 return N->hasOneUse();
323 // An 'xor' node with a single use.
324 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
325 return N->hasOneUse();
328 // An 'fmul' node with a single use.
329 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
330 return N->hasOneUse();
333 // An 'fadd' node which checks for single non-hazardous use.
334 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
335 return hasNoVMLxHazardUse(N);
338 // An 'fsub' node which checks for single non-hazardous use.
339 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
340 return hasNoVMLxHazardUse(N);
343 //===----------------------------------------------------------------------===//
344 // Operand Definitions.
347 // Immediate operands with a shared generic asm render method.
348 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
351 // FIXME: rename brtarget to t2_brtarget
352 def brtarget : Operand<OtherVT> {
353 let EncoderMethod = "getBranchTargetOpValue";
354 let OperandType = "OPERAND_PCREL";
355 let DecoderMethod = "DecodeT2BROperand";
358 // FIXME: get rid of this one?
359 def uncondbrtarget : Operand<OtherVT> {
360 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
361 let OperandType = "OPERAND_PCREL";
364 // Branch target for ARM. Handles conditional/unconditional
365 def br_target : Operand<OtherVT> {
366 let EncoderMethod = "getARMBranchTargetOpValue";
367 let OperandType = "OPERAND_PCREL";
371 // FIXME: rename bltarget to t2_bl_target?
372 def bltarget : Operand<i32> {
373 // Encoded the same as branch targets.
374 let EncoderMethod = "getBranchTargetOpValue";
375 let OperandType = "OPERAND_PCREL";
378 // Call target for ARM. Handles conditional/unconditional
379 // FIXME: rename bl_target to t2_bltarget?
380 def bl_target : Operand<i32> {
381 let EncoderMethod = "getARMBLTargetOpValue";
382 let OperandType = "OPERAND_PCREL";
385 def blx_target : Operand<i32> {
386 let EncoderMethod = "getARMBLXTargetOpValue";
387 let OperandType = "OPERAND_PCREL";
390 // A list of registers separated by comma. Used by load/store multiple.
391 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
392 def reglist : Operand<i32> {
393 let EncoderMethod = "getRegisterListOpValue";
394 let ParserMatchClass = RegListAsmOperand;
395 let PrintMethod = "printRegisterList";
396 let DecoderMethod = "DecodeRegListOperand";
399 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
400 def dpr_reglist : Operand<i32> {
401 let EncoderMethod = "getRegisterListOpValue";
402 let ParserMatchClass = DPRRegListAsmOperand;
403 let PrintMethod = "printRegisterList";
404 let DecoderMethod = "DecodeDPRRegListOperand";
407 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
408 def spr_reglist : Operand<i32> {
409 let EncoderMethod = "getRegisterListOpValue";
410 let ParserMatchClass = SPRRegListAsmOperand;
411 let PrintMethod = "printRegisterList";
412 let DecoderMethod = "DecodeSPRRegListOperand";
415 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
416 def cpinst_operand : Operand<i32> {
417 let PrintMethod = "printCPInstOperand";
421 def pclabel : Operand<i32> {
422 let PrintMethod = "printPCLabel";
425 // ADR instruction labels.
426 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
427 def adrlabel : Operand<i32> {
428 let EncoderMethod = "getAdrLabelOpValue";
429 let ParserMatchClass = AdrLabelAsmOperand;
430 let PrintMethod = "printAdrLabelOperand";
433 def neon_vcvt_imm32 : Operand<i32> {
434 let EncoderMethod = "getNEONVcvtImm32OpValue";
435 let DecoderMethod = "DecodeVCVTImmOperand";
438 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
439 def rot_imm_XFORM: SDNodeXForm<imm, [{
440 switch (N->getZExtValue()){
442 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
443 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
444 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
445 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
448 def RotImmAsmOperand : AsmOperandClass {
450 let ParserMethod = "parseRotImm";
452 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
453 int32_t v = N->getZExtValue();
454 return v == 8 || v == 16 || v == 24; }],
456 let PrintMethod = "printRotImmOperand";
457 let ParserMatchClass = RotImmAsmOperand;
460 // shift_imm: An integer that encodes a shift amount and the type of shift
461 // (asr or lsl). The 6-bit immediate encodes as:
464 // {4-0} imm5 shift amount.
465 // asr #32 encoded as imm5 == 0.
466 def ShifterImmAsmOperand : AsmOperandClass {
467 let Name = "ShifterImm";
468 let ParserMethod = "parseShifterImm";
470 def shift_imm : Operand<i32> {
471 let PrintMethod = "printShiftImmOperand";
472 let ParserMatchClass = ShifterImmAsmOperand;
475 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
476 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
477 def so_reg_reg : Operand<i32>, // reg reg imm
478 ComplexPattern<i32, 3, "SelectRegShifterOperand",
479 [shl, srl, sra, rotr]> {
480 let EncoderMethod = "getSORegRegOpValue";
481 let PrintMethod = "printSORegRegOperand";
482 let DecoderMethod = "DecodeSORegRegOperand";
483 let ParserMatchClass = ShiftedRegAsmOperand;
484 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
487 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
488 def so_reg_imm : Operand<i32>, // reg imm
489 ComplexPattern<i32, 2, "SelectImmShifterOperand",
490 [shl, srl, sra, rotr]> {
491 let EncoderMethod = "getSORegImmOpValue";
492 let PrintMethod = "printSORegImmOperand";
493 let DecoderMethod = "DecodeSORegImmOperand";
494 let ParserMatchClass = ShiftedImmAsmOperand;
495 let MIOperandInfo = (ops GPR, i32imm);
498 // FIXME: Does this need to be distinct from so_reg?
499 def shift_so_reg_reg : Operand<i32>, // reg reg imm
500 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
501 [shl,srl,sra,rotr]> {
502 let EncoderMethod = "getSORegRegOpValue";
503 let PrintMethod = "printSORegRegOperand";
504 let DecoderMethod = "DecodeSORegRegOperand";
505 let ParserMatchClass = ShiftedRegAsmOperand;
506 let MIOperandInfo = (ops GPR, GPR, i32imm);
509 // FIXME: Does this need to be distinct from so_reg?
510 def shift_so_reg_imm : Operand<i32>, // reg reg imm
511 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
512 [shl,srl,sra,rotr]> {
513 let EncoderMethod = "getSORegImmOpValue";
514 let PrintMethod = "printSORegImmOperand";
515 let DecoderMethod = "DecodeSORegImmOperand";
516 let ParserMatchClass = ShiftedImmAsmOperand;
517 let MIOperandInfo = (ops GPR, i32imm);
521 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
522 // 8-bit immediate rotated by an arbitrary number of bits.
523 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
524 def so_imm : Operand<i32>, ImmLeaf<i32, [{
525 return ARM_AM::getSOImmVal(Imm) != -1;
527 let EncoderMethod = "getSOImmOpValue";
528 let ParserMatchClass = SOImmAsmOperand;
529 let DecoderMethod = "DecodeSOImmOperand";
532 // Break so_imm's up into two pieces. This handles immediates with up to 16
533 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
534 // get the first/second pieces.
535 def so_imm2part : PatLeaf<(imm), [{
536 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
539 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
541 def arm_i32imm : PatLeaf<(imm), [{
542 if (Subtarget->hasV6T2Ops())
544 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
547 /// imm0_1 predicate - Immediate in the range [0,1].
548 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
549 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
551 /// imm0_3 predicate - Immediate in the range [0,3].
552 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
553 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
555 /// imm0_7 predicate - Immediate in the range [0,7].
556 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
557 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
558 return Imm >= 0 && Imm < 8;
560 let ParserMatchClass = Imm0_7AsmOperand;
563 /// imm8 predicate - Immediate is exactly 8.
564 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
565 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
566 let ParserMatchClass = Imm8AsmOperand;
569 /// imm16 predicate - Immediate is exactly 16.
570 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
571 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
572 let ParserMatchClass = Imm16AsmOperand;
575 /// imm32 predicate - Immediate is exactly 32.
576 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
577 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
578 let ParserMatchClass = Imm32AsmOperand;
581 /// imm1_7 predicate - Immediate in the range [1,7].
582 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
583 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
584 let ParserMatchClass = Imm1_7AsmOperand;
587 /// imm1_15 predicate - Immediate in the range [1,15].
588 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
589 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
590 let ParserMatchClass = Imm1_15AsmOperand;
593 /// imm1_31 predicate - Immediate in the range [1,31].
594 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
595 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
596 let ParserMatchClass = Imm1_31AsmOperand;
599 /// imm0_15 predicate - Immediate in the range [0,15].
600 def Imm0_15AsmOperand: ImmAsmOperand {
601 let Name = "Imm0_15";
602 let DiagnosticType = "ImmRange0_15";
604 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
605 return Imm >= 0 && Imm < 16;
607 let ParserMatchClass = Imm0_15AsmOperand;
610 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
611 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
612 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
613 return Imm >= 0 && Imm < 32;
615 let ParserMatchClass = Imm0_31AsmOperand;
618 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
619 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
620 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
621 return Imm >= 0 && Imm < 32;
623 let ParserMatchClass = Imm0_32AsmOperand;
626 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
627 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
628 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
629 return Imm >= 0 && Imm < 64;
631 let ParserMatchClass = Imm0_63AsmOperand;
634 /// imm0_255 predicate - Immediate in the range [0,255].
635 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
636 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
637 let ParserMatchClass = Imm0_255AsmOperand;
640 /// imm0_65535 - An immediate is in the range [0.65535].
641 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
642 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
643 return Imm >= 0 && Imm < 65536;
645 let ParserMatchClass = Imm0_65535AsmOperand;
648 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
649 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
650 return -Imm >= 0 && -Imm < 65536;
653 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
654 // a relocatable expression.
656 // FIXME: This really needs a Thumb version separate from the ARM version.
657 // While the range is the same, and can thus use the same match class,
658 // the encoding is different so it should have a different encoder method.
659 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
660 def imm0_65535_expr : Operand<i32> {
661 let EncoderMethod = "getHiLo16ImmOpValue";
662 let ParserMatchClass = Imm0_65535ExprAsmOperand;
665 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
666 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
667 def imm24b : Operand<i32>, ImmLeaf<i32, [{
668 return Imm >= 0 && Imm <= 0xffffff;
670 let ParserMatchClass = Imm24bitAsmOperand;
674 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
676 def BitfieldAsmOperand : AsmOperandClass {
677 let Name = "Bitfield";
678 let ParserMethod = "parseBitfield";
681 def bf_inv_mask_imm : Operand<i32>,
683 return ARM::isBitFieldInvertedMask(N->getZExtValue());
685 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
686 let PrintMethod = "printBitfieldInvMaskImmOperand";
687 let DecoderMethod = "DecodeBitfieldMaskOperand";
688 let ParserMatchClass = BitfieldAsmOperand;
691 def imm1_32_XFORM: SDNodeXForm<imm, [{
692 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
694 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
695 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
696 uint64_t Imm = N->getZExtValue();
697 return Imm > 0 && Imm <= 32;
700 let PrintMethod = "printImmPlusOneOperand";
701 let ParserMatchClass = Imm1_32AsmOperand;
704 def imm1_16_XFORM: SDNodeXForm<imm, [{
705 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
707 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
708 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
710 let PrintMethod = "printImmPlusOneOperand";
711 let ParserMatchClass = Imm1_16AsmOperand;
714 // Define ARM specific addressing modes.
715 // addrmode_imm12 := reg +/- imm12
717 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
718 def addrmode_imm12 : Operand<i32>,
719 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
720 // 12-bit immediate operand. Note that instructions using this encode
721 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
722 // immediate values are as normal.
724 let EncoderMethod = "getAddrModeImm12OpValue";
725 let PrintMethod = "printAddrModeImm12Operand";
726 let DecoderMethod = "DecodeAddrModeImm12Operand";
727 let ParserMatchClass = MemImm12OffsetAsmOperand;
728 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
730 // ldst_so_reg := reg +/- reg shop imm
732 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
733 def ldst_so_reg : Operand<i32>,
734 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
735 let EncoderMethod = "getLdStSORegOpValue";
736 // FIXME: Simplify the printer
737 let PrintMethod = "printAddrMode2Operand";
738 let DecoderMethod = "DecodeSORegMemOperand";
739 let ParserMatchClass = MemRegOffsetAsmOperand;
740 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
743 // postidx_imm8 := +/- [0,255]
746 // {8} 1 is imm8 is non-negative. 0 otherwise.
747 // {7-0} [0,255] imm8 value.
748 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
749 def postidx_imm8 : Operand<i32> {
750 let PrintMethod = "printPostIdxImm8Operand";
751 let ParserMatchClass = PostIdxImm8AsmOperand;
752 let MIOperandInfo = (ops i32imm);
755 // postidx_imm8s4 := +/- [0,1020]
758 // {8} 1 is imm8 is non-negative. 0 otherwise.
759 // {7-0} [0,255] imm8 value, scaled by 4.
760 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
761 def postidx_imm8s4 : Operand<i32> {
762 let PrintMethod = "printPostIdxImm8s4Operand";
763 let ParserMatchClass = PostIdxImm8s4AsmOperand;
764 let MIOperandInfo = (ops i32imm);
768 // postidx_reg := +/- reg
770 def PostIdxRegAsmOperand : AsmOperandClass {
771 let Name = "PostIdxReg";
772 let ParserMethod = "parsePostIdxReg";
774 def postidx_reg : Operand<i32> {
775 let EncoderMethod = "getPostIdxRegOpValue";
776 let DecoderMethod = "DecodePostIdxReg";
777 let PrintMethod = "printPostIdxRegOperand";
778 let ParserMatchClass = PostIdxRegAsmOperand;
779 let MIOperandInfo = (ops GPRnopc, i32imm);
783 // addrmode2 := reg +/- imm12
784 // := reg +/- reg shop imm
786 // FIXME: addrmode2 should be refactored the rest of the way to always
787 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
788 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
789 def addrmode2 : Operand<i32>,
790 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
791 let EncoderMethod = "getAddrMode2OpValue";
792 let PrintMethod = "printAddrMode2Operand";
793 let ParserMatchClass = AddrMode2AsmOperand;
794 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
797 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
798 let Name = "PostIdxRegShifted";
799 let ParserMethod = "parsePostIdxReg";
801 def am2offset_reg : Operand<i32>,
802 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
803 [], [SDNPWantRoot]> {
804 let EncoderMethod = "getAddrMode2OffsetOpValue";
805 let PrintMethod = "printAddrMode2OffsetOperand";
806 // When using this for assembly, it's always as a post-index offset.
807 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
808 let MIOperandInfo = (ops GPRnopc, i32imm);
811 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
812 // the GPR is purely vestigal at this point.
813 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
814 def am2offset_imm : Operand<i32>,
815 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
816 [], [SDNPWantRoot]> {
817 let EncoderMethod = "getAddrMode2OffsetOpValue";
818 let PrintMethod = "printAddrMode2OffsetOperand";
819 let ParserMatchClass = AM2OffsetImmAsmOperand;
820 let MIOperandInfo = (ops GPRnopc, i32imm);
824 // addrmode3 := reg +/- reg
825 // addrmode3 := reg +/- imm8
827 // FIXME: split into imm vs. reg versions.
828 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
829 def addrmode3 : Operand<i32>,
830 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
831 let EncoderMethod = "getAddrMode3OpValue";
832 let PrintMethod = "printAddrMode3Operand";
833 let ParserMatchClass = AddrMode3AsmOperand;
834 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
837 // FIXME: split into imm vs. reg versions.
838 // FIXME: parser method to handle +/- register.
839 def AM3OffsetAsmOperand : AsmOperandClass {
840 let Name = "AM3Offset";
841 let ParserMethod = "parseAM3Offset";
843 def am3offset : Operand<i32>,
844 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
845 [], [SDNPWantRoot]> {
846 let EncoderMethod = "getAddrMode3OffsetOpValue";
847 let PrintMethod = "printAddrMode3OffsetOperand";
848 let ParserMatchClass = AM3OffsetAsmOperand;
849 let MIOperandInfo = (ops GPR, i32imm);
852 // ldstm_mode := {ia, ib, da, db}
854 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
855 let EncoderMethod = "getLdStmModeOpValue";
856 let PrintMethod = "printLdStmModeOperand";
859 // addrmode5 := reg +/- imm8*4
861 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
862 def addrmode5 : Operand<i32>,
863 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
864 let PrintMethod = "printAddrMode5Operand";
865 let EncoderMethod = "getAddrMode5OpValue";
866 let DecoderMethod = "DecodeAddrMode5Operand";
867 let ParserMatchClass = AddrMode5AsmOperand;
868 let MIOperandInfo = (ops GPR:$base, i32imm);
871 // addrmode6 := reg with optional alignment
873 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
874 def addrmode6 : Operand<i32>,
875 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
876 let PrintMethod = "printAddrMode6Operand";
877 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
878 let EncoderMethod = "getAddrMode6AddressOpValue";
879 let DecoderMethod = "DecodeAddrMode6Operand";
880 let ParserMatchClass = AddrMode6AsmOperand;
883 def am6offset : Operand<i32>,
884 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
885 [], [SDNPWantRoot]> {
886 let PrintMethod = "printAddrMode6OffsetOperand";
887 let MIOperandInfo = (ops GPR);
888 let EncoderMethod = "getAddrMode6OffsetOpValue";
889 let DecoderMethod = "DecodeGPRRegisterClass";
892 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
893 // (single element from one lane) for size 32.
894 def addrmode6oneL32 : Operand<i32>,
895 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
896 let PrintMethod = "printAddrMode6Operand";
897 let MIOperandInfo = (ops GPR:$addr, i32imm);
898 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
901 // Special version of addrmode6 to handle alignment encoding for VLD-dup
902 // instructions, specifically VLD4-dup.
903 def addrmode6dup : Operand<i32>,
904 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
905 let PrintMethod = "printAddrMode6Operand";
906 let MIOperandInfo = (ops GPR:$addr, i32imm);
907 let EncoderMethod = "getAddrMode6DupAddressOpValue";
908 // FIXME: This is close, but not quite right. The alignment specifier is
910 let ParserMatchClass = AddrMode6AsmOperand;
913 // addrmodepc := pc + reg
915 def addrmodepc : Operand<i32>,
916 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
917 let PrintMethod = "printAddrModePCOperand";
918 let MIOperandInfo = (ops GPR, i32imm);
921 // addr_offset_none := reg
923 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
924 def addr_offset_none : Operand<i32>,
925 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
926 let PrintMethod = "printAddrMode7Operand";
927 let DecoderMethod = "DecodeAddrMode7Operand";
928 let ParserMatchClass = MemNoOffsetAsmOperand;
929 let MIOperandInfo = (ops GPR:$base);
932 def nohash_imm : Operand<i32> {
933 let PrintMethod = "printNoHashImmediate";
936 def CoprocNumAsmOperand : AsmOperandClass {
937 let Name = "CoprocNum";
938 let ParserMethod = "parseCoprocNumOperand";
940 def p_imm : Operand<i32> {
941 let PrintMethod = "printPImmediate";
942 let ParserMatchClass = CoprocNumAsmOperand;
943 let DecoderMethod = "DecodeCoprocessor";
946 def pf_imm : Operand<i32> {
947 let PrintMethod = "printPImmediate";
948 let ParserMatchClass = CoprocNumAsmOperand;
951 def CoprocRegAsmOperand : AsmOperandClass {
952 let Name = "CoprocReg";
953 let ParserMethod = "parseCoprocRegOperand";
955 def c_imm : Operand<i32> {
956 let PrintMethod = "printCImmediate";
957 let ParserMatchClass = CoprocRegAsmOperand;
959 def CoprocOptionAsmOperand : AsmOperandClass {
960 let Name = "CoprocOption";
961 let ParserMethod = "parseCoprocOptionOperand";
963 def coproc_option_imm : Operand<i32> {
964 let PrintMethod = "printCoprocOptionImm";
965 let ParserMatchClass = CoprocOptionAsmOperand;
968 //===----------------------------------------------------------------------===//
970 include "ARMInstrFormats.td"
972 //===----------------------------------------------------------------------===//
973 // Multiclass helpers...
976 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
977 /// binop that produces a value.
978 let TwoOperandAliasConstraint = "$Rn = $Rd" in
979 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
980 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
981 PatFrag opnode, bit Commutable = 0> {
982 // The register-immediate version is re-materializable. This is useful
983 // in particular for taking the address of a local.
984 let isReMaterializable = 1 in {
985 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
986 iii, opc, "\t$Rd, $Rn, $imm",
987 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
992 let Inst{19-16} = Rn;
993 let Inst{15-12} = Rd;
994 let Inst{11-0} = imm;
997 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
998 iir, opc, "\t$Rd, $Rn, $Rm",
999 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
1004 let isCommutable = Commutable;
1005 let Inst{19-16} = Rn;
1006 let Inst{15-12} = Rd;
1007 let Inst{11-4} = 0b00000000;
1011 def rsi : AsI1<opcod, (outs GPR:$Rd),
1012 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1013 iis, opc, "\t$Rd, $Rn, $shift",
1014 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
1019 let Inst{19-16} = Rn;
1020 let Inst{15-12} = Rd;
1021 let Inst{11-5} = shift{11-5};
1023 let Inst{3-0} = shift{3-0};
1026 def rsr : AsI1<opcod, (outs GPR:$Rd),
1027 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1028 iis, opc, "\t$Rd, $Rn, $shift",
1029 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
1034 let Inst{19-16} = Rn;
1035 let Inst{15-12} = Rd;
1036 let Inst{11-8} = shift{11-8};
1038 let Inst{6-5} = shift{6-5};
1040 let Inst{3-0} = shift{3-0};
1044 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1045 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1046 /// it is equivalent to the AsI1_bin_irs counterpart.
1047 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1048 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1049 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1050 PatFrag opnode, bit Commutable = 0> {
1051 // The register-immediate version is re-materializable. This is useful
1052 // in particular for taking the address of a local.
1053 let isReMaterializable = 1 in {
1054 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1055 iii, opc, "\t$Rd, $Rn, $imm",
1056 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
1061 let Inst{19-16} = Rn;
1062 let Inst{15-12} = Rd;
1063 let Inst{11-0} = imm;
1066 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1067 iir, opc, "\t$Rd, $Rn, $Rm",
1068 [/* pattern left blank */]> {
1072 let Inst{11-4} = 0b00000000;
1075 let Inst{15-12} = Rd;
1076 let Inst{19-16} = Rn;
1079 def rsi : AsI1<opcod, (outs GPR:$Rd),
1080 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1081 iis, opc, "\t$Rd, $Rn, $shift",
1082 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1087 let Inst{19-16} = Rn;
1088 let Inst{15-12} = Rd;
1089 let Inst{11-5} = shift{11-5};
1091 let Inst{3-0} = shift{3-0};
1094 def rsr : AsI1<opcod, (outs GPR:$Rd),
1095 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1096 iis, opc, "\t$Rd, $Rn, $shift",
1097 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1102 let Inst{19-16} = Rn;
1103 let Inst{15-12} = Rd;
1104 let Inst{11-8} = shift{11-8};
1106 let Inst{6-5} = shift{6-5};
1108 let Inst{3-0} = shift{3-0};
1112 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1114 /// These opcodes will be converted to the real non-S opcodes by
1115 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1116 let hasPostISelHook = 1, Defs = [CPSR] in {
1117 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1118 InstrItinClass iis, PatFrag opnode,
1119 bit Commutable = 0> {
1120 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1122 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
1124 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1126 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1127 let isCommutable = Commutable;
1129 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1130 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1132 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1133 so_reg_imm:$shift))]>;
1135 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1136 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1138 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1139 so_reg_reg:$shift))]>;
1143 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1144 /// operands are reversed.
1145 let hasPostISelHook = 1, Defs = [CPSR] in {
1146 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1147 InstrItinClass iis, PatFrag opnode,
1148 bit Commutable = 0> {
1149 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1151 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
1153 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1154 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1156 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1159 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1160 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1162 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1167 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1168 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1169 /// a explicit result, only implicitly set CPSR.
1170 let isCompare = 1, Defs = [CPSR] in {
1171 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1172 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1173 PatFrag opnode, bit Commutable = 0> {
1174 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1176 [(opnode GPR:$Rn, so_imm:$imm)]> {
1181 let Inst{19-16} = Rn;
1182 let Inst{15-12} = 0b0000;
1183 let Inst{11-0} = imm;
1185 let Unpredictable{15-12} = 0b1111;
1187 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1189 [(opnode GPR:$Rn, GPR:$Rm)]> {
1192 let isCommutable = Commutable;
1195 let Inst{19-16} = Rn;
1196 let Inst{15-12} = 0b0000;
1197 let Inst{11-4} = 0b00000000;
1200 let Unpredictable{15-12} = 0b1111;
1202 def rsi : AI1<opcod, (outs),
1203 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1204 opc, "\t$Rn, $shift",
1205 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1210 let Inst{19-16} = Rn;
1211 let Inst{15-12} = 0b0000;
1212 let Inst{11-5} = shift{11-5};
1214 let Inst{3-0} = shift{3-0};
1216 let Unpredictable{15-12} = 0b1111;
1218 def rsr : AI1<opcod, (outs),
1219 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1220 opc, "\t$Rn, $shift",
1221 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]> {
1226 let Inst{19-16} = Rn;
1227 let Inst{15-12} = 0b0000;
1228 let Inst{11-8} = shift{11-8};
1230 let Inst{6-5} = shift{6-5};
1232 let Inst{3-0} = shift{3-0};
1234 let Unpredictable{15-12} = 0b1111;
1240 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1241 /// register and one whose operand is a register rotated by 8/16/24.
1242 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1243 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1244 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1245 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1246 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1247 Requires<[IsARM, HasV6]> {
1251 let Inst{19-16} = 0b1111;
1252 let Inst{15-12} = Rd;
1253 let Inst{11-10} = rot;
1257 class AI_ext_rrot_np<bits<8> opcod, string opc>
1258 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1259 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1260 Requires<[IsARM, HasV6]> {
1262 let Inst{19-16} = 0b1111;
1263 let Inst{11-10} = rot;
1266 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1267 /// register and one whose operand is a register rotated by 8/16/24.
1268 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1269 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1270 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1271 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1272 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1273 Requires<[IsARM, HasV6]> {
1278 let Inst{19-16} = Rn;
1279 let Inst{15-12} = Rd;
1280 let Inst{11-10} = rot;
1281 let Inst{9-4} = 0b000111;
1285 class AI_exta_rrot_np<bits<8> opcod, string opc>
1286 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1287 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1288 Requires<[IsARM, HasV6]> {
1291 let Inst{19-16} = Rn;
1292 let Inst{11-10} = rot;
1295 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1296 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1297 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1298 bit Commutable = 0> {
1299 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1300 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1301 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1302 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1308 let Inst{15-12} = Rd;
1309 let Inst{19-16} = Rn;
1310 let Inst{11-0} = imm;
1312 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1313 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1314 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1319 let Inst{11-4} = 0b00000000;
1321 let isCommutable = Commutable;
1323 let Inst{15-12} = Rd;
1324 let Inst{19-16} = Rn;
1326 def rsi : AsI1<opcod, (outs GPR:$Rd),
1327 (ins GPR:$Rn, so_reg_imm:$shift),
1328 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1329 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1335 let Inst{19-16} = Rn;
1336 let Inst{15-12} = Rd;
1337 let Inst{11-5} = shift{11-5};
1339 let Inst{3-0} = shift{3-0};
1341 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1342 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1343 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1344 [(set GPRnopc:$Rd, CPSR,
1345 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1351 let Inst{19-16} = Rn;
1352 let Inst{15-12} = Rd;
1353 let Inst{11-8} = shift{11-8};
1355 let Inst{6-5} = shift{6-5};
1357 let Inst{3-0} = shift{3-0};
1362 /// AI1_rsc_irs - Define instructions and patterns for rsc
1363 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1364 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1365 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1366 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1367 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1368 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1374 let Inst{15-12} = Rd;
1375 let Inst{19-16} = Rn;
1376 let Inst{11-0} = imm;
1378 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1379 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1380 [/* pattern left blank */]> {
1384 let Inst{11-4} = 0b00000000;
1387 let Inst{15-12} = Rd;
1388 let Inst{19-16} = Rn;
1390 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1391 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1392 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1398 let Inst{19-16} = Rn;
1399 let Inst{15-12} = Rd;
1400 let Inst{11-5} = shift{11-5};
1402 let Inst{3-0} = shift{3-0};
1404 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1405 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1406 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1412 let Inst{19-16} = Rn;
1413 let Inst{15-12} = Rd;
1414 let Inst{11-8} = shift{11-8};
1416 let Inst{6-5} = shift{6-5};
1418 let Inst{3-0} = shift{3-0};
1423 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1424 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1425 InstrItinClass iir, PatFrag opnode> {
1426 // Note: We use the complex addrmode_imm12 rather than just an input
1427 // GPR and a constrained immediate so that we can use this to match
1428 // frame index references and avoid matching constant pool references.
1429 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1430 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1431 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1434 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1435 let Inst{19-16} = addr{16-13}; // Rn
1436 let Inst{15-12} = Rt;
1437 let Inst{11-0} = addr{11-0}; // imm12
1439 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1440 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1441 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1444 let shift{4} = 0; // Inst{4} = 0
1445 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1446 let Inst{19-16} = shift{16-13}; // Rn
1447 let Inst{15-12} = Rt;
1448 let Inst{11-0} = shift{11-0};
1453 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1454 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1455 InstrItinClass iir, PatFrag opnode> {
1456 // Note: We use the complex addrmode_imm12 rather than just an input
1457 // GPR and a constrained immediate so that we can use this to match
1458 // frame index references and avoid matching constant pool references.
1459 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1460 (ins addrmode_imm12:$addr),
1461 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1462 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1465 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1466 let Inst{19-16} = addr{16-13}; // Rn
1467 let Inst{15-12} = Rt;
1468 let Inst{11-0} = addr{11-0}; // imm12
1470 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1471 (ins ldst_so_reg:$shift),
1472 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1473 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1476 let shift{4} = 0; // Inst{4} = 0
1477 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1478 let Inst{19-16} = shift{16-13}; // Rn
1479 let Inst{15-12} = Rt;
1480 let Inst{11-0} = shift{11-0};
1486 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1487 InstrItinClass iir, PatFrag opnode> {
1488 // Note: We use the complex addrmode_imm12 rather than just an input
1489 // GPR and a constrained immediate so that we can use this to match
1490 // frame index references and avoid matching constant pool references.
1491 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1492 (ins GPR:$Rt, addrmode_imm12:$addr),
1493 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1494 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1497 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1498 let Inst{19-16} = addr{16-13}; // Rn
1499 let Inst{15-12} = Rt;
1500 let Inst{11-0} = addr{11-0}; // imm12
1502 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1503 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1504 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1507 let shift{4} = 0; // Inst{4} = 0
1508 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1509 let Inst{19-16} = shift{16-13}; // Rn
1510 let Inst{15-12} = Rt;
1511 let Inst{11-0} = shift{11-0};
1515 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1516 InstrItinClass iir, PatFrag opnode> {
1517 // Note: We use the complex addrmode_imm12 rather than just an input
1518 // GPR and a constrained immediate so that we can use this to match
1519 // frame index references and avoid matching constant pool references.
1520 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1521 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1522 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1523 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1526 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1527 let Inst{19-16} = addr{16-13}; // Rn
1528 let Inst{15-12} = Rt;
1529 let Inst{11-0} = addr{11-0}; // imm12
1531 def rs : AI2ldst<0b011, 0, isByte, (outs),
1532 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1533 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1534 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1537 let shift{4} = 0; // Inst{4} = 0
1538 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1539 let Inst{19-16} = shift{16-13}; // Rn
1540 let Inst{15-12} = Rt;
1541 let Inst{11-0} = shift{11-0};
1546 //===----------------------------------------------------------------------===//
1548 //===----------------------------------------------------------------------===//
1550 //===----------------------------------------------------------------------===//
1551 // Miscellaneous Instructions.
1554 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1555 /// the function. The first operand is the ID# for this instruction, the second
1556 /// is the index into the MachineConstantPool that this is, the third is the
1557 /// size in bytes of this constant pool entry.
1558 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1559 def CONSTPOOL_ENTRY :
1560 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1561 i32imm:$size), NoItinerary, []>;
1563 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1564 // from removing one half of the matched pairs. That breaks PEI, which assumes
1565 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1566 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1567 def ADJCALLSTACKUP :
1568 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1569 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1571 def ADJCALLSTACKDOWN :
1572 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1573 [(ARMcallseq_start timm:$amt)]>;
1576 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1577 // (These pseudos use a hand-written selection code).
1578 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1579 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1580 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1582 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1583 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1585 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1586 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1588 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1589 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1591 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1592 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1594 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1595 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1597 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1598 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1600 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1601 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1602 GPR:$set1, GPR:$set2),
1606 def HINT : AI<(outs), (ins imm0_255:$imm), MiscFrm, NoItinerary,
1607 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1609 let Inst{27-8} = 0b00110010000011110000;
1610 let Inst{7-0} = imm;
1613 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1614 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1615 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1616 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1617 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1619 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1620 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1625 let Inst{15-12} = Rd;
1626 let Inst{19-16} = Rn;
1627 let Inst{27-20} = 0b01101000;
1628 let Inst{7-4} = 0b1011;
1629 let Inst{11-8} = 0b1111;
1630 let Unpredictable{11-8} = 0b1111;
1633 // The 16-bit operand $val can be used by a debugger to store more information
1634 // about the breakpoint.
1635 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1636 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1638 let Inst{3-0} = val{3-0};
1639 let Inst{19-8} = val{15-4};
1640 let Inst{27-20} = 0b00010010;
1641 let Inst{7-4} = 0b0111;
1644 // Change Processor State
1645 // FIXME: We should use InstAlias to handle the optional operands.
1646 class CPS<dag iops, string asm_ops>
1647 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1648 []>, Requires<[IsARM]> {
1654 let Inst{31-28} = 0b1111;
1655 let Inst{27-20} = 0b00010000;
1656 let Inst{19-18} = imod;
1657 let Inst{17} = M; // Enabled if mode is set;
1658 let Inst{16-9} = 0b00000000;
1659 let Inst{8-6} = iflags;
1661 let Inst{4-0} = mode;
1664 let DecoderMethod = "DecodeCPSInstruction" in {
1666 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1667 "$imod\t$iflags, $mode">;
1668 let mode = 0, M = 0 in
1669 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1671 let imod = 0, iflags = 0, M = 1 in
1672 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1675 // Preload signals the memory system of possible future data/instruction access.
1676 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1678 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1679 !strconcat(opc, "\t$addr"),
1680 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1683 let Inst{31-26} = 0b111101;
1684 let Inst{25} = 0; // 0 for immediate form
1685 let Inst{24} = data;
1686 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1687 let Inst{22} = read;
1688 let Inst{21-20} = 0b01;
1689 let Inst{19-16} = addr{16-13}; // Rn
1690 let Inst{15-12} = 0b1111;
1691 let Inst{11-0} = addr{11-0}; // imm12
1694 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1695 !strconcat(opc, "\t$shift"),
1696 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1698 let Inst{31-26} = 0b111101;
1699 let Inst{25} = 1; // 1 for register form
1700 let Inst{24} = data;
1701 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1702 let Inst{22} = read;
1703 let Inst{21-20} = 0b01;
1704 let Inst{19-16} = shift{16-13}; // Rn
1705 let Inst{15-12} = 0b1111;
1706 let Inst{11-0} = shift{11-0};
1711 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1712 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1713 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1715 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1716 "setend\t$end", []>, Requires<[IsARM]> {
1718 let Inst{31-10} = 0b1111000100000001000000;
1723 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1724 []>, Requires<[IsARM, HasV7]> {
1726 let Inst{27-4} = 0b001100100000111100001111;
1727 let Inst{3-0} = opt;
1730 // A5.4 Permanently UNDEFINED instructions.
1731 let isBarrier = 1, isTerminator = 1 in
1732 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1735 let Inst = 0xe7ffdefe;
1738 // Address computation and loads and stores in PIC mode.
1739 let isNotDuplicable = 1 in {
1740 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1742 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1744 let AddedComplexity = 10 in {
1745 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1747 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1749 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1751 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1753 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1755 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1757 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1759 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1761 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1763 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1765 let AddedComplexity = 10 in {
1766 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1767 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1769 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1770 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1771 addrmodepc:$addr)]>;
1773 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1774 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1776 } // isNotDuplicable = 1
1779 // LEApcrel - Load a pc-relative address into a register without offending the
1781 let neverHasSideEffects = 1, isReMaterializable = 1 in
1782 // The 'adr' mnemonic encodes differently if the label is before or after
1783 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1784 // know until then which form of the instruction will be used.
1785 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1786 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1789 let Inst{27-25} = 0b001;
1791 let Inst{23-22} = label{13-12};
1794 let Inst{19-16} = 0b1111;
1795 let Inst{15-12} = Rd;
1796 let Inst{11-0} = label{11-0};
1798 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1801 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1802 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1805 //===----------------------------------------------------------------------===//
1806 // Control Flow Instructions.
1809 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1811 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1812 "bx", "\tlr", [(ARMretflag)]>,
1813 Requires<[IsARM, HasV4T]> {
1814 let Inst{27-0} = 0b0001001011111111111100011110;
1818 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1819 "mov", "\tpc, lr", [(ARMretflag)]>,
1820 Requires<[IsARM, NoV4T]> {
1821 let Inst{27-0} = 0b0001101000001111000000001110;
1825 // Indirect branches
1826 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1828 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1829 [(brind GPR:$dst)]>,
1830 Requires<[IsARM, HasV4T]> {
1832 let Inst{31-4} = 0b1110000100101111111111110001;
1833 let Inst{3-0} = dst;
1836 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1837 "bx", "\t$dst", [/* pattern left blank */]>,
1838 Requires<[IsARM, HasV4T]> {
1840 let Inst{27-4} = 0b000100101111111111110001;
1841 let Inst{3-0} = dst;
1845 // SP is marked as a use to prevent stack-pointer assignments that appear
1846 // immediately before calls from potentially appearing dead.
1848 // FIXME: Do we really need a non-predicated version? If so, it should
1849 // at least be a pseudo instruction expanding to the predicated version
1850 // at MC lowering time.
1851 Defs = [LR], Uses = [SP] in {
1852 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1853 IIC_Br, "bl\t$func",
1854 [(ARMcall tglobaladdr:$func)]>,
1856 let Inst{31-28} = 0b1110;
1858 let Inst{23-0} = func;
1859 let DecoderMethod = "DecodeBranchImmInstruction";
1862 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1863 IIC_Br, "bl", "\t$func",
1864 [(ARMcall_pred tglobaladdr:$func)]>,
1867 let Inst{23-0} = func;
1868 let DecoderMethod = "DecodeBranchImmInstruction";
1872 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
1873 IIC_Br, "blx\t$func",
1874 [(ARMcall GPR:$func)]>,
1875 Requires<[IsARM, HasV5T]> {
1877 let Inst{31-4} = 0b1110000100101111111111110011;
1878 let Inst{3-0} = func;
1881 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
1882 IIC_Br, "blx", "\t$func",
1883 [(ARMcall_pred GPR:$func)]>,
1884 Requires<[IsARM, HasV5T]> {
1886 let Inst{27-4} = 0b000100101111111111110011;
1887 let Inst{3-0} = func;
1891 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1892 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
1893 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1894 Requires<[IsARM, HasV4T]>;
1897 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
1898 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1899 Requires<[IsARM, NoV4T]>;
1901 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
1902 // return stack predictor.
1903 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
1904 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
1908 let isBranch = 1, isTerminator = 1 in {
1909 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1910 // a two-value operand where a dag node expects two operands. :(
1911 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1912 IIC_Br, "b", "\t$target",
1913 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1915 let Inst{23-0} = target;
1916 let DecoderMethod = "DecodeBranchImmInstruction";
1919 let isBarrier = 1 in {
1920 // B is "predicable" since it's just a Bcc with an 'always' condition.
1921 let isPredicable = 1 in
1922 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1923 // should be sufficient.
1924 // FIXME: Is B really a Barrier? That doesn't seem right.
1925 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
1926 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1928 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1929 def BR_JTr : ARMPseudoInst<(outs),
1930 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1932 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1933 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1934 // into i12 and rs suffixed versions.
1935 def BR_JTm : ARMPseudoInst<(outs),
1936 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1938 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1940 def BR_JTadd : ARMPseudoInst<(outs),
1941 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1943 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1945 } // isNotDuplicable = 1, isIndirectBranch = 1
1951 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
1952 "blx\t$target", []>,
1953 Requires<[IsARM, HasV5T]> {
1954 let Inst{31-25} = 0b1111101;
1956 let Inst{23-0} = target{24-1};
1957 let Inst{24} = target{0};
1960 // Branch and Exchange Jazelle
1961 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1962 [/* pattern left blank */]> {
1964 let Inst{23-20} = 0b0010;
1965 let Inst{19-8} = 0xfff;
1966 let Inst{7-4} = 0b0010;
1967 let Inst{3-0} = func;
1972 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
1973 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>;
1975 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>;
1977 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
1979 (Bcc br_target:$dst, (ops 14, zero_reg))>,
1982 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
1988 // Secure Monitor Call is a system instruction.
1989 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
1992 let Inst{23-4} = 0b01100000000000000111;
1993 let Inst{3-0} = opt;
1996 // Supervisor Call (Software Interrupt)
1997 let isCall = 1, Uses = [SP] in {
1998 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2000 let Inst{23-0} = svc;
2004 // Store Return State
2005 class SRSI<bit wb, string asm>
2006 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2007 NoItinerary, asm, "", []> {
2009 let Inst{31-28} = 0b1111;
2010 let Inst{27-25} = 0b100;
2014 let Inst{19-16} = 0b1101; // SP
2015 let Inst{15-5} = 0b00000101000;
2016 let Inst{4-0} = mode;
2019 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2020 let Inst{24-23} = 0;
2022 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2023 let Inst{24-23} = 0;
2025 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2026 let Inst{24-23} = 0b10;
2028 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2029 let Inst{24-23} = 0b10;
2031 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2032 let Inst{24-23} = 0b01;
2034 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2035 let Inst{24-23} = 0b01;
2037 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2038 let Inst{24-23} = 0b11;
2040 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2041 let Inst{24-23} = 0b11;
2044 // Return From Exception
2045 class RFEI<bit wb, string asm>
2046 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2047 NoItinerary, asm, "", []> {
2049 let Inst{31-28} = 0b1111;
2050 let Inst{27-25} = 0b100;
2054 let Inst{19-16} = Rn;
2055 let Inst{15-0} = 0xa00;
2058 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2059 let Inst{24-23} = 0;
2061 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2062 let Inst{24-23} = 0;
2064 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2065 let Inst{24-23} = 0b10;
2067 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2068 let Inst{24-23} = 0b10;
2070 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2071 let Inst{24-23} = 0b01;
2073 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2074 let Inst{24-23} = 0b01;
2076 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2077 let Inst{24-23} = 0b11;
2079 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2080 let Inst{24-23} = 0b11;
2083 //===----------------------------------------------------------------------===//
2084 // Load / Store Instructions.
2090 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2091 UnOpFrag<(load node:$Src)>>;
2092 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2093 UnOpFrag<(zextloadi8 node:$Src)>>;
2094 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2095 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2096 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2097 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2099 // Special LDR for loads from non-pc-relative constpools.
2100 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2101 isReMaterializable = 1, isCodeGenOnly = 1 in
2102 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2103 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2107 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2108 let Inst{19-16} = 0b1111;
2109 let Inst{15-12} = Rt;
2110 let Inst{11-0} = addr{11-0}; // imm12
2113 // Loads with zero extension
2114 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2115 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2116 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2118 // Loads with sign extension
2119 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2120 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2121 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2123 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2124 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2125 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2127 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2129 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2130 (ins addrmode3:$addr), LdMiscFrm,
2131 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2132 []>, Requires<[IsARM, HasV5TE]>;
2136 multiclass AI2_ldridx<bit isByte, string opc,
2137 InstrItinClass iii, InstrItinClass iir> {
2138 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2139 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, iii,
2140 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2143 let Inst{23} = addr{12};
2144 let Inst{19-16} = addr{16-13};
2145 let Inst{11-0} = addr{11-0};
2146 let DecoderMethod = "DecodeLDRPreImm";
2147 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2150 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2151 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2152 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2155 let Inst{23} = addr{12};
2156 let Inst{19-16} = addr{16-13};
2157 let Inst{11-0} = addr{11-0};
2159 let DecoderMethod = "DecodeLDRPreReg";
2160 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2163 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2164 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2165 IndexModePost, LdFrm, iir,
2166 opc, "\t$Rt, $addr, $offset",
2167 "$addr.base = $Rn_wb", []> {
2173 let Inst{23} = offset{12};
2174 let Inst{19-16} = addr;
2175 let Inst{11-0} = offset{11-0};
2177 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2180 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2181 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2182 IndexModePost, LdFrm, iii,
2183 opc, "\t$Rt, $addr, $offset",
2184 "$addr.base = $Rn_wb", []> {
2190 let Inst{23} = offset{12};
2191 let Inst{19-16} = addr;
2192 let Inst{11-0} = offset{11-0};
2194 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2199 let mayLoad = 1, neverHasSideEffects = 1 in {
2200 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2201 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2202 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2203 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2206 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2207 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2208 (ins addrmode3:$addr), IndexModePre,
2210 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2212 let Inst{23} = addr{8}; // U bit
2213 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2214 let Inst{19-16} = addr{12-9}; // Rn
2215 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2216 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2217 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2218 let DecoderMethod = "DecodeAddrMode3Instruction";
2220 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2221 (ins addr_offset_none:$addr, am3offset:$offset),
2222 IndexModePost, LdMiscFrm, itin,
2223 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2227 let Inst{23} = offset{8}; // U bit
2228 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2229 let Inst{19-16} = addr;
2230 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2231 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2232 let DecoderMethod = "DecodeAddrMode3Instruction";
2236 let mayLoad = 1, neverHasSideEffects = 1 in {
2237 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2238 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2239 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2240 let hasExtraDefRegAllocReq = 1 in {
2241 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2242 (ins addrmode3:$addr), IndexModePre,
2243 LdMiscFrm, IIC_iLoad_d_ru,
2244 "ldrd", "\t$Rt, $Rt2, $addr!",
2245 "$addr.base = $Rn_wb", []> {
2247 let Inst{23} = addr{8}; // U bit
2248 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2249 let Inst{19-16} = addr{12-9}; // Rn
2250 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2251 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2252 let DecoderMethod = "DecodeAddrMode3Instruction";
2253 let AsmMatchConverter = "cvtLdrdPre";
2255 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2256 (ins addr_offset_none:$addr, am3offset:$offset),
2257 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2258 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2259 "$addr.base = $Rn_wb", []> {
2262 let Inst{23} = offset{8}; // U bit
2263 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2264 let Inst{19-16} = addr;
2265 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2266 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2267 let DecoderMethod = "DecodeAddrMode3Instruction";
2269 } // hasExtraDefRegAllocReq = 1
2270 } // mayLoad = 1, neverHasSideEffects = 1
2272 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2273 let mayLoad = 1, neverHasSideEffects = 1 in {
2274 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2275 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2276 IndexModePost, LdFrm, IIC_iLoad_ru,
2277 "ldrt", "\t$Rt, $addr, $offset",
2278 "$addr.base = $Rn_wb", []> {
2284 let Inst{23} = offset{12};
2285 let Inst{21} = 1; // overwrite
2286 let Inst{19-16} = addr;
2287 let Inst{11-5} = offset{11-5};
2289 let Inst{3-0} = offset{3-0};
2290 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2293 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2294 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2295 IndexModePost, LdFrm, IIC_iLoad_ru,
2296 "ldrt", "\t$Rt, $addr, $offset",
2297 "$addr.base = $Rn_wb", []> {
2303 let Inst{23} = offset{12};
2304 let Inst{21} = 1; // overwrite
2305 let Inst{19-16} = addr;
2306 let Inst{11-0} = offset{11-0};
2307 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2310 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2311 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2312 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2313 "ldrbt", "\t$Rt, $addr, $offset",
2314 "$addr.base = $Rn_wb", []> {
2320 let Inst{23} = offset{12};
2321 let Inst{21} = 1; // overwrite
2322 let Inst{19-16} = addr;
2323 let Inst{11-5} = offset{11-5};
2325 let Inst{3-0} = offset{3-0};
2326 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2329 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2330 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2331 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2332 "ldrbt", "\t$Rt, $addr, $offset",
2333 "$addr.base = $Rn_wb", []> {
2339 let Inst{23} = offset{12};
2340 let Inst{21} = 1; // overwrite
2341 let Inst{19-16} = addr;
2342 let Inst{11-0} = offset{11-0};
2343 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2346 multiclass AI3ldrT<bits<4> op, string opc> {
2347 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2348 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2349 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2350 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2352 let Inst{23} = offset{8};
2354 let Inst{11-8} = offset{7-4};
2355 let Inst{3-0} = offset{3-0};
2356 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2358 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2359 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2360 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2361 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2363 let Inst{23} = Rm{4};
2366 let Unpredictable{11-8} = 0b1111;
2367 let Inst{3-0} = Rm{3-0};
2368 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2369 let DecoderMethod = "DecodeLDR";
2373 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2374 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2375 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2380 // Stores with truncate
2381 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2382 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2383 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2386 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2387 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2388 StMiscFrm, IIC_iStore_d_r,
2389 "strd", "\t$Rt, $src2, $addr", []>,
2390 Requires<[IsARM, HasV5TE]> {
2395 multiclass AI2_stridx<bit isByte, string opc,
2396 InstrItinClass iii, InstrItinClass iir> {
2397 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2398 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2400 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2403 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2404 let Inst{19-16} = addr{16-13}; // Rn
2405 let Inst{11-0} = addr{11-0}; // imm12
2406 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2407 let DecoderMethod = "DecodeSTRPreImm";
2410 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2411 (ins GPR:$Rt, ldst_so_reg:$addr),
2412 IndexModePre, StFrm, iir,
2413 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2416 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2417 let Inst{19-16} = addr{16-13}; // Rn
2418 let Inst{11-0} = addr{11-0};
2419 let Inst{4} = 0; // Inst{4} = 0
2420 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2421 let DecoderMethod = "DecodeSTRPreReg";
2423 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2424 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2425 IndexModePost, StFrm, iir,
2426 opc, "\t$Rt, $addr, $offset",
2427 "$addr.base = $Rn_wb", []> {
2433 let Inst{23} = offset{12};
2434 let Inst{19-16} = addr;
2435 let Inst{11-0} = offset{11-0};
2438 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2441 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2442 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2443 IndexModePost, StFrm, iii,
2444 opc, "\t$Rt, $addr, $offset",
2445 "$addr.base = $Rn_wb", []> {
2451 let Inst{23} = offset{12};
2452 let Inst{19-16} = addr;
2453 let Inst{11-0} = offset{11-0};
2455 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2459 let mayStore = 1, neverHasSideEffects = 1 in {
2460 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2461 // IIC_iStore_siu depending on whether it the offset register is shifted.
2462 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2463 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2466 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2467 am2offset_reg:$offset),
2468 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2469 am2offset_reg:$offset)>;
2470 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2471 am2offset_imm:$offset),
2472 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2473 am2offset_imm:$offset)>;
2474 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2475 am2offset_reg:$offset),
2476 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2477 am2offset_reg:$offset)>;
2478 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2479 am2offset_imm:$offset),
2480 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2481 am2offset_imm:$offset)>;
2483 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2484 // put the patterns on the instruction definitions directly as ISel wants
2485 // the address base and offset to be separate operands, not a single
2486 // complex operand like we represent the instructions themselves. The
2487 // pseudos map between the two.
2488 let usesCustomInserter = 1,
2489 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2490 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2491 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2494 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2495 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2496 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2499 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2500 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2501 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2504 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2505 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2506 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2509 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2510 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2511 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2514 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2519 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2520 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2521 StMiscFrm, IIC_iStore_bh_ru,
2522 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2524 let Inst{23} = addr{8}; // U bit
2525 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2526 let Inst{19-16} = addr{12-9}; // Rn
2527 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2528 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2529 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2530 let DecoderMethod = "DecodeAddrMode3Instruction";
2533 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2534 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2535 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2536 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2537 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2538 addr_offset_none:$addr,
2539 am3offset:$offset))]> {
2542 let Inst{23} = offset{8}; // U bit
2543 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2544 let Inst{19-16} = addr;
2545 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2546 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2547 let DecoderMethod = "DecodeAddrMode3Instruction";
2550 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2551 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2552 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2553 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2554 "strd", "\t$Rt, $Rt2, $addr!",
2555 "$addr.base = $Rn_wb", []> {
2557 let Inst{23} = addr{8}; // U bit
2558 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2559 let Inst{19-16} = addr{12-9}; // Rn
2560 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2561 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2562 let DecoderMethod = "DecodeAddrMode3Instruction";
2563 let AsmMatchConverter = "cvtStrdPre";
2566 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2567 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2569 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2570 "strd", "\t$Rt, $Rt2, $addr, $offset",
2571 "$addr.base = $Rn_wb", []> {
2574 let Inst{23} = offset{8}; // U bit
2575 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2576 let Inst{19-16} = addr;
2577 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2578 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2579 let DecoderMethod = "DecodeAddrMode3Instruction";
2581 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2583 // STRT, STRBT, and STRHT
2585 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2586 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2587 IndexModePost, StFrm, IIC_iStore_bh_ru,
2588 "strbt", "\t$Rt, $addr, $offset",
2589 "$addr.base = $Rn_wb", []> {
2595 let Inst{23} = offset{12};
2596 let Inst{21} = 1; // overwrite
2597 let Inst{19-16} = addr;
2598 let Inst{11-5} = offset{11-5};
2600 let Inst{3-0} = offset{3-0};
2601 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2604 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2605 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2606 IndexModePost, StFrm, IIC_iStore_bh_ru,
2607 "strbt", "\t$Rt, $addr, $offset",
2608 "$addr.base = $Rn_wb", []> {
2614 let Inst{23} = offset{12};
2615 let Inst{21} = 1; // overwrite
2616 let Inst{19-16} = addr;
2617 let Inst{11-0} = offset{11-0};
2618 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2621 let mayStore = 1, neverHasSideEffects = 1 in {
2622 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2623 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2624 IndexModePost, StFrm, IIC_iStore_ru,
2625 "strt", "\t$Rt, $addr, $offset",
2626 "$addr.base = $Rn_wb", []> {
2632 let Inst{23} = offset{12};
2633 let Inst{21} = 1; // overwrite
2634 let Inst{19-16} = addr;
2635 let Inst{11-5} = offset{11-5};
2637 let Inst{3-0} = offset{3-0};
2638 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2641 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2642 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2643 IndexModePost, StFrm, IIC_iStore_ru,
2644 "strt", "\t$Rt, $addr, $offset",
2645 "$addr.base = $Rn_wb", []> {
2651 let Inst{23} = offset{12};
2652 let Inst{21} = 1; // overwrite
2653 let Inst{19-16} = addr;
2654 let Inst{11-0} = offset{11-0};
2655 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2660 multiclass AI3strT<bits<4> op, string opc> {
2661 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2662 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2663 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2664 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2666 let Inst{23} = offset{8};
2668 let Inst{11-8} = offset{7-4};
2669 let Inst{3-0} = offset{3-0};
2670 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2672 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2673 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2674 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2675 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2677 let Inst{23} = Rm{4};
2680 let Inst{3-0} = Rm{3-0};
2681 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2686 defm STRHT : AI3strT<0b1011, "strht">;
2689 //===----------------------------------------------------------------------===//
2690 // Load / store multiple Instructions.
2693 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2694 InstrItinClass itin, InstrItinClass itin_upd> {
2695 // IA is the default, so no need for an explicit suffix on the
2696 // mnemonic here. Without it is the canonical spelling.
2698 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2699 IndexModeNone, f, itin,
2700 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2701 let Inst{24-23} = 0b01; // Increment After
2702 let Inst{22} = P_bit;
2703 let Inst{21} = 0; // No writeback
2704 let Inst{20} = L_bit;
2707 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2708 IndexModeUpd, f, itin_upd,
2709 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2710 let Inst{24-23} = 0b01; // Increment After
2711 let Inst{22} = P_bit;
2712 let Inst{21} = 1; // Writeback
2713 let Inst{20} = L_bit;
2715 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2718 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2719 IndexModeNone, f, itin,
2720 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2721 let Inst{24-23} = 0b00; // Decrement After
2722 let Inst{22} = P_bit;
2723 let Inst{21} = 0; // No writeback
2724 let Inst{20} = L_bit;
2727 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2728 IndexModeUpd, f, itin_upd,
2729 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2730 let Inst{24-23} = 0b00; // Decrement After
2731 let Inst{22} = P_bit;
2732 let Inst{21} = 1; // Writeback
2733 let Inst{20} = L_bit;
2735 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2738 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2739 IndexModeNone, f, itin,
2740 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2741 let Inst{24-23} = 0b10; // Decrement Before
2742 let Inst{22} = P_bit;
2743 let Inst{21} = 0; // No writeback
2744 let Inst{20} = L_bit;
2747 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2748 IndexModeUpd, f, itin_upd,
2749 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2750 let Inst{24-23} = 0b10; // Decrement Before
2751 let Inst{22} = P_bit;
2752 let Inst{21} = 1; // Writeback
2753 let Inst{20} = L_bit;
2755 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2758 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2759 IndexModeNone, f, itin,
2760 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2761 let Inst{24-23} = 0b11; // Increment Before
2762 let Inst{22} = P_bit;
2763 let Inst{21} = 0; // No writeback
2764 let Inst{20} = L_bit;
2767 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2768 IndexModeUpd, f, itin_upd,
2769 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2770 let Inst{24-23} = 0b11; // Increment Before
2771 let Inst{22} = P_bit;
2772 let Inst{21} = 1; // Writeback
2773 let Inst{20} = L_bit;
2775 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2779 let neverHasSideEffects = 1 in {
2781 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2782 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2785 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2786 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2789 } // neverHasSideEffects
2791 // FIXME: remove when we have a way to marking a MI with these properties.
2792 // FIXME: Should pc be an implicit operand like PICADD, etc?
2793 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2794 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2795 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2796 reglist:$regs, variable_ops),
2797 4, IIC_iLoad_mBr, [],
2798 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2799 RegConstraint<"$Rn = $wb">;
2801 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2802 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2805 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2806 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2811 //===----------------------------------------------------------------------===//
2812 // Move Instructions.
2815 let neverHasSideEffects = 1 in
2816 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2817 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2821 let Inst{19-16} = 0b0000;
2822 let Inst{11-4} = 0b00000000;
2825 let Inst{15-12} = Rd;
2828 // A version for the smaller set of tail call registers.
2829 let neverHasSideEffects = 1 in
2830 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2831 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2835 let Inst{11-4} = 0b00000000;
2838 let Inst{15-12} = Rd;
2841 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2842 DPSoRegRegFrm, IIC_iMOVsr,
2843 "mov", "\t$Rd, $src",
2844 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2847 let Inst{15-12} = Rd;
2848 let Inst{19-16} = 0b0000;
2849 let Inst{11-8} = src{11-8};
2851 let Inst{6-5} = src{6-5};
2853 let Inst{3-0} = src{3-0};
2857 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2858 DPSoRegImmFrm, IIC_iMOVsr,
2859 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2863 let Inst{15-12} = Rd;
2864 let Inst{19-16} = 0b0000;
2865 let Inst{11-5} = src{11-5};
2867 let Inst{3-0} = src{3-0};
2871 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2872 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2873 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2877 let Inst{15-12} = Rd;
2878 let Inst{19-16} = 0b0000;
2879 let Inst{11-0} = imm;
2882 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2883 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
2885 "movw", "\t$Rd, $imm",
2886 [(set GPR:$Rd, imm0_65535:$imm)]>,
2887 Requires<[IsARM, HasV6T2]>, UnaryDP {
2890 let Inst{15-12} = Rd;
2891 let Inst{11-0} = imm{11-0};
2892 let Inst{19-16} = imm{15-12};
2895 let DecoderMethod = "DecodeArmMOVTWInstruction";
2898 def : InstAlias<"mov${p} $Rd, $imm",
2899 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
2902 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2903 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2905 let Constraints = "$src = $Rd" in {
2906 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
2907 (ins GPR:$src, imm0_65535_expr:$imm),
2909 "movt", "\t$Rd, $imm",
2911 (or (and GPR:$src, 0xffff),
2912 lo16AllZero:$imm))]>, UnaryDP,
2913 Requires<[IsARM, HasV6T2]> {
2916 let Inst{15-12} = Rd;
2917 let Inst{11-0} = imm{11-0};
2918 let Inst{19-16} = imm{15-12};
2921 let DecoderMethod = "DecodeArmMOVTWInstruction";
2924 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2925 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2929 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2930 Requires<[IsARM, HasV6T2]>;
2932 let Uses = [CPSR] in
2933 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2934 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2937 // These aren't really mov instructions, but we have to define them this way
2938 // due to flag operands.
2940 let Defs = [CPSR] in {
2941 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2942 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2944 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2945 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2949 //===----------------------------------------------------------------------===//
2950 // Extend Instructions.
2955 def SXTB : AI_ext_rrot<0b01101010,
2956 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2957 def SXTH : AI_ext_rrot<0b01101011,
2958 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2960 def SXTAB : AI_exta_rrot<0b01101010,
2961 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2962 def SXTAH : AI_exta_rrot<0b01101011,
2963 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2965 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2967 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2971 let AddedComplexity = 16 in {
2972 def UXTB : AI_ext_rrot<0b01101110,
2973 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2974 def UXTH : AI_ext_rrot<0b01101111,
2975 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2976 def UXTB16 : AI_ext_rrot<0b01101100,
2977 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2979 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2980 // The transformation should probably be done as a combiner action
2981 // instead so we can include a check for masking back in the upper
2982 // eight bits of the source into the lower eight bits of the result.
2983 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2984 // (UXTB16r_rot GPR:$Src, 3)>;
2985 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2986 (UXTB16 GPR:$Src, 1)>;
2988 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2989 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2990 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2991 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2994 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2995 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2998 def SBFX : I<(outs GPRnopc:$Rd),
2999 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3000 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3001 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3002 Requires<[IsARM, HasV6T2]> {
3007 let Inst{27-21} = 0b0111101;
3008 let Inst{6-4} = 0b101;
3009 let Inst{20-16} = width;
3010 let Inst{15-12} = Rd;
3011 let Inst{11-7} = lsb;
3015 def UBFX : I<(outs GPR:$Rd),
3016 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3017 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3018 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3019 Requires<[IsARM, HasV6T2]> {
3024 let Inst{27-21} = 0b0111111;
3025 let Inst{6-4} = 0b101;
3026 let Inst{20-16} = width;
3027 let Inst{15-12} = Rd;
3028 let Inst{11-7} = lsb;
3032 //===----------------------------------------------------------------------===//
3033 // Arithmetic Instructions.
3036 defm ADD : AsI1_bin_irs<0b0100, "add",
3037 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3038 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3039 defm SUB : AsI1_bin_irs<0b0010, "sub",
3040 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3041 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3043 // ADD and SUB with 's' bit set.
3045 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3046 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3047 // AdjustInstrPostInstrSelection where we determine whether or not to
3048 // set the "s" bit based on CPSR liveness.
3050 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3051 // support for an optional CPSR definition that corresponds to the DAG
3052 // node's second value. We can then eliminate the implicit def of CPSR.
3053 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3054 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3055 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3056 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3058 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3059 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3060 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3061 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3063 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3064 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3065 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3067 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3068 // CPSR and the implicit def of CPSR is not needed.
3069 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3070 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3072 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3073 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3075 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3076 // The assume-no-carry-in form uses the negation of the input since add/sub
3077 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3078 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3080 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3081 (SUBri GPR:$src, so_imm_neg:$imm)>;
3082 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3083 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3085 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3086 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>;
3087 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3088 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>;
3090 // The with-carry-in form matches bitwise not instead of the negation.
3091 // Effectively, the inverse interpretation of the carry flag already accounts
3092 // for part of the negation.
3093 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3094 (SBCri GPR:$src, so_imm_not:$imm)>;
3096 // Note: These are implemented in C++ code, because they have to generate
3097 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3099 // (mul X, 2^n+1) -> (add (X << n), X)
3100 // (mul X, 2^n-1) -> (rsb X, (X << n))
3102 // ARM Arithmetic Instruction
3103 // GPR:$dst = GPR:$a op GPR:$b
3104 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3105 list<dag> pattern = [],
3106 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3107 string asm = "\t$Rd, $Rn, $Rm">
3108 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3112 let Inst{27-20} = op27_20;
3113 let Inst{11-4} = op11_4;
3114 let Inst{19-16} = Rn;
3115 let Inst{15-12} = Rd;
3118 let Unpredictable{11-8} = 0b1111;
3121 // Saturating add/subtract
3123 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3124 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3125 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3126 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3127 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3128 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3129 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3130 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3132 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3133 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3136 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3137 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3138 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3139 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3140 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3141 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3142 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3143 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3144 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3145 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3146 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3147 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3149 // Signed/Unsigned add/subtract
3151 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3152 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3153 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3154 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3155 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3156 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3157 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3158 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3159 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3160 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3161 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3162 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3164 // Signed/Unsigned halving add/subtract
3166 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3167 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3168 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3169 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3170 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3171 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3172 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3173 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3174 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3175 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3176 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3177 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3179 // Unsigned Sum of Absolute Differences [and Accumulate].
3181 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3182 MulFrm /* for convenience */, NoItinerary, "usad8",
3183 "\t$Rd, $Rn, $Rm", []>,
3184 Requires<[IsARM, HasV6]> {
3188 let Inst{27-20} = 0b01111000;
3189 let Inst{15-12} = 0b1111;
3190 let Inst{7-4} = 0b0001;
3191 let Inst{19-16} = Rd;
3192 let Inst{11-8} = Rm;
3195 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3196 MulFrm /* for convenience */, NoItinerary, "usada8",
3197 "\t$Rd, $Rn, $Rm, $Ra", []>,
3198 Requires<[IsARM, HasV6]> {
3203 let Inst{27-20} = 0b01111000;
3204 let Inst{7-4} = 0b0001;
3205 let Inst{19-16} = Rd;
3206 let Inst{15-12} = Ra;
3207 let Inst{11-8} = Rm;
3211 // Signed/Unsigned saturate
3213 def SSAT : AI<(outs GPRnopc:$Rd),
3214 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3215 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3220 let Inst{27-21} = 0b0110101;
3221 let Inst{5-4} = 0b01;
3222 let Inst{20-16} = sat_imm;
3223 let Inst{15-12} = Rd;
3224 let Inst{11-7} = sh{4-0};
3225 let Inst{6} = sh{5};
3229 def SSAT16 : AI<(outs GPRnopc:$Rd),
3230 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3231 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3235 let Inst{27-20} = 0b01101010;
3236 let Inst{11-4} = 0b11110011;
3237 let Inst{15-12} = Rd;
3238 let Inst{19-16} = sat_imm;
3242 def USAT : AI<(outs GPRnopc:$Rd),
3243 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3244 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3249 let Inst{27-21} = 0b0110111;
3250 let Inst{5-4} = 0b01;
3251 let Inst{15-12} = Rd;
3252 let Inst{11-7} = sh{4-0};
3253 let Inst{6} = sh{5};
3254 let Inst{20-16} = sat_imm;
3258 def USAT16 : AI<(outs GPRnopc:$Rd),
3259 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3260 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3264 let Inst{27-20} = 0b01101110;
3265 let Inst{11-4} = 0b11110011;
3266 let Inst{15-12} = Rd;
3267 let Inst{19-16} = sat_imm;
3271 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3272 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3273 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3274 (USAT imm:$pos, GPRnopc:$a, 0)>;
3276 //===----------------------------------------------------------------------===//
3277 // Bitwise Instructions.
3280 defm AND : AsI1_bin_irs<0b0000, "and",
3281 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3282 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3283 defm ORR : AsI1_bin_irs<0b1100, "orr",
3284 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3285 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3286 defm EOR : AsI1_bin_irs<0b0001, "eor",
3287 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3288 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3289 defm BIC : AsI1_bin_irs<0b1110, "bic",
3290 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3291 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3293 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3294 // like in the actual instruction encoding. The complexity of mapping the mask
3295 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3296 // instruction description.
3297 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3298 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3299 "bfc", "\t$Rd, $imm", "$src = $Rd",
3300 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3301 Requires<[IsARM, HasV6T2]> {
3304 let Inst{27-21} = 0b0111110;
3305 let Inst{6-0} = 0b0011111;
3306 let Inst{15-12} = Rd;
3307 let Inst{11-7} = imm{4-0}; // lsb
3308 let Inst{20-16} = imm{9-5}; // msb
3311 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3312 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3313 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3314 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3315 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3316 bf_inv_mask_imm:$imm))]>,
3317 Requires<[IsARM, HasV6T2]> {
3321 let Inst{27-21} = 0b0111110;
3322 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3323 let Inst{15-12} = Rd;
3324 let Inst{11-7} = imm{4-0}; // lsb
3325 let Inst{20-16} = imm{9-5}; // width
3329 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3330 "mvn", "\t$Rd, $Rm",
3331 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3335 let Inst{19-16} = 0b0000;
3336 let Inst{11-4} = 0b00000000;
3337 let Inst{15-12} = Rd;
3340 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3341 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3342 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3346 let Inst{19-16} = 0b0000;
3347 let Inst{15-12} = Rd;
3348 let Inst{11-5} = shift{11-5};
3350 let Inst{3-0} = shift{3-0};
3352 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3353 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3354 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3358 let Inst{19-16} = 0b0000;
3359 let Inst{15-12} = Rd;
3360 let Inst{11-8} = shift{11-8};
3362 let Inst{6-5} = shift{6-5};
3364 let Inst{3-0} = shift{3-0};
3366 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3367 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3368 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3369 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3373 let Inst{19-16} = 0b0000;
3374 let Inst{15-12} = Rd;
3375 let Inst{11-0} = imm;
3378 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3379 (BICri GPR:$src, so_imm_not:$imm)>;
3381 //===----------------------------------------------------------------------===//
3382 // Multiply Instructions.
3384 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3385 string opc, string asm, list<dag> pattern>
3386 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3390 let Inst{19-16} = Rd;
3391 let Inst{11-8} = Rm;
3394 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3395 string opc, string asm, list<dag> pattern>
3396 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3401 let Inst{19-16} = RdHi;
3402 let Inst{15-12} = RdLo;
3403 let Inst{11-8} = Rm;
3406 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3407 string opc, string asm, list<dag> pattern>
3408 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3413 let Inst{19-16} = RdHi;
3414 let Inst{15-12} = RdLo;
3415 let Inst{11-8} = Rm;
3419 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3420 // property. Remove them when it's possible to add those properties
3421 // on an individual MachineInstr, not just an instruction description.
3422 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3423 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3424 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3425 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3426 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3427 Requires<[IsARM, HasV6]> {
3428 let Inst{15-12} = 0b0000;
3429 let Unpredictable{15-12} = 0b1111;
3432 let Constraints = "@earlyclobber $Rd" in
3433 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3434 pred:$p, cc_out:$s),
3436 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3437 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3438 Requires<[IsARM, NoV6]>;
3441 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3442 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3443 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3444 Requires<[IsARM, HasV6]> {
3446 let Inst{15-12} = Ra;
3449 let Constraints = "@earlyclobber $Rd" in
3450 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3451 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3453 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3454 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3455 Requires<[IsARM, NoV6]>;
3457 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3458 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3459 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3460 Requires<[IsARM, HasV6T2]> {
3465 let Inst{19-16} = Rd;
3466 let Inst{15-12} = Ra;
3467 let Inst{11-8} = Rm;
3471 // Extra precision multiplies with low / high results
3472 let neverHasSideEffects = 1 in {
3473 let isCommutable = 1 in {
3474 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3475 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3476 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3477 Requires<[IsARM, HasV6]>;
3479 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3480 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3481 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3482 Requires<[IsARM, HasV6]>;
3484 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3485 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3486 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3488 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3489 Requires<[IsARM, NoV6]>;
3491 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3492 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3494 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3495 Requires<[IsARM, NoV6]>;
3499 // Multiply + accumulate
3500 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3501 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3502 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3503 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3504 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3505 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3506 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3507 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3509 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3510 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3511 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3512 Requires<[IsARM, HasV6]> {
3517 let Inst{19-16} = RdHi;
3518 let Inst{15-12} = RdLo;
3519 let Inst{11-8} = Rm;
3523 let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
3524 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3525 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3527 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3528 pred:$p, cc_out:$s)>,
3529 Requires<[IsARM, NoV6]>;
3530 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3531 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3533 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3534 pred:$p, cc_out:$s)>,
3535 Requires<[IsARM, NoV6]>;
3538 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3539 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3540 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3542 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3543 Requires<[IsARM, NoV6]>;
3546 } // neverHasSideEffects
3548 // Most significant word multiply
3549 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3550 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3551 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3552 Requires<[IsARM, HasV6]> {
3553 let Inst{15-12} = 0b1111;
3556 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3557 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3558 Requires<[IsARM, HasV6]> {
3559 let Inst{15-12} = 0b1111;
3562 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3563 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3564 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3565 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3566 Requires<[IsARM, HasV6]>;
3568 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3569 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3570 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3571 Requires<[IsARM, HasV6]>;
3573 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3574 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3575 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3576 Requires<[IsARM, HasV6]>;
3578 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3579 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3580 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3581 Requires<[IsARM, HasV6]>;
3583 multiclass AI_smul<string opc, PatFrag opnode> {
3584 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3585 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3586 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3587 (sext_inreg GPR:$Rm, i16)))]>,
3588 Requires<[IsARM, HasV5TE]>;
3590 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3591 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3592 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3593 (sra GPR:$Rm, (i32 16))))]>,
3594 Requires<[IsARM, HasV5TE]>;
3596 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3597 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3598 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3599 (sext_inreg GPR:$Rm, i16)))]>,
3600 Requires<[IsARM, HasV5TE]>;
3602 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3603 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3604 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3605 (sra GPR:$Rm, (i32 16))))]>,
3606 Requires<[IsARM, HasV5TE]>;
3608 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3609 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3610 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3611 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3612 Requires<[IsARM, HasV5TE]>;
3614 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3615 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3616 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3617 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3618 Requires<[IsARM, HasV5TE]>;
3622 multiclass AI_smla<string opc, PatFrag opnode> {
3623 let DecoderMethod = "DecodeSMLAInstruction" in {
3624 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3625 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3626 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3627 [(set GPRnopc:$Rd, (add GPR:$Ra,
3628 (opnode (sext_inreg GPRnopc:$Rn, i16),
3629 (sext_inreg GPRnopc:$Rm, i16))))]>,
3630 Requires<[IsARM, HasV5TE]>;
3632 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3633 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3634 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3636 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3637 (sra GPRnopc:$Rm, (i32 16)))))]>,
3638 Requires<[IsARM, HasV5TE]>;
3640 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3641 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3642 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3644 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3645 (sext_inreg GPRnopc:$Rm, i16))))]>,
3646 Requires<[IsARM, HasV5TE]>;
3648 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3649 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3650 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3652 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3653 (sra GPRnopc:$Rm, (i32 16)))))]>,
3654 Requires<[IsARM, HasV5TE]>;
3656 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3657 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3658 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3660 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3661 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3662 Requires<[IsARM, HasV5TE]>;
3664 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3665 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3666 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3668 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3669 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3670 Requires<[IsARM, HasV5TE]>;
3674 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3675 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3677 // Halfword multiply accumulate long: SMLAL<x><y>.
3678 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3679 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3680 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3681 Requires<[IsARM, HasV5TE]>;
3683 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3684 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3685 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3686 Requires<[IsARM, HasV5TE]>;
3688 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3689 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3690 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3691 Requires<[IsARM, HasV5TE]>;
3693 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3694 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3695 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3696 Requires<[IsARM, HasV5TE]>;
3698 // Helper class for AI_smld.
3699 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3700 InstrItinClass itin, string opc, string asm>
3701 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3704 let Inst{27-23} = 0b01110;
3705 let Inst{22} = long;
3706 let Inst{21-20} = 0b00;
3707 let Inst{11-8} = Rm;
3714 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3715 InstrItinClass itin, string opc, string asm>
3716 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3718 let Inst{15-12} = 0b1111;
3719 let Inst{19-16} = Rd;
3721 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3722 InstrItinClass itin, string opc, string asm>
3723 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3726 let Inst{19-16} = Rd;
3727 let Inst{15-12} = Ra;
3729 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3730 InstrItinClass itin, string opc, string asm>
3731 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3734 let Inst{19-16} = RdHi;
3735 let Inst{15-12} = RdLo;
3738 multiclass AI_smld<bit sub, string opc> {
3740 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3741 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3742 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3744 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3745 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3746 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3748 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3749 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3750 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3752 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3753 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3754 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3758 defm SMLA : AI_smld<0, "smla">;
3759 defm SMLS : AI_smld<1, "smls">;
3761 multiclass AI_sdml<bit sub, string opc> {
3763 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3764 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3765 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3766 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3769 defm SMUA : AI_sdml<0, "smua">;
3770 defm SMUS : AI_sdml<1, "smus">;
3772 //===----------------------------------------------------------------------===//
3773 // Misc. Arithmetic Instructions.
3776 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3777 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3778 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3780 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3781 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3782 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3783 Requires<[IsARM, HasV6T2]>;
3785 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3786 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3787 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3789 let AddedComplexity = 5 in
3790 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3791 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3792 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3793 Requires<[IsARM, HasV6]>;
3795 let AddedComplexity = 5 in
3796 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3797 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3798 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3799 Requires<[IsARM, HasV6]>;
3801 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3802 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3805 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3806 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3807 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3808 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3809 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3811 Requires<[IsARM, HasV6]>;
3813 // Alternate cases for PKHBT where identities eliminate some nodes.
3814 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3815 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3816 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3817 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3819 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3820 // will match the pattern below.
3821 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3822 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3823 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3824 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3825 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
3827 Requires<[IsARM, HasV6]>;
3829 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3830 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3831 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3832 (srl GPRnopc:$src2, imm16_31:$sh)),
3833 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
3834 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
3835 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
3836 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
3838 //===----------------------------------------------------------------------===//
3839 // Comparison Instructions...
3842 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3843 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3844 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3846 // ARMcmpZ can re-use the above instruction definitions.
3847 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3848 (CMPri GPR:$src, so_imm:$imm)>;
3849 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3850 (CMPrr GPR:$src, GPR:$rhs)>;
3851 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3852 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3853 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3854 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3856 // CMN register-integer
3857 let isCompare = 1, Defs = [CPSR] in {
3858 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
3859 "cmn", "\t$Rn, $imm",
3860 [(ARMcmn GPR:$Rn, so_imm:$imm)]> {
3865 let Inst{19-16} = Rn;
3866 let Inst{15-12} = 0b0000;
3867 let Inst{11-0} = imm;
3869 let Unpredictable{15-12} = 0b1111;
3872 // CMN register-register/shift
3873 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
3874 "cmn", "\t$Rn, $Rm",
3875 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3876 GPR:$Rn, GPR:$Rm)]> {
3879 let isCommutable = 1;
3882 let Inst{19-16} = Rn;
3883 let Inst{15-12} = 0b0000;
3884 let Inst{11-4} = 0b00000000;
3887 let Unpredictable{15-12} = 0b1111;
3890 def CMNzrsi : AI1<0b1011, (outs),
3891 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
3892 "cmn", "\t$Rn, $shift",
3893 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3894 GPR:$Rn, so_reg_imm:$shift)]> {
3899 let Inst{19-16} = Rn;
3900 let Inst{15-12} = 0b0000;
3901 let Inst{11-5} = shift{11-5};
3903 let Inst{3-0} = shift{3-0};
3905 let Unpredictable{15-12} = 0b1111;
3908 def CMNzrsr : AI1<0b1011, (outs),
3909 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
3910 "cmn", "\t$Rn, $shift",
3911 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
3912 GPRnopc:$Rn, so_reg_reg:$shift)]> {
3917 let Inst{19-16} = Rn;
3918 let Inst{15-12} = 0b0000;
3919 let Inst{11-8} = shift{11-8};
3921 let Inst{6-5} = shift{6-5};
3923 let Inst{3-0} = shift{3-0};
3925 let Unpredictable{15-12} = 0b1111;
3930 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3931 (CMNri GPR:$src, so_imm_neg:$imm)>;
3933 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3934 (CMNri GPR:$src, so_imm_neg:$imm)>;
3936 // Note that TST/TEQ don't set all the same flags that CMP does!
3937 defm TST : AI1_cmp_irs<0b1000, "tst",
3938 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3939 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3940 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3941 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3942 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3944 // Pseudo i64 compares for some floating point compares.
3945 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3947 def BCCi64 : PseudoInst<(outs),
3948 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3950 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3952 def BCCZi64 : PseudoInst<(outs),
3953 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3954 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3955 } // usesCustomInserter
3958 // Conditional moves
3959 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3960 // a two-value operand where a dag node expects two operands. :(
3961 let neverHasSideEffects = 1 in {
3963 let isCommutable = 1 in
3964 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3966 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3967 RegConstraint<"$false = $Rd">;
3969 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
3970 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
3972 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
3973 imm:$cc, CCR:$ccr))*/]>,
3974 RegConstraint<"$false = $Rd">;
3975 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
3976 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
3978 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
3979 imm:$cc, CCR:$ccr))*/]>,
3980 RegConstraint<"$false = $Rd">;
3983 let isMoveImm = 1 in
3984 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3985 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
3988 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3990 let isMoveImm = 1 in
3991 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3992 (ins GPR:$false, so_imm:$imm, pred:$p),
3994 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3995 RegConstraint<"$false = $Rd">;
3997 // Two instruction predicate mov immediate.
3998 let isMoveImm = 1 in
3999 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4000 (ins GPR:$false, i32imm:$src, pred:$p),
4001 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4003 let isMoveImm = 1 in
4004 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4005 (ins GPR:$false, so_imm:$imm, pred:$p),
4007 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4008 RegConstraint<"$false = $Rd">;
4010 // Conditional instructions
4011 multiclass AsI1_bincc_irs<Instruction iri, Instruction irr, Instruction irsi,
4013 InstrItinClass iii, InstrItinClass iir,
4014 InstrItinClass iis> {
4015 def ri : ARMPseudoExpand<(outs GPR:$Rd),
4016 (ins GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s),
4018 (iri GPR:$Rd, GPR:$Rn, so_imm:$imm, pred:$p, cc_out:$s)>,
4019 RegConstraint<"$Rn = $Rd">;
4020 def rr : ARMPseudoExpand<(outs GPR:$Rd),
4021 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4023 (irr GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4024 RegConstraint<"$Rn = $Rd">;
4025 def rsi : ARMPseudoExpand<(outs GPR:$Rd),
4026 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s),
4028 (irsi GPR:$Rd, GPR:$Rn, so_reg_imm:$shift, pred:$p, cc_out:$s)>,
4029 RegConstraint<"$Rn = $Rd">;
4030 def rsr : ARMPseudoExpand<(outs GPRnopc:$Rd),
4031 (ins GPRnopc:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s),
4033 (irsr GPR:$Rd, GPR:$Rn, so_reg_reg:$shift, pred:$p, cc_out:$s)>,
4034 RegConstraint<"$Rn = $Rd">;
4037 defm ANDCC : AsI1_bincc_irs<ANDri, ANDrr, ANDrsi, ANDrsr,
4038 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4039 defm ORRCC : AsI1_bincc_irs<ORRri, ORRrr, ORRrsi, ORRrsr,
4040 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4041 defm EORCC : AsI1_bincc_irs<EORri, EORrr, EORrsi, EORrsr,
4042 IIC_iBITi, IIC_iBITr, IIC_iBITsr>;
4044 } // neverHasSideEffects
4047 //===----------------------------------------------------------------------===//
4048 // Atomic operations intrinsics
4051 def MemBarrierOptOperand : AsmOperandClass {
4052 let Name = "MemBarrierOpt";
4053 let ParserMethod = "parseMemBarrierOptOperand";
4055 def memb_opt : Operand<i32> {
4056 let PrintMethod = "printMemBOption";
4057 let ParserMatchClass = MemBarrierOptOperand;
4058 let DecoderMethod = "DecodeMemBarrierOption";
4061 // memory barriers protect the atomic sequences
4062 let hasSideEffects = 1 in {
4063 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4064 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4065 Requires<[IsARM, HasDB]> {
4067 let Inst{31-4} = 0xf57ff05;
4068 let Inst{3-0} = opt;
4072 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4073 "dsb", "\t$opt", []>,
4074 Requires<[IsARM, HasDB]> {
4076 let Inst{31-4} = 0xf57ff04;
4077 let Inst{3-0} = opt;
4080 // ISB has only full system option
4081 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4082 "isb", "\t$opt", []>,
4083 Requires<[IsARM, HasDB]> {
4085 let Inst{31-4} = 0xf57ff06;
4086 let Inst{3-0} = opt;
4089 // Pseudo instruction that combines movs + predicated rsbmi
4090 // to implement integer ABS
4091 let usesCustomInserter = 1, Defs = [CPSR] in
4092 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4094 let usesCustomInserter = 1 in {
4095 let Defs = [CPSR] in {
4096 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4097 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4098 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4099 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4100 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4101 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4102 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4103 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4104 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4105 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4106 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4107 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4108 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4109 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4110 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4111 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4112 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4113 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4114 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4115 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4116 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4117 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4118 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4119 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4120 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4121 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4122 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4123 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4124 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4125 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4126 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4127 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4128 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4129 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4130 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4131 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4132 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4133 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4134 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4135 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4136 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4137 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4138 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4139 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4140 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4141 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4142 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4143 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4144 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4145 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4146 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4147 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4148 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4149 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4150 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4151 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4152 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4153 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4154 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4155 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4156 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4157 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4158 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4159 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4160 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4161 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4162 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4163 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4164 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4165 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4166 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4167 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4168 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4169 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4170 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4171 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4172 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4173 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4174 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4175 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4176 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4177 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4178 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4179 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4180 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4181 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4182 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4183 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4184 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4185 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4187 def ATOMIC_SWAP_I8 : PseudoInst<
4188 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4189 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4190 def ATOMIC_SWAP_I16 : PseudoInst<
4191 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4192 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4193 def ATOMIC_SWAP_I32 : PseudoInst<
4194 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4195 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4197 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4198 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4199 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4200 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4201 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4202 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4203 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4204 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4205 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4209 let usesCustomInserter = 1 in {
4210 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4211 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4213 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4216 let mayLoad = 1 in {
4217 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4219 "ldrexb", "\t$Rt, $addr", []>;
4220 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4221 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4222 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4223 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4224 let hasExtraDefRegAllocReq = 1 in
4225 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4226 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4227 let DecoderMethod = "DecodeDoubleRegLoad";
4231 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4232 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4233 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4234 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4235 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4236 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4237 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4238 let hasExtraSrcRegAllocReq = 1 in
4239 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4240 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4241 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4242 let DecoderMethod = "DecodeDoubleRegStore";
4247 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4248 Requires<[IsARM, HasV7]> {
4249 let Inst{31-0} = 0b11110101011111111111000000011111;
4252 // SWP/SWPB are deprecated in V6/V7.
4253 let mayLoad = 1, mayStore = 1 in {
4254 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4255 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4256 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4257 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4260 //===----------------------------------------------------------------------===//
4261 // Coprocessor Instructions.
4264 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4265 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4266 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4267 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4268 imm:$CRm, imm:$opc2)]> {
4276 let Inst{3-0} = CRm;
4278 let Inst{7-5} = opc2;
4279 let Inst{11-8} = cop;
4280 let Inst{15-12} = CRd;
4281 let Inst{19-16} = CRn;
4282 let Inst{23-20} = opc1;
4285 def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
4286 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4287 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4288 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4289 imm:$CRm, imm:$opc2)]> {
4290 let Inst{31-28} = 0b1111;
4298 let Inst{3-0} = CRm;
4300 let Inst{7-5} = opc2;
4301 let Inst{11-8} = cop;
4302 let Inst{15-12} = CRd;
4303 let Inst{19-16} = CRn;
4304 let Inst{23-20} = opc1;
4307 class ACI<dag oops, dag iops, string opc, string asm,
4308 IndexMode im = IndexModeNone>
4309 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4311 let Inst{27-25} = 0b110;
4313 class ACInoP<dag oops, dag iops, string opc, string asm,
4314 IndexMode im = IndexModeNone>
4315 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4317 let Inst{31-28} = 0b1111;
4318 let Inst{27-25} = 0b110;
4320 multiclass LdStCop<bit load, bit Dbit, string asm> {
4321 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4322 asm, "\t$cop, $CRd, $addr"> {
4326 let Inst{24} = 1; // P = 1
4327 let Inst{23} = addr{8};
4328 let Inst{22} = Dbit;
4329 let Inst{21} = 0; // W = 0
4330 let Inst{20} = load;
4331 let Inst{19-16} = addr{12-9};
4332 let Inst{15-12} = CRd;
4333 let Inst{11-8} = cop;
4334 let Inst{7-0} = addr{7-0};
4335 let DecoderMethod = "DecodeCopMemInstruction";
4337 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4338 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4342 let Inst{24} = 1; // P = 1
4343 let Inst{23} = addr{8};
4344 let Inst{22} = Dbit;
4345 let Inst{21} = 1; // W = 1
4346 let Inst{20} = load;
4347 let Inst{19-16} = addr{12-9};
4348 let Inst{15-12} = CRd;
4349 let Inst{11-8} = cop;
4350 let Inst{7-0} = addr{7-0};
4351 let DecoderMethod = "DecodeCopMemInstruction";
4353 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4354 postidx_imm8s4:$offset),
4355 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4360 let Inst{24} = 0; // P = 0
4361 let Inst{23} = offset{8};
4362 let Inst{22} = Dbit;
4363 let Inst{21} = 1; // W = 1
4364 let Inst{20} = load;
4365 let Inst{19-16} = addr;
4366 let Inst{15-12} = CRd;
4367 let Inst{11-8} = cop;
4368 let Inst{7-0} = offset{7-0};
4369 let DecoderMethod = "DecodeCopMemInstruction";
4371 def _OPTION : ACI<(outs),
4372 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4373 coproc_option_imm:$option),
4374 asm, "\t$cop, $CRd, $addr, $option"> {
4379 let Inst{24} = 0; // P = 0
4380 let Inst{23} = 1; // U = 1
4381 let Inst{22} = Dbit;
4382 let Inst{21} = 0; // W = 0
4383 let Inst{20} = load;
4384 let Inst{19-16} = addr;
4385 let Inst{15-12} = CRd;
4386 let Inst{11-8} = cop;
4387 let Inst{7-0} = option;
4388 let DecoderMethod = "DecodeCopMemInstruction";
4391 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4392 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4393 asm, "\t$cop, $CRd, $addr"> {
4397 let Inst{24} = 1; // P = 1
4398 let Inst{23} = addr{8};
4399 let Inst{22} = Dbit;
4400 let Inst{21} = 0; // W = 0
4401 let Inst{20} = load;
4402 let Inst{19-16} = addr{12-9};
4403 let Inst{15-12} = CRd;
4404 let Inst{11-8} = cop;
4405 let Inst{7-0} = addr{7-0};
4406 let DecoderMethod = "DecodeCopMemInstruction";
4408 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4409 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4413 let Inst{24} = 1; // P = 1
4414 let Inst{23} = addr{8};
4415 let Inst{22} = Dbit;
4416 let Inst{21} = 1; // W = 1
4417 let Inst{20} = load;
4418 let Inst{19-16} = addr{12-9};
4419 let Inst{15-12} = CRd;
4420 let Inst{11-8} = cop;
4421 let Inst{7-0} = addr{7-0};
4422 let DecoderMethod = "DecodeCopMemInstruction";
4424 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4425 postidx_imm8s4:$offset),
4426 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4431 let Inst{24} = 0; // P = 0
4432 let Inst{23} = offset{8};
4433 let Inst{22} = Dbit;
4434 let Inst{21} = 1; // W = 1
4435 let Inst{20} = load;
4436 let Inst{19-16} = addr;
4437 let Inst{15-12} = CRd;
4438 let Inst{11-8} = cop;
4439 let Inst{7-0} = offset{7-0};
4440 let DecoderMethod = "DecodeCopMemInstruction";
4442 def _OPTION : ACInoP<(outs),
4443 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4444 coproc_option_imm:$option),
4445 asm, "\t$cop, $CRd, $addr, $option"> {
4450 let Inst{24} = 0; // P = 0
4451 let Inst{23} = 1; // U = 1
4452 let Inst{22} = Dbit;
4453 let Inst{21} = 0; // W = 0
4454 let Inst{20} = load;
4455 let Inst{19-16} = addr;
4456 let Inst{15-12} = CRd;
4457 let Inst{11-8} = cop;
4458 let Inst{7-0} = option;
4459 let DecoderMethod = "DecodeCopMemInstruction";
4463 defm LDC : LdStCop <1, 0, "ldc">;
4464 defm LDCL : LdStCop <1, 1, "ldcl">;
4465 defm STC : LdStCop <0, 0, "stc">;
4466 defm STCL : LdStCop <0, 1, "stcl">;
4467 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4468 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4469 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4470 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4472 //===----------------------------------------------------------------------===//
4473 // Move between coprocessor and ARM core register.
4476 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4478 : ABI<0b1110, oops, iops, NoItinerary, opc,
4479 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4480 let Inst{20} = direction;
4490 let Inst{15-12} = Rt;
4491 let Inst{11-8} = cop;
4492 let Inst{23-21} = opc1;
4493 let Inst{7-5} = opc2;
4494 let Inst{3-0} = CRm;
4495 let Inst{19-16} = CRn;
4498 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4500 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4501 c_imm:$CRm, imm0_7:$opc2),
4502 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4503 imm:$CRm, imm:$opc2)]>;
4504 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4505 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4506 c_imm:$CRm, 0, pred:$p)>;
4507 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4509 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4511 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4512 (MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4513 c_imm:$CRm, 0, pred:$p)>;
4515 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4516 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4518 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4520 : ABXI<0b1110, oops, iops, NoItinerary,
4521 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4522 let Inst{31-28} = 0b1111;
4523 let Inst{20} = direction;
4533 let Inst{15-12} = Rt;
4534 let Inst{11-8} = cop;
4535 let Inst{23-21} = opc1;
4536 let Inst{7-5} = opc2;
4537 let Inst{3-0} = CRm;
4538 let Inst{19-16} = CRn;
4541 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4543 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4544 c_imm:$CRm, imm0_7:$opc2),
4545 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4546 imm:$CRm, imm:$opc2)]>;
4547 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4548 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4550 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4552 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4554 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4555 (MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4558 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4559 imm:$CRm, imm:$opc2),
4560 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4562 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4563 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4564 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4565 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4566 let Inst{23-21} = 0b010;
4567 let Inst{20} = direction;
4575 let Inst{15-12} = Rt;
4576 let Inst{19-16} = Rt2;
4577 let Inst{11-8} = cop;
4578 let Inst{7-4} = opc1;
4579 let Inst{3-0} = CRm;
4582 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4583 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4584 GPRnopc:$Rt2, imm:$CRm)]>;
4585 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4587 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4588 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4589 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4590 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4591 let Inst{31-28} = 0b1111;
4592 let Inst{23-21} = 0b010;
4593 let Inst{20} = direction;
4601 let Inst{15-12} = Rt;
4602 let Inst{19-16} = Rt2;
4603 let Inst{11-8} = cop;
4604 let Inst{7-4} = opc1;
4605 let Inst{3-0} = CRm;
4607 let DecoderMethod = "DecodeMRRC2";
4610 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4611 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4612 GPRnopc:$Rt2, imm:$CRm)]>;
4613 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4615 //===----------------------------------------------------------------------===//
4616 // Move between special register and ARM core register
4619 // Move to ARM core register from Special Register
4620 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4621 "mrs", "\t$Rd, apsr", []> {
4623 let Inst{23-16} = 0b00001111;
4624 let Unpredictable{19-17} = 0b111;
4626 let Inst{15-12} = Rd;
4628 let Inst{11-0} = 0b000000000000;
4629 let Unpredictable{11-0} = 0b110100001111;
4632 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4635 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4636 // section B9.3.9, with the R bit set to 1.
4637 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4638 "mrs", "\t$Rd, spsr", []> {
4640 let Inst{23-16} = 0b01001111;
4641 let Unpredictable{19-16} = 0b1111;
4643 let Inst{15-12} = Rd;
4645 let Inst{11-0} = 0b000000000000;
4646 let Unpredictable{11-0} = 0b110100001111;
4649 // Move from ARM core register to Special Register
4651 // No need to have both system and application versions, the encodings are the
4652 // same and the assembly parser has no way to distinguish between them. The mask
4653 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4654 // the mask with the fields to be accessed in the special register.
4655 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4656 "msr", "\t$mask, $Rn", []> {
4661 let Inst{22} = mask{4}; // R bit
4662 let Inst{21-20} = 0b10;
4663 let Inst{19-16} = mask{3-0};
4664 let Inst{15-12} = 0b1111;
4665 let Inst{11-4} = 0b00000000;
4669 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4670 "msr", "\t$mask, $a", []> {
4675 let Inst{22} = mask{4}; // R bit
4676 let Inst{21-20} = 0b10;
4677 let Inst{19-16} = mask{3-0};
4678 let Inst{15-12} = 0b1111;
4682 //===----------------------------------------------------------------------===//
4686 // __aeabi_read_tp preserves the registers r1-r3.
4687 // This is a pseudo inst so that we can get the encoding right,
4688 // complete with fixup for the aeabi_read_tp function.
4690 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4691 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4692 [(set R0, ARMthread_pointer)]>;
4695 //===----------------------------------------------------------------------===//
4696 // SJLJ Exception handling intrinsics
4697 // eh_sjlj_setjmp() is an instruction sequence to store the return
4698 // address and save #0 in R0 for the non-longjmp case.
4699 // Since by its nature we may be coming from some other function to get
4700 // here, and we're using the stack frame for the containing function to
4701 // save/restore registers, we can't keep anything live in regs across
4702 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4703 // when we get here from a longjmp(). We force everything out of registers
4704 // except for our own input by listing the relevant registers in Defs. By
4705 // doing so, we also cause the prologue/epilogue code to actively preserve
4706 // all of the callee-saved resgisters, which is exactly what we want.
4707 // A constant value is passed in $val, and we use the location as a scratch.
4709 // These are pseudo-instructions and are lowered to individual MC-insts, so
4710 // no encoding information is necessary.
4712 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4713 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4714 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4715 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4717 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4718 Requires<[IsARM, HasVFP2]>;
4722 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4723 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4724 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4726 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4727 Requires<[IsARM, NoVFP]>;
4730 // FIXME: Non-IOS version(s)
4731 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4732 Defs = [ R7, LR, SP ] in {
4733 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4735 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4736 Requires<[IsARM, IsIOS]>;
4739 // eh.sjlj.dispatchsetup pseudo-instructions.
4740 // These pseudos are used for both ARM and Thumb2. Any differences are
4741 // handled when the pseudo is expanded (which happens before any passes
4742 // that need the instruction size).
4744 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4745 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4747 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4750 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4752 def Int_eh_sjlj_dispatchsetup_nofp : PseudoInst<(outs), (ins), NoItinerary, []>;
4755 //===----------------------------------------------------------------------===//
4756 // Non-Instruction Patterns
4759 // ARMv4 indirect branch using (MOVr PC, dst)
4760 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4761 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4762 4, IIC_Br, [(brind GPR:$dst)],
4763 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4764 Requires<[IsARM, NoV4T]>;
4766 // Large immediate handling.
4768 // 32-bit immediate using two piece so_imms or movw + movt.
4769 // This is a single pseudo instruction, the benefit is that it can be remat'd
4770 // as a single unit instead of having to handle reg inputs.
4771 // FIXME: Remove this when we can do generalized remat.
4772 let isReMaterializable = 1, isMoveImm = 1 in
4773 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4774 [(set GPR:$dst, (arm_i32imm:$src))]>,
4777 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4778 // It also makes it possible to rematerialize the instructions.
4779 // FIXME: Remove this when we can do generalized remat and when machine licm
4780 // can properly the instructions.
4781 let isReMaterializable = 1 in {
4782 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4784 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4785 Requires<[IsARM, UseMovt]>;
4787 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4789 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4790 Requires<[IsARM, UseMovt]>;
4792 let AddedComplexity = 10 in
4793 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4795 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4796 Requires<[IsARM, UseMovt]>;
4797 } // isReMaterializable
4799 // ConstantPool, GlobalAddress, and JumpTable
4800 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4801 Requires<[IsARM, DontUseMovt]>;
4802 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4803 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4804 Requires<[IsARM, UseMovt]>;
4805 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4806 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4808 // TODO: add,sub,and, 3-instr forms?
4810 // Tail calls. These patterns also apply to Thumb mode.
4811 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4812 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4813 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4816 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4817 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4818 (BMOVPCB_CALL texternalsym:$func)>;
4820 // zextload i1 -> zextload i8
4821 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4822 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4824 // extload -> zextload
4825 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4826 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4827 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4828 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4830 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4832 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4833 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4836 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4837 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4838 (SMULBB GPR:$a, GPR:$b)>;
4839 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4840 (SMULBB GPR:$a, GPR:$b)>;
4841 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4842 (sra GPR:$b, (i32 16))),
4843 (SMULBT GPR:$a, GPR:$b)>;
4844 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4845 (SMULBT GPR:$a, GPR:$b)>;
4846 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4847 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4848 (SMULTB GPR:$a, GPR:$b)>;
4849 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4850 (SMULTB GPR:$a, GPR:$b)>;
4851 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4853 (SMULWB GPR:$a, GPR:$b)>;
4854 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4855 (SMULWB GPR:$a, GPR:$b)>;
4857 def : ARMV5TEPat<(add GPR:$acc,
4858 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4859 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4860 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4861 def : ARMV5TEPat<(add GPR:$acc,
4862 (mul sext_16_node:$a, sext_16_node:$b)),
4863 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4864 def : ARMV5TEPat<(add GPR:$acc,
4865 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4866 (sra GPR:$b, (i32 16)))),
4867 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4868 def : ARMV5TEPat<(add GPR:$acc,
4869 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4870 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4871 def : ARMV5TEPat<(add GPR:$acc,
4872 (mul (sra GPR:$a, (i32 16)),
4873 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4874 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4875 def : ARMV5TEPat<(add GPR:$acc,
4876 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4877 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4878 def : ARMV5TEPat<(add GPR:$acc,
4879 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4881 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4882 def : ARMV5TEPat<(add GPR:$acc,
4883 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4884 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4887 // Pre-v7 uses MCR for synchronization barriers.
4888 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4889 Requires<[IsARM, HasV6]>;
4891 // SXT/UXT with no rotate
4892 let AddedComplexity = 16 in {
4893 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4894 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4895 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4896 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4897 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4898 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4899 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4902 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4903 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4905 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4906 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4907 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4908 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4910 // Atomic load/store patterns
4911 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4912 (LDRBrs ldst_so_reg:$src)>;
4913 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4914 (LDRBi12 addrmode_imm12:$src)>;
4915 def : ARMPat<(atomic_load_16 addrmode3:$src),
4916 (LDRH addrmode3:$src)>;
4917 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4918 (LDRrs ldst_so_reg:$src)>;
4919 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4920 (LDRi12 addrmode_imm12:$src)>;
4921 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4922 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4923 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4924 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4925 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4926 (STRH GPR:$val, addrmode3:$ptr)>;
4927 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4928 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4929 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4930 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4933 //===----------------------------------------------------------------------===//
4937 include "ARMInstrThumb.td"
4939 //===----------------------------------------------------------------------===//
4943 include "ARMInstrThumb2.td"
4945 //===----------------------------------------------------------------------===//
4946 // Floating Point Support
4949 include "ARMInstrVFP.td"
4951 //===----------------------------------------------------------------------===//
4952 // Advanced SIMD (NEON) Support
4955 include "ARMInstrNEON.td"
4957 //===----------------------------------------------------------------------===//
4958 // Assembler aliases
4962 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4963 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4964 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4966 // System instructions
4967 def : MnemonicAlias<"swi", "svc">;
4969 // Load / Store Multiple
4970 def : MnemonicAlias<"ldmfd", "ldm">;
4971 def : MnemonicAlias<"ldmia", "ldm">;
4972 def : MnemonicAlias<"ldmea", "ldmdb">;
4973 def : MnemonicAlias<"stmfd", "stmdb">;
4974 def : MnemonicAlias<"stmia", "stm">;
4975 def : MnemonicAlias<"stmea", "stm">;
4977 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4978 // shift amount is zero (i.e., unspecified).
4979 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4980 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4981 Requires<[IsARM, HasV6]>;
4982 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4983 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
4984 Requires<[IsARM, HasV6]>;
4986 // PUSH/POP aliases for STM/LDM
4987 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4988 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4990 // SSAT/USAT optional shift operand.
4991 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4992 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4993 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4994 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4997 // Extend instruction optional rotate operand.
4998 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4999 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5000 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5001 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5002 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5003 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5004 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5005 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5006 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5007 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5008 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5009 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5011 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5012 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5013 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5014 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5015 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5016 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5017 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5018 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5019 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5020 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5021 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5022 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5026 def : MnemonicAlias<"rfefa", "rfeda">;
5027 def : MnemonicAlias<"rfeea", "rfedb">;
5028 def : MnemonicAlias<"rfefd", "rfeia">;
5029 def : MnemonicAlias<"rfeed", "rfeib">;
5030 def : MnemonicAlias<"rfe", "rfeia">;
5033 def : MnemonicAlias<"srsfa", "srsda">;
5034 def : MnemonicAlias<"srsea", "srsdb">;
5035 def : MnemonicAlias<"srsfd", "srsia">;
5036 def : MnemonicAlias<"srsed", "srsib">;
5037 def : MnemonicAlias<"srs", "srsia">;
5040 def : MnemonicAlias<"qsubaddx", "qsax">;
5042 def : MnemonicAlias<"saddsubx", "sasx">;
5043 // SHASX == SHADDSUBX
5044 def : MnemonicAlias<"shaddsubx", "shasx">;
5045 // SHSAX == SHSUBADDX
5046 def : MnemonicAlias<"shsubaddx", "shsax">;
5048 def : MnemonicAlias<"ssubaddx", "ssax">;
5050 def : MnemonicAlias<"uaddsubx", "uasx">;
5051 // UHASX == UHADDSUBX
5052 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5053 // UHSAX == UHSUBADDX
5054 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5055 // UQASX == UQADDSUBX
5056 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5057 // UQSAX == UQSUBADDX
5058 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5060 def : MnemonicAlias<"usubaddx", "usax">;
5062 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5064 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5065 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5066 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5067 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5068 // Same for AND <--> BIC
5069 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5070 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5071 pred:$p, cc_out:$s)>;
5072 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5073 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5074 pred:$p, cc_out:$s)>;
5075 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5076 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5077 pred:$p, cc_out:$s)>;
5078 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5079 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5080 pred:$p, cc_out:$s)>;
5082 // Likewise, "add Rd, so_imm_neg" -> sub
5083 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5084 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5085 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5086 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5087 // Same for CMP <--> CMN via so_imm_neg
5088 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5089 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5090 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5091 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5093 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5094 // LSR, ROR, and RRX instructions.
5095 // FIXME: We need C++ parser hooks to map the alias to the MOV
5096 // encoding. It seems we should be able to do that sort of thing
5097 // in tblgen, but it could get ugly.
5098 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5099 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5100 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5102 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5103 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5105 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5106 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5108 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5109 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5112 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5113 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5114 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5115 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5116 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5118 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5119 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5121 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5122 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5124 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5125 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5129 // "neg" is and alias for "rsb rd, rn, #0"
5130 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5131 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5133 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5134 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5135 Requires<[IsARM, NoV6]>;
5137 // UMULL/SMULL are available on all arches, but the instruction definitions
5138 // need difference constraints pre-v6. Use these aliases for the assembly
5139 // parsing on pre-v6.
5140 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5141 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5142 Requires<[IsARM, NoV6]>;
5143 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5144 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5145 Requires<[IsARM, NoV6]>;
5147 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5149 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;