1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
75 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
76 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
77 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
79 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
80 [SDNPHasChain, SDNPOutGlue]>;
81 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
84 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
90 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
91 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
94 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
95 [SDNPHasChain, SDNPOptInGlue]>;
97 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
100 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
101 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
103 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
105 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
108 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
111 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
114 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
115 [SDNPOutGlue, SDNPCommutative]>;
117 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
119 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
120 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
121 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
123 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
124 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
125 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
126 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
127 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
128 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
129 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
132 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
134 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
136 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
137 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
139 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
141 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
142 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
145 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
147 //===----------------------------------------------------------------------===//
148 // ARM Instruction Predicate Definitions.
150 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
151 AssemblerPredicate<"HasV4TOps">;
152 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
153 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
154 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
155 AssemblerPredicate<"HasV5TEOps">;
156 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
157 AssemblerPredicate<"HasV6Ops">;
158 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
159 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
160 AssemblerPredicate<"HasV6T2Ops">;
161 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
162 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
163 AssemblerPredicate<"HasV7Ops">;
164 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
165 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
166 AssemblerPredicate<"FeatureVFP2">;
167 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
168 AssemblerPredicate<"FeatureVFP3">;
169 def HasNEON : Predicate<"Subtarget->hasNEON()">,
170 AssemblerPredicate<"FeatureNEON">;
171 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
172 AssemblerPredicate<"FeatureFP16">;
173 def HasDivide : Predicate<"Subtarget->hasDivide()">,
174 AssemblerPredicate<"FeatureHWDiv">;
175 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
176 AssemblerPredicate<"FeatureT2XtPk">;
177 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
178 AssemblerPredicate<"FeatureDSPThumb2">;
179 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
180 AssemblerPredicate<"FeatureDB">;
181 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
182 AssemblerPredicate<"FeatureMP">;
183 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
184 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
185 def IsThumb : Predicate<"Subtarget->isThumb()">,
186 AssemblerPredicate<"ModeThumb">;
187 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
188 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
189 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
190 def IsARM : Predicate<"!Subtarget->isThumb()">,
191 AssemblerPredicate<"!ModeThumb">;
192 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
193 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
195 // FIXME: Eventually this will be just "hasV6T2Ops".
196 def UseMovt : Predicate<"Subtarget->useMovt()">;
197 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
198 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
200 //===----------------------------------------------------------------------===//
201 // ARM Flag Definitions.
203 class RegConstraint<string C> {
204 string Constraints = C;
207 //===----------------------------------------------------------------------===//
208 // ARM specific transformation functions and pattern fragments.
211 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
212 // so_imm_neg def below.
213 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
214 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
217 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
218 // so_imm_not def below.
219 def so_imm_not_XFORM : SDNodeXForm<imm, [{
220 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
223 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
224 def imm1_15 : ImmLeaf<i32, [{
225 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
228 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
229 def imm16_31 : ImmLeaf<i32, [{
230 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
235 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
236 }], so_imm_neg_XFORM>;
240 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
241 }], so_imm_not_XFORM>;
243 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
244 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
245 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
248 /// Split a 32-bit immediate into two 16 bit parts.
249 def hi16 : SDNodeXForm<imm, [{
250 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
253 def lo16AllZero : PatLeaf<(i32 imm), [{
254 // Returns true if all low 16-bits are 0.
255 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
258 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
260 def imm0_65535 : ImmLeaf<i32, [{
261 return Imm >= 0 && Imm < 65536;
264 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
265 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
267 /// adde and sube predicates - True based on whether the carry flag output
268 /// will be needed or not.
269 def adde_dead_carry :
270 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
271 [{return !N->hasAnyUseOfValue(1);}]>;
272 def sube_dead_carry :
273 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
274 [{return !N->hasAnyUseOfValue(1);}]>;
275 def adde_live_carry :
276 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
277 [{return N->hasAnyUseOfValue(1);}]>;
278 def sube_live_carry :
279 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
280 [{return N->hasAnyUseOfValue(1);}]>;
282 // An 'and' node with a single use.
283 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
284 return N->hasOneUse();
287 // An 'xor' node with a single use.
288 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
289 return N->hasOneUse();
292 // An 'fmul' node with a single use.
293 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
294 return N->hasOneUse();
297 // An 'fadd' node which checks for single non-hazardous use.
298 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
299 return hasNoVMLxHazardUse(N);
302 // An 'fsub' node which checks for single non-hazardous use.
303 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
304 return hasNoVMLxHazardUse(N);
307 //===----------------------------------------------------------------------===//
308 // Operand Definitions.
312 // FIXME: rename brtarget to t2_brtarget
313 def brtarget : Operand<OtherVT> {
314 let EncoderMethod = "getBranchTargetOpValue";
317 // FIXME: get rid of this one?
318 def uncondbrtarget : Operand<OtherVT> {
319 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
322 // Branch target for ARM. Handles conditional/unconditional
323 def br_target : Operand<OtherVT> {
324 let EncoderMethod = "getARMBranchTargetOpValue";
328 // FIXME: rename bltarget to t2_bl_target?
329 def bltarget : Operand<i32> {
330 // Encoded the same as branch targets.
331 let EncoderMethod = "getBranchTargetOpValue";
334 // Call target for ARM. Handles conditional/unconditional
335 // FIXME: rename bl_target to t2_bltarget?
336 def bl_target : Operand<i32> {
337 // Encoded the same as branch targets.
338 let EncoderMethod = "getARMBranchTargetOpValue";
342 // A list of registers separated by comma. Used by load/store multiple.
343 def RegListAsmOperand : AsmOperandClass {
344 let Name = "RegList";
345 let SuperClasses = [];
348 def DPRRegListAsmOperand : AsmOperandClass {
349 let Name = "DPRRegList";
350 let SuperClasses = [];
353 def SPRRegListAsmOperand : AsmOperandClass {
354 let Name = "SPRRegList";
355 let SuperClasses = [];
358 def reglist : Operand<i32> {
359 let EncoderMethod = "getRegisterListOpValue";
360 let ParserMatchClass = RegListAsmOperand;
361 let PrintMethod = "printRegisterList";
364 def dpr_reglist : Operand<i32> {
365 let EncoderMethod = "getRegisterListOpValue";
366 let ParserMatchClass = DPRRegListAsmOperand;
367 let PrintMethod = "printRegisterList";
370 def spr_reglist : Operand<i32> {
371 let EncoderMethod = "getRegisterListOpValue";
372 let ParserMatchClass = SPRRegListAsmOperand;
373 let PrintMethod = "printRegisterList";
376 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
377 def cpinst_operand : Operand<i32> {
378 let PrintMethod = "printCPInstOperand";
382 def pclabel : Operand<i32> {
383 let PrintMethod = "printPCLabel";
386 // ADR instruction labels.
387 def adrlabel : Operand<i32> {
388 let EncoderMethod = "getAdrLabelOpValue";
391 def neon_vcvt_imm32 : Operand<i32> {
392 let EncoderMethod = "getNEONVcvtImm32OpValue";
395 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
396 def rot_imm : Operand<i32>, ImmLeaf<i32, [{
397 int32_t v = (int32_t)Imm;
398 return v == 8 || v == 16 || v == 24; }]> {
399 let EncoderMethod = "getRotImmOpValue";
402 def ShifterAsmOperand : AsmOperandClass {
403 let Name = "Shifter";
404 let SuperClasses = [];
407 // shift_imm: An integer that encodes a shift amount and the type of shift
408 // (currently either asr or lsl) using the same encoding used for the
409 // immediates in so_reg operands.
410 def shift_imm : Operand<i32> {
411 let PrintMethod = "printShiftImmOperand";
412 let ParserMatchClass = ShifterAsmOperand;
415 // shifter_operand operands: so_reg and so_imm.
416 def so_reg : Operand<i32>, // reg reg imm
417 ComplexPattern<i32, 3, "SelectShifterOperandReg",
418 [shl,srl,sra,rotr]> {
419 let EncoderMethod = "getSORegOpValue";
420 let PrintMethod = "printSORegOperand";
421 let MIOperandInfo = (ops GPR, GPR, shift_imm);
423 def shift_so_reg : Operand<i32>, // reg reg imm
424 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
425 [shl,srl,sra,rotr]> {
426 let EncoderMethod = "getSORegOpValue";
427 let PrintMethod = "printSORegOperand";
428 let MIOperandInfo = (ops GPR, GPR, shift_imm);
431 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
432 // 8-bit immediate rotated by an arbitrary number of bits.
433 def so_imm : Operand<i32>, ImmLeaf<i32, [{
434 return ARM_AM::getSOImmVal(Imm) != -1;
436 let EncoderMethod = "getSOImmOpValue";
437 let PrintMethod = "printSOImmOperand";
440 // Break so_imm's up into two pieces. This handles immediates with up to 16
441 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
442 // get the first/second pieces.
443 def so_imm2part : PatLeaf<(imm), [{
444 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
447 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
449 def arm_i32imm : PatLeaf<(imm), [{
450 if (Subtarget->hasV6T2Ops())
452 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
455 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
456 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
457 return Imm >= 0 && Imm < 32;
460 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
461 def imm0_31_m1 : Operand<i32>, ImmLeaf<i32, [{
462 return Imm >= 0 && Imm < 32;
464 let EncoderMethod = "getImmMinusOneOpValue";
467 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
468 // The imm is split into imm{15-12}, imm{11-0}
470 def i32imm_hilo16 : Operand<i32> {
471 let EncoderMethod = "getHiLo16ImmOpValue";
474 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
476 def bf_inv_mask_imm : Operand<i32>,
478 return ARM::isBitFieldInvertedMask(N->getZExtValue());
480 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
481 let PrintMethod = "printBitfieldInvMaskImmOperand";
484 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
485 def lsb_pos_imm : Operand<i32>, ImmLeaf<i32, [{
486 return isInt<5>(Imm);
489 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
490 def width_imm : Operand<i32>, ImmLeaf<i32, [{
491 return Imm > 0 && Imm <= 32;
493 let EncoderMethod = "getMsbOpValue";
496 def ssat_imm : Operand<i32>, ImmLeaf<i32, [{
497 return Imm > 0 && Imm <= 32;
499 let EncoderMethod = "getSsatBitPosValue";
502 // Define ARM specific addressing modes.
504 def MemMode2AsmOperand : AsmOperandClass {
505 let Name = "MemMode2";
506 let SuperClasses = [];
507 let ParserMethod = "tryParseMemMode2Operand";
510 def MemMode3AsmOperand : AsmOperandClass {
511 let Name = "MemMode3";
512 let SuperClasses = [];
513 let ParserMethod = "tryParseMemMode3Operand";
516 // addrmode_imm12 := reg +/- imm12
518 def addrmode_imm12 : Operand<i32>,
519 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
520 // 12-bit immediate operand. Note that instructions using this encode
521 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
522 // immediate values are as normal.
524 let EncoderMethod = "getAddrModeImm12OpValue";
525 let PrintMethod = "printAddrModeImm12Operand";
526 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
528 // ldst_so_reg := reg +/- reg shop imm
530 def ldst_so_reg : Operand<i32>,
531 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
532 let EncoderMethod = "getLdStSORegOpValue";
533 // FIXME: Simplify the printer
534 let PrintMethod = "printAddrMode2Operand";
535 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
538 // addrmode2 := reg +/- imm12
539 // := reg +/- reg shop imm
541 def addrmode2 : Operand<i32>,
542 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
543 let EncoderMethod = "getAddrMode2OpValue";
544 let PrintMethod = "printAddrMode2Operand";
545 let ParserMatchClass = MemMode2AsmOperand;
546 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
549 def am2offset : Operand<i32>,
550 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
551 [], [SDNPWantRoot]> {
552 let EncoderMethod = "getAddrMode2OffsetOpValue";
553 let PrintMethod = "printAddrMode2OffsetOperand";
554 let MIOperandInfo = (ops GPR, i32imm);
557 // addrmode3 := reg +/- reg
558 // addrmode3 := reg +/- imm8
560 def addrmode3 : Operand<i32>,
561 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
562 let EncoderMethod = "getAddrMode3OpValue";
563 let PrintMethod = "printAddrMode3Operand";
564 let ParserMatchClass = MemMode3AsmOperand;
565 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
568 def am3offset : Operand<i32>,
569 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
570 [], [SDNPWantRoot]> {
571 let EncoderMethod = "getAddrMode3OffsetOpValue";
572 let PrintMethod = "printAddrMode3OffsetOperand";
573 let MIOperandInfo = (ops GPR, i32imm);
576 // ldstm_mode := {ia, ib, da, db}
578 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
579 let EncoderMethod = "getLdStmModeOpValue";
580 let PrintMethod = "printLdStmModeOperand";
583 def MemMode5AsmOperand : AsmOperandClass {
584 let Name = "MemMode5";
585 let SuperClasses = [];
588 // addrmode5 := reg +/- imm8*4
590 def addrmode5 : Operand<i32>,
591 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
592 let PrintMethod = "printAddrMode5Operand";
593 let MIOperandInfo = (ops GPR:$base, i32imm);
594 let ParserMatchClass = MemMode5AsmOperand;
595 let EncoderMethod = "getAddrMode5OpValue";
598 // addrmode6 := reg with optional alignment
600 def addrmode6 : Operand<i32>,
601 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
602 let PrintMethod = "printAddrMode6Operand";
603 let MIOperandInfo = (ops GPR:$addr, i32imm);
604 let EncoderMethod = "getAddrMode6AddressOpValue";
607 def am6offset : Operand<i32>,
608 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
609 [], [SDNPWantRoot]> {
610 let PrintMethod = "printAddrMode6OffsetOperand";
611 let MIOperandInfo = (ops GPR);
612 let EncoderMethod = "getAddrMode6OffsetOpValue";
615 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
616 // (single element from one lane) for size 32.
617 def addrmode6oneL32 : Operand<i32>,
618 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
619 let PrintMethod = "printAddrMode6Operand";
620 let MIOperandInfo = (ops GPR:$addr, i32imm);
621 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
624 // Special version of addrmode6 to handle alignment encoding for VLD-dup
625 // instructions, specifically VLD4-dup.
626 def addrmode6dup : Operand<i32>,
627 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
628 let PrintMethod = "printAddrMode6Operand";
629 let MIOperandInfo = (ops GPR:$addr, i32imm);
630 let EncoderMethod = "getAddrMode6DupAddressOpValue";
633 // addrmodepc := pc + reg
635 def addrmodepc : Operand<i32>,
636 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
637 let PrintMethod = "printAddrModePCOperand";
638 let MIOperandInfo = (ops GPR, i32imm);
641 def MemMode7AsmOperand : AsmOperandClass {
642 let Name = "MemMode7";
643 let SuperClasses = [];
647 // Used by load/store exclusive instructions. Useful to enable right assembly
648 // parsing and printing. Not used for any codegen matching.
650 def addrmode7 : Operand<i32> {
651 let PrintMethod = "printAddrMode7Operand";
652 let MIOperandInfo = (ops GPR);
653 let ParserMatchClass = MemMode7AsmOperand;
656 def nohash_imm : Operand<i32> {
657 let PrintMethod = "printNoHashImmediate";
660 def CoprocNumAsmOperand : AsmOperandClass {
661 let Name = "CoprocNum";
662 let SuperClasses = [];
663 let ParserMethod = "tryParseCoprocNumOperand";
666 def CoprocRegAsmOperand : AsmOperandClass {
667 let Name = "CoprocReg";
668 let SuperClasses = [];
669 let ParserMethod = "tryParseCoprocRegOperand";
672 def p_imm : Operand<i32> {
673 let PrintMethod = "printPImmediate";
674 let ParserMatchClass = CoprocNumAsmOperand;
677 def c_imm : Operand<i32> {
678 let PrintMethod = "printCImmediate";
679 let ParserMatchClass = CoprocRegAsmOperand;
682 //===----------------------------------------------------------------------===//
684 include "ARMInstrFormats.td"
686 //===----------------------------------------------------------------------===//
687 // Multiclass helpers...
690 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
691 /// binop that produces a value.
692 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
693 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
694 PatFrag opnode, string baseOpc, bit Commutable = 0> {
695 // The register-immediate version is re-materializable. This is useful
696 // in particular for taking the address of a local.
697 let isReMaterializable = 1 in {
698 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
699 iii, opc, "\t$Rd, $Rn, $imm",
700 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
705 let Inst{19-16} = Rn;
706 let Inst{15-12} = Rd;
707 let Inst{11-0} = imm;
710 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
711 iir, opc, "\t$Rd, $Rn, $Rm",
712 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
717 let isCommutable = Commutable;
718 let Inst{19-16} = Rn;
719 let Inst{15-12} = Rd;
720 let Inst{11-4} = 0b00000000;
723 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
724 iis, opc, "\t$Rd, $Rn, $shift",
725 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
730 let Inst{19-16} = Rn;
731 let Inst{15-12} = Rd;
732 let Inst{11-0} = shift;
735 // Assembly aliases for optional destination operand when it's the same
736 // as the source operand.
737 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
738 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
739 so_imm:$imm, pred:$p,
742 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
743 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
747 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
748 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPR:$Rdn, GPR:$Rdn,
749 so_reg:$shift, pred:$p,
754 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
755 /// instruction modifies the CPSR register.
756 let isCodeGenOnly = 1, Defs = [CPSR] in {
757 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
758 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
759 PatFrag opnode, bit Commutable = 0> {
760 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
761 iii, opc, "\t$Rd, $Rn, $imm",
762 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
768 let Inst{19-16} = Rn;
769 let Inst{15-12} = Rd;
770 let Inst{11-0} = imm;
772 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
773 iir, opc, "\t$Rd, $Rn, $Rm",
774 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
778 let isCommutable = Commutable;
781 let Inst{19-16} = Rn;
782 let Inst{15-12} = Rd;
783 let Inst{11-4} = 0b00000000;
786 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
787 iis, opc, "\t$Rd, $Rn, $shift",
788 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
794 let Inst{19-16} = Rn;
795 let Inst{15-12} = Rd;
796 let Inst{11-0} = shift;
801 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
802 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
803 /// a explicit result, only implicitly set CPSR.
804 let isCompare = 1, Defs = [CPSR] in {
805 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
806 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
807 PatFrag opnode, bit Commutable = 0> {
808 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
810 [(opnode GPR:$Rn, so_imm:$imm)]> {
815 let Inst{19-16} = Rn;
816 let Inst{15-12} = 0b0000;
817 let Inst{11-0} = imm;
819 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
821 [(opnode GPR:$Rn, GPR:$Rm)]> {
824 let isCommutable = Commutable;
827 let Inst{19-16} = Rn;
828 let Inst{15-12} = 0b0000;
829 let Inst{11-4} = 0b00000000;
832 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
833 opc, "\t$Rn, $shift",
834 [(opnode GPR:$Rn, so_reg:$shift)]> {
839 let Inst{19-16} = Rn;
840 let Inst{15-12} = 0b0000;
841 let Inst{11-0} = shift;
846 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
847 /// register and one whose operand is a register rotated by 8/16/24.
848 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
849 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
850 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
851 IIC_iEXTr, opc, "\t$Rd, $Rm",
852 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
853 Requires<[IsARM, HasV6]> {
856 let Inst{19-16} = 0b1111;
857 let Inst{15-12} = Rd;
858 let Inst{11-10} = 0b00;
861 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
862 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
863 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
864 Requires<[IsARM, HasV6]> {
868 let Inst{19-16} = 0b1111;
869 let Inst{15-12} = Rd;
870 let Inst{11-10} = rot;
875 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
876 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
877 IIC_iEXTr, opc, "\t$Rd, $Rm",
878 [/* For disassembly only; pattern left blank */]>,
879 Requires<[IsARM, HasV6]> {
880 let Inst{19-16} = 0b1111;
881 let Inst{11-10} = 0b00;
883 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
884 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
885 [/* For disassembly only; pattern left blank */]>,
886 Requires<[IsARM, HasV6]> {
888 let Inst{19-16} = 0b1111;
889 let Inst{11-10} = rot;
893 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
894 /// register and one whose operand is a register rotated by 8/16/24.
895 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
896 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
897 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
898 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
899 Requires<[IsARM, HasV6]> {
903 let Inst{19-16} = Rn;
904 let Inst{15-12} = Rd;
905 let Inst{11-10} = 0b00;
906 let Inst{9-4} = 0b000111;
909 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
911 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
912 [(set GPR:$Rd, (opnode GPR:$Rn,
913 (rotr GPR:$Rm, rot_imm:$rot)))]>,
914 Requires<[IsARM, HasV6]> {
919 let Inst{19-16} = Rn;
920 let Inst{15-12} = Rd;
921 let Inst{11-10} = rot;
922 let Inst{9-4} = 0b000111;
927 // For disassembly only.
928 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
929 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
930 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
931 [/* For disassembly only; pattern left blank */]>,
932 Requires<[IsARM, HasV6]> {
933 let Inst{11-10} = 0b00;
935 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
937 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
938 [/* For disassembly only; pattern left blank */]>,
939 Requires<[IsARM, HasV6]> {
942 let Inst{19-16} = Rn;
943 let Inst{11-10} = rot;
947 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
948 let Uses = [CPSR] in {
949 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
950 bit Commutable = 0> {
951 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
952 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
953 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
959 let Inst{15-12} = Rd;
960 let Inst{19-16} = Rn;
961 let Inst{11-0} = imm;
963 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
964 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
965 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
970 let Inst{11-4} = 0b00000000;
972 let isCommutable = Commutable;
974 let Inst{15-12} = Rd;
975 let Inst{19-16} = Rn;
977 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
978 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
979 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
985 let Inst{11-0} = shift;
986 let Inst{15-12} = Rd;
987 let Inst{19-16} = Rn;
992 // Carry setting variants
993 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
994 let usesCustomInserter = 1 in {
995 multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
996 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
997 Size4Bytes, IIC_iALUi,
998 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>;
999 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1000 Size4Bytes, IIC_iALUr,
1001 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
1002 let isCommutable = Commutable;
1004 def rs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
1005 Size4Bytes, IIC_iALUsr,
1006 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>;
1010 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1011 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1012 InstrItinClass iir, PatFrag opnode> {
1013 // Note: We use the complex addrmode_imm12 rather than just an input
1014 // GPR and a constrained immediate so that we can use this to match
1015 // frame index references and avoid matching constant pool references.
1016 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1017 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1018 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1021 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1022 let Inst{19-16} = addr{16-13}; // Rn
1023 let Inst{15-12} = Rt;
1024 let Inst{11-0} = addr{11-0}; // imm12
1026 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1027 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1028 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1031 let shift{4} = 0; // Inst{4} = 0
1032 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1033 let Inst{19-16} = shift{16-13}; // Rn
1034 let Inst{15-12} = Rt;
1035 let Inst{11-0} = shift{11-0};
1040 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1041 InstrItinClass iir, PatFrag opnode> {
1042 // Note: We use the complex addrmode_imm12 rather than just an input
1043 // GPR and a constrained immediate so that we can use this to match
1044 // frame index references and avoid matching constant pool references.
1045 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1046 (ins GPR:$Rt, addrmode_imm12:$addr),
1047 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1048 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1051 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1052 let Inst{19-16} = addr{16-13}; // Rn
1053 let Inst{15-12} = Rt;
1054 let Inst{11-0} = addr{11-0}; // imm12
1056 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1057 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1058 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1061 let shift{4} = 0; // Inst{4} = 0
1062 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1063 let Inst{19-16} = shift{16-13}; // Rn
1064 let Inst{15-12} = Rt;
1065 let Inst{11-0} = shift{11-0};
1068 //===----------------------------------------------------------------------===//
1070 //===----------------------------------------------------------------------===//
1072 //===----------------------------------------------------------------------===//
1073 // Miscellaneous Instructions.
1076 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1077 /// the function. The first operand is the ID# for this instruction, the second
1078 /// is the index into the MachineConstantPool that this is, the third is the
1079 /// size in bytes of this constant pool entry.
1080 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1081 def CONSTPOOL_ENTRY :
1082 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1083 i32imm:$size), NoItinerary, []>;
1085 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1086 // from removing one half of the matched pairs. That breaks PEI, which assumes
1087 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1088 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1089 def ADJCALLSTACKUP :
1090 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1091 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1093 def ADJCALLSTACKDOWN :
1094 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1095 [(ARMcallseq_start timm:$amt)]>;
1098 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1099 [/* For disassembly only; pattern left blank */]>,
1100 Requires<[IsARM, HasV6T2]> {
1101 let Inst{27-16} = 0b001100100000;
1102 let Inst{15-8} = 0b11110000;
1103 let Inst{7-0} = 0b00000000;
1106 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1107 [/* For disassembly only; pattern left blank */]>,
1108 Requires<[IsARM, HasV6T2]> {
1109 let Inst{27-16} = 0b001100100000;
1110 let Inst{15-8} = 0b11110000;
1111 let Inst{7-0} = 0b00000001;
1114 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1115 [/* For disassembly only; pattern left blank */]>,
1116 Requires<[IsARM, HasV6T2]> {
1117 let Inst{27-16} = 0b001100100000;
1118 let Inst{15-8} = 0b11110000;
1119 let Inst{7-0} = 0b00000010;
1122 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1123 [/* For disassembly only; pattern left blank */]>,
1124 Requires<[IsARM, HasV6T2]> {
1125 let Inst{27-16} = 0b001100100000;
1126 let Inst{15-8} = 0b11110000;
1127 let Inst{7-0} = 0b00000011;
1130 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1132 [/* For disassembly only; pattern left blank */]>,
1133 Requires<[IsARM, HasV6]> {
1138 let Inst{15-12} = Rd;
1139 let Inst{19-16} = Rn;
1140 let Inst{27-20} = 0b01101000;
1141 let Inst{7-4} = 0b1011;
1142 let Inst{11-8} = 0b1111;
1145 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1146 [/* For disassembly only; pattern left blank */]>,
1147 Requires<[IsARM, HasV6T2]> {
1148 let Inst{27-16} = 0b001100100000;
1149 let Inst{15-8} = 0b11110000;
1150 let Inst{7-0} = 0b00000100;
1153 // The i32imm operand $val can be used by a debugger to store more information
1154 // about the breakpoint.
1155 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1156 [/* For disassembly only; pattern left blank */]>,
1159 let Inst{3-0} = val{3-0};
1160 let Inst{19-8} = val{15-4};
1161 let Inst{27-20} = 0b00010010;
1162 let Inst{7-4} = 0b0111;
1165 // Change Processor State is a system instruction -- for disassembly and
1167 // FIXME: Since the asm parser has currently no clean way to handle optional
1168 // operands, create 3 versions of the same instruction. Once there's a clean
1169 // framework to represent optional operands, change this behavior.
1170 class CPS<dag iops, string asm_ops>
1171 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1172 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1178 let Inst{31-28} = 0b1111;
1179 let Inst{27-20} = 0b00010000;
1180 let Inst{19-18} = imod;
1181 let Inst{17} = M; // Enabled if mode is set;
1183 let Inst{8-6} = iflags;
1185 let Inst{4-0} = mode;
1189 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1190 "$imod\t$iflags, $mode">;
1191 let mode = 0, M = 0 in
1192 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1194 let imod = 0, iflags = 0, M = 1 in
1195 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1197 // Preload signals the memory system of possible future data/instruction access.
1198 // These are for disassembly only.
1199 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1201 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1202 !strconcat(opc, "\t$addr"),
1203 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1206 let Inst{31-26} = 0b111101;
1207 let Inst{25} = 0; // 0 for immediate form
1208 let Inst{24} = data;
1209 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1210 let Inst{22} = read;
1211 let Inst{21-20} = 0b01;
1212 let Inst{19-16} = addr{16-13}; // Rn
1213 let Inst{15-12} = 0b1111;
1214 let Inst{11-0} = addr{11-0}; // imm12
1217 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1218 !strconcat(opc, "\t$shift"),
1219 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1221 let Inst{31-26} = 0b111101;
1222 let Inst{25} = 1; // 1 for register form
1223 let Inst{24} = data;
1224 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1225 let Inst{22} = read;
1226 let Inst{21-20} = 0b01;
1227 let Inst{19-16} = shift{16-13}; // Rn
1228 let Inst{15-12} = 0b1111;
1229 let Inst{11-0} = shift{11-0};
1233 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1234 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1235 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1237 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1239 [/* For disassembly only; pattern left blank */]>,
1242 let Inst{31-10} = 0b1111000100000001000000;
1247 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1248 [/* For disassembly only; pattern left blank */]>,
1249 Requires<[IsARM, HasV7]> {
1251 let Inst{27-4} = 0b001100100000111100001111;
1252 let Inst{3-0} = opt;
1255 // A5.4 Permanently UNDEFINED instructions.
1256 let isBarrier = 1, isTerminator = 1 in
1257 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1260 let Inst = 0xe7ffdefe;
1263 // Address computation and loads and stores in PIC mode.
1264 let isNotDuplicable = 1 in {
1265 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1266 Size4Bytes, IIC_iALUr,
1267 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1269 let AddedComplexity = 10 in {
1270 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1271 Size4Bytes, IIC_iLoad_r,
1272 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1274 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1275 Size4Bytes, IIC_iLoad_bh_r,
1276 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1278 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1279 Size4Bytes, IIC_iLoad_bh_r,
1280 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1282 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1283 Size4Bytes, IIC_iLoad_bh_r,
1284 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1286 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1287 Size4Bytes, IIC_iLoad_bh_r,
1288 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1290 let AddedComplexity = 10 in {
1291 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1292 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1294 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1295 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1296 addrmodepc:$addr)]>;
1298 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1299 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1301 } // isNotDuplicable = 1
1304 // LEApcrel - Load a pc-relative address into a register without offending the
1306 let neverHasSideEffects = 1, isReMaterializable = 1 in
1307 // The 'adr' mnemonic encodes differently if the label is before or after
1308 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1309 // know until then which form of the instruction will be used.
1310 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1311 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1314 let Inst{27-25} = 0b001;
1316 let Inst{19-16} = 0b1111;
1317 let Inst{15-12} = Rd;
1318 let Inst{11-0} = label;
1320 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1321 Size4Bytes, IIC_iALUi, []>;
1323 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1324 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1325 Size4Bytes, IIC_iALUi, []>;
1327 //===----------------------------------------------------------------------===//
1328 // Control Flow Instructions.
1331 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1333 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1334 "bx", "\tlr", [(ARMretflag)]>,
1335 Requires<[IsARM, HasV4T]> {
1336 let Inst{27-0} = 0b0001001011111111111100011110;
1340 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1341 "mov", "\tpc, lr", [(ARMretflag)]>,
1342 Requires<[IsARM, NoV4T]> {
1343 let Inst{27-0} = 0b0001101000001111000000001110;
1347 // Indirect branches
1348 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1350 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1351 [(brind GPR:$dst)]>,
1352 Requires<[IsARM, HasV4T]> {
1354 let Inst{31-4} = 0b1110000100101111111111110001;
1355 let Inst{3-0} = dst;
1358 // For disassembly only.
1359 def BX_pred : AXI<(outs), (ins GPR:$dst, pred:$p), BrMiscFrm, IIC_Br,
1360 "bx$p\t$dst", [/* pattern left blank */]>,
1361 Requires<[IsARM, HasV4T]> {
1363 let Inst{27-4} = 0b000100101111111111110001;
1364 let Inst{3-0} = dst;
1368 // All calls clobber the non-callee saved registers. SP is marked as
1369 // a use to prevent stack-pointer assignments that appear immediately
1370 // before calls from potentially appearing dead.
1372 // On non-Darwin platforms R9 is callee-saved.
1373 // FIXME: Do we really need a non-predicated version? If so, it should
1374 // at least be a pseudo instruction expanding to the predicated version
1375 // at MC lowering time.
1376 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1378 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1379 IIC_Br, "bl\t$func",
1380 [(ARMcall tglobaladdr:$func)]>,
1381 Requires<[IsARM, IsNotDarwin]> {
1382 let Inst{31-28} = 0b1110;
1384 let Inst{23-0} = func;
1387 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1388 IIC_Br, "bl", "\t$func",
1389 [(ARMcall_pred tglobaladdr:$func)]>,
1390 Requires<[IsARM, IsNotDarwin]> {
1392 let Inst{23-0} = func;
1396 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1397 IIC_Br, "blx\t$func",
1398 [(ARMcall GPR:$func)]>,
1399 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1401 let Inst{31-4} = 0b1110000100101111111111110011;
1402 let Inst{3-0} = func;
1405 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1406 IIC_Br, "blx", "\t$func",
1407 [(ARMcall_pred GPR:$func)]>,
1408 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1410 let Inst{27-4} = 0b000100101111111111110011;
1411 let Inst{3-0} = func;
1415 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1416 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1417 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1418 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1421 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1422 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1423 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1427 // On Darwin R9 is call-clobbered.
1428 // R7 is marked as a use to prevent frame-pointer assignments from being
1429 // moved above / below calls.
1430 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1431 Uses = [R7, SP] in {
1432 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1434 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1435 Requires<[IsARM, IsDarwin]>;
1437 def BLr9_pred : ARMPseudoExpand<(outs),
1438 (ins bl_target:$func, pred:$p, variable_ops),
1440 [(ARMcall_pred tglobaladdr:$func)],
1441 (BL_pred bl_target:$func, pred:$p)>,
1442 Requires<[IsARM, IsDarwin]>;
1445 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
1447 [(ARMcall GPR:$func)],
1449 Requires<[IsARM, HasV5T, IsDarwin]>;
1451 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
1453 [(ARMcall_pred GPR:$func)],
1454 (BLX_pred GPR:$func, pred:$p)>,
1455 Requires<[IsARM, HasV5T, IsDarwin]>;
1458 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1459 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1460 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1461 Requires<[IsARM, HasV4T, IsDarwin]>;
1464 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1465 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1466 Requires<[IsARM, NoV4T, IsDarwin]>;
1469 let isBranch = 1, isTerminator = 1 in {
1470 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1471 // a two-value operand where a dag node expects two operands. :(
1472 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1473 IIC_Br, "b", "\t$target",
1474 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1476 let Inst{23-0} = target;
1479 let isBarrier = 1 in {
1480 // B is "predicable" since it's just a Bcc with an 'always' condition.
1481 let isPredicable = 1 in
1482 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1483 // should be sufficient.
1484 // FIXME: Is B really a Barrier? That doesn't seem right.
1485 def B : ARMPseudoExpand<(outs), (ins br_target:$target), Size4Bytes, IIC_Br,
1486 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
1488 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1489 def BR_JTr : ARMPseudoInst<(outs),
1490 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1491 SizeSpecial, IIC_Br,
1492 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1493 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1494 // into i12 and rs suffixed versions.
1495 def BR_JTm : ARMPseudoInst<(outs),
1496 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1497 SizeSpecial, IIC_Br,
1498 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1500 def BR_JTadd : ARMPseudoInst<(outs),
1501 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1502 SizeSpecial, IIC_Br,
1503 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1505 } // isNotDuplicable = 1, isIndirectBranch = 1
1510 // BLX (immediate) -- for disassembly only
1511 def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
1512 "blx\t$target", [/* pattern left blank */]>,
1513 Requires<[IsARM, HasV5T]> {
1514 let Inst{31-25} = 0b1111101;
1516 let Inst{23-0} = target{24-1};
1517 let Inst{24} = target{0};
1520 // Branch and Exchange Jazelle -- for disassembly only
1521 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1522 [/* For disassembly only; pattern left blank */]> {
1523 let Inst{23-20} = 0b0010;
1524 //let Inst{19-8} = 0xfff;
1525 let Inst{7-4} = 0b0010;
1530 // FIXME: The Thumb versions of these should live in ARMInstrThumb.td
1531 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1533 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1535 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1536 IIC_Br, []>, Requires<[IsDarwin]>;
1538 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1539 IIC_Br, []>, Requires<[IsDarwin]>;
1541 def TAILJMPd : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1543 []>, Requires<[IsARM, IsDarwin]>;
1545 def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1547 []>, Requires<[IsThumb, IsDarwin]>;
1549 def TAILJMPr : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1551 []>, Requires<[IsARM, IsDarwin]>;
1553 def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1555 []>, Requires<[IsThumb, IsDarwin]>;
1558 // Non-Darwin versions (the difference is R9).
1559 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1561 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1562 IIC_Br, []>, Requires<[IsNotDarwin]>;
1564 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1565 IIC_Br, []>, Requires<[IsNotDarwin]>;
1567 def TAILJMPdND : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1569 []>, Requires<[IsARM, IsNotDarwin]>;
1571 def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1573 []>, Requires<[IsThumb, IsNotDarwin]>;
1575 def TAILJMPrND : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1577 []>, Requires<[IsARM, IsNotDarwin]>;
1578 def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1580 []>, Requires<[IsThumb, IsNotDarwin]>;
1588 // Secure Monitor Call is a system instruction -- for disassembly only
1589 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1590 [/* For disassembly only; pattern left blank */]> {
1592 let Inst{23-4} = 0b01100000000000000111;
1593 let Inst{3-0} = opt;
1596 // Supervisor Call (Software Interrupt) -- for disassembly only
1597 let isCall = 1, Uses = [SP] in {
1598 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1599 [/* For disassembly only; pattern left blank */]> {
1601 let Inst{23-0} = svc;
1604 def : MnemonicAlias<"swi", "svc">;
1606 // Store Return State is a system instruction -- for disassembly only
1607 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1608 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1609 NoItinerary, "srs${amode}\tsp!, $mode",
1610 [/* For disassembly only; pattern left blank */]> {
1611 let Inst{31-28} = 0b1111;
1612 let Inst{22-20} = 0b110; // W = 1
1613 let Inst{19-8} = 0xd05;
1614 let Inst{7-5} = 0b000;
1617 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1618 NoItinerary, "srs${amode}\tsp, $mode",
1619 [/* For disassembly only; pattern left blank */]> {
1620 let Inst{31-28} = 0b1111;
1621 let Inst{22-20} = 0b100; // W = 0
1622 let Inst{19-8} = 0xd05;
1623 let Inst{7-5} = 0b000;
1626 // Return From Exception is a system instruction -- for disassembly only
1627 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1628 NoItinerary, "rfe${amode}\t$base!",
1629 [/* For disassembly only; pattern left blank */]> {
1630 let Inst{31-28} = 0b1111;
1631 let Inst{22-20} = 0b011; // W = 1
1632 let Inst{15-0} = 0x0a00;
1635 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1636 NoItinerary, "rfe${amode}\t$base",
1637 [/* For disassembly only; pattern left blank */]> {
1638 let Inst{31-28} = 0b1111;
1639 let Inst{22-20} = 0b001; // W = 0
1640 let Inst{15-0} = 0x0a00;
1642 } // isCodeGenOnly = 1
1644 //===----------------------------------------------------------------------===//
1645 // Load / store Instructions.
1651 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1652 UnOpFrag<(load node:$Src)>>;
1653 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1654 UnOpFrag<(zextloadi8 node:$Src)>>;
1655 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1656 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1657 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1658 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1660 // Special LDR for loads from non-pc-relative constpools.
1661 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1662 isReMaterializable = 1 in
1663 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1664 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1668 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1669 let Inst{19-16} = 0b1111;
1670 let Inst{15-12} = Rt;
1671 let Inst{11-0} = addr{11-0}; // imm12
1674 // Loads with zero extension
1675 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1676 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1677 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1679 // Loads with sign extension
1680 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1681 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1682 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1684 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1685 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1686 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1688 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1690 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1691 (ins addrmode3:$addr), LdMiscFrm,
1692 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
1693 []>, Requires<[IsARM, HasV5TE]>;
1697 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1698 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1699 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1700 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1702 // {13} 1 == Rm, 0 == imm12
1706 let Inst{25} = addr{13};
1707 let Inst{23} = addr{12};
1708 let Inst{19-16} = addr{17-14};
1709 let Inst{11-0} = addr{11-0};
1710 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1712 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1713 (ins GPR:$Rn, am2offset:$offset),
1714 IndexModePost, LdFrm, itin,
1715 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1716 // {13} 1 == Rm, 0 == imm12
1721 let Inst{25} = offset{13};
1722 let Inst{23} = offset{12};
1723 let Inst{19-16} = Rn;
1724 let Inst{11-0} = offset{11-0};
1728 let mayLoad = 1, neverHasSideEffects = 1 in {
1729 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1730 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1733 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1734 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1735 (ins addrmode3:$addr), IndexModePre,
1737 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1739 let Inst{23} = addr{8}; // U bit
1740 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1741 let Inst{19-16} = addr{12-9}; // Rn
1742 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1743 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1745 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1746 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1748 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1751 let Inst{23} = offset{8}; // U bit
1752 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1753 let Inst{19-16} = Rn;
1754 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1755 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1759 let mayLoad = 1, neverHasSideEffects = 1 in {
1760 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1761 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1762 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1763 let hasExtraDefRegAllocReq = 1 in {
1764 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1765 (ins addrmode3:$addr), IndexModePre,
1766 LdMiscFrm, IIC_iLoad_d_ru,
1767 "ldrd", "\t$Rt, $Rt2, $addr!",
1768 "$addr.base = $Rn_wb", []> {
1770 let Inst{23} = addr{8}; // U bit
1771 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1772 let Inst{19-16} = addr{12-9}; // Rn
1773 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1774 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1776 def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1777 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1778 LdMiscFrm, IIC_iLoad_d_ru,
1779 "ldrd", "\t$Rt, $Rt2, [$Rn], $offset",
1780 "$Rn = $Rn_wb", []> {
1783 let Inst{23} = offset{8}; // U bit
1784 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1785 let Inst{19-16} = Rn;
1786 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1787 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1789 } // hasExtraDefRegAllocReq = 1
1790 } // mayLoad = 1, neverHasSideEffects = 1
1792 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1793 let mayLoad = 1, neverHasSideEffects = 1 in {
1794 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
1795 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
1796 "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1798 // {13} 1 == Rm, 0 == imm12
1802 let Inst{25} = addr{13};
1803 let Inst{23} = addr{12};
1804 let Inst{21} = 1; // overwrite
1805 let Inst{19-16} = addr{17-14};
1806 let Inst{11-0} = addr{11-0};
1807 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1809 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1810 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
1811 "ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1813 // {13} 1 == Rm, 0 == imm12
1817 let Inst{25} = addr{13};
1818 let Inst{23} = addr{12};
1819 let Inst{21} = 1; // overwrite
1820 let Inst{19-16} = addr{17-14};
1821 let Inst{11-0} = addr{11-0};
1822 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1824 def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1825 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1826 "ldrsbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1827 let Inst{21} = 1; // overwrite
1829 def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1830 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1831 "ldrht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1832 let Inst{21} = 1; // overwrite
1834 def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1835 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1836 "ldrsht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1837 let Inst{21} = 1; // overwrite
1843 // Stores with truncate
1844 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1845 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1846 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1849 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1850 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
1851 StMiscFrm, IIC_iStore_d_r,
1852 "strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>;
1855 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1856 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1857 IndexModePre, StFrm, IIC_iStore_ru,
1858 "str", "\t$Rt, [$Rn, $offset]!",
1859 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1861 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1863 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1864 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1865 IndexModePost, StFrm, IIC_iStore_ru,
1866 "str", "\t$Rt, [$Rn], $offset",
1867 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1869 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1871 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1872 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1873 IndexModePre, StFrm, IIC_iStore_bh_ru,
1874 "strb", "\t$Rt, [$Rn, $offset]!",
1875 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1876 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1877 GPR:$Rn, am2offset:$offset))]>;
1878 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1879 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1880 IndexModePost, StFrm, IIC_iStore_bh_ru,
1881 "strb", "\t$Rt, [$Rn], $offset",
1882 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1883 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1884 GPR:$Rn, am2offset:$offset))]>;
1886 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1887 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1888 IndexModePre, StMiscFrm, IIC_iStore_ru,
1889 "strh", "\t$Rt, [$Rn, $offset]!",
1890 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1892 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1894 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1895 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1896 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1897 "strh", "\t$Rt, [$Rn], $offset",
1898 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1899 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1900 GPR:$Rn, am3offset:$offset))]>;
1902 // For disassembly only
1903 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1904 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1905 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1906 StMiscFrm, IIC_iStore_d_ru,
1907 "strd", "\t$src1, $src2, [$base, $offset]!",
1908 "$base = $base_wb", []>;
1910 // For disassembly only
1911 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1912 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1913 StMiscFrm, IIC_iStore_d_ru,
1914 "strd", "\t$src1, $src2, [$base], $offset",
1915 "$base = $base_wb", []>;
1916 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1918 // STRT, STRBT, and STRHT are for disassembly only.
1920 def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1921 IndexModePost, StFrm, IIC_iStore_ru,
1922 "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1923 [/* For disassembly only; pattern left blank */]> {
1924 let Inst{21} = 1; // overwrite
1925 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1928 def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1929 IndexModePost, StFrm, IIC_iStore_bh_ru,
1930 "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1931 [/* For disassembly only; pattern left blank */]> {
1932 let Inst{21} = 1; // overwrite
1933 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1936 def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
1937 StMiscFrm, IIC_iStore_bh_ru,
1938 "strht", "\t$Rt, $addr", "$addr.base = $base_wb",
1939 [/* For disassembly only; pattern left blank */]> {
1940 let Inst{21} = 1; // overwrite
1941 let AsmMatchConverter = "CvtStWriteBackRegAddrMode3";
1944 //===----------------------------------------------------------------------===//
1945 // Load / store multiple Instructions.
1948 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1949 InstrItinClass itin, InstrItinClass itin_upd> {
1951 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1952 IndexModeNone, f, itin,
1953 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1954 let Inst{24-23} = 0b01; // Increment After
1955 let Inst{21} = 0; // No writeback
1956 let Inst{20} = L_bit;
1959 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1960 IndexModeUpd, f, itin_upd,
1961 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1962 let Inst{24-23} = 0b01; // Increment After
1963 let Inst{21} = 1; // Writeback
1964 let Inst{20} = L_bit;
1967 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1968 IndexModeNone, f, itin,
1969 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1970 let Inst{24-23} = 0b00; // Decrement After
1971 let Inst{21} = 0; // No writeback
1972 let Inst{20} = L_bit;
1975 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1976 IndexModeUpd, f, itin_upd,
1977 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1978 let Inst{24-23} = 0b00; // Decrement After
1979 let Inst{21} = 1; // Writeback
1980 let Inst{20} = L_bit;
1983 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1984 IndexModeNone, f, itin,
1985 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1986 let Inst{24-23} = 0b10; // Decrement Before
1987 let Inst{21} = 0; // No writeback
1988 let Inst{20} = L_bit;
1991 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1992 IndexModeUpd, f, itin_upd,
1993 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1994 let Inst{24-23} = 0b10; // Decrement Before
1995 let Inst{21} = 1; // Writeback
1996 let Inst{20} = L_bit;
1999 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2000 IndexModeNone, f, itin,
2001 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
2002 let Inst{24-23} = 0b11; // Increment Before
2003 let Inst{21} = 0; // No writeback
2004 let Inst{20} = L_bit;
2007 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2008 IndexModeUpd, f, itin_upd,
2009 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2010 let Inst{24-23} = 0b11; // Increment Before
2011 let Inst{21} = 1; // Writeback
2012 let Inst{20} = L_bit;
2016 let neverHasSideEffects = 1 in {
2018 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2019 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
2021 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2022 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
2024 } // neverHasSideEffects
2026 // Load / Store Multiple Mnemonic Aliases
2027 def : MnemonicAlias<"ldmfd", "ldmia">;
2028 def : MnemonicAlias<"stmfd", "stmdb">;
2029 def : MnemonicAlias<"ldm", "ldmia">;
2030 def : MnemonicAlias<"stm", "stmia">;
2032 // FIXME: remove when we have a way to marking a MI with these properties.
2033 // FIXME: Should pc be an implicit operand like PICADD, etc?
2034 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2035 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2036 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2037 reglist:$regs, variable_ops),
2038 Size4Bytes, IIC_iLoad_mBr, [],
2039 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2040 RegConstraint<"$Rn = $wb">;
2042 //===----------------------------------------------------------------------===//
2043 // Move Instructions.
2046 let neverHasSideEffects = 1 in
2047 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2048 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2052 let Inst{19-16} = 0b0000;
2053 let Inst{11-4} = 0b00000000;
2056 let Inst{15-12} = Rd;
2059 // A version for the smaller set of tail call registers.
2060 let neverHasSideEffects = 1 in
2061 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2062 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2066 let Inst{11-4} = 0b00000000;
2069 let Inst{15-12} = Rd;
2072 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
2073 DPSoRegFrm, IIC_iMOVsr,
2074 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
2078 let Inst{15-12} = Rd;
2079 let Inst{19-16} = 0b0000;
2080 let Inst{11-0} = src;
2084 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2085 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2086 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2090 let Inst{15-12} = Rd;
2091 let Inst{19-16} = 0b0000;
2092 let Inst{11-0} = imm;
2095 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2096 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
2098 "movw", "\t$Rd, $imm",
2099 [(set GPR:$Rd, imm0_65535:$imm)]>,
2100 Requires<[IsARM, HasV6T2]>, UnaryDP {
2103 let Inst{15-12} = Rd;
2104 let Inst{11-0} = imm{11-0};
2105 let Inst{19-16} = imm{15-12};
2110 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2111 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2113 let Constraints = "$src = $Rd" in {
2114 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
2116 "movt", "\t$Rd, $imm",
2118 (or (and GPR:$src, 0xffff),
2119 lo16AllZero:$imm))]>, UnaryDP,
2120 Requires<[IsARM, HasV6T2]> {
2123 let Inst{15-12} = Rd;
2124 let Inst{11-0} = imm{11-0};
2125 let Inst{19-16} = imm{15-12};
2130 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2131 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2135 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2136 Requires<[IsARM, HasV6T2]>;
2138 let Uses = [CPSR] in
2139 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2140 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2143 // These aren't really mov instructions, but we have to define them this way
2144 // due to flag operands.
2146 let Defs = [CPSR] in {
2147 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2148 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2150 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2151 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2155 //===----------------------------------------------------------------------===//
2156 // Extend Instructions.
2161 defm SXTB : AI_ext_rrot<0b01101010,
2162 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2163 defm SXTH : AI_ext_rrot<0b01101011,
2164 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2166 defm SXTAB : AI_exta_rrot<0b01101010,
2167 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2168 defm SXTAH : AI_exta_rrot<0b01101011,
2169 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2171 // For disassembly only
2172 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2174 // For disassembly only
2175 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2179 let AddedComplexity = 16 in {
2180 defm UXTB : AI_ext_rrot<0b01101110,
2181 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2182 defm UXTH : AI_ext_rrot<0b01101111,
2183 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2184 defm UXTB16 : AI_ext_rrot<0b01101100,
2185 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2187 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2188 // The transformation should probably be done as a combiner action
2189 // instead so we can include a check for masking back in the upper
2190 // eight bits of the source into the lower eight bits of the result.
2191 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2192 // (UXTB16r_rot GPR:$Src, 24)>;
2193 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2194 (UXTB16r_rot GPR:$Src, 8)>;
2196 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2197 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2198 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2199 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2202 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2203 // For disassembly only
2204 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2207 def SBFX : I<(outs GPR:$Rd),
2208 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2209 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2210 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2211 Requires<[IsARM, HasV6T2]> {
2216 let Inst{27-21} = 0b0111101;
2217 let Inst{6-4} = 0b101;
2218 let Inst{20-16} = width;
2219 let Inst{15-12} = Rd;
2220 let Inst{11-7} = lsb;
2224 def UBFX : I<(outs GPR:$Rd),
2225 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2226 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2227 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2228 Requires<[IsARM, HasV6T2]> {
2233 let Inst{27-21} = 0b0111111;
2234 let Inst{6-4} = 0b101;
2235 let Inst{20-16} = width;
2236 let Inst{15-12} = Rd;
2237 let Inst{11-7} = lsb;
2241 //===----------------------------------------------------------------------===//
2242 // Arithmetic Instructions.
2245 defm ADD : AsI1_bin_irs<0b0100, "add",
2246 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2247 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
2248 defm SUB : AsI1_bin_irs<0b0010, "sub",
2249 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2250 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
2252 // ADD and SUB with 's' bit set.
2253 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2254 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2255 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2256 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2257 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2258 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2260 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2261 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2262 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2263 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2265 // ADC and SUBC with 's' bit set.
2266 let usesCustomInserter = 1 in {
2267 defm ADCS : AI1_adde_sube_s_irs<
2268 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2269 defm SBCS : AI1_adde_sube_s_irs<
2270 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2273 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2274 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2275 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2280 let Inst{15-12} = Rd;
2281 let Inst{19-16} = Rn;
2282 let Inst{11-0} = imm;
2285 // The reg/reg form is only defined for the disassembler; for codegen it is
2286 // equivalent to SUBrr.
2287 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2288 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2289 [/* For disassembly only; pattern left blank */]> {
2293 let Inst{11-4} = 0b00000000;
2296 let Inst{15-12} = Rd;
2297 let Inst{19-16} = Rn;
2300 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2301 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2302 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2307 let Inst{11-0} = shift;
2308 let Inst{15-12} = Rd;
2309 let Inst{19-16} = Rn;
2312 // RSB with 's' bit set.
2313 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2314 let usesCustomInserter = 1 in {
2315 def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2316 Size4Bytes, IIC_iALUi,
2317 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
2318 def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2319 Size4Bytes, IIC_iALUr,
2320 [/* For disassembly only; pattern left blank */]>;
2321 def RSBSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2322 Size4Bytes, IIC_iALUsr,
2323 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]>;
2326 let Uses = [CPSR] in {
2327 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2328 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2329 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2335 let Inst{15-12} = Rd;
2336 let Inst{19-16} = Rn;
2337 let Inst{11-0} = imm;
2339 // The reg/reg form is only defined for the disassembler; for codegen it is
2340 // equivalent to SUBrr.
2341 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2342 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2343 [/* For disassembly only; pattern left blank */]> {
2347 let Inst{11-4} = 0b00000000;
2350 let Inst{15-12} = Rd;
2351 let Inst{19-16} = Rn;
2353 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2354 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2355 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2361 let Inst{11-0} = shift;
2362 let Inst{15-12} = Rd;
2363 let Inst{19-16} = Rn;
2367 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2368 let usesCustomInserter = 1, Uses = [CPSR] in {
2369 def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2370 Size4Bytes, IIC_iALUi,
2371 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>;
2372 def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2373 Size4Bytes, IIC_iALUsr,
2374 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>;
2377 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2378 // The assume-no-carry-in form uses the negation of the input since add/sub
2379 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2380 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2382 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2383 (SUBri GPR:$src, so_imm_neg:$imm)>;
2384 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2385 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2386 // The with-carry-in form matches bitwise not instead of the negation.
2387 // Effectively, the inverse interpretation of the carry flag already accounts
2388 // for part of the negation.
2389 def : ARMPat<(adde_dead_carry GPR:$src, so_imm_not:$imm),
2390 (SBCri GPR:$src, so_imm_not:$imm)>;
2391 def : ARMPat<(adde_live_carry GPR:$src, so_imm_not:$imm),
2392 (SBCSri GPR:$src, so_imm_not:$imm)>;
2394 // Note: These are implemented in C++ code, because they have to generate
2395 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2397 // (mul X, 2^n+1) -> (add (X << n), X)
2398 // (mul X, 2^n-1) -> (rsb X, (X << n))
2400 // ARM Arithmetic Instruction -- for disassembly only
2401 // GPR:$dst = GPR:$a op GPR:$b
2402 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2403 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2404 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2405 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2409 let Inst{27-20} = op27_20;
2410 let Inst{11-4} = op11_4;
2411 let Inst{19-16} = Rn;
2412 let Inst{15-12} = Rd;
2416 // Saturating add/subtract -- for disassembly only
2418 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2419 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2420 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2421 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2422 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2423 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2424 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2426 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2429 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2430 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2431 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2432 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2433 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2434 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2435 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2436 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2437 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2438 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2439 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2440 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2442 // Signed/Unsigned add/subtract -- for disassembly only
2444 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2445 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2446 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2447 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2448 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2449 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2450 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2451 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2452 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2453 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2454 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2455 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2457 // Signed/Unsigned halving add/subtract -- for disassembly only
2459 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2460 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2461 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2462 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2463 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2464 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2465 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2466 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2467 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2468 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2469 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2470 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2472 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2474 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2475 MulFrm /* for convenience */, NoItinerary, "usad8",
2476 "\t$Rd, $Rn, $Rm", []>,
2477 Requires<[IsARM, HasV6]> {
2481 let Inst{27-20} = 0b01111000;
2482 let Inst{15-12} = 0b1111;
2483 let Inst{7-4} = 0b0001;
2484 let Inst{19-16} = Rd;
2485 let Inst{11-8} = Rm;
2488 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2489 MulFrm /* for convenience */, NoItinerary, "usada8",
2490 "\t$Rd, $Rn, $Rm, $Ra", []>,
2491 Requires<[IsARM, HasV6]> {
2496 let Inst{27-20} = 0b01111000;
2497 let Inst{7-4} = 0b0001;
2498 let Inst{19-16} = Rd;
2499 let Inst{15-12} = Ra;
2500 let Inst{11-8} = Rm;
2504 // Signed/Unsigned saturate -- for disassembly only
2506 def SSAT : AI<(outs GPR:$Rd), (ins ssat_imm:$sat_imm, GPR:$a, shift_imm:$sh),
2507 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2508 [/* For disassembly only; pattern left blank */]> {
2513 let Inst{27-21} = 0b0110101;
2514 let Inst{5-4} = 0b01;
2515 let Inst{20-16} = sat_imm;
2516 let Inst{15-12} = Rd;
2517 let Inst{11-7} = sh{7-3};
2518 let Inst{6} = sh{0};
2522 def SSAT16 : AI<(outs GPR:$Rd), (ins ssat_imm:$sat_imm, GPR:$Rn), SatFrm,
2523 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2524 [/* For disassembly only; pattern left blank */]> {
2528 let Inst{27-20} = 0b01101010;
2529 let Inst{11-4} = 0b11110011;
2530 let Inst{15-12} = Rd;
2531 let Inst{19-16} = sat_imm;
2535 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2536 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2537 [/* For disassembly only; pattern left blank */]> {
2542 let Inst{27-21} = 0b0110111;
2543 let Inst{5-4} = 0b01;
2544 let Inst{15-12} = Rd;
2545 let Inst{11-7} = sh{7-3};
2546 let Inst{6} = sh{0};
2547 let Inst{20-16} = sat_imm;
2551 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2552 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2553 [/* For disassembly only; pattern left blank */]> {
2557 let Inst{27-20} = 0b01101110;
2558 let Inst{11-4} = 0b11110011;
2559 let Inst{15-12} = Rd;
2560 let Inst{19-16} = sat_imm;
2564 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2565 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2567 //===----------------------------------------------------------------------===//
2568 // Bitwise Instructions.
2571 defm AND : AsI1_bin_irs<0b0000, "and",
2572 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2573 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
2574 defm ORR : AsI1_bin_irs<0b1100, "orr",
2575 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2576 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
2577 defm EOR : AsI1_bin_irs<0b0001, "eor",
2578 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2579 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
2580 defm BIC : AsI1_bin_irs<0b1110, "bic",
2581 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2582 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
2584 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2585 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2586 "bfc", "\t$Rd, $imm", "$src = $Rd",
2587 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2588 Requires<[IsARM, HasV6T2]> {
2591 let Inst{27-21} = 0b0111110;
2592 let Inst{6-0} = 0b0011111;
2593 let Inst{15-12} = Rd;
2594 let Inst{11-7} = imm{4-0}; // lsb
2595 let Inst{20-16} = imm{9-5}; // width
2598 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2599 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2600 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2601 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2602 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2603 bf_inv_mask_imm:$imm))]>,
2604 Requires<[IsARM, HasV6T2]> {
2608 let Inst{27-21} = 0b0111110;
2609 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2610 let Inst{15-12} = Rd;
2611 let Inst{11-7} = imm{4-0}; // lsb
2612 let Inst{20-16} = imm{9-5}; // width
2616 // GNU as only supports this form of bfi (w/ 4 arguments)
2617 let isAsmParserOnly = 1 in
2618 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2619 lsb_pos_imm:$lsb, width_imm:$width),
2620 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2621 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2622 []>, Requires<[IsARM, HasV6T2]> {
2627 let Inst{27-21} = 0b0111110;
2628 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2629 let Inst{15-12} = Rd;
2630 let Inst{11-7} = lsb;
2631 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2635 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2636 "mvn", "\t$Rd, $Rm",
2637 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2641 let Inst{19-16} = 0b0000;
2642 let Inst{11-4} = 0b00000000;
2643 let Inst{15-12} = Rd;
2646 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2647 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2648 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2652 let Inst{19-16} = 0b0000;
2653 let Inst{15-12} = Rd;
2654 let Inst{11-0} = shift;
2656 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2657 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2658 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2659 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2663 let Inst{19-16} = 0b0000;
2664 let Inst{15-12} = Rd;
2665 let Inst{11-0} = imm;
2668 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2669 (BICri GPR:$src, so_imm_not:$imm)>;
2671 //===----------------------------------------------------------------------===//
2672 // Multiply Instructions.
2674 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2675 string opc, string asm, list<dag> pattern>
2676 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2680 let Inst{19-16} = Rd;
2681 let Inst{11-8} = Rm;
2684 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2685 string opc, string asm, list<dag> pattern>
2686 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2691 let Inst{19-16} = RdHi;
2692 let Inst{15-12} = RdLo;
2693 let Inst{11-8} = Rm;
2697 // FIXME: The v5 pseudos are only necessary for the additional Constraint
2698 // property. Remove them when it's possible to add those properties
2699 // on an individual MachineInstr, not just an instuction description.
2700 let isCommutable = 1 in {
2701 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2702 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2703 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2704 Requires<[IsARM, HasV6]> {
2705 let Inst{15-12} = 0b0000;
2708 let Constraints = "@earlyclobber $Rd" in
2709 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2710 pred:$p, cc_out:$s),
2711 Size4Bytes, IIC_iMUL32,
2712 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
2713 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2714 Requires<[IsARM, NoV6]>;
2717 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2718 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2719 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2720 Requires<[IsARM, HasV6]> {
2722 let Inst{15-12} = Ra;
2725 let Constraints = "@earlyclobber $Rd" in
2726 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
2727 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2728 Size4Bytes, IIC_iMAC32,
2729 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
2730 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
2731 Requires<[IsARM, NoV6]>;
2733 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2734 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2735 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2736 Requires<[IsARM, HasV6T2]> {
2741 let Inst{19-16} = Rd;
2742 let Inst{15-12} = Ra;
2743 let Inst{11-8} = Rm;
2747 // Extra precision multiplies with low / high results
2748 let neverHasSideEffects = 1 in {
2749 let isCommutable = 1 in {
2750 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2751 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2752 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2753 Requires<[IsARM, HasV6]>;
2755 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2756 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2757 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2758 Requires<[IsARM, HasV6]>;
2760 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2761 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2762 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2763 Size4Bytes, IIC_iMUL64, [],
2764 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2765 Requires<[IsARM, NoV6]>;
2767 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2768 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2769 Size4Bytes, IIC_iMUL64, [],
2770 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2771 Requires<[IsARM, NoV6]>;
2775 // Multiply + accumulate
2776 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2777 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2778 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2779 Requires<[IsARM, HasV6]>;
2780 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2781 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2782 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2783 Requires<[IsARM, HasV6]>;
2785 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2786 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2787 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2788 Requires<[IsARM, HasV6]> {
2793 let Inst{19-16} = RdLo;
2794 let Inst{15-12} = RdHi;
2795 let Inst{11-8} = Rm;
2799 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2800 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2801 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2802 Size4Bytes, IIC_iMAC64, [],
2803 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2804 Requires<[IsARM, NoV6]>;
2805 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2806 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2807 Size4Bytes, IIC_iMAC64, [],
2808 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
2809 Requires<[IsARM, NoV6]>;
2810 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
2811 (ins GPR:$Rn, GPR:$Rm, pred:$p),
2812 Size4Bytes, IIC_iMAC64, [],
2813 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
2814 Requires<[IsARM, NoV6]>;
2817 } // neverHasSideEffects
2819 // Most significant word multiply
2820 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2821 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2822 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2823 Requires<[IsARM, HasV6]> {
2824 let Inst{15-12} = 0b1111;
2827 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2828 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2829 [/* For disassembly only; pattern left blank */]>,
2830 Requires<[IsARM, HasV6]> {
2831 let Inst{15-12} = 0b1111;
2834 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2835 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2836 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2837 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2838 Requires<[IsARM, HasV6]>;
2840 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2841 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2842 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2843 [/* For disassembly only; pattern left blank */]>,
2844 Requires<[IsARM, HasV6]>;
2846 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2847 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2848 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2849 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2850 Requires<[IsARM, HasV6]>;
2852 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2853 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2854 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2855 [/* For disassembly only; pattern left blank */]>,
2856 Requires<[IsARM, HasV6]>;
2858 multiclass AI_smul<string opc, PatFrag opnode> {
2859 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2860 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2861 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2862 (sext_inreg GPR:$Rm, i16)))]>,
2863 Requires<[IsARM, HasV5TE]>;
2865 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2866 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2867 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2868 (sra GPR:$Rm, (i32 16))))]>,
2869 Requires<[IsARM, HasV5TE]>;
2871 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2872 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2873 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2874 (sext_inreg GPR:$Rm, i16)))]>,
2875 Requires<[IsARM, HasV5TE]>;
2877 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2878 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2879 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2880 (sra GPR:$Rm, (i32 16))))]>,
2881 Requires<[IsARM, HasV5TE]>;
2883 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2884 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2885 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2886 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2887 Requires<[IsARM, HasV5TE]>;
2889 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2890 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2891 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2892 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2893 Requires<[IsARM, HasV5TE]>;
2897 multiclass AI_smla<string opc, PatFrag opnode> {
2898 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2899 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2900 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2901 [(set GPR:$Rd, (add GPR:$Ra,
2902 (opnode (sext_inreg GPR:$Rn, i16),
2903 (sext_inreg GPR:$Rm, i16))))]>,
2904 Requires<[IsARM, HasV5TE]>;
2906 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2907 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2908 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2909 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2910 (sra GPR:$Rm, (i32 16)))))]>,
2911 Requires<[IsARM, HasV5TE]>;
2913 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2914 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2915 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2916 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2917 (sext_inreg GPR:$Rm, i16))))]>,
2918 Requires<[IsARM, HasV5TE]>;
2920 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2921 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2922 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2923 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2924 (sra GPR:$Rm, (i32 16)))))]>,
2925 Requires<[IsARM, HasV5TE]>;
2927 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2928 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2929 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2930 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2931 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2932 Requires<[IsARM, HasV5TE]>;
2934 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2935 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2936 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2937 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2938 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2939 Requires<[IsARM, HasV5TE]>;
2942 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2943 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2945 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2946 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2947 (ins GPR:$Rn, GPR:$Rm),
2948 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2949 [/* For disassembly only; pattern left blank */]>,
2950 Requires<[IsARM, HasV5TE]>;
2952 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2953 (ins GPR:$Rn, GPR:$Rm),
2954 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2955 [/* For disassembly only; pattern left blank */]>,
2956 Requires<[IsARM, HasV5TE]>;
2958 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2959 (ins GPR:$Rn, GPR:$Rm),
2960 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2961 [/* For disassembly only; pattern left blank */]>,
2962 Requires<[IsARM, HasV5TE]>;
2964 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2965 (ins GPR:$Rn, GPR:$Rm),
2966 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2967 [/* For disassembly only; pattern left blank */]>,
2968 Requires<[IsARM, HasV5TE]>;
2970 // Helper class for AI_smld -- for disassembly only
2971 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2972 InstrItinClass itin, string opc, string asm>
2973 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2980 let Inst{21-20} = 0b00;
2981 let Inst{22} = long;
2982 let Inst{27-23} = 0b01110;
2983 let Inst{11-8} = Rm;
2986 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2987 InstrItinClass itin, string opc, string asm>
2988 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2990 let Inst{15-12} = 0b1111;
2991 let Inst{19-16} = Rd;
2993 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2994 InstrItinClass itin, string opc, string asm>
2995 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2997 let Inst{15-12} = Ra;
2999 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3000 InstrItinClass itin, string opc, string asm>
3001 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3004 let Inst{19-16} = RdHi;
3005 let Inst{15-12} = RdLo;
3008 multiclass AI_smld<bit sub, string opc> {
3010 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3011 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3013 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3014 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3016 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
3017 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
3018 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3020 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
3021 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
3022 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3026 defm SMLA : AI_smld<0, "smla">;
3027 defm SMLS : AI_smld<1, "smls">;
3029 multiclass AI_sdml<bit sub, string opc> {
3031 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3032 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3033 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3034 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3037 defm SMUA : AI_sdml<0, "smua">;
3038 defm SMUS : AI_sdml<1, "smus">;
3040 //===----------------------------------------------------------------------===//
3041 // Misc. Arithmetic Instructions.
3044 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3045 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3046 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3048 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3049 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3050 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3051 Requires<[IsARM, HasV6T2]>;
3053 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3054 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3055 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3057 let AddedComplexity = 5 in
3058 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3059 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3060 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3061 Requires<[IsARM, HasV6]>;
3063 let AddedComplexity = 5 in
3064 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3065 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3066 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3067 Requires<[IsARM, HasV6]>;
3069 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3070 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3073 def lsl_shift_imm : SDNodeXForm<imm, [{
3074 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
3075 return CurDAG->getTargetConstant(Sh, MVT::i32);
3078 def lsl_amt : ImmLeaf<i32, [{
3079 return Imm > 0 && Imm < 32;
3082 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3083 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3084 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3085 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3086 (and (shl GPR:$Rm, lsl_amt:$sh),
3088 Requires<[IsARM, HasV6]>;
3090 // Alternate cases for PKHBT where identities eliminate some nodes.
3091 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3092 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3093 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3094 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3096 def asr_shift_imm : SDNodeXForm<imm, [{
3097 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3098 return CurDAG->getTargetConstant(Sh, MVT::i32);
3101 def asr_amt : ImmLeaf<i32, [{
3102 return Imm > 0 && Imm <= 32;
3105 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3106 // will match the pattern below.
3107 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3108 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3109 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3110 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3111 (and (sra GPR:$Rm, asr_amt:$sh),
3113 Requires<[IsARM, HasV6]>;
3115 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3116 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3117 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3118 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3119 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3120 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3121 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3123 //===----------------------------------------------------------------------===//
3124 // Comparison Instructions...
3127 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3128 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3129 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3131 // ARMcmpZ can re-use the above instruction definitions.
3132 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3133 (CMPri GPR:$src, so_imm:$imm)>;
3134 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3135 (CMPrr GPR:$src, GPR:$rhs)>;
3136 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3137 (CMPrs GPR:$src, so_reg:$rhs)>;
3139 // FIXME: We have to be careful when using the CMN instruction and comparison
3140 // with 0. One would expect these two pieces of code should give identical
3156 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3157 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3158 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3159 // value of r0 and the carry bit (because the "carry bit" parameter to
3160 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3161 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3162 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3163 // parameter to AddWithCarry is defined as 0).
3165 // When x is 0 and unsigned:
3169 // ~x + 1 = 0x1 0000 0000
3170 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3172 // Therefore, we should disable CMN when comparing against zero, until we can
3173 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3174 // when it's a comparison which doesn't look at the 'carry' flag).
3176 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3178 // This is related to <rdar://problem/7569620>.
3180 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3181 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3183 // Note that TST/TEQ don't set all the same flags that CMP does!
3184 defm TST : AI1_cmp_irs<0b1000, "tst",
3185 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3186 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3187 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3188 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3189 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3191 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3192 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3193 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3195 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3196 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3198 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3199 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3201 // Pseudo i64 compares for some floating point compares.
3202 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3204 def BCCi64 : PseudoInst<(outs),
3205 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3207 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3209 def BCCZi64 : PseudoInst<(outs),
3210 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3211 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3212 } // usesCustomInserter
3215 // Conditional moves
3216 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3217 // a two-value operand where a dag node expects two operands. :(
3218 let neverHasSideEffects = 1 in {
3219 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3220 Size4Bytes, IIC_iCMOVr,
3221 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3222 RegConstraint<"$false = $Rd">;
3223 def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
3224 (ins GPR:$false, so_reg:$shift, pred:$p),
3225 Size4Bytes, IIC_iCMOVsr,
3226 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3227 RegConstraint<"$false = $Rd">;
3229 let isMoveImm = 1 in
3230 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3231 (ins GPR:$false, i32imm_hilo16:$imm, pred:$p),
3232 Size4Bytes, IIC_iMOVi,
3234 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3236 let isMoveImm = 1 in
3237 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3238 (ins GPR:$false, so_imm:$imm, pred:$p),
3239 Size4Bytes, IIC_iCMOVi,
3240 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3241 RegConstraint<"$false = $Rd">;
3243 // Two instruction predicate mov immediate.
3244 let isMoveImm = 1 in
3245 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3246 (ins GPR:$false, i32imm:$src, pred:$p),
3247 Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3249 let isMoveImm = 1 in
3250 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3251 (ins GPR:$false, so_imm:$imm, pred:$p),
3252 Size4Bytes, IIC_iCMOVi,
3253 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3254 RegConstraint<"$false = $Rd">;
3255 } // neverHasSideEffects
3257 //===----------------------------------------------------------------------===//
3258 // Atomic operations intrinsics
3261 def memb_opt : Operand<i32> {
3262 let PrintMethod = "printMemBOption";
3263 let ParserMatchClass = MemBarrierOptOperand;
3266 // memory barriers protect the atomic sequences
3267 let hasSideEffects = 1 in {
3268 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3269 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3270 Requires<[IsARM, HasDB]> {
3272 let Inst{31-4} = 0xf57ff05;
3273 let Inst{3-0} = opt;
3277 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3279 [/* For disassembly only; pattern left blank */]>,
3280 Requires<[IsARM, HasDB]> {
3282 let Inst{31-4} = 0xf57ff04;
3283 let Inst{3-0} = opt;
3286 // ISB has only full system option -- for disassembly only
3287 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3288 Requires<[IsARM, HasDB]> {
3289 let Inst{31-4} = 0xf57ff06;
3290 let Inst{3-0} = 0b1111;
3293 let usesCustomInserter = 1 in {
3294 let Uses = [CPSR] in {
3295 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3296 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3297 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3298 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3299 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3300 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3301 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3302 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3303 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3304 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3305 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3306 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3307 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3308 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3309 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3310 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3311 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3312 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3313 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
3314 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3315 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3316 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
3317 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3318 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3319 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
3320 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3321 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3322 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
3323 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3324 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3325 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3326 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3327 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3328 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3329 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3330 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3331 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3332 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3333 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3334 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3335 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3336 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3337 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3338 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3339 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3340 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3341 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3342 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3343 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
3344 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3345 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3346 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
3347 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3348 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3349 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
3350 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3351 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3352 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
3353 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3354 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3355 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3356 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3357 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3358 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3359 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3360 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3361 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3362 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3363 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3364 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3365 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3366 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3367 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3368 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3369 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3370 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3371 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3372 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3373 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
3374 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3375 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3376 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
3377 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3378 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3379 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
3380 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3381 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3382 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
3383 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3384 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3386 def ATOMIC_SWAP_I8 : PseudoInst<
3387 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3388 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3389 def ATOMIC_SWAP_I16 : PseudoInst<
3390 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3391 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3392 def ATOMIC_SWAP_I32 : PseudoInst<
3393 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3394 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3396 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3397 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3398 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3399 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3400 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3401 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3402 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3403 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3404 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3408 let mayLoad = 1 in {
3409 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3410 "ldrexb", "\t$Rt, $addr", []>;
3411 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3412 "ldrexh", "\t$Rt, $addr", []>;
3413 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3414 "ldrex", "\t$Rt, $addr", []>;
3415 let hasExtraDefRegAllocReq = 1 in
3416 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
3417 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3420 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3421 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3422 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3423 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3424 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3425 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3426 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3429 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
3430 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3431 (ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
3432 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3434 // Clear-Exclusive is for disassembly only.
3435 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3436 [/* For disassembly only; pattern left blank */]>,
3437 Requires<[IsARM, HasV7]> {
3438 let Inst{31-0} = 0b11110101011111111111000000011111;
3441 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3442 let mayLoad = 1 in {
3443 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3444 [/* For disassembly only; pattern left blank */]>;
3445 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3446 [/* For disassembly only; pattern left blank */]>;
3449 //===----------------------------------------------------------------------===//
3450 // Coprocessor Instructions.
3453 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3454 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3455 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3456 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3457 imm:$CRm, imm:$opc2)]> {
3465 let Inst{3-0} = CRm;
3467 let Inst{7-5} = opc2;
3468 let Inst{11-8} = cop;
3469 let Inst{15-12} = CRd;
3470 let Inst{19-16} = CRn;
3471 let Inst{23-20} = opc1;
3474 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3475 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3476 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3477 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3478 imm:$CRm, imm:$opc2)]> {
3479 let Inst{31-28} = 0b1111;
3487 let Inst{3-0} = CRm;
3489 let Inst{7-5} = opc2;
3490 let Inst{11-8} = cop;
3491 let Inst{15-12} = CRd;
3492 let Inst{19-16} = CRn;
3493 let Inst{23-20} = opc1;
3496 class ACI<dag oops, dag iops, string opc, string asm,
3497 IndexMode im = IndexModeNone>
3498 : InoP<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
3499 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3500 let Inst{27-25} = 0b110;
3503 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
3505 def _OFFSET : ACI<(outs),
3506 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3507 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
3508 let Inst{31-28} = op31_28;
3509 let Inst{24} = 1; // P = 1
3510 let Inst{21} = 0; // W = 0
3511 let Inst{22} = 0; // D = 0
3512 let Inst{20} = load;
3515 def _PRE : ACI<(outs),
3516 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3517 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
3518 let Inst{31-28} = op31_28;
3519 let Inst{24} = 1; // P = 1
3520 let Inst{21} = 1; // W = 1
3521 let Inst{22} = 0; // D = 0
3522 let Inst{20} = load;
3525 def _POST : ACI<(outs),
3526 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3527 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
3528 let Inst{31-28} = op31_28;
3529 let Inst{24} = 0; // P = 0
3530 let Inst{21} = 1; // W = 1
3531 let Inst{22} = 0; // D = 0
3532 let Inst{20} = load;
3535 def _OPTION : ACI<(outs),
3536 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3538 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3539 let Inst{31-28} = op31_28;
3540 let Inst{24} = 0; // P = 0
3541 let Inst{23} = 1; // U = 1
3542 let Inst{21} = 0; // W = 0
3543 let Inst{22} = 0; // D = 0
3544 let Inst{20} = load;
3547 def L_OFFSET : ACI<(outs),
3548 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3549 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
3550 let Inst{31-28} = op31_28;
3551 let Inst{24} = 1; // P = 1
3552 let Inst{21} = 0; // W = 0
3553 let Inst{22} = 1; // D = 1
3554 let Inst{20} = load;
3557 def L_PRE : ACI<(outs),
3558 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3559 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
3561 let Inst{31-28} = op31_28;
3562 let Inst{24} = 1; // P = 1
3563 let Inst{21} = 1; // W = 1
3564 let Inst{22} = 1; // D = 1
3565 let Inst{20} = load;
3568 def L_POST : ACI<(outs),
3569 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3570 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr",
3572 let Inst{31-28} = op31_28;
3573 let Inst{24} = 0; // P = 0
3574 let Inst{21} = 1; // W = 1
3575 let Inst{22} = 1; // D = 1
3576 let Inst{20} = load;
3579 def L_OPTION : ACI<(outs),
3580 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3582 !strconcat(!strconcat(opc, "l"), cond),
3583 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3584 let Inst{31-28} = op31_28;
3585 let Inst{24} = 0; // P = 0
3586 let Inst{23} = 1; // U = 1
3587 let Inst{21} = 0; // W = 0
3588 let Inst{22} = 1; // D = 1
3589 let Inst{20} = load;
3593 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
3594 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
3595 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
3596 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
3598 //===----------------------------------------------------------------------===//
3599 // Move between coprocessor and ARM core register -- for disassembly only
3602 class MovRCopro<string opc, bit direction, dag oops, dag iops,
3604 : ABI<0b1110, oops, iops, NoItinerary, opc,
3605 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
3606 let Inst{20} = direction;
3616 let Inst{15-12} = Rt;
3617 let Inst{11-8} = cop;
3618 let Inst{23-21} = opc1;
3619 let Inst{7-5} = opc2;
3620 let Inst{3-0} = CRm;
3621 let Inst{19-16} = CRn;
3624 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3626 (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
3627 c_imm:$CRm, i32imm:$opc2),
3628 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3629 imm:$CRm, imm:$opc2)]>;
3630 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3632 (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm,
3635 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3636 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3638 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
3640 : ABXI<0b1110, oops, iops, NoItinerary,
3641 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
3642 let Inst{31-28} = 0b1111;
3643 let Inst{20} = direction;
3653 let Inst{15-12} = Rt;
3654 let Inst{11-8} = cop;
3655 let Inst{23-21} = opc1;
3656 let Inst{7-5} = opc2;
3657 let Inst{3-0} = CRm;
3658 let Inst{19-16} = CRn;
3661 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3663 (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
3664 c_imm:$CRm, i32imm:$opc2),
3665 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3666 imm:$CRm, imm:$opc2)]>;
3667 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3669 (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm,
3672 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
3673 imm:$CRm, imm:$opc2),
3674 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3676 class MovRRCopro<string opc, bit direction,
3677 list<dag> pattern = [/* For disassembly only */]>
3678 : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3679 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3680 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
3681 let Inst{23-21} = 0b010;
3682 let Inst{20} = direction;
3690 let Inst{15-12} = Rt;
3691 let Inst{19-16} = Rt2;
3692 let Inst{11-8} = cop;
3693 let Inst{7-4} = opc1;
3694 let Inst{3-0} = CRm;
3697 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
3698 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3700 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3702 class MovRRCopro2<string opc, bit direction,
3703 list<dag> pattern = [/* For disassembly only */]>
3704 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3705 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
3706 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3707 let Inst{31-28} = 0b1111;
3708 let Inst{23-21} = 0b010;
3709 let Inst{20} = direction;
3717 let Inst{15-12} = Rt;
3718 let Inst{19-16} = Rt2;
3719 let Inst{11-8} = cop;
3720 let Inst{7-4} = opc1;
3721 let Inst{3-0} = CRm;
3724 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
3725 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3727 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3729 //===----------------------------------------------------------------------===//
3730 // Move between special register and ARM core register -- for disassembly only
3733 // Move to ARM core register from Special Register
3734 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3735 [/* For disassembly only; pattern left blank */]> {
3737 let Inst{23-16} = 0b00001111;
3738 let Inst{15-12} = Rd;
3739 let Inst{7-4} = 0b0000;
3742 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3743 [/* For disassembly only; pattern left blank */]> {
3745 let Inst{23-16} = 0b01001111;
3746 let Inst{15-12} = Rd;
3747 let Inst{7-4} = 0b0000;
3750 // Move from ARM core register to Special Register
3752 // No need to have both system and application versions, the encodings are the
3753 // same and the assembly parser has no way to distinguish between them. The mask
3754 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3755 // the mask with the fields to be accessed in the special register.
3756 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3757 "msr", "\t$mask, $Rn",
3758 [/* For disassembly only; pattern left blank */]> {
3763 let Inst{22} = mask{4}; // R bit
3764 let Inst{21-20} = 0b10;
3765 let Inst{19-16} = mask{3-0};
3766 let Inst{15-12} = 0b1111;
3767 let Inst{11-4} = 0b00000000;
3771 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3772 "msr", "\t$mask, $a",
3773 [/* For disassembly only; pattern left blank */]> {
3778 let Inst{22} = mask{4}; // R bit
3779 let Inst{21-20} = 0b10;
3780 let Inst{19-16} = mask{3-0};
3781 let Inst{15-12} = 0b1111;
3785 //===----------------------------------------------------------------------===//
3789 // __aeabi_read_tp preserves the registers r1-r3.
3790 // This is a pseudo inst so that we can get the encoding right,
3791 // complete with fixup for the aeabi_read_tp function.
3793 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3794 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3795 [(set R0, ARMthread_pointer)]>;
3798 //===----------------------------------------------------------------------===//
3799 // SJLJ Exception handling intrinsics
3800 // eh_sjlj_setjmp() is an instruction sequence to store the return
3801 // address and save #0 in R0 for the non-longjmp case.
3802 // Since by its nature we may be coming from some other function to get
3803 // here, and we're using the stack frame for the containing function to
3804 // save/restore registers, we can't keep anything live in regs across
3805 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3806 // when we get here from a longjmp(). We force everything out of registers
3807 // except for our own input by listing the relevant registers in Defs. By
3808 // doing so, we also cause the prologue/epilogue code to actively preserve
3809 // all of the callee-saved resgisters, which is exactly what we want.
3810 // A constant value is passed in $val, and we use the location as a scratch.
3812 // These are pseudo-instructions and are lowered to individual MC-insts, so
3813 // no encoding information is necessary.
3815 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3816 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1 in {
3817 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3819 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3820 Requires<[IsARM, HasVFP2]>;
3824 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3825 hasSideEffects = 1, isBarrier = 1 in {
3826 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3828 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3829 Requires<[IsARM, NoVFP]>;
3832 // FIXME: Non-Darwin version(s)
3833 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3834 Defs = [ R7, LR, SP ] in {
3835 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3837 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3838 Requires<[IsARM, IsDarwin]>;
3841 // eh.sjlj.dispatchsetup pseudo-instruction.
3842 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3843 // handled when the pseudo is expanded (which happens before any passes
3844 // that need the instruction size).
3845 let isBarrier = 1, hasSideEffects = 1 in
3846 def Int_eh_sjlj_dispatchsetup :
3847 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3848 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3849 Requires<[IsDarwin]>;
3851 //===----------------------------------------------------------------------===//
3852 // Non-Instruction Patterns
3855 // ARMv4 indirect branch using (MOVr PC, dst)
3856 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
3857 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
3858 Size4Bytes, IIC_Br, [(brind GPR:$dst)],
3859 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
3860 Requires<[IsARM, NoV4T]>;
3862 // Large immediate handling.
3864 // 32-bit immediate using two piece so_imms or movw + movt.
3865 // This is a single pseudo instruction, the benefit is that it can be remat'd
3866 // as a single unit instead of having to handle reg inputs.
3867 // FIXME: Remove this when we can do generalized remat.
3868 let isReMaterializable = 1, isMoveImm = 1 in
3869 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3870 [(set GPR:$dst, (arm_i32imm:$src))]>,
3873 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3874 // It also makes it possible to rematerialize the instructions.
3875 // FIXME: Remove this when we can do generalized remat and when machine licm
3876 // can properly the instructions.
3877 let isReMaterializable = 1 in {
3878 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3880 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3881 Requires<[IsARM, UseMovt]>;
3883 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3885 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3886 Requires<[IsARM, UseMovt]>;
3888 let AddedComplexity = 10 in
3889 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3891 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3892 Requires<[IsARM, UseMovt]>;
3893 } // isReMaterializable
3895 // ConstantPool, GlobalAddress, and JumpTable
3896 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3897 Requires<[IsARM, DontUseMovt]>;
3898 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3899 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3900 Requires<[IsARM, UseMovt]>;
3901 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3902 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3904 // TODO: add,sub,and, 3-instr forms?
3907 def : ARMPat<(ARMtcret tcGPR:$dst),
3908 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3910 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3911 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3913 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3914 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3916 def : ARMPat<(ARMtcret tcGPR:$dst),
3917 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3919 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3920 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3922 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3923 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3926 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3927 Requires<[IsARM, IsNotDarwin]>;
3928 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3929 Requires<[IsARM, IsDarwin]>;
3931 // zextload i1 -> zextload i8
3932 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3933 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3935 // extload -> zextload
3936 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3937 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3938 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3939 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3941 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3943 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3944 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3947 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3948 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3949 (SMULBB GPR:$a, GPR:$b)>;
3950 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3951 (SMULBB GPR:$a, GPR:$b)>;
3952 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3953 (sra GPR:$b, (i32 16))),
3954 (SMULBT GPR:$a, GPR:$b)>;
3955 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3956 (SMULBT GPR:$a, GPR:$b)>;
3957 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3958 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3959 (SMULTB GPR:$a, GPR:$b)>;
3960 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3961 (SMULTB GPR:$a, GPR:$b)>;
3962 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3964 (SMULWB GPR:$a, GPR:$b)>;
3965 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3966 (SMULWB GPR:$a, GPR:$b)>;
3968 def : ARMV5TEPat<(add GPR:$acc,
3969 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3970 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3971 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3972 def : ARMV5TEPat<(add GPR:$acc,
3973 (mul sext_16_node:$a, sext_16_node:$b)),
3974 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3975 def : ARMV5TEPat<(add GPR:$acc,
3976 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3977 (sra GPR:$b, (i32 16)))),
3978 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3979 def : ARMV5TEPat<(add GPR:$acc,
3980 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3981 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3982 def : ARMV5TEPat<(add GPR:$acc,
3983 (mul (sra GPR:$a, (i32 16)),
3984 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3985 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3986 def : ARMV5TEPat<(add GPR:$acc,
3987 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3988 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3989 def : ARMV5TEPat<(add GPR:$acc,
3990 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3992 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3993 def : ARMV5TEPat<(add GPR:$acc,
3994 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3995 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3998 // Pre-v7 uses MCR for synchronization barriers.
3999 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4000 Requires<[IsARM, HasV6]>;
4003 //===----------------------------------------------------------------------===//
4007 include "ARMInstrThumb.td"
4009 //===----------------------------------------------------------------------===//
4013 include "ARMInstrThumb2.td"
4015 //===----------------------------------------------------------------------===//
4016 // Floating Point Support
4019 include "ARMInstrVFP.td"
4021 //===----------------------------------------------------------------------===//
4022 // Advanced SIMD (NEON) Support
4025 include "ARMInstrNEON.td"