1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
153 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
154 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
155 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
156 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
157 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
158 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
159 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
160 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
162 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
164 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
166 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
167 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
168 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
169 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
170 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
171 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
172 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
173 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
175 // FIXME: Eventually this will be just "hasV6T2Ops".
176 def UseMovt : Predicate<"Subtarget->useMovt()">;
177 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
178 def UseVMLx : Predicate<"Subtarget->useVMLx()">;
180 //===----------------------------------------------------------------------===//
181 // ARM Flag Definitions.
183 class RegConstraint<string C> {
184 string Constraints = C;
187 //===----------------------------------------------------------------------===//
188 // ARM specific transformation functions and pattern fragments.
191 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
192 // so_imm_neg def below.
193 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
194 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
197 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
198 // so_imm_not def below.
199 def so_imm_not_XFORM : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
203 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
204 def imm1_15 : PatLeaf<(i32 imm), [{
205 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
208 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
209 def imm16_31 : PatLeaf<(i32 imm), [{
210 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
215 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
216 }], so_imm_neg_XFORM>;
220 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
221 }], so_imm_not_XFORM>;
223 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
224 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
225 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
228 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
230 def bf_inv_mask_imm : Operand<i32>,
232 return ARM::isBitFieldInvertedMask(N->getZExtValue());
234 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
235 let PrintMethod = "printBitfieldInvMaskImmOperand";
238 /// Split a 32-bit immediate into two 16 bit parts.
239 def hi16 : SDNodeXForm<imm, [{
240 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
243 def lo16AllZero : PatLeaf<(i32 imm), [{
244 // Returns true if all low 16-bits are 0.
245 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
248 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
250 def imm0_65535 : PatLeaf<(i32 imm), [{
251 return (uint32_t)N->getZExtValue() < 65536;
254 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
255 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
257 /// adde and sube predicates - True based on whether the carry flag output
258 /// will be needed or not.
259 def adde_dead_carry :
260 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
261 [{return !N->hasAnyUseOfValue(1);}]>;
262 def sube_dead_carry :
263 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
264 [{return !N->hasAnyUseOfValue(1);}]>;
265 def adde_live_carry :
266 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
267 [{return N->hasAnyUseOfValue(1);}]>;
268 def sube_live_carry :
269 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
270 [{return N->hasAnyUseOfValue(1);}]>;
272 // An 'and' node with a single use.
273 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
274 return N->hasOneUse();
277 // An 'xor' node with a single use.
278 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
279 return N->hasOneUse();
282 //===----------------------------------------------------------------------===//
283 // Operand Definitions.
287 def brtarget : Operand<OtherVT> {
288 let EncoderMethod = "getBranchTargetOpValue";
292 def bltarget : Operand<i32> {
293 // Encoded the same as branch targets.
294 let EncoderMethod = "getBranchTargetOpValue";
297 // A list of registers separated by comma. Used by load/store multiple.
298 def RegListAsmOperand : AsmOperandClass {
299 let Name = "RegList";
300 let SuperClasses = [];
303 def DPRRegListAsmOperand : AsmOperandClass {
304 let Name = "DPRRegList";
305 let SuperClasses = [];
308 def SPRRegListAsmOperand : AsmOperandClass {
309 let Name = "SPRRegList";
310 let SuperClasses = [];
313 def reglist : Operand<i32> {
314 let EncoderMethod = "getRegisterListOpValue";
315 let ParserMatchClass = RegListAsmOperand;
316 let PrintMethod = "printRegisterList";
319 def dpr_reglist : Operand<i32> {
320 let EncoderMethod = "getRegisterListOpValue";
321 let ParserMatchClass = DPRRegListAsmOperand;
322 let PrintMethod = "printRegisterList";
325 def spr_reglist : Operand<i32> {
326 let EncoderMethod = "getRegisterListOpValue";
327 let ParserMatchClass = SPRRegListAsmOperand;
328 let PrintMethod = "printRegisterList";
331 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
332 def cpinst_operand : Operand<i32> {
333 let PrintMethod = "printCPInstOperand";
336 def jtblock_operand : Operand<i32> {
337 let PrintMethod = "printJTBlockOperand";
339 def jt2block_operand : Operand<i32> {
340 let PrintMethod = "printJT2BlockOperand";
344 def pclabel : Operand<i32> {
345 let PrintMethod = "printPCLabel";
348 def neon_vcvt_imm32 : Operand<i32> {
349 let EncoderMethod = "getNEONVcvtImm32OpValue";
352 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
353 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
354 int32_t v = (int32_t)N->getZExtValue();
355 return v == 8 || v == 16 || v == 24; }]> {
356 let EncoderMethod = "getRotImmOpValue";
359 // shift_imm: An integer that encodes a shift amount and the type of shift
360 // (currently either asr or lsl) using the same encoding used for the
361 // immediates in so_reg operands.
362 def shift_imm : Operand<i32> {
363 let PrintMethod = "printShiftImmOperand";
366 // shifter_operand operands: so_reg and so_imm.
367 def so_reg : Operand<i32>, // reg reg imm
368 ComplexPattern<i32, 3, "SelectShifterOperandReg",
369 [shl,srl,sra,rotr]> {
370 let EncoderMethod = "getSORegOpValue";
371 let PrintMethod = "printSORegOperand";
372 let MIOperandInfo = (ops GPR, GPR, i32imm);
374 def shift_so_reg : Operand<i32>, // reg reg imm
375 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
376 [shl,srl,sra,rotr]> {
377 let EncoderMethod = "getSORegOpValue";
378 let PrintMethod = "printSORegOperand";
379 let MIOperandInfo = (ops GPR, GPR, i32imm);
382 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
383 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
384 // represented in the imm field in the same 12-bit form that they are encoded
385 // into so_imm instructions: the 8-bit immediate is the least significant bits
386 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
387 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
388 let EncoderMethod = "getSOImmOpValue";
389 let PrintMethod = "printSOImmOperand";
392 // Break so_imm's up into two pieces. This handles immediates with up to 16
393 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
394 // get the first/second pieces.
395 def so_imm2part : PatLeaf<(imm), [{
396 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
399 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
401 def arm_i32imm : PatLeaf<(imm), [{
402 if (Subtarget->hasV6T2Ops())
404 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
407 def so_imm2part_1 : SDNodeXForm<imm, [{
408 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
409 return CurDAG->getTargetConstant(V, MVT::i32);
412 def so_imm2part_2 : SDNodeXForm<imm, [{
413 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
414 return CurDAG->getTargetConstant(V, MVT::i32);
417 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
418 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
420 let PrintMethod = "printSOImm2PartOperand";
423 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
424 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
425 return CurDAG->getTargetConstant(V, MVT::i32);
428 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
429 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
430 return CurDAG->getTargetConstant(V, MVT::i32);
433 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
434 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
435 return (int32_t)N->getZExtValue() < 32;
438 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
439 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
440 return (int32_t)N->getZExtValue() < 32;
442 let EncoderMethod = "getImmMinusOneOpValue";
445 // For movt/movw - sets the MC Encoder method.
446 // The imm is split into imm{15-12}, imm{11-0}
448 def movt_imm : Operand<i32> {
449 let EncoderMethod = "getMovtImmOpValue";
452 // Define ARM specific addressing modes.
455 // addrmode_imm12 := reg +/- imm12
457 def addrmode_imm12 : Operand<i32>,
458 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
459 // 12-bit immediate operand. Note that instructions using this encode
460 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
461 // immediate values are as normal.
463 let EncoderMethod = "getAddrModeImm12OpValue";
464 let PrintMethod = "printAddrModeImm12Operand";
465 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
467 // ldst_so_reg := reg +/- reg shop imm
469 def ldst_so_reg : Operand<i32>,
470 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
471 let EncoderMethod = "getLdStSORegOpValue";
472 // FIXME: Simplify the printer
473 let PrintMethod = "printAddrMode2Operand";
474 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
477 // addrmode2 := reg +/- imm12
478 // := reg +/- reg shop imm
480 def addrmode2 : Operand<i32>,
481 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
482 string EncoderMethod = "getAddrMode2OpValue";
483 let PrintMethod = "printAddrMode2Operand";
484 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
487 def am2offset : Operand<i32>,
488 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
489 [], [SDNPWantRoot]> {
490 string EncoderMethod = "getAddrMode2OffsetOpValue";
491 let PrintMethod = "printAddrMode2OffsetOperand";
492 let MIOperandInfo = (ops GPR, i32imm);
495 // addrmode3 := reg +/- reg
496 // addrmode3 := reg +/- imm8
498 def addrmode3 : Operand<i32>,
499 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
500 let EncoderMethod = "getAddrMode3OpValue";
501 let PrintMethod = "printAddrMode3Operand";
502 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
505 def am3offset : Operand<i32>,
506 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
507 [], [SDNPWantRoot]> {
508 let EncoderMethod = "getAddrMode3OffsetOpValue";
509 let PrintMethod = "printAddrMode3OffsetOperand";
510 let MIOperandInfo = (ops GPR, i32imm);
513 // ldstm_mode := {ia, ib, da, db}
515 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
516 let EncoderMethod = "getLdStmModeOpValue";
517 let PrintMethod = "printLdStmModeOperand";
520 def MemMode5AsmOperand : AsmOperandClass {
521 let Name = "MemMode5";
522 let SuperClasses = [];
525 // addrmode5 := reg +/- imm8*4
527 def addrmode5 : Operand<i32>,
528 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
529 let PrintMethod = "printAddrMode5Operand";
530 let MIOperandInfo = (ops GPR:$base, i32imm);
531 let ParserMatchClass = MemMode5AsmOperand;
532 let EncoderMethod = "getAddrMode5OpValue";
535 // addrmode6 := reg with optional writeback
537 def addrmode6 : Operand<i32>,
538 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
539 let PrintMethod = "printAddrMode6Operand";
540 let MIOperandInfo = (ops GPR:$addr, i32imm);
541 let EncoderMethod = "getAddrMode6AddressOpValue";
544 def am6offset : Operand<i32> {
545 let PrintMethod = "printAddrMode6OffsetOperand";
546 let MIOperandInfo = (ops GPR);
547 let EncoderMethod = "getAddrMode6OffsetOpValue";
550 // addrmodepc := pc + reg
552 def addrmodepc : Operand<i32>,
553 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
554 let PrintMethod = "printAddrModePCOperand";
555 let MIOperandInfo = (ops GPR, i32imm);
558 def nohash_imm : Operand<i32> {
559 let PrintMethod = "printNoHashImmediate";
562 //===----------------------------------------------------------------------===//
564 include "ARMInstrFormats.td"
566 //===----------------------------------------------------------------------===//
567 // Multiclass helpers...
570 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
571 /// binop that produces a value.
572 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
573 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
574 PatFrag opnode, bit Commutable = 0> {
575 // The register-immediate version is re-materializable. This is useful
576 // in particular for taking the address of a local.
577 let isReMaterializable = 1 in {
578 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
579 iii, opc, "\t$Rd, $Rn, $imm",
580 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
585 let Inst{19-16} = Rn;
586 let Inst{15-12} = Rd;
587 let Inst{11-0} = imm;
590 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
591 iir, opc, "\t$Rd, $Rn, $Rm",
592 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
597 let isCommutable = Commutable;
598 let Inst{19-16} = Rn;
599 let Inst{15-12} = Rd;
600 let Inst{11-4} = 0b00000000;
603 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
604 iis, opc, "\t$Rd, $Rn, $shift",
605 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
610 let Inst{19-16} = Rn;
611 let Inst{15-12} = Rd;
612 let Inst{11-0} = shift;
616 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
617 /// instruction modifies the CPSR register.
618 let Defs = [CPSR] in {
619 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
620 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
621 PatFrag opnode, bit Commutable = 0> {
622 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
623 iii, opc, "\t$Rd, $Rn, $imm",
624 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
630 let Inst{19-16} = Rn;
631 let Inst{15-12} = Rd;
632 let Inst{11-0} = imm;
634 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
635 iir, opc, "\t$Rd, $Rn, $Rm",
636 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
640 let isCommutable = Commutable;
643 let Inst{19-16} = Rn;
644 let Inst{15-12} = Rd;
645 let Inst{11-4} = 0b00000000;
648 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
649 iis, opc, "\t$Rd, $Rn, $shift",
650 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
656 let Inst{19-16} = Rn;
657 let Inst{15-12} = Rd;
658 let Inst{11-0} = shift;
663 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
664 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
665 /// a explicit result, only implicitly set CPSR.
666 let isCompare = 1, Defs = [CPSR] in {
667 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
668 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
669 PatFrag opnode, bit Commutable = 0> {
670 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
672 [(opnode GPR:$Rn, so_imm:$imm)]> {
677 let Inst{19-16} = Rn;
678 let Inst{15-12} = 0b0000;
679 let Inst{11-0} = imm;
681 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
683 [(opnode GPR:$Rn, GPR:$Rm)]> {
686 let isCommutable = Commutable;
689 let Inst{19-16} = Rn;
690 let Inst{15-12} = 0b0000;
691 let Inst{11-4} = 0b00000000;
694 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
695 opc, "\t$Rn, $shift",
696 [(opnode GPR:$Rn, so_reg:$shift)]> {
701 let Inst{19-16} = Rn;
702 let Inst{15-12} = 0b0000;
703 let Inst{11-0} = shift;
708 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
709 /// register and one whose operand is a register rotated by 8/16/24.
710 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
711 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
712 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
713 IIC_iEXTr, opc, "\t$Rd, $Rm",
714 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
715 Requires<[IsARM, HasV6]> {
718 let Inst{19-16} = 0b1111;
719 let Inst{15-12} = Rd;
720 let Inst{11-10} = 0b00;
723 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
724 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
725 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
726 Requires<[IsARM, HasV6]> {
730 let Inst{19-16} = 0b1111;
731 let Inst{15-12} = Rd;
732 let Inst{11-10} = rot;
737 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
738 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
739 IIC_iEXTr, opc, "\t$Rd, $Rm",
740 [/* For disassembly only; pattern left blank */]>,
741 Requires<[IsARM, HasV6]> {
742 let Inst{19-16} = 0b1111;
743 let Inst{11-10} = 0b00;
745 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
746 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
747 [/* For disassembly only; pattern left blank */]>,
748 Requires<[IsARM, HasV6]> {
750 let Inst{19-16} = 0b1111;
751 let Inst{11-10} = rot;
755 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
756 /// register and one whose operand is a register rotated by 8/16/24.
757 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
758 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
759 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
760 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
761 Requires<[IsARM, HasV6]> {
765 let Inst{19-16} = Rn;
766 let Inst{15-12} = Rd;
767 let Inst{11-10} = 0b00;
768 let Inst{9-4} = 0b000111;
771 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
773 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
774 [(set GPR:$Rd, (opnode GPR:$Rn,
775 (rotr GPR:$Rm, rot_imm:$rot)))]>,
776 Requires<[IsARM, HasV6]> {
781 let Inst{19-16} = Rn;
782 let Inst{15-12} = Rd;
783 let Inst{11-10} = rot;
784 let Inst{9-4} = 0b000111;
789 // For disassembly only.
790 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
791 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
792 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
793 [/* For disassembly only; pattern left blank */]>,
794 Requires<[IsARM, HasV6]> {
795 let Inst{11-10} = 0b00;
797 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
799 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
800 [/* For disassembly only; pattern left blank */]>,
801 Requires<[IsARM, HasV6]> {
804 let Inst{19-16} = Rn;
805 let Inst{11-10} = rot;
809 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
810 let Uses = [CPSR] in {
811 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
812 bit Commutable = 0> {
813 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
814 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
815 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
821 let Inst{15-12} = Rd;
822 let Inst{19-16} = Rn;
823 let Inst{11-0} = imm;
825 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
826 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
827 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
832 let Inst{11-4} = 0b00000000;
834 let isCommutable = Commutable;
836 let Inst{15-12} = Rd;
837 let Inst{19-16} = Rn;
839 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
840 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
841 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
847 let Inst{11-0} = shift;
848 let Inst{15-12} = Rd;
849 let Inst{19-16} = Rn;
852 // Carry setting variants
853 let Defs = [CPSR] in {
854 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
855 bit Commutable = 0> {
856 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
857 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
858 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
863 let Inst{15-12} = Rd;
864 let Inst{19-16} = Rn;
865 let Inst{11-0} = imm;
869 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
870 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
871 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
876 let Inst{11-4} = 0b00000000;
877 let isCommutable = Commutable;
879 let Inst{15-12} = Rd;
880 let Inst{19-16} = Rn;
884 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
885 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
886 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
891 let Inst{11-0} = shift;
892 let Inst{15-12} = Rd;
893 let Inst{19-16} = Rn;
901 let canFoldAsLoad = 1, isReMaterializable = 1 in {
902 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
903 InstrItinClass iir, PatFrag opnode> {
904 // Note: We use the complex addrmode_imm12 rather than just an input
905 // GPR and a constrained immediate so that we can use this to match
906 // frame index references and avoid matching constant pool references.
907 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
908 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
909 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
912 let Inst{23} = addr{12}; // U (add = ('U' == 1))
913 let Inst{19-16} = addr{16-13}; // Rn
914 let Inst{15-12} = Rt;
915 let Inst{11-0} = addr{11-0}; // imm12
917 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
918 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
919 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
922 let Inst{23} = shift{12}; // U (add = ('U' == 1))
923 let Inst{19-16} = shift{16-13}; // Rn
924 let Inst{15-12} = Rt;
925 let Inst{11-0} = shift{11-0};
930 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
931 InstrItinClass iir, PatFrag opnode> {
932 // Note: We use the complex addrmode_imm12 rather than just an input
933 // GPR and a constrained immediate so that we can use this to match
934 // frame index references and avoid matching constant pool references.
935 def i12 : AI2ldst<0b010, 0, isByte, (outs),
936 (ins GPR:$Rt, addrmode_imm12:$addr),
937 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
938 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
941 let Inst{23} = addr{12}; // U (add = ('U' == 1))
942 let Inst{19-16} = addr{16-13}; // Rn
943 let Inst{15-12} = Rt;
944 let Inst{11-0} = addr{11-0}; // imm12
946 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
947 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
948 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
951 let Inst{23} = shift{12}; // U (add = ('U' == 1))
952 let Inst{19-16} = shift{16-13}; // Rn
953 let Inst{15-12} = Rt;
954 let Inst{11-0} = shift{11-0};
957 //===----------------------------------------------------------------------===//
959 //===----------------------------------------------------------------------===//
961 //===----------------------------------------------------------------------===//
962 // Miscellaneous Instructions.
965 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
966 /// the function. The first operand is the ID# for this instruction, the second
967 /// is the index into the MachineConstantPool that this is, the third is the
968 /// size in bytes of this constant pool entry.
969 let neverHasSideEffects = 1, isNotDuplicable = 1 in
970 def CONSTPOOL_ENTRY :
971 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
972 i32imm:$size), NoItinerary, []>;
974 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
975 // from removing one half of the matched pairs. That breaks PEI, which assumes
976 // these will always be in pairs, and asserts if it finds otherwise. Better way?
977 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
979 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
980 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
982 def ADJCALLSTACKDOWN :
983 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
984 [(ARMcallseq_start timm:$amt)]>;
987 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
988 [/* For disassembly only; pattern left blank */]>,
989 Requires<[IsARM, HasV6T2]> {
990 let Inst{27-16} = 0b001100100000;
991 let Inst{15-8} = 0b11110000;
992 let Inst{7-0} = 0b00000000;
995 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
996 [/* For disassembly only; pattern left blank */]>,
997 Requires<[IsARM, HasV6T2]> {
998 let Inst{27-16} = 0b001100100000;
999 let Inst{15-8} = 0b11110000;
1000 let Inst{7-0} = 0b00000001;
1003 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1004 [/* For disassembly only; pattern left blank */]>,
1005 Requires<[IsARM, HasV6T2]> {
1006 let Inst{27-16} = 0b001100100000;
1007 let Inst{15-8} = 0b11110000;
1008 let Inst{7-0} = 0b00000010;
1011 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1012 [/* For disassembly only; pattern left blank */]>,
1013 Requires<[IsARM, HasV6T2]> {
1014 let Inst{27-16} = 0b001100100000;
1015 let Inst{15-8} = 0b11110000;
1016 let Inst{7-0} = 0b00000011;
1019 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1021 [/* For disassembly only; pattern left blank */]>,
1022 Requires<[IsARM, HasV6]> {
1027 let Inst{15-12} = Rd;
1028 let Inst{19-16} = Rn;
1029 let Inst{27-20} = 0b01101000;
1030 let Inst{7-4} = 0b1011;
1031 let Inst{11-8} = 0b1111;
1034 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1035 [/* For disassembly only; pattern left blank */]>,
1036 Requires<[IsARM, HasV6T2]> {
1037 let Inst{27-16} = 0b001100100000;
1038 let Inst{15-8} = 0b11110000;
1039 let Inst{7-0} = 0b00000100;
1042 // The i32imm operand $val can be used by a debugger to store more information
1043 // about the breakpoint.
1044 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1045 [/* For disassembly only; pattern left blank */]>,
1048 let Inst{3-0} = val{3-0};
1049 let Inst{19-8} = val{15-4};
1050 let Inst{27-20} = 0b00010010;
1051 let Inst{7-4} = 0b0111;
1054 // Change Processor State is a system instruction -- for disassembly only.
1055 // The singleton $opt operand contains the following information:
1056 // opt{4-0} = mode from Inst{4-0}
1057 // opt{5} = changemode from Inst{17}
1058 // opt{8-6} = AIF from Inst{8-6}
1059 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
1060 // FIXME: Integrated assembler will need these split out.
1061 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
1062 [/* For disassembly only; pattern left blank */]>,
1064 let Inst{31-28} = 0b1111;
1065 let Inst{27-20} = 0b00010000;
1070 // Preload signals the memory system of possible future data/instruction access.
1071 // These are for disassembly only.
1072 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1074 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1075 !strconcat(opc, "\t$addr"),
1076 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1079 let Inst{31-26} = 0b111101;
1080 let Inst{25} = 0; // 0 for immediate form
1081 let Inst{24} = data;
1082 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1083 let Inst{22} = read;
1084 let Inst{21-20} = 0b01;
1085 let Inst{19-16} = addr{16-13}; // Rn
1086 let Inst{15-12} = Rt;
1087 let Inst{11-0} = addr{11-0}; // imm12
1090 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1091 !strconcat(opc, "\t$shift"),
1092 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1095 let Inst{31-26} = 0b111101;
1096 let Inst{25} = 1; // 1 for register form
1097 let Inst{24} = data;
1098 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1099 let Inst{22} = read;
1100 let Inst{21-20} = 0b01;
1101 let Inst{19-16} = shift{16-13}; // Rn
1102 let Inst{11-0} = shift{11-0};
1106 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1107 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1108 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1110 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1112 [/* For disassembly only; pattern left blank */]>,
1115 let Inst{31-10} = 0b1111000100000001000000;
1120 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1121 [/* For disassembly only; pattern left blank */]>,
1122 Requires<[IsARM, HasV7]> {
1124 let Inst{27-4} = 0b001100100000111100001111;
1125 let Inst{3-0} = opt;
1128 // A5.4 Permanently UNDEFINED instructions.
1129 let isBarrier = 1, isTerminator = 1 in
1130 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1133 let Inst{27-25} = 0b011;
1134 let Inst{24-20} = 0b11111;
1135 let Inst{7-5} = 0b111;
1139 // Address computation and loads and stores in PIC mode.
1140 let isNotDuplicable = 1 in {
1141 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1143 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1145 let AddedComplexity = 10 in {
1146 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1148 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1150 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1152 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1154 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1156 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1158 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1160 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1162 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1164 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1166 let AddedComplexity = 10 in {
1167 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1168 IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1170 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1171 IIC_iStore_bh_r, [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1173 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1174 IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1176 } // isNotDuplicable = 1
1179 // LEApcrel - Load a pc-relative address into a register without offending the
1181 let neverHasSideEffects = 1 in {
1182 let isReMaterializable = 1 in
1183 // FIXME: We want one cannonical LEApcrel instruction and to express one or
1184 // both of these as pseudo-instructions that get expanded to it.
1185 def LEApcrel : AXI1<0, (outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1187 "adr$p\t$Rd, #$label", []>;
1189 } // neverHasSideEffects
1190 def LEApcrelJT : AXI1<0b0100, (outs GPR:$Rd),
1191 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1193 "adr$p\t$Rd, #${label}_${id}", []> {
1196 let Inst{31-28} = p;
1197 let Inst{27-25} = 0b001;
1199 let Inst{19-16} = 0b1111;
1200 let Inst{15-12} = Rd;
1201 // FIXME: Add label encoding/fixup
1204 //===----------------------------------------------------------------------===//
1205 // Control Flow Instructions.
1208 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1210 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1211 "bx", "\tlr", [(ARMretflag)]>,
1212 Requires<[IsARM, HasV4T]> {
1213 let Inst{27-0} = 0b0001001011111111111100011110;
1217 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1218 "mov", "\tpc, lr", [(ARMretflag)]>,
1219 Requires<[IsARM, NoV4T]> {
1220 let Inst{27-0} = 0b0001101000001111000000001110;
1224 // Indirect branches
1225 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1227 def BRIND : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1228 [(brind GPR:$dst)]>,
1229 Requires<[IsARM, HasV4T]> {
1231 let Inst{31-4} = 0b1110000100101111111111110001;
1232 let Inst{3-0} = dst;
1236 def MOVPCRX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "mov\tpc, $dst",
1237 [(brind GPR:$dst)]>,
1238 Requires<[IsARM, NoV4T]> {
1240 let Inst{31-4} = 0b1110000110100000111100000000;
1241 let Inst{3-0} = dst;
1245 // On non-Darwin platforms R9 is callee-saved.
1247 Defs = [R0, R1, R2, R3, R12, LR,
1248 D0, D1, D2, D3, D4, D5, D6, D7,
1249 D16, D17, D18, D19, D20, D21, D22, D23,
1250 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1251 def BL : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1252 IIC_Br, "bl\t$func",
1253 [(ARMcall tglobaladdr:$func)]>,
1254 Requires<[IsARM, IsNotDarwin]> {
1255 let Inst{31-28} = 0b1110;
1257 let Inst{23-0} = func;
1260 def BL_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1261 IIC_Br, "bl", "\t$func",
1262 [(ARMcall_pred tglobaladdr:$func)]>,
1263 Requires<[IsARM, IsNotDarwin]> {
1265 let Inst{23-0} = func;
1269 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1270 IIC_Br, "blx\t$func",
1271 [(ARMcall GPR:$func)]>,
1272 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1274 let Inst{31-4} = 0b1110000100101111111111110011;
1275 let Inst{3-0} = func;
1279 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1280 // FIXME: x2 insn patterns like this need to be pseudo instructions.
1281 def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1282 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1283 [(ARMcall_nolink tGPR:$func)]>,
1284 Requires<[IsARM, HasV4T, IsNotDarwin]> {
1286 let Inst{27-4} = 0b000100101111111111110001;
1287 let Inst{3-0} = func;
1291 def BMOVPCRX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1292 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1293 [(ARMcall_nolink tGPR:$func)]>,
1294 Requires<[IsARM, NoV4T, IsNotDarwin]> {
1296 let Inst{27-4} = 0b000110100000111100000000;
1297 let Inst{3-0} = func;
1301 // On Darwin R9 is call-clobbered.
1303 Defs = [R0, R1, R2, R3, R9, R12, LR,
1304 D0, D1, D2, D3, D4, D5, D6, D7,
1305 D16, D17, D18, D19, D20, D21, D22, D23,
1306 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
1307 def BLr9 : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1308 IIC_Br, "bl\t$func",
1309 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1310 let Inst{31-28} = 0b1110;
1312 let Inst{23-0} = func;
1315 def BLr9_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1316 IIC_Br, "bl", "\t$func",
1317 [(ARMcall_pred tglobaladdr:$func)]>,
1318 Requires<[IsARM, IsDarwin]> {
1320 let Inst{23-0} = func;
1324 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1325 IIC_Br, "blx\t$func",
1326 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1328 let Inst{31-4} = 0b1110000100101111111111110011;
1329 let Inst{3-0} = func;
1333 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1334 def BXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1335 IIC_Br, "mov\tlr, pc\n\tbx\t$func",
1336 [(ARMcall_nolink tGPR:$func)]>,
1337 Requires<[IsARM, HasV4T, IsDarwin]> {
1339 let Inst{27-4} = 0b000100101111111111110001;
1340 let Inst{3-0} = func;
1344 def BMOVPCRXr9 : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
1345 IIC_Br, "mov\tlr, pc\n\tmov\tpc, $func",
1346 [(ARMcall_nolink tGPR:$func)]>,
1347 Requires<[IsARM, NoV4T, IsDarwin]> {
1349 let Inst{27-4} = 0b000110100000111100000000;
1350 let Inst{3-0} = func;
1356 // FIXME: These should probably be xformed into the non-TC versions of the
1357 // instructions as part of MC lowering.
1358 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1360 let Defs = [R0, R1, R2, R3, R9, R12,
1361 D0, D1, D2, D3, D4, D5, D6, D7,
1362 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1363 D27, D28, D29, D30, D31, PC],
1365 def TCRETURNdi : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1367 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1369 def TCRETURNri : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1371 "@TC_RETURN","\t$dst", []>, Requires<[IsDarwin]>;
1373 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1374 IIC_Br, "b\t$dst @ TAILCALL",
1375 []>, Requires<[IsDarwin]>;
1377 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1378 IIC_Br, "b.w\t$dst @ TAILCALL",
1379 []>, Requires<[IsDarwin]>;
1381 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1382 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1383 []>, Requires<[IsDarwin]> {
1385 let Inst{31-4} = 0b1110000100101111111111110001;
1386 let Inst{3-0} = dst;
1390 // Non-Darwin versions (the difference is R9).
1391 let Defs = [R0, R1, R2, R3, R12,
1392 D0, D1, D2, D3, D4, D5, D6, D7,
1393 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1394 D27, D28, D29, D30, D31, PC],
1396 def TCRETURNdiND : AInoP<(outs), (ins i32imm:$dst, variable_ops),
1398 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1400 def TCRETURNriND : AInoP<(outs), (ins tcGPR:$dst, variable_ops),
1402 "@TC_RETURN","\t$dst", []>, Requires<[IsNotDarwin]>;
1404 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1405 IIC_Br, "b\t$dst @ TAILCALL",
1406 []>, Requires<[IsARM, IsNotDarwin]>;
1408 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1409 IIC_Br, "b.w\t$dst @ TAILCALL",
1410 []>, Requires<[IsThumb, IsNotDarwin]>;
1412 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1413 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1414 []>, Requires<[IsNotDarwin]> {
1416 let Inst{31-4} = 0b1110000100101111111111110001;
1417 let Inst{3-0} = dst;
1422 let isBranch = 1, isTerminator = 1 in {
1423 // B is "predicable" since it can be xformed into a Bcc.
1424 let isBarrier = 1 in {
1425 let isPredicable = 1 in
1426 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1427 "b\t$target", [(br bb:$target)]> {
1429 let Inst{31-28} = 0b1110;
1430 let Inst{23-0} = target;
1433 let isNotDuplicable = 1, isIndirectBranch = 1,
1434 // FIXME: $imm field is not specified by asm string. Mark as cgonly.
1435 isCodeGenOnly = 1 in {
1436 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
1437 IIC_Br, "mov\tpc, $target$jt",
1438 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
1439 let Inst{11-4} = 0b00000000;
1440 let Inst{15-12} = 0b1111;
1441 let Inst{20} = 0; // S Bit
1442 let Inst{24-21} = 0b1101;
1443 let Inst{27-25} = 0b000;
1445 def BR_JTm : JTI<(outs),
1446 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
1447 IIC_Br, "ldr\tpc, $target$jt",
1448 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1450 let Inst{15-12} = 0b1111;
1451 let Inst{20} = 1; // L bit
1452 let Inst{21} = 0; // W bit
1453 let Inst{22} = 0; // B bit
1454 let Inst{24} = 1; // P bit
1455 let Inst{27-25} = 0b011;
1457 def BR_JTadd : ARMPseudoInst<(outs),
1458 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
1460 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1462 } // isNotDuplicable = 1, isIndirectBranch = 1
1465 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1466 // a two-value operand where a dag node expects two operands. :(
1467 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1468 IIC_Br, "b", "\t$target",
1469 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1471 let Inst{23-0} = target;
1475 // Branch and Exchange Jazelle -- for disassembly only
1476 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1477 [/* For disassembly only; pattern left blank */]> {
1478 let Inst{23-20} = 0b0010;
1479 //let Inst{19-8} = 0xfff;
1480 let Inst{7-4} = 0b0010;
1483 // Secure Monitor Call is a system instruction -- for disassembly only
1484 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1485 [/* For disassembly only; pattern left blank */]> {
1487 let Inst{23-4} = 0b01100000000000000111;
1488 let Inst{3-0} = opt;
1491 // Supervisor Call (Software Interrupt) -- for disassembly only
1493 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1494 [/* For disassembly only; pattern left blank */]> {
1496 let Inst{23-0} = svc;
1500 // Store Return State is a system instruction -- for disassembly only
1501 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1502 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1503 NoItinerary, "srs${amode}\tsp!, $mode",
1504 [/* For disassembly only; pattern left blank */]> {
1505 let Inst{31-28} = 0b1111;
1506 let Inst{22-20} = 0b110; // W = 1
1509 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1510 NoItinerary, "srs${amode}\tsp, $mode",
1511 [/* For disassembly only; pattern left blank */]> {
1512 let Inst{31-28} = 0b1111;
1513 let Inst{22-20} = 0b100; // W = 0
1516 // Return From Exception is a system instruction -- for disassembly only
1517 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1518 NoItinerary, "rfe${amode}\t$base!",
1519 [/* For disassembly only; pattern left blank */]> {
1520 let Inst{31-28} = 0b1111;
1521 let Inst{22-20} = 0b011; // W = 1
1524 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1525 NoItinerary, "rfe${amode}\t$base",
1526 [/* For disassembly only; pattern left blank */]> {
1527 let Inst{31-28} = 0b1111;
1528 let Inst{22-20} = 0b001; // W = 0
1530 } // isCodeGenOnly = 1
1532 //===----------------------------------------------------------------------===//
1533 // Load / store Instructions.
1539 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1540 UnOpFrag<(load node:$Src)>>;
1541 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1542 UnOpFrag<(zextloadi8 node:$Src)>>;
1543 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1544 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1545 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1546 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1548 // Special LDR for loads from non-pc-relative constpools.
1549 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1550 isReMaterializable = 1 in
1551 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1552 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1556 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1557 let Inst{19-16} = 0b1111;
1558 let Inst{15-12} = Rt;
1559 let Inst{11-0} = addr{11-0}; // imm12
1562 // Loads with zero extension
1563 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1564 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1565 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1567 // Loads with sign extension
1568 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1569 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1570 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1572 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1573 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1574 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1576 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1577 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1578 // FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1)
1579 // how to represent that such that tblgen is happy and we don't
1580 // mark this codegen only?
1582 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1583 (ins addrmode3:$addr), LdMiscFrm,
1584 IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
1585 []>, Requires<[IsARM, HasV5TE]>;
1589 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1590 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1591 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1592 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1594 // {13} 1 == Rm, 0 == imm12
1598 let Inst{25} = addr{13};
1599 let Inst{23} = addr{12};
1600 let Inst{19-16} = addr{17-14};
1601 let Inst{11-0} = addr{11-0};
1603 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1604 (ins GPR:$Rn, am2offset:$offset),
1605 IndexModePost, LdFrm, itin,
1606 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1607 // {13} 1 == Rm, 0 == imm12
1612 let Inst{25} = offset{13};
1613 let Inst{23} = offset{12};
1614 let Inst{19-16} = Rn;
1615 let Inst{11-0} = offset{11-0};
1619 let mayLoad = 1, neverHasSideEffects = 1 in {
1620 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1621 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1624 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1625 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1626 (ins addrmode3:$addr), IndexModePre,
1628 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1630 let Inst{23} = addr{8}; // U bit
1631 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1632 let Inst{19-16} = addr{12-9}; // Rn
1633 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1634 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1636 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1637 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1639 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1642 let Inst{23} = offset{8}; // U bit
1643 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1644 let Inst{19-16} = Rn;
1645 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1646 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1650 let mayLoad = 1, neverHasSideEffects = 1 in {
1651 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1652 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1653 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1654 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1655 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1656 } // mayLoad = 1, neverHasSideEffects = 1
1658 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1659 let mayLoad = 1, neverHasSideEffects = 1 in {
1660 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1661 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1662 LdFrm, IIC_iLoad_ru,
1663 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1664 let Inst{21} = 1; // overwrite
1666 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1667 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1668 LdFrm, IIC_iLoad_bh_ru,
1669 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1670 let Inst{21} = 1; // overwrite
1672 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1673 (ins GPR:$base, am3offset:$offset), IndexModePost,
1674 LdMiscFrm, IIC_iLoad_bh_ru,
1675 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1676 let Inst{21} = 1; // overwrite
1678 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1679 (ins GPR:$base, am3offset:$offset), IndexModePost,
1680 LdMiscFrm, IIC_iLoad_bh_ru,
1681 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1682 let Inst{21} = 1; // overwrite
1684 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1685 (ins GPR:$base, am3offset:$offset), IndexModePost,
1686 LdMiscFrm, IIC_iLoad_bh_ru,
1687 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1688 let Inst{21} = 1; // overwrite
1694 // Stores with truncate
1695 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1696 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1697 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1700 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1701 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1702 def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1703 StMiscFrm, IIC_iStore_d_r,
1704 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1707 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1708 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1709 IndexModePre, StFrm, IIC_iStore_ru,
1710 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1712 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1714 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1715 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1716 IndexModePost, StFrm, IIC_iStore_ru,
1717 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1719 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1721 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1722 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1723 IndexModePre, StFrm, IIC_iStore_bh_ru,
1724 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1725 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1726 GPR:$Rn, am2offset:$offset))]>;
1727 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1728 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1729 IndexModePost, StFrm, IIC_iStore_bh_ru,
1730 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1731 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1732 GPR:$Rn, am2offset:$offset))]>;
1734 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
1735 (ins GPR:$src, GPR:$base,am3offset:$offset),
1736 StMiscFrm, IIC_iStore_ru,
1737 "strh", "\t$src, [$base, $offset]!", "$base = $base_wb",
1739 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
1741 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
1742 (ins GPR:$src, GPR:$base,am3offset:$offset),
1743 StMiscFrm, IIC_iStore_bh_ru,
1744 "strh", "\t$src, [$base], $offset", "$base = $base_wb",
1745 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
1746 GPR:$base, am3offset:$offset))]>;
1748 // For disassembly only
1749 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1750 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1751 StMiscFrm, IIC_iStore_d_ru,
1752 "strd", "\t$src1, $src2, [$base, $offset]!",
1753 "$base = $base_wb", []>;
1755 // For disassembly only
1756 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1757 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1758 StMiscFrm, IIC_iStore_d_ru,
1759 "strd", "\t$src1, $src2, [$base], $offset",
1760 "$base = $base_wb", []>;
1762 // STRT, STRBT, and STRHT are for disassembly only.
1764 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1765 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
1766 IndexModeNone, StFrm, IIC_iStore_ru,
1767 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1768 [/* For disassembly only; pattern left blank */]> {
1769 let Inst{21} = 1; // overwrite
1772 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1773 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1774 IndexModeNone, StFrm, IIC_iStore_bh_ru,
1775 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1776 [/* For disassembly only; pattern left blank */]> {
1777 let Inst{21} = 1; // overwrite
1780 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1781 (ins GPR:$src, GPR:$base,am3offset:$offset),
1782 StMiscFrm, IIC_iStore_bh_ru,
1783 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1784 [/* For disassembly only; pattern left blank */]> {
1785 let Inst{21} = 1; // overwrite
1788 //===----------------------------------------------------------------------===//
1789 // Load / store multiple Instructions.
1792 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1793 InstrItinClass itin, InstrItinClass itin_upd> {
1795 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1796 IndexModeNone, f, itin,
1797 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1798 let Inst{24-23} = 0b01; // Increment After
1799 let Inst{21} = 0; // No writeback
1800 let Inst{20} = L_bit;
1803 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1804 IndexModeUpd, f, itin_upd,
1805 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1806 let Inst{24-23} = 0b01; // Increment After
1807 let Inst{21} = 1; // Writeback
1808 let Inst{20} = L_bit;
1811 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1812 IndexModeNone, f, itin,
1813 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1814 let Inst{24-23} = 0b00; // Decrement After
1815 let Inst{21} = 0; // No writeback
1816 let Inst{20} = L_bit;
1819 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1820 IndexModeUpd, f, itin_upd,
1821 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1822 let Inst{24-23} = 0b00; // Decrement After
1823 let Inst{21} = 1; // Writeback
1824 let Inst{20} = L_bit;
1827 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1828 IndexModeNone, f, itin,
1829 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1830 let Inst{24-23} = 0b10; // Decrement Before
1831 let Inst{21} = 0; // No writeback
1832 let Inst{20} = L_bit;
1835 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1836 IndexModeUpd, f, itin_upd,
1837 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1838 let Inst{24-23} = 0b10; // Decrement Before
1839 let Inst{21} = 1; // Writeback
1840 let Inst{20} = L_bit;
1843 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1844 IndexModeNone, f, itin,
1845 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1846 let Inst{24-23} = 0b11; // Increment Before
1847 let Inst{21} = 0; // No writeback
1848 let Inst{20} = L_bit;
1851 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1852 IndexModeUpd, f, itin_upd,
1853 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1854 let Inst{24-23} = 0b11; // Increment Before
1855 let Inst{21} = 1; // Writeback
1856 let Inst{20} = L_bit;
1860 let neverHasSideEffects = 1 in {
1862 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1863 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1865 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1866 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1868 } // neverHasSideEffects
1870 // Load / Store Multiple Mnemnoic Aliases
1871 def : MnemonicAlias<"ldm", "ldmia">;
1872 def : MnemonicAlias<"stm", "stmia">;
1874 // FIXME: remove when we have a way to marking a MI with these properties.
1875 // FIXME: Should pc be an implicit operand like PICADD, etc?
1876 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1877 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1878 def LDMIA_RET : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1879 reglist:$regs, variable_ops),
1880 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1881 "ldmia${p}\t$Rn!, $regs",
1883 let Inst{24-23} = 0b01; // Increment After
1884 let Inst{21} = 1; // Writeback
1885 let Inst{20} = 1; // Load
1888 //===----------------------------------------------------------------------===//
1889 // Move Instructions.
1892 let neverHasSideEffects = 1 in
1893 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1894 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1898 let Inst{11-4} = 0b00000000;
1901 let Inst{15-12} = Rd;
1904 // A version for the smaller set of tail call registers.
1905 let neverHasSideEffects = 1 in
1906 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1907 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1911 let Inst{11-4} = 0b00000000;
1914 let Inst{15-12} = Rd;
1917 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1918 DPSoRegFrm, IIC_iMOVsr,
1919 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1923 let Inst{15-12} = Rd;
1924 let Inst{11-0} = src;
1928 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1929 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1930 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1934 let Inst{15-12} = Rd;
1935 let Inst{19-16} = 0b0000;
1936 let Inst{11-0} = imm;
1939 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1940 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins movt_imm:$imm),
1942 "movw", "\t$Rd, $imm",
1943 [(set GPR:$Rd, imm0_65535:$imm)]>,
1944 Requires<[IsARM, HasV6T2]>, UnaryDP {
1947 let Inst{15-12} = Rd;
1948 let Inst{11-0} = imm{11-0};
1949 let Inst{19-16} = imm{15-12};
1954 let Constraints = "$src = $Rd" in
1955 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, movt_imm:$imm),
1957 "movt", "\t$Rd, $imm",
1959 (or (and GPR:$src, 0xffff),
1960 lo16AllZero:$imm))]>, UnaryDP,
1961 Requires<[IsARM, HasV6T2]> {
1964 let Inst{15-12} = Rd;
1965 let Inst{11-0} = imm{11-0};
1966 let Inst{19-16} = imm{15-12};
1971 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1972 Requires<[IsARM, HasV6T2]>;
1974 let Uses = [CPSR] in
1975 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
1976 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1979 // These aren't really mov instructions, but we have to define them this way
1980 // due to flag operands.
1982 let Defs = [CPSR] in {
1983 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1984 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1986 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1987 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1991 //===----------------------------------------------------------------------===//
1992 // Extend Instructions.
1997 defm SXTB : AI_ext_rrot<0b01101010,
1998 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1999 defm SXTH : AI_ext_rrot<0b01101011,
2000 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2002 defm SXTAB : AI_exta_rrot<0b01101010,
2003 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2004 defm SXTAH : AI_exta_rrot<0b01101011,
2005 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2007 // For disassembly only
2008 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2010 // For disassembly only
2011 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2015 let AddedComplexity = 16 in {
2016 defm UXTB : AI_ext_rrot<0b01101110,
2017 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2018 defm UXTH : AI_ext_rrot<0b01101111,
2019 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2020 defm UXTB16 : AI_ext_rrot<0b01101100,
2021 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2023 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2024 // The transformation should probably be done as a combiner action
2025 // instead so we can include a check for masking back in the upper
2026 // eight bits of the source into the lower eight bits of the result.
2027 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2028 // (UXTB16r_rot GPR:$Src, 24)>;
2029 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2030 (UXTB16r_rot GPR:$Src, 8)>;
2032 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2033 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2034 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2035 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2038 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2039 // For disassembly only
2040 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2043 def SBFX : I<(outs GPR:$Rd),
2044 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2045 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2046 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2047 Requires<[IsARM, HasV6T2]> {
2052 let Inst{27-21} = 0b0111101;
2053 let Inst{6-4} = 0b101;
2054 let Inst{20-16} = width;
2055 let Inst{15-12} = Rd;
2056 let Inst{11-7} = lsb;
2060 def UBFX : I<(outs GPR:$Rd),
2061 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2062 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2063 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2064 Requires<[IsARM, HasV6T2]> {
2069 let Inst{27-21} = 0b0111111;
2070 let Inst{6-4} = 0b101;
2071 let Inst{20-16} = width;
2072 let Inst{15-12} = Rd;
2073 let Inst{11-7} = lsb;
2077 //===----------------------------------------------------------------------===//
2078 // Arithmetic Instructions.
2081 defm ADD : AsI1_bin_irs<0b0100, "add",
2082 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2083 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2084 defm SUB : AsI1_bin_irs<0b0010, "sub",
2085 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2086 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2088 // ADD and SUB with 's' bit set.
2089 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2090 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2091 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2092 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2093 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2094 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2096 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2097 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2098 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2099 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2100 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2101 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2102 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2103 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2105 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2106 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2107 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2112 let Inst{15-12} = Rd;
2113 let Inst{19-16} = Rn;
2114 let Inst{11-0} = imm;
2117 // The reg/reg form is only defined for the disassembler; for codegen it is
2118 // equivalent to SUBrr.
2119 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2120 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2121 [/* For disassembly only; pattern left blank */]> {
2125 let Inst{11-4} = 0b00000000;
2128 let Inst{15-12} = Rd;
2129 let Inst{19-16} = Rn;
2132 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2133 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2134 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2139 let Inst{11-0} = shift;
2140 let Inst{15-12} = Rd;
2141 let Inst{19-16} = Rn;
2144 // RSB with 's' bit set.
2145 let Defs = [CPSR] in {
2146 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2147 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2148 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2154 let Inst{15-12} = Rd;
2155 let Inst{19-16} = Rn;
2156 let Inst{11-0} = imm;
2158 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2159 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2160 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2166 let Inst{11-0} = shift;
2167 let Inst{15-12} = Rd;
2168 let Inst{19-16} = Rn;
2172 let Uses = [CPSR] in {
2173 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2174 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2175 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2181 let Inst{15-12} = Rd;
2182 let Inst{19-16} = Rn;
2183 let Inst{11-0} = imm;
2185 // The reg/reg form is only defined for the disassembler; for codegen it is
2186 // equivalent to SUBrr.
2187 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2188 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2189 [/* For disassembly only; pattern left blank */]> {
2193 let Inst{11-4} = 0b00000000;
2196 let Inst{15-12} = Rd;
2197 let Inst{19-16} = Rn;
2199 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2200 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2201 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2207 let Inst{11-0} = shift;
2208 let Inst{15-12} = Rd;
2209 let Inst{19-16} = Rn;
2213 // FIXME: Allow these to be predicated.
2214 let Defs = [CPSR], Uses = [CPSR] in {
2215 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2216 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2217 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2224 let Inst{15-12} = Rd;
2225 let Inst{19-16} = Rn;
2226 let Inst{11-0} = imm;
2228 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2229 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2230 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2237 let Inst{11-0} = shift;
2238 let Inst{15-12} = Rd;
2239 let Inst{19-16} = Rn;
2243 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2244 // The assume-no-carry-in form uses the negation of the input since add/sub
2245 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2246 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2248 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2249 (SUBri GPR:$src, so_imm_neg:$imm)>;
2250 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2251 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2252 // The with-carry-in form matches bitwise not instead of the negation.
2253 // Effectively, the inverse interpretation of the carry flag already accounts
2254 // for part of the negation.
2255 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2256 (SBCri GPR:$src, so_imm_not:$imm)>;
2258 // Note: These are implemented in C++ code, because they have to generate
2259 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2261 // (mul X, 2^n+1) -> (add (X << n), X)
2262 // (mul X, 2^n-1) -> (rsb X, (X << n))
2264 // ARM Arithmetic Instruction -- for disassembly only
2265 // GPR:$dst = GPR:$a op GPR:$b
2266 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2267 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2268 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2269 opc, "\t$Rd, $Rn, $Rm", pattern> {
2273 let Inst{27-20} = op27_20;
2274 let Inst{11-4} = op11_4;
2275 let Inst{19-16} = Rn;
2276 let Inst{15-12} = Rd;
2280 // Saturating add/subtract -- for disassembly only
2282 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2283 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2284 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2285 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2286 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2287 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2289 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2290 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2291 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2292 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2293 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2294 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2295 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2296 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2297 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2298 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2299 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2300 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2302 // Signed/Unsigned add/subtract -- for disassembly only
2304 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2305 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2306 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2307 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2308 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2309 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2310 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2311 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2312 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2313 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2314 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2315 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2317 // Signed/Unsigned halving add/subtract -- for disassembly only
2319 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2320 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2321 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2322 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2323 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2324 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2325 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2326 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2327 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2328 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2329 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2330 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2332 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2334 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2335 MulFrm /* for convenience */, NoItinerary, "usad8",
2336 "\t$Rd, $Rn, $Rm", []>,
2337 Requires<[IsARM, HasV6]> {
2341 let Inst{27-20} = 0b01111000;
2342 let Inst{15-12} = 0b1111;
2343 let Inst{7-4} = 0b0001;
2344 let Inst{19-16} = Rd;
2345 let Inst{11-8} = Rm;
2348 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2349 MulFrm /* for convenience */, NoItinerary, "usada8",
2350 "\t$Rd, $Rn, $Rm, $Ra", []>,
2351 Requires<[IsARM, HasV6]> {
2356 let Inst{27-20} = 0b01111000;
2357 let Inst{7-4} = 0b0001;
2358 let Inst{19-16} = Rd;
2359 let Inst{15-12} = Ra;
2360 let Inst{11-8} = Rm;
2364 // Signed/Unsigned saturate -- for disassembly only
2366 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2367 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2368 [/* For disassembly only; pattern left blank */]> {
2373 let Inst{27-21} = 0b0110101;
2374 let Inst{5-4} = 0b01;
2375 let Inst{20-16} = sat_imm;
2376 let Inst{15-12} = Rd;
2377 let Inst{11-7} = sh{7-3};
2378 let Inst{6} = sh{0};
2382 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2383 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2384 [/* For disassembly only; pattern left blank */]> {
2388 let Inst{27-20} = 0b01101010;
2389 let Inst{11-4} = 0b11110011;
2390 let Inst{15-12} = Rd;
2391 let Inst{19-16} = sat_imm;
2395 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2396 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2397 [/* For disassembly only; pattern left blank */]> {
2402 let Inst{27-21} = 0b0110111;
2403 let Inst{5-4} = 0b01;
2404 let Inst{15-12} = Rd;
2405 let Inst{11-7} = sh{7-3};
2406 let Inst{6} = sh{0};
2407 let Inst{20-16} = sat_imm;
2411 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2412 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2413 [/* For disassembly only; pattern left blank */]> {
2417 let Inst{27-20} = 0b01101110;
2418 let Inst{11-4} = 0b11110011;
2419 let Inst{15-12} = Rd;
2420 let Inst{19-16} = sat_imm;
2424 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2425 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2427 //===----------------------------------------------------------------------===//
2428 // Bitwise Instructions.
2431 defm AND : AsI1_bin_irs<0b0000, "and",
2432 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2433 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2434 defm ORR : AsI1_bin_irs<0b1100, "orr",
2435 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2436 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2437 defm EOR : AsI1_bin_irs<0b0001, "eor",
2438 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2439 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2440 defm BIC : AsI1_bin_irs<0b1110, "bic",
2441 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2442 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2444 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2445 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2446 "bfc", "\t$Rd, $imm", "$src = $Rd",
2447 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2448 Requires<[IsARM, HasV6T2]> {
2451 let Inst{27-21} = 0b0111110;
2452 let Inst{6-0} = 0b0011111;
2453 let Inst{15-12} = Rd;
2454 let Inst{11-7} = imm{4-0}; // lsb
2455 let Inst{20-16} = imm{9-5}; // width
2458 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2459 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2460 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2461 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2462 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2463 bf_inv_mask_imm:$imm))]>,
2464 Requires<[IsARM, HasV6T2]> {
2468 let Inst{27-21} = 0b0111110;
2469 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2470 let Inst{15-12} = Rd;
2471 let Inst{11-7} = imm{4-0}; // lsb
2472 let Inst{20-16} = imm{9-5}; // width
2476 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2477 "mvn", "\t$Rd, $Rm",
2478 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2482 let Inst{19-16} = 0b0000;
2483 let Inst{11-4} = 0b00000000;
2484 let Inst{15-12} = Rd;
2487 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2488 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2489 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2493 let Inst{19-16} = 0b0000;
2494 let Inst{15-12} = Rd;
2495 let Inst{11-0} = shift;
2497 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2498 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2499 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2500 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2504 let Inst{19-16} = 0b0000;
2505 let Inst{15-12} = Rd;
2506 let Inst{11-0} = imm;
2509 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2510 (BICri GPR:$src, so_imm_not:$imm)>;
2512 //===----------------------------------------------------------------------===//
2513 // Multiply Instructions.
2515 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2516 string opc, string asm, list<dag> pattern>
2517 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2521 let Inst{19-16} = Rd;
2522 let Inst{11-8} = Rm;
2525 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2526 string opc, string asm, list<dag> pattern>
2527 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2532 let Inst{19-16} = RdHi;
2533 let Inst{15-12} = RdLo;
2534 let Inst{11-8} = Rm;
2538 let isCommutable = 1 in
2539 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2540 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2541 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2543 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2544 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2545 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2547 let Inst{15-12} = Ra;
2550 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2551 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2552 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2553 Requires<[IsARM, HasV6T2]> {
2558 let Inst{19-16} = Rd;
2559 let Inst{15-12} = Ra;
2560 let Inst{11-8} = Rm;
2564 // Extra precision multiplies with low / high results
2566 let neverHasSideEffects = 1 in {
2567 let isCommutable = 1 in {
2568 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2569 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2570 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2572 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2573 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2574 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2577 // Multiply + accumulate
2578 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2579 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2580 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2582 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2583 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2584 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2586 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2587 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2588 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2589 Requires<[IsARM, HasV6]> {
2594 let Inst{19-16} = RdLo;
2595 let Inst{15-12} = RdHi;
2596 let Inst{11-8} = Rm;
2599 } // neverHasSideEffects
2601 // Most significant word multiply
2602 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2603 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2604 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2605 Requires<[IsARM, HasV6]> {
2606 let Inst{15-12} = 0b1111;
2609 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2610 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2611 [/* For disassembly only; pattern left blank */]>,
2612 Requires<[IsARM, HasV6]> {
2613 let Inst{15-12} = 0b1111;
2616 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2617 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2618 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2619 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2620 Requires<[IsARM, HasV6]>;
2622 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2623 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2624 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2625 [/* For disassembly only; pattern left blank */]>,
2626 Requires<[IsARM, HasV6]>;
2628 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2629 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2630 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2631 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2632 Requires<[IsARM, HasV6]>;
2634 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2635 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2636 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2637 [/* For disassembly only; pattern left blank */]>,
2638 Requires<[IsARM, HasV6]>;
2640 multiclass AI_smul<string opc, PatFrag opnode> {
2641 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2642 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2643 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2644 (sext_inreg GPR:$Rm, i16)))]>,
2645 Requires<[IsARM, HasV5TE]>;
2647 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2648 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2649 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2650 (sra GPR:$Rm, (i32 16))))]>,
2651 Requires<[IsARM, HasV5TE]>;
2653 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2654 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2655 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2656 (sext_inreg GPR:$Rm, i16)))]>,
2657 Requires<[IsARM, HasV5TE]>;
2659 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2660 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2661 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2662 (sra GPR:$Rm, (i32 16))))]>,
2663 Requires<[IsARM, HasV5TE]>;
2665 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2666 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2667 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2668 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2669 Requires<[IsARM, HasV5TE]>;
2671 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2672 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2673 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2674 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2675 Requires<[IsARM, HasV5TE]>;
2679 multiclass AI_smla<string opc, PatFrag opnode> {
2680 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2681 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2682 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2683 [(set GPR:$Rd, (add GPR:$Ra,
2684 (opnode (sext_inreg GPR:$Rn, i16),
2685 (sext_inreg GPR:$Rm, i16))))]>,
2686 Requires<[IsARM, HasV5TE]>;
2688 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2689 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2690 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2691 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2692 (sra GPR:$Rm, (i32 16)))))]>,
2693 Requires<[IsARM, HasV5TE]>;
2695 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2696 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2697 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2698 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2699 (sext_inreg GPR:$Rm, i16))))]>,
2700 Requires<[IsARM, HasV5TE]>;
2702 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2703 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2704 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2705 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2706 (sra GPR:$Rm, (i32 16)))))]>,
2707 Requires<[IsARM, HasV5TE]>;
2709 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2710 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2711 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2712 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2713 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2714 Requires<[IsARM, HasV5TE]>;
2716 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2717 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2718 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2719 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2720 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2721 Requires<[IsARM, HasV5TE]>;
2724 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2725 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2727 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2728 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2729 (ins GPR:$Rn, GPR:$Rm),
2730 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2731 [/* For disassembly only; pattern left blank */]>,
2732 Requires<[IsARM, HasV5TE]>;
2734 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2735 (ins GPR:$Rn, GPR:$Rm),
2736 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2737 [/* For disassembly only; pattern left blank */]>,
2738 Requires<[IsARM, HasV5TE]>;
2740 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2741 (ins GPR:$Rn, GPR:$Rm),
2742 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2743 [/* For disassembly only; pattern left blank */]>,
2744 Requires<[IsARM, HasV5TE]>;
2746 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2747 (ins GPR:$Rn, GPR:$Rm),
2748 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2749 [/* For disassembly only; pattern left blank */]>,
2750 Requires<[IsARM, HasV5TE]>;
2752 // Helper class for AI_smld -- for disassembly only
2753 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2754 InstrItinClass itin, string opc, string asm>
2755 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2762 let Inst{21-20} = 0b00;
2763 let Inst{22} = long;
2764 let Inst{27-23} = 0b01110;
2765 let Inst{11-8} = Rm;
2768 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2769 InstrItinClass itin, string opc, string asm>
2770 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2772 let Inst{15-12} = 0b1111;
2773 let Inst{19-16} = Rd;
2775 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2776 InstrItinClass itin, string opc, string asm>
2777 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2779 let Inst{15-12} = Ra;
2781 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2782 InstrItinClass itin, string opc, string asm>
2783 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2786 let Inst{19-16} = RdHi;
2787 let Inst{15-12} = RdLo;
2790 multiclass AI_smld<bit sub, string opc> {
2792 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2793 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2795 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2796 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2798 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2799 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2800 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2802 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2803 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2804 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2808 defm SMLA : AI_smld<0, "smla">;
2809 defm SMLS : AI_smld<1, "smls">;
2811 multiclass AI_sdml<bit sub, string opc> {
2813 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2814 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2815 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2816 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2819 defm SMUA : AI_sdml<0, "smua">;
2820 defm SMUS : AI_sdml<1, "smus">;
2822 //===----------------------------------------------------------------------===//
2823 // Misc. Arithmetic Instructions.
2826 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2827 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2828 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2830 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2831 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2832 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2833 Requires<[IsARM, HasV6T2]>;
2835 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2836 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2837 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2839 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2840 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2842 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2843 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2844 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2845 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2846 Requires<[IsARM, HasV6]>;
2848 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2849 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2852 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2853 (shl GPR:$Rm, (i32 8))), i16))]>,
2854 Requires<[IsARM, HasV6]>;
2856 def lsl_shift_imm : SDNodeXForm<imm, [{
2857 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2858 return CurDAG->getTargetConstant(Sh, MVT::i32);
2861 def lsl_amt : PatLeaf<(i32 imm), [{
2862 return (N->getZExtValue() < 32);
2865 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2866 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2867 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2868 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2869 (and (shl GPR:$Rm, lsl_amt:$sh),
2871 Requires<[IsARM, HasV6]>;
2873 // Alternate cases for PKHBT where identities eliminate some nodes.
2874 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2875 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2876 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2877 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2879 def asr_shift_imm : SDNodeXForm<imm, [{
2880 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2881 return CurDAG->getTargetConstant(Sh, MVT::i32);
2884 def asr_amt : PatLeaf<(i32 imm), [{
2885 return (N->getZExtValue() <= 32);
2888 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2889 // will match the pattern below.
2890 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2891 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2892 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2893 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2894 (and (sra GPR:$Rm, asr_amt:$sh),
2896 Requires<[IsARM, HasV6]>;
2898 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2899 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2900 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2901 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2902 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2903 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2904 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2906 //===----------------------------------------------------------------------===//
2907 // Comparison Instructions...
2910 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2911 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2912 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2914 // FIXME: We have to be careful when using the CMN instruction and comparison
2915 // with 0. One would expect these two pieces of code should give identical
2931 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2932 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2933 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2934 // value of r0 and the carry bit (because the "carry bit" parameter to
2935 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2936 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2937 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2938 // parameter to AddWithCarry is defined as 0).
2940 // When x is 0 and unsigned:
2944 // ~x + 1 = 0x1 0000 0000
2945 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2947 // Therefore, we should disable CMN when comparing against zero, until we can
2948 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2949 // when it's a comparison which doesn't look at the 'carry' flag).
2951 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2953 // This is related to <rdar://problem/7569620>.
2955 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2956 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2958 // Note that TST/TEQ don't set all the same flags that CMP does!
2959 defm TST : AI1_cmp_irs<0b1000, "tst",
2960 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2961 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
2962 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2963 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2964 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
2966 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
2967 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2968 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
2969 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2970 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2971 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2973 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2974 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2976 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2977 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2979 // Pseudo i64 compares for some floating point compares.
2980 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2982 def BCCi64 : PseudoInst<(outs),
2983 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2985 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2987 def BCCZi64 : PseudoInst<(outs),
2988 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
2989 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2990 } // usesCustomInserter
2993 // Conditional moves
2994 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2995 // a two-value operand where a dag node expects two operands. :(
2996 // FIXME: These should all be pseudo-instructions that get expanded to
2997 // the normal MOV instructions. That would fix the dependency on
2998 // special casing them in tblgen.
2999 let neverHasSideEffects = 1 in {
3000 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
3001 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
3002 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3003 RegConstraint<"$false = $Rd">, UnaryDP {
3008 let Inst{15-12} = Rd;
3009 let Inst{11-4} = 0b00000000;
3013 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
3014 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
3015 "mov", "\t$Rd, $shift",
3016 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3017 RegConstraint<"$false = $Rd">, UnaryDP {
3022 let Inst{19-16} = 0;
3023 let Inst{15-12} = Rd;
3024 let Inst{11-0} = shift;
3027 let isMoveImm = 1 in
3028 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, movt_imm:$imm),
3030 "movw", "\t$Rd, $imm",
3032 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
3038 let Inst{19-16} = imm{15-12};
3039 let Inst{15-12} = Rd;
3040 let Inst{11-0} = imm{11-0};
3043 let isMoveImm = 1 in
3044 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
3045 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3046 "mov", "\t$Rd, $imm",
3047 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3048 RegConstraint<"$false = $Rd">, UnaryDP {
3053 let Inst{19-16} = 0b0000;
3054 let Inst{15-12} = Rd;
3055 let Inst{11-0} = imm;
3058 // Two instruction predicate mov immediate.
3059 let isMoveImm = 1 in
3060 def MOVCCi32imm : PseudoInst<(outs GPR:$Rd),
3061 (ins GPR:$false, i32imm:$src, pred:$p),
3062 IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3064 let isMoveImm = 1 in
3065 def MVNCCi : AI1<0b1111, (outs GPR:$Rd),
3066 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3067 "mvn", "\t$Rd, $imm",
3068 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3069 RegConstraint<"$false = $Rd">, UnaryDP {
3074 let Inst{19-16} = 0b0000;
3075 let Inst{15-12} = Rd;
3076 let Inst{11-0} = imm;
3078 } // neverHasSideEffects
3080 //===----------------------------------------------------------------------===//
3081 // Atomic operations intrinsics
3084 def memb_opt : Operand<i32> {
3085 let PrintMethod = "printMemBOption";
3088 // memory barriers protect the atomic sequences
3089 let hasSideEffects = 1 in {
3090 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3091 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3092 Requires<[IsARM, HasDB]> {
3094 let Inst{31-4} = 0xf57ff05;
3095 let Inst{3-0} = opt;
3098 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
3099 "mcr", "\tp15, 0, $zero, c7, c10, 5",
3100 [(ARMMemBarrierMCR GPR:$zero)]>,
3101 Requires<[IsARM, HasV6]> {
3102 // FIXME: add encoding
3106 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3108 [/* For disassembly only; pattern left blank */]>,
3109 Requires<[IsARM, HasDB]> {
3111 let Inst{31-4} = 0xf57ff04;
3112 let Inst{3-0} = opt;
3115 // ISB has only full system option -- for disassembly only
3116 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3117 Requires<[IsARM, HasDB]> {
3118 let Inst{31-4} = 0xf57ff06;
3119 let Inst{3-0} = 0b1111;
3122 let usesCustomInserter = 1 in {
3123 let Uses = [CPSR] in {
3124 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3125 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3126 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3127 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3128 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3129 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3130 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3131 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3132 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3133 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3134 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3135 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3136 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3137 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3138 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3139 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3140 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3141 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3142 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3143 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3144 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3145 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3146 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3147 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3148 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3149 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3150 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3151 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3152 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3153 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3154 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3155 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3156 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3157 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3158 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3159 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3160 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3161 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3162 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3163 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3164 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3165 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3166 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3167 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3168 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3169 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3170 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3171 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3172 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3173 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3174 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3175 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3176 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3177 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3179 def ATOMIC_SWAP_I8 : PseudoInst<
3180 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3181 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3182 def ATOMIC_SWAP_I16 : PseudoInst<
3183 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3184 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3185 def ATOMIC_SWAP_I32 : PseudoInst<
3186 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3187 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3189 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3190 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3191 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3192 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3193 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3194 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3195 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3196 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3197 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3201 let mayLoad = 1 in {
3202 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3203 "ldrexb", "\t$Rt, [$Rn]",
3205 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3206 "ldrexh", "\t$Rt, [$Rn]",
3208 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3209 "ldrex", "\t$Rt, [$Rn]",
3211 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3213 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3217 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3218 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3220 "strexb", "\t$Rd, $src, [$Rn]",
3222 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3224 "strexh", "\t$Rd, $Rt, [$Rn]",
3226 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3228 "strex", "\t$Rd, $Rt, [$Rn]",
3230 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3231 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3233 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3237 // Clear-Exclusive is for disassembly only.
3238 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3239 [/* For disassembly only; pattern left blank */]>,
3240 Requires<[IsARM, HasV7]> {
3241 let Inst{31-0} = 0b11110101011111111111000000011111;
3244 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3245 let mayLoad = 1 in {
3246 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3247 [/* For disassembly only; pattern left blank */]>;
3248 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3249 [/* For disassembly only; pattern left blank */]>;
3252 //===----------------------------------------------------------------------===//
3256 // __aeabi_read_tp preserves the registers r1-r3.
3257 // FIXME: This needs to be a pseudo of some sort so that we can get the
3258 // encoding right, complete with fixup for the aeabi_read_tp function.
3260 Defs = [R0, R12, LR, CPSR] in {
3261 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
3262 "bl\t__aeabi_read_tp",
3263 [(set R0, ARMthread_pointer)]>;
3266 //===----------------------------------------------------------------------===//
3267 // SJLJ Exception handling intrinsics
3268 // eh_sjlj_setjmp() is an instruction sequence to store the return
3269 // address and save #0 in R0 for the non-longjmp case.
3270 // Since by its nature we may be coming from some other function to get
3271 // here, and we're using the stack frame for the containing function to
3272 // save/restore registers, we can't keep anything live in regs across
3273 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3274 // when we get here from a longjmp(). We force everthing out of registers
3275 // except for our own input by listing the relevant registers in Defs. By
3276 // doing so, we also cause the prologue/epilogue code to actively preserve
3277 // all of the callee-saved resgisters, which is exactly what we want.
3278 // A constant value is passed in $val, and we use the location as a scratch.
3280 // These are pseudo-instructions and are lowered to individual MC-insts, so
3281 // no encoding information is necessary.
3283 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3284 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3285 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3286 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3287 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src, GPR:$val),
3288 AddrModeNone, SizeSpecial, IndexModeNone,
3289 Pseudo, NoItinerary, "", "",
3290 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3291 Requires<[IsARM, HasVFP2]>;
3295 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3296 hasSideEffects = 1, isBarrier = 1 in {
3297 def Int_eh_sjlj_setjmp_nofp : XI<(outs), (ins GPR:$src, GPR:$val),
3298 AddrModeNone, SizeSpecial, IndexModeNone,
3299 Pseudo, NoItinerary, "", "",
3300 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3301 Requires<[IsARM, NoVFP]>;
3304 // FIXME: Non-Darwin version(s)
3305 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3306 Defs = [ R7, LR, SP ] in {
3307 def Int_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
3308 AddrModeNone, SizeSpecial, IndexModeNone,
3309 Pseudo, NoItinerary, "", "",
3310 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3311 Requires<[IsARM, IsDarwin]>;
3314 // eh.sjlj.dispatchsetup pseudo-instruction.
3315 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3316 // handled when the pseudo is expanded (which happens before any passes
3317 // that need the instruction size).
3318 let isBarrier = 1, hasSideEffects = 1 in
3319 def Int_eh_sjlj_dispatchsetup :
3320 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3321 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3322 Requires<[IsDarwin]>;
3324 //===----------------------------------------------------------------------===//
3325 // Non-Instruction Patterns
3328 // Large immediate handling.
3330 // 32-bit immediate using two piece so_imms or movw + movt.
3331 // This is a single pseudo instruction, the benefit is that it can be remat'd
3332 // as a single unit instead of having to handle reg inputs.
3333 // FIXME: Remove this when we can do generalized remat.
3334 let isReMaterializable = 1, isMoveImm = 1 in
3335 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3336 [(set GPR:$dst, (arm_i32imm:$src))]>,
3339 // ConstantPool, GlobalAddress, and JumpTable
3340 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3341 Requires<[IsARM, DontUseMovt]>;
3342 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3343 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3344 Requires<[IsARM, UseMovt]>;
3345 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3346 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3348 // TODO: add,sub,and, 3-instr forms?
3351 def : ARMPat<(ARMtcret tcGPR:$dst),
3352 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3354 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3355 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3357 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3358 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3360 def : ARMPat<(ARMtcret tcGPR:$dst),
3361 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3363 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3364 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3366 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3367 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3370 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3371 Requires<[IsARM, IsNotDarwin]>;
3372 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3373 Requires<[IsARM, IsDarwin]>;
3375 // zextload i1 -> zextload i8
3376 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3377 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3379 // extload -> zextload
3380 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3381 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3382 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3383 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3385 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3387 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3388 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3391 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3392 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3393 (SMULBB GPR:$a, GPR:$b)>;
3394 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3395 (SMULBB GPR:$a, GPR:$b)>;
3396 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3397 (sra GPR:$b, (i32 16))),
3398 (SMULBT GPR:$a, GPR:$b)>;
3399 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3400 (SMULBT GPR:$a, GPR:$b)>;
3401 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3402 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3403 (SMULTB GPR:$a, GPR:$b)>;
3404 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3405 (SMULTB GPR:$a, GPR:$b)>;
3406 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3408 (SMULWB GPR:$a, GPR:$b)>;
3409 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3410 (SMULWB GPR:$a, GPR:$b)>;
3412 def : ARMV5TEPat<(add GPR:$acc,
3413 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3414 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3415 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3416 def : ARMV5TEPat<(add GPR:$acc,
3417 (mul sext_16_node:$a, sext_16_node:$b)),
3418 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3419 def : ARMV5TEPat<(add GPR:$acc,
3420 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3421 (sra GPR:$b, (i32 16)))),
3422 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3423 def : ARMV5TEPat<(add GPR:$acc,
3424 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3425 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3426 def : ARMV5TEPat<(add GPR:$acc,
3427 (mul (sra GPR:$a, (i32 16)),
3428 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3429 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3430 def : ARMV5TEPat<(add GPR:$acc,
3431 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3432 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3433 def : ARMV5TEPat<(add GPR:$acc,
3434 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3436 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3437 def : ARMV5TEPat<(add GPR:$acc,
3438 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3439 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3441 //===----------------------------------------------------------------------===//
3445 include "ARMInstrThumb.td"
3447 //===----------------------------------------------------------------------===//
3451 include "ARMInstrThumb2.td"
3453 //===----------------------------------------------------------------------===//
3454 // Floating Point Support
3457 include "ARMInstrVFP.td"
3459 //===----------------------------------------------------------------------===//
3460 // Advanced SIMD (NEON) Support
3463 include "ARMInstrNEON.td"
3465 //===----------------------------------------------------------------------===//
3466 // Coprocessor Instructions. For disassembly only.
3469 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3470 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3471 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3472 [/* For disassembly only; pattern left blank */]> {
3476 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3477 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3478 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3479 [/* For disassembly only; pattern left blank */]> {
3480 let Inst{31-28} = 0b1111;
3484 class ACI<dag oops, dag iops, string opc, string asm>
3485 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3486 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3487 let Inst{27-25} = 0b110;
3490 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3492 def _OFFSET : ACI<(outs),
3493 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3494 opc, "\tp$cop, cr$CRd, $addr"> {
3495 let Inst{31-28} = op31_28;
3496 let Inst{24} = 1; // P = 1
3497 let Inst{21} = 0; // W = 0
3498 let Inst{22} = 0; // D = 0
3499 let Inst{20} = load;
3502 def _PRE : ACI<(outs),
3503 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3504 opc, "\tp$cop, cr$CRd, $addr!"> {
3505 let Inst{31-28} = op31_28;
3506 let Inst{24} = 1; // P = 1
3507 let Inst{21} = 1; // W = 1
3508 let Inst{22} = 0; // D = 0
3509 let Inst{20} = load;
3512 def _POST : ACI<(outs),
3513 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3514 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3515 let Inst{31-28} = op31_28;
3516 let Inst{24} = 0; // P = 0
3517 let Inst{21} = 1; // W = 1
3518 let Inst{22} = 0; // D = 0
3519 let Inst{20} = load;
3522 def _OPTION : ACI<(outs),
3523 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3524 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3525 let Inst{31-28} = op31_28;
3526 let Inst{24} = 0; // P = 0
3527 let Inst{23} = 1; // U = 1
3528 let Inst{21} = 0; // W = 0
3529 let Inst{22} = 0; // D = 0
3530 let Inst{20} = load;
3533 def L_OFFSET : ACI<(outs),
3534 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3535 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3536 let Inst{31-28} = op31_28;
3537 let Inst{24} = 1; // P = 1
3538 let Inst{21} = 0; // W = 0
3539 let Inst{22} = 1; // D = 1
3540 let Inst{20} = load;
3543 def L_PRE : ACI<(outs),
3544 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3545 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3546 let Inst{31-28} = op31_28;
3547 let Inst{24} = 1; // P = 1
3548 let Inst{21} = 1; // W = 1
3549 let Inst{22} = 1; // D = 1
3550 let Inst{20} = load;
3553 def L_POST : ACI<(outs),
3554 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3555 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3556 let Inst{31-28} = op31_28;
3557 let Inst{24} = 0; // P = 0
3558 let Inst{21} = 1; // W = 1
3559 let Inst{22} = 1; // D = 1
3560 let Inst{20} = load;
3563 def L_OPTION : ACI<(outs),
3564 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3565 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3566 let Inst{31-28} = op31_28;
3567 let Inst{24} = 0; // P = 0
3568 let Inst{23} = 1; // U = 1
3569 let Inst{21} = 0; // W = 0
3570 let Inst{22} = 1; // D = 1
3571 let Inst{20} = load;
3575 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3576 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3577 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3578 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3580 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3581 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3582 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3583 [/* For disassembly only; pattern left blank */]> {
3588 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3589 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3590 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3591 [/* For disassembly only; pattern left blank */]> {
3592 let Inst{31-28} = 0b1111;
3597 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3598 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3599 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3600 [/* For disassembly only; pattern left blank */]> {
3605 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3606 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3607 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3608 [/* For disassembly only; pattern left blank */]> {
3609 let Inst{31-28} = 0b1111;
3614 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3615 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3616 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3617 [/* For disassembly only; pattern left blank */]> {
3618 let Inst{23-20} = 0b0100;
3621 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3622 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3623 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3624 [/* For disassembly only; pattern left blank */]> {
3625 let Inst{31-28} = 0b1111;
3626 let Inst{23-20} = 0b0100;
3629 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3630 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3631 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3632 [/* For disassembly only; pattern left blank */]> {
3633 let Inst{23-20} = 0b0101;
3636 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3637 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3638 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3639 [/* For disassembly only; pattern left blank */]> {
3640 let Inst{31-28} = 0b1111;
3641 let Inst{23-20} = 0b0101;
3644 //===----------------------------------------------------------------------===//
3645 // Move between special register and ARM core register -- for disassembly only
3648 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3649 [/* For disassembly only; pattern left blank */]> {
3650 let Inst{23-20} = 0b0000;
3651 let Inst{7-4} = 0b0000;
3654 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3655 [/* For disassembly only; pattern left blank */]> {
3656 let Inst{23-20} = 0b0100;
3657 let Inst{7-4} = 0b0000;
3660 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3661 "msr", "\tcpsr$mask, $src",
3662 [/* For disassembly only; pattern left blank */]> {
3663 let Inst{23-20} = 0b0010;
3664 let Inst{7-4} = 0b0000;
3667 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3668 "msr", "\tcpsr$mask, $a",
3669 [/* For disassembly only; pattern left blank */]> {
3670 let Inst{23-20} = 0b0010;
3671 let Inst{7-4} = 0b0000;
3674 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3675 "msr", "\tspsr$mask, $src",
3676 [/* For disassembly only; pattern left blank */]> {
3677 let Inst{23-20} = 0b0110;
3678 let Inst{7-4} = 0b0000;
3681 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3682 "msr", "\tspsr$mask, $a",
3683 [/* For disassembly only; pattern left blank */]> {
3684 let Inst{23-20} = 0b0110;
3685 let Inst{7-4} = 0b0000;