1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
73 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
74 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
76 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
77 [SDNPHasChain, SDNPOutGlue]>;
78 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
81 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
84 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
85 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
87 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
88 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
91 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
92 [SDNPHasChain, SDNPOptInGlue]>;
94 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutGlue, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
153 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
154 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
155 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
156 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
157 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
158 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
159 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
160 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
161 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
162 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
164 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
166 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
168 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
169 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
170 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
171 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
172 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
173 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
174 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
175 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
177 // FIXME: Eventually this will be just "hasV6T2Ops".
178 def UseMovt : Predicate<"Subtarget->useMovt()">;
179 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
180 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
182 //===----------------------------------------------------------------------===//
183 // ARM Flag Definitions.
185 class RegConstraint<string C> {
186 string Constraints = C;
189 //===----------------------------------------------------------------------===//
190 // ARM specific transformation functions and pattern fragments.
193 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
194 // so_imm_neg def below.
195 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
199 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
200 // so_imm_not def below.
201 def so_imm_not_XFORM : SDNodeXForm<imm, [{
202 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
205 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
206 def imm1_15 : ImmLeaf<i32, [{
207 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
210 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
211 def imm16_31 : ImmLeaf<i32, [{
212 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
217 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
218 }], so_imm_neg_XFORM>;
222 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
223 }], so_imm_not_XFORM>;
225 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
226 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
227 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
230 /// Split a 32-bit immediate into two 16 bit parts.
231 def hi16 : SDNodeXForm<imm, [{
232 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
235 def lo16AllZero : PatLeaf<(i32 imm), [{
236 // Returns true if all low 16-bits are 0.
237 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
240 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
242 def imm0_65535 : ImmLeaf<i32, [{
243 return Imm >= 0 && Imm < 65536;
246 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
247 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
249 /// adde and sube predicates - True based on whether the carry flag output
250 /// will be needed or not.
251 def adde_dead_carry :
252 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
253 [{return !N->hasAnyUseOfValue(1);}]>;
254 def sube_dead_carry :
255 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
256 [{return !N->hasAnyUseOfValue(1);}]>;
257 def adde_live_carry :
258 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
259 [{return N->hasAnyUseOfValue(1);}]>;
260 def sube_live_carry :
261 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
262 [{return N->hasAnyUseOfValue(1);}]>;
264 // An 'and' node with a single use.
265 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
266 return N->hasOneUse();
269 // An 'xor' node with a single use.
270 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
271 return N->hasOneUse();
274 // An 'fmul' node with a single use.
275 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
276 return N->hasOneUse();
279 // An 'fadd' node which checks for single non-hazardous use.
280 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
281 return hasNoVMLxHazardUse(N);
284 // An 'fsub' node which checks for single non-hazardous use.
285 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
286 return hasNoVMLxHazardUse(N);
289 //===----------------------------------------------------------------------===//
290 // Operand Definitions.
294 // FIXME: rename brtarget to t2_brtarget
295 def brtarget : Operand<OtherVT> {
296 let EncoderMethod = "getBranchTargetOpValue";
299 // FIXME: get rid of this one?
300 def uncondbrtarget : Operand<OtherVT> {
301 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
304 // Branch target for ARM. Handles conditional/unconditional
305 def br_target : Operand<OtherVT> {
306 let EncoderMethod = "getARMBranchTargetOpValue";
310 // FIXME: rename bltarget to t2_bl_target?
311 def bltarget : Operand<i32> {
312 // Encoded the same as branch targets.
313 let EncoderMethod = "getBranchTargetOpValue";
316 // Call target for ARM. Handles conditional/unconditional
317 // FIXME: rename bl_target to t2_bltarget?
318 def bl_target : Operand<i32> {
319 // Encoded the same as branch targets.
320 let EncoderMethod = "getARMBranchTargetOpValue";
324 // A list of registers separated by comma. Used by load/store multiple.
325 def RegListAsmOperand : AsmOperandClass {
326 let Name = "RegList";
327 let SuperClasses = [];
330 def DPRRegListAsmOperand : AsmOperandClass {
331 let Name = "DPRRegList";
332 let SuperClasses = [];
335 def SPRRegListAsmOperand : AsmOperandClass {
336 let Name = "SPRRegList";
337 let SuperClasses = [];
340 def reglist : Operand<i32> {
341 let EncoderMethod = "getRegisterListOpValue";
342 let ParserMatchClass = RegListAsmOperand;
343 let PrintMethod = "printRegisterList";
346 def dpr_reglist : Operand<i32> {
347 let EncoderMethod = "getRegisterListOpValue";
348 let ParserMatchClass = DPRRegListAsmOperand;
349 let PrintMethod = "printRegisterList";
352 def spr_reglist : Operand<i32> {
353 let EncoderMethod = "getRegisterListOpValue";
354 let ParserMatchClass = SPRRegListAsmOperand;
355 let PrintMethod = "printRegisterList";
358 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
359 def cpinst_operand : Operand<i32> {
360 let PrintMethod = "printCPInstOperand";
364 def pclabel : Operand<i32> {
365 let PrintMethod = "printPCLabel";
368 // ADR instruction labels.
369 def adrlabel : Operand<i32> {
370 let EncoderMethod = "getAdrLabelOpValue";
373 def neon_vcvt_imm32 : Operand<i32> {
374 let EncoderMethod = "getNEONVcvtImm32OpValue";
377 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
378 def rot_imm : Operand<i32>, ImmLeaf<i32, [{
379 int32_t v = (int32_t)Imm;
380 return v == 8 || v == 16 || v == 24; }]> {
381 let EncoderMethod = "getRotImmOpValue";
384 def ShifterAsmOperand : AsmOperandClass {
385 let Name = "Shifter";
386 let SuperClasses = [];
389 // shift_imm: An integer that encodes a shift amount and the type of shift
390 // (currently either asr or lsl) using the same encoding used for the
391 // immediates in so_reg operands.
392 def shift_imm : Operand<i32> {
393 let PrintMethod = "printShiftImmOperand";
394 let ParserMatchClass = ShifterAsmOperand;
397 // shifter_operand operands: so_reg and so_imm.
398 def so_reg : Operand<i32>, // reg reg imm
399 ComplexPattern<i32, 3, "SelectShifterOperandReg",
400 [shl,srl,sra,rotr]> {
401 let EncoderMethod = "getSORegOpValue";
402 let PrintMethod = "printSORegOperand";
403 let MIOperandInfo = (ops GPR, GPR, shift_imm);
405 def shift_so_reg : Operand<i32>, // reg reg imm
406 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
407 [shl,srl,sra,rotr]> {
408 let EncoderMethod = "getSORegOpValue";
409 let PrintMethod = "printSORegOperand";
410 let MIOperandInfo = (ops GPR, GPR, shift_imm);
413 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
414 // 8-bit immediate rotated by an arbitrary number of bits.
415 def so_imm : Operand<i32>, ImmLeaf<i32, [{
416 return ARM_AM::getSOImmVal(Imm) != -1;
418 let EncoderMethod = "getSOImmOpValue";
419 let PrintMethod = "printSOImmOperand";
422 // Break so_imm's up into two pieces. This handles immediates with up to 16
423 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
424 // get the first/second pieces.
425 def so_imm2part : PatLeaf<(imm), [{
426 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
429 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
431 def arm_i32imm : PatLeaf<(imm), [{
432 if (Subtarget->hasV6T2Ops())
434 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
437 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
438 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
439 return Imm >= 0 && Imm < 32;
442 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
443 def imm0_31_m1 : Operand<i32>, ImmLeaf<i32, [{
444 return Imm >= 0 && Imm < 32;
446 let EncoderMethod = "getImmMinusOneOpValue";
449 // i32imm_hilo16 - For movt/movw - sets the MC Encoder method.
450 // The imm is split into imm{15-12}, imm{11-0}
452 def i32imm_hilo16 : Operand<i32> {
453 let EncoderMethod = "getHiLo16ImmOpValue";
456 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
458 def bf_inv_mask_imm : Operand<i32>,
460 return ARM::isBitFieldInvertedMask(N->getZExtValue());
462 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
463 let PrintMethod = "printBitfieldInvMaskImmOperand";
466 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
467 def lsb_pos_imm : Operand<i32>, ImmLeaf<i32, [{
468 return isInt<5>(Imm);
471 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
472 def width_imm : Operand<i32>, ImmLeaf<i32, [{
473 return Imm > 0 && Imm <= 32;
475 let EncoderMethod = "getMsbOpValue";
478 def ssat_imm : Operand<i32>, ImmLeaf<i32, [{
479 return Imm > 0 && Imm <= 32;
481 let EncoderMethod = "getSsatBitPosValue";
484 // Define ARM specific addressing modes.
486 def MemMode2AsmOperand : AsmOperandClass {
487 let Name = "MemMode2";
488 let SuperClasses = [];
489 let ParserMethod = "tryParseMemMode2Operand";
492 def MemMode3AsmOperand : AsmOperandClass {
493 let Name = "MemMode3";
494 let SuperClasses = [];
495 let ParserMethod = "tryParseMemMode3Operand";
498 // addrmode_imm12 := reg +/- imm12
500 def addrmode_imm12 : Operand<i32>,
501 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
502 // 12-bit immediate operand. Note that instructions using this encode
503 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
504 // immediate values are as normal.
506 let EncoderMethod = "getAddrModeImm12OpValue";
507 let PrintMethod = "printAddrModeImm12Operand";
508 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
510 // ldst_so_reg := reg +/- reg shop imm
512 def ldst_so_reg : Operand<i32>,
513 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
514 let EncoderMethod = "getLdStSORegOpValue";
515 // FIXME: Simplify the printer
516 let PrintMethod = "printAddrMode2Operand";
517 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
520 // addrmode2 := reg +/- imm12
521 // := reg +/- reg shop imm
523 def addrmode2 : Operand<i32>,
524 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
525 let EncoderMethod = "getAddrMode2OpValue";
526 let PrintMethod = "printAddrMode2Operand";
527 let ParserMatchClass = MemMode2AsmOperand;
528 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
531 def am2offset : Operand<i32>,
532 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
533 [], [SDNPWantRoot]> {
534 let EncoderMethod = "getAddrMode2OffsetOpValue";
535 let PrintMethod = "printAddrMode2OffsetOperand";
536 let MIOperandInfo = (ops GPR, i32imm);
539 // addrmode3 := reg +/- reg
540 // addrmode3 := reg +/- imm8
542 def addrmode3 : Operand<i32>,
543 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
544 let EncoderMethod = "getAddrMode3OpValue";
545 let PrintMethod = "printAddrMode3Operand";
546 let ParserMatchClass = MemMode3AsmOperand;
547 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
550 def am3offset : Operand<i32>,
551 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
552 [], [SDNPWantRoot]> {
553 let EncoderMethod = "getAddrMode3OffsetOpValue";
554 let PrintMethod = "printAddrMode3OffsetOperand";
555 let MIOperandInfo = (ops GPR, i32imm);
558 // ldstm_mode := {ia, ib, da, db}
560 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
561 let EncoderMethod = "getLdStmModeOpValue";
562 let PrintMethod = "printLdStmModeOperand";
565 def MemMode5AsmOperand : AsmOperandClass {
566 let Name = "MemMode5";
567 let SuperClasses = [];
570 // addrmode5 := reg +/- imm8*4
572 def addrmode5 : Operand<i32>,
573 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
574 let PrintMethod = "printAddrMode5Operand";
575 let MIOperandInfo = (ops GPR:$base, i32imm);
576 let ParserMatchClass = MemMode5AsmOperand;
577 let EncoderMethod = "getAddrMode5OpValue";
580 // addrmode6 := reg with optional alignment
582 def addrmode6 : Operand<i32>,
583 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
584 let PrintMethod = "printAddrMode6Operand";
585 let MIOperandInfo = (ops GPR:$addr, i32imm);
586 let EncoderMethod = "getAddrMode6AddressOpValue";
589 def am6offset : Operand<i32>,
590 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
591 [], [SDNPWantRoot]> {
592 let PrintMethod = "printAddrMode6OffsetOperand";
593 let MIOperandInfo = (ops GPR);
594 let EncoderMethod = "getAddrMode6OffsetOpValue";
597 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
598 // (single element from one lane) for size 32.
599 def addrmode6oneL32 : Operand<i32>,
600 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
601 let PrintMethod = "printAddrMode6Operand";
602 let MIOperandInfo = (ops GPR:$addr, i32imm);
603 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
606 // Special version of addrmode6 to handle alignment encoding for VLD-dup
607 // instructions, specifically VLD4-dup.
608 def addrmode6dup : Operand<i32>,
609 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
610 let PrintMethod = "printAddrMode6Operand";
611 let MIOperandInfo = (ops GPR:$addr, i32imm);
612 let EncoderMethod = "getAddrMode6DupAddressOpValue";
615 // addrmodepc := pc + reg
617 def addrmodepc : Operand<i32>,
618 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
619 let PrintMethod = "printAddrModePCOperand";
620 let MIOperandInfo = (ops GPR, i32imm);
623 def MemMode7AsmOperand : AsmOperandClass {
624 let Name = "MemMode7";
625 let SuperClasses = [];
629 // Used by load/store exclusive instructions. Useful to enable right assembly
630 // parsing and printing. Not used for any codegen matching.
632 def addrmode7 : Operand<i32> {
633 let PrintMethod = "printAddrMode7Operand";
634 let MIOperandInfo = (ops GPR);
635 let ParserMatchClass = MemMode7AsmOperand;
638 def nohash_imm : Operand<i32> {
639 let PrintMethod = "printNoHashImmediate";
642 def CoprocNumAsmOperand : AsmOperandClass {
643 let Name = "CoprocNum";
644 let SuperClasses = [];
645 let ParserMethod = "tryParseCoprocNumOperand";
648 def CoprocRegAsmOperand : AsmOperandClass {
649 let Name = "CoprocReg";
650 let SuperClasses = [];
651 let ParserMethod = "tryParseCoprocRegOperand";
654 def p_imm : Operand<i32> {
655 let PrintMethod = "printPImmediate";
656 let ParserMatchClass = CoprocNumAsmOperand;
659 def c_imm : Operand<i32> {
660 let PrintMethod = "printCImmediate";
661 let ParserMatchClass = CoprocRegAsmOperand;
664 //===----------------------------------------------------------------------===//
666 include "ARMInstrFormats.td"
668 //===----------------------------------------------------------------------===//
669 // Multiclass helpers...
672 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
673 /// binop that produces a value.
674 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
675 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
676 PatFrag opnode, bit Commutable = 0> {
677 // The register-immediate version is re-materializable. This is useful
678 // in particular for taking the address of a local.
679 let isReMaterializable = 1 in {
680 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
681 iii, opc, "\t$Rd, $Rn, $imm",
682 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
687 let Inst{19-16} = Rn;
688 let Inst{15-12} = Rd;
689 let Inst{11-0} = imm;
692 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
693 iir, opc, "\t$Rd, $Rn, $Rm",
694 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
699 let isCommutable = Commutable;
700 let Inst{19-16} = Rn;
701 let Inst{15-12} = Rd;
702 let Inst{11-4} = 0b00000000;
705 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
706 iis, opc, "\t$Rd, $Rn, $shift",
707 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
712 let Inst{19-16} = Rn;
713 let Inst{15-12} = Rd;
714 let Inst{11-0} = shift;
718 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
719 /// instruction modifies the CPSR register.
720 let isCodeGenOnly = 1, Defs = [CPSR] in {
721 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
722 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
723 PatFrag opnode, bit Commutable = 0> {
724 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
725 iii, opc, "\t$Rd, $Rn, $imm",
726 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
732 let Inst{19-16} = Rn;
733 let Inst{15-12} = Rd;
734 let Inst{11-0} = imm;
736 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
737 iir, opc, "\t$Rd, $Rn, $Rm",
738 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
742 let isCommutable = Commutable;
745 let Inst{19-16} = Rn;
746 let Inst{15-12} = Rd;
747 let Inst{11-4} = 0b00000000;
750 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
751 iis, opc, "\t$Rd, $Rn, $shift",
752 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
758 let Inst{19-16} = Rn;
759 let Inst{15-12} = Rd;
760 let Inst{11-0} = shift;
765 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
766 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
767 /// a explicit result, only implicitly set CPSR.
768 let isCompare = 1, Defs = [CPSR] in {
769 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
770 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
771 PatFrag opnode, bit Commutable = 0> {
772 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
774 [(opnode GPR:$Rn, so_imm:$imm)]> {
779 let Inst{19-16} = Rn;
780 let Inst{15-12} = 0b0000;
781 let Inst{11-0} = imm;
783 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
785 [(opnode GPR:$Rn, GPR:$Rm)]> {
788 let isCommutable = Commutable;
791 let Inst{19-16} = Rn;
792 let Inst{15-12} = 0b0000;
793 let Inst{11-4} = 0b00000000;
796 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
797 opc, "\t$Rn, $shift",
798 [(opnode GPR:$Rn, so_reg:$shift)]> {
803 let Inst{19-16} = Rn;
804 let Inst{15-12} = 0b0000;
805 let Inst{11-0} = shift;
810 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
811 /// register and one whose operand is a register rotated by 8/16/24.
812 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
813 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
814 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
815 IIC_iEXTr, opc, "\t$Rd, $Rm",
816 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
817 Requires<[IsARM, HasV6]> {
820 let Inst{19-16} = 0b1111;
821 let Inst{15-12} = Rd;
822 let Inst{11-10} = 0b00;
825 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
826 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
827 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
828 Requires<[IsARM, HasV6]> {
832 let Inst{19-16} = 0b1111;
833 let Inst{15-12} = Rd;
834 let Inst{11-10} = rot;
839 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
840 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
841 IIC_iEXTr, opc, "\t$Rd, $Rm",
842 [/* For disassembly only; pattern left blank */]>,
843 Requires<[IsARM, HasV6]> {
844 let Inst{19-16} = 0b1111;
845 let Inst{11-10} = 0b00;
847 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
848 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
849 [/* For disassembly only; pattern left blank */]>,
850 Requires<[IsARM, HasV6]> {
852 let Inst{19-16} = 0b1111;
853 let Inst{11-10} = rot;
857 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
858 /// register and one whose operand is a register rotated by 8/16/24.
859 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
860 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
861 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
862 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
863 Requires<[IsARM, HasV6]> {
867 let Inst{19-16} = Rn;
868 let Inst{15-12} = Rd;
869 let Inst{11-10} = 0b00;
870 let Inst{9-4} = 0b000111;
873 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
875 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
876 [(set GPR:$Rd, (opnode GPR:$Rn,
877 (rotr GPR:$Rm, rot_imm:$rot)))]>,
878 Requires<[IsARM, HasV6]> {
883 let Inst{19-16} = Rn;
884 let Inst{15-12} = Rd;
885 let Inst{11-10} = rot;
886 let Inst{9-4} = 0b000111;
891 // For disassembly only.
892 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
893 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
894 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
895 [/* For disassembly only; pattern left blank */]>,
896 Requires<[IsARM, HasV6]> {
897 let Inst{11-10} = 0b00;
899 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
901 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
902 [/* For disassembly only; pattern left blank */]>,
903 Requires<[IsARM, HasV6]> {
906 let Inst{19-16} = Rn;
907 let Inst{11-10} = rot;
911 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
912 let Uses = [CPSR] in {
913 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
914 bit Commutable = 0> {
915 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
916 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
917 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
923 let Inst{15-12} = Rd;
924 let Inst{19-16} = Rn;
925 let Inst{11-0} = imm;
927 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
928 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
929 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
934 let Inst{11-4} = 0b00000000;
936 let isCommutable = Commutable;
938 let Inst{15-12} = Rd;
939 let Inst{19-16} = Rn;
941 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
942 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
943 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
949 let Inst{11-0} = shift;
950 let Inst{15-12} = Rd;
951 let Inst{19-16} = Rn;
956 // Carry setting variants
957 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
958 let usesCustomInserter = 1 in {
959 multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
960 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
961 Size4Bytes, IIC_iALUi,
962 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>;
963 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
964 Size4Bytes, IIC_iALUr,
965 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
966 let isCommutable = Commutable;
968 def rs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
969 Size4Bytes, IIC_iALUsr,
970 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>;
974 let canFoldAsLoad = 1, isReMaterializable = 1 in {
975 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
976 InstrItinClass iir, PatFrag opnode> {
977 // Note: We use the complex addrmode_imm12 rather than just an input
978 // GPR and a constrained immediate so that we can use this to match
979 // frame index references and avoid matching constant pool references.
980 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
981 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
982 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
985 let Inst{23} = addr{12}; // U (add = ('U' == 1))
986 let Inst{19-16} = addr{16-13}; // Rn
987 let Inst{15-12} = Rt;
988 let Inst{11-0} = addr{11-0}; // imm12
990 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
991 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
992 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
995 let shift{4} = 0; // Inst{4} = 0
996 let Inst{23} = shift{12}; // U (add = ('U' == 1))
997 let Inst{19-16} = shift{16-13}; // Rn
998 let Inst{15-12} = Rt;
999 let Inst{11-0} = shift{11-0};
1004 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1005 InstrItinClass iir, PatFrag opnode> {
1006 // Note: We use the complex addrmode_imm12 rather than just an input
1007 // GPR and a constrained immediate so that we can use this to match
1008 // frame index references and avoid matching constant pool references.
1009 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1010 (ins GPR:$Rt, addrmode_imm12:$addr),
1011 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1012 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1015 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1016 let Inst{19-16} = addr{16-13}; // Rn
1017 let Inst{15-12} = Rt;
1018 let Inst{11-0} = addr{11-0}; // imm12
1020 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1021 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1022 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1025 let shift{4} = 0; // Inst{4} = 0
1026 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1027 let Inst{19-16} = shift{16-13}; // Rn
1028 let Inst{15-12} = Rt;
1029 let Inst{11-0} = shift{11-0};
1032 //===----------------------------------------------------------------------===//
1034 //===----------------------------------------------------------------------===//
1036 //===----------------------------------------------------------------------===//
1037 // Miscellaneous Instructions.
1040 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1041 /// the function. The first operand is the ID# for this instruction, the second
1042 /// is the index into the MachineConstantPool that this is, the third is the
1043 /// size in bytes of this constant pool entry.
1044 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1045 def CONSTPOOL_ENTRY :
1046 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1047 i32imm:$size), NoItinerary, []>;
1049 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1050 // from removing one half of the matched pairs. That breaks PEI, which assumes
1051 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1052 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1053 def ADJCALLSTACKUP :
1054 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1055 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1057 def ADJCALLSTACKDOWN :
1058 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1059 [(ARMcallseq_start timm:$amt)]>;
1062 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1063 [/* For disassembly only; pattern left blank */]>,
1064 Requires<[IsARM, HasV6T2]> {
1065 let Inst{27-16} = 0b001100100000;
1066 let Inst{15-8} = 0b11110000;
1067 let Inst{7-0} = 0b00000000;
1070 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1071 [/* For disassembly only; pattern left blank */]>,
1072 Requires<[IsARM, HasV6T2]> {
1073 let Inst{27-16} = 0b001100100000;
1074 let Inst{15-8} = 0b11110000;
1075 let Inst{7-0} = 0b00000001;
1078 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1079 [/* For disassembly only; pattern left blank */]>,
1080 Requires<[IsARM, HasV6T2]> {
1081 let Inst{27-16} = 0b001100100000;
1082 let Inst{15-8} = 0b11110000;
1083 let Inst{7-0} = 0b00000010;
1086 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1087 [/* For disassembly only; pattern left blank */]>,
1088 Requires<[IsARM, HasV6T2]> {
1089 let Inst{27-16} = 0b001100100000;
1090 let Inst{15-8} = 0b11110000;
1091 let Inst{7-0} = 0b00000011;
1094 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1096 [/* For disassembly only; pattern left blank */]>,
1097 Requires<[IsARM, HasV6]> {
1102 let Inst{15-12} = Rd;
1103 let Inst{19-16} = Rn;
1104 let Inst{27-20} = 0b01101000;
1105 let Inst{7-4} = 0b1011;
1106 let Inst{11-8} = 0b1111;
1109 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1110 [/* For disassembly only; pattern left blank */]>,
1111 Requires<[IsARM, HasV6T2]> {
1112 let Inst{27-16} = 0b001100100000;
1113 let Inst{15-8} = 0b11110000;
1114 let Inst{7-0} = 0b00000100;
1117 // The i32imm operand $val can be used by a debugger to store more information
1118 // about the breakpoint.
1119 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1120 [/* For disassembly only; pattern left blank */]>,
1123 let Inst{3-0} = val{3-0};
1124 let Inst{19-8} = val{15-4};
1125 let Inst{27-20} = 0b00010010;
1126 let Inst{7-4} = 0b0111;
1129 // Change Processor State is a system instruction -- for disassembly and
1131 // FIXME: Since the asm parser has currently no clean way to handle optional
1132 // operands, create 3 versions of the same instruction. Once there's a clean
1133 // framework to represent optional operands, change this behavior.
1134 class CPS<dag iops, string asm_ops>
1135 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1136 [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> {
1142 let Inst{31-28} = 0b1111;
1143 let Inst{27-20} = 0b00010000;
1144 let Inst{19-18} = imod;
1145 let Inst{17} = M; // Enabled if mode is set;
1147 let Inst{8-6} = iflags;
1149 let Inst{4-0} = mode;
1153 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
1154 "$imod\t$iflags, $mode">;
1155 let mode = 0, M = 0 in
1156 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1158 let imod = 0, iflags = 0, M = 1 in
1159 def CPS1p : CPS<(ins i32imm:$mode), "\t$mode">;
1161 // Preload signals the memory system of possible future data/instruction access.
1162 // These are for disassembly only.
1163 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1165 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1166 !strconcat(opc, "\t$addr"),
1167 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1170 let Inst{31-26} = 0b111101;
1171 let Inst{25} = 0; // 0 for immediate form
1172 let Inst{24} = data;
1173 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1174 let Inst{22} = read;
1175 let Inst{21-20} = 0b01;
1176 let Inst{19-16} = addr{16-13}; // Rn
1177 let Inst{15-12} = 0b1111;
1178 let Inst{11-0} = addr{11-0}; // imm12
1181 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1182 !strconcat(opc, "\t$shift"),
1183 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1185 let Inst{31-26} = 0b111101;
1186 let Inst{25} = 1; // 1 for register form
1187 let Inst{24} = data;
1188 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1189 let Inst{22} = read;
1190 let Inst{21-20} = 0b01;
1191 let Inst{19-16} = shift{16-13}; // Rn
1192 let Inst{15-12} = 0b1111;
1193 let Inst{11-0} = shift{11-0};
1197 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1198 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1199 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1201 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1203 [/* For disassembly only; pattern left blank */]>,
1206 let Inst{31-10} = 0b1111000100000001000000;
1211 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1212 [/* For disassembly only; pattern left blank */]>,
1213 Requires<[IsARM, HasV7]> {
1215 let Inst{27-4} = 0b001100100000111100001111;
1216 let Inst{3-0} = opt;
1219 // A5.4 Permanently UNDEFINED instructions.
1220 let isBarrier = 1, isTerminator = 1 in
1221 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1224 let Inst = 0xe7ffdefe;
1227 // Address computation and loads and stores in PIC mode.
1228 let isNotDuplicable = 1 in {
1229 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1230 Size4Bytes, IIC_iALUr,
1231 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1233 let AddedComplexity = 10 in {
1234 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1235 Size4Bytes, IIC_iLoad_r,
1236 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1238 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1239 Size4Bytes, IIC_iLoad_bh_r,
1240 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1242 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1243 Size4Bytes, IIC_iLoad_bh_r,
1244 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1246 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1247 Size4Bytes, IIC_iLoad_bh_r,
1248 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1250 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1251 Size4Bytes, IIC_iLoad_bh_r,
1252 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1254 let AddedComplexity = 10 in {
1255 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1256 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1258 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1259 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1260 addrmodepc:$addr)]>;
1262 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1263 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1265 } // isNotDuplicable = 1
1268 // LEApcrel - Load a pc-relative address into a register without offending the
1270 let neverHasSideEffects = 1, isReMaterializable = 1 in
1271 // The 'adr' mnemonic encodes differently if the label is before or after
1272 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1273 // know until then which form of the instruction will be used.
1274 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1275 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1278 let Inst{27-25} = 0b001;
1280 let Inst{19-16} = 0b1111;
1281 let Inst{15-12} = Rd;
1282 let Inst{11-0} = label;
1284 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1285 Size4Bytes, IIC_iALUi, []>;
1287 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1288 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1289 Size4Bytes, IIC_iALUi, []>;
1291 //===----------------------------------------------------------------------===//
1292 // Control Flow Instructions.
1295 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1297 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1298 "bx", "\tlr", [(ARMretflag)]>,
1299 Requires<[IsARM, HasV4T]> {
1300 let Inst{27-0} = 0b0001001011111111111100011110;
1304 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1305 "mov", "\tpc, lr", [(ARMretflag)]>,
1306 Requires<[IsARM, NoV4T]> {
1307 let Inst{27-0} = 0b0001101000001111000000001110;
1311 // Indirect branches
1312 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1314 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1315 [(brind GPR:$dst)]>,
1316 Requires<[IsARM, HasV4T]> {
1318 let Inst{31-4} = 0b1110000100101111111111110001;
1319 let Inst{3-0} = dst;
1322 // For disassembly only.
1323 def BX_pred : AXI<(outs), (ins GPR:$dst, pred:$p), BrMiscFrm, IIC_Br,
1324 "bx$p\t$dst", [/* pattern left blank */]>,
1325 Requires<[IsARM, HasV4T]> {
1327 let Inst{27-4} = 0b000100101111111111110001;
1328 let Inst{3-0} = dst;
1332 // FIXME: We would really like to define this as a vanilla ARMPat like:
1333 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1334 // With that, however, we can't set isBranch, isTerminator, etc..
1335 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1336 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1337 Requires<[IsARM, NoV4T]>;
1340 // All calls clobber the non-callee saved registers. SP is marked as
1341 // a use to prevent stack-pointer assignments that appear immediately
1342 // before calls from potentially appearing dead.
1344 // On non-Darwin platforms R9 is callee-saved.
1345 // FIXME: Do we really need a non-predicated version? If so, it should
1346 // at least be a pseudo instruction expanding to the predicated version
1347 // at MC lowering time.
1348 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1350 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1351 IIC_Br, "bl\t$func",
1352 [(ARMcall tglobaladdr:$func)]>,
1353 Requires<[IsARM, IsNotDarwin]> {
1354 let Inst{31-28} = 0b1110;
1356 let Inst{23-0} = func;
1359 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1360 IIC_Br, "bl", "\t$func",
1361 [(ARMcall_pred tglobaladdr:$func)]>,
1362 Requires<[IsARM, IsNotDarwin]> {
1364 let Inst{23-0} = func;
1368 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1369 IIC_Br, "blx\t$func",
1370 [(ARMcall GPR:$func)]>,
1371 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1373 let Inst{31-4} = 0b1110000100101111111111110011;
1374 let Inst{3-0} = func;
1377 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1378 IIC_Br, "blx", "\t$func",
1379 [(ARMcall_pred GPR:$func)]>,
1380 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1382 let Inst{27-4} = 0b000100101111111111110011;
1383 let Inst{3-0} = func;
1387 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1388 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1389 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1390 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1393 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1394 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1395 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1399 // On Darwin R9 is call-clobbered.
1400 // R7 is marked as a use to prevent frame-pointer assignments from being
1401 // moved above / below calls.
1402 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1403 Uses = [R7, SP] in {
1404 def BLr9 : ARMPseudoInst<(outs), (ins bltarget:$func, variable_ops),
1406 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
1408 def BLr9_pred : ARMPseudoInst<(outs),
1409 (ins bltarget:$func, pred:$p, variable_ops),
1411 [(ARMcall_pred tglobaladdr:$func)]>,
1412 Requires<[IsARM, IsDarwin]>;
1415 def BLXr9 : ARMPseudoInst<(outs), (ins GPR:$func, variable_ops),
1417 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]>;
1419 def BLXr9_pred: ARMPseudoInst<(outs), (ins GPR:$func, pred:$p, variable_ops),
1421 [(ARMcall_pred GPR:$func)]>,
1422 Requires<[IsARM, HasV5T, IsDarwin]>;
1425 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1426 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1427 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1428 Requires<[IsARM, HasV4T, IsDarwin]>;
1431 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1432 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1433 Requires<[IsARM, NoV4T, IsDarwin]>;
1438 // FIXME: The Thumb versions of these should live in ARMInstrThumb.td
1439 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1441 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1443 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1444 IIC_Br, []>, Requires<[IsDarwin]>;
1446 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1447 IIC_Br, []>, Requires<[IsDarwin]>;
1449 def TAILJMPd : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1451 []>, Requires<[IsARM, IsDarwin]>;
1453 def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1455 []>, Requires<[IsThumb, IsDarwin]>;
1457 def TAILJMPr : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1459 []>, Requires<[IsARM, IsDarwin]>;
1461 def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1463 []>, Requires<[IsThumb, IsDarwin]>;
1466 // Non-Darwin versions (the difference is R9).
1467 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
1469 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1470 IIC_Br, []>, Requires<[IsNotDarwin]>;
1472 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1473 IIC_Br, []>, Requires<[IsNotDarwin]>;
1475 def TAILJMPdND : ARMPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1477 []>, Requires<[IsARM, IsNotDarwin]>;
1479 def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
1481 []>, Requires<[IsThumb, IsNotDarwin]>;
1483 def TAILJMPrND : ARMPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1485 []>, Requires<[IsARM, IsNotDarwin]>;
1486 def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1488 []>, Requires<[IsThumb, IsNotDarwin]>;
1492 let isBranch = 1, isTerminator = 1 in {
1493 // B is "predicable" since it's just a Bcc with an 'always' condition.
1494 let isBarrier = 1 in {
1495 let isPredicable = 1 in
1496 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
1497 // should be sufficient.
1498 def B : ARMPseudoInst<(outs), (ins brtarget:$target), Size4Bytes, IIC_Br,
1501 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1502 def BR_JTr : ARMPseudoInst<(outs),
1503 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1504 SizeSpecial, IIC_Br,
1505 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1506 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1507 // into i12 and rs suffixed versions.
1508 def BR_JTm : ARMPseudoInst<(outs),
1509 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1510 SizeSpecial, IIC_Br,
1511 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1513 def BR_JTadd : ARMPseudoInst<(outs),
1514 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1515 SizeSpecial, IIC_Br,
1516 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1518 } // isNotDuplicable = 1, isIndirectBranch = 1
1521 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1522 // a two-value operand where a dag node expects two operands. :(
1523 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
1524 IIC_Br, "b", "\t$target",
1525 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1527 let Inst{23-0} = target;
1531 // BLX (immediate) -- for disassembly only
1532 def BLXi : AXI<(outs), (ins br_target:$target), BrMiscFrm, NoItinerary,
1533 "blx\t$target", [/* pattern left blank */]>,
1534 Requires<[IsARM, HasV5T]> {
1535 let Inst{31-25} = 0b1111101;
1537 let Inst{23-0} = target{24-1};
1538 let Inst{24} = target{0};
1541 // Branch and Exchange Jazelle -- for disassembly only
1542 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1543 [/* For disassembly only; pattern left blank */]> {
1544 let Inst{23-20} = 0b0010;
1545 //let Inst{19-8} = 0xfff;
1546 let Inst{7-4} = 0b0010;
1549 // Secure Monitor Call is a system instruction -- for disassembly only
1550 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1551 [/* For disassembly only; pattern left blank */]> {
1553 let Inst{23-4} = 0b01100000000000000111;
1554 let Inst{3-0} = opt;
1557 // Supervisor Call (Software Interrupt) -- for disassembly only
1558 let isCall = 1, Uses = [SP] in {
1559 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1560 [/* For disassembly only; pattern left blank */]> {
1562 let Inst{23-0} = svc;
1565 def : MnemonicAlias<"swi", "svc">;
1567 // Store Return State is a system instruction -- for disassembly only
1568 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1569 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1570 NoItinerary, "srs${amode}\tsp!, $mode",
1571 [/* For disassembly only; pattern left blank */]> {
1572 let Inst{31-28} = 0b1111;
1573 let Inst{22-20} = 0b110; // W = 1
1574 let Inst{19-8} = 0xd05;
1575 let Inst{7-5} = 0b000;
1578 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1579 NoItinerary, "srs${amode}\tsp, $mode",
1580 [/* For disassembly only; pattern left blank */]> {
1581 let Inst{31-28} = 0b1111;
1582 let Inst{22-20} = 0b100; // W = 0
1583 let Inst{19-8} = 0xd05;
1584 let Inst{7-5} = 0b000;
1587 // Return From Exception is a system instruction -- for disassembly only
1588 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1589 NoItinerary, "rfe${amode}\t$base!",
1590 [/* For disassembly only; pattern left blank */]> {
1591 let Inst{31-28} = 0b1111;
1592 let Inst{22-20} = 0b011; // W = 1
1593 let Inst{15-0} = 0x0a00;
1596 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1597 NoItinerary, "rfe${amode}\t$base",
1598 [/* For disassembly only; pattern left blank */]> {
1599 let Inst{31-28} = 0b1111;
1600 let Inst{22-20} = 0b001; // W = 0
1601 let Inst{15-0} = 0x0a00;
1603 } // isCodeGenOnly = 1
1605 //===----------------------------------------------------------------------===//
1606 // Load / store Instructions.
1612 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1613 UnOpFrag<(load node:$Src)>>;
1614 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1615 UnOpFrag<(zextloadi8 node:$Src)>>;
1616 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1617 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1618 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1619 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1621 // Special LDR for loads from non-pc-relative constpools.
1622 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1623 isReMaterializable = 1 in
1624 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1625 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1629 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1630 let Inst{19-16} = 0b1111;
1631 let Inst{15-12} = Rt;
1632 let Inst{11-0} = addr{11-0}; // imm12
1635 // Loads with zero extension
1636 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1637 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1638 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1640 // Loads with sign extension
1641 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1642 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1643 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1645 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1646 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1647 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1649 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1651 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1652 (ins addrmode3:$addr), LdMiscFrm,
1653 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
1654 []>, Requires<[IsARM, HasV5TE]>;
1658 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1659 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1660 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1661 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1663 // {13} 1 == Rm, 0 == imm12
1667 let Inst{25} = addr{13};
1668 let Inst{23} = addr{12};
1669 let Inst{19-16} = addr{17-14};
1670 let Inst{11-0} = addr{11-0};
1671 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1673 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1674 (ins GPR:$Rn, am2offset:$offset),
1675 IndexModePost, LdFrm, itin,
1676 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1677 // {13} 1 == Rm, 0 == imm12
1682 let Inst{25} = offset{13};
1683 let Inst{23} = offset{12};
1684 let Inst{19-16} = Rn;
1685 let Inst{11-0} = offset{11-0};
1689 let mayLoad = 1, neverHasSideEffects = 1 in {
1690 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1691 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1694 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1695 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1696 (ins addrmode3:$addr), IndexModePre,
1698 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1700 let Inst{23} = addr{8}; // U bit
1701 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1702 let Inst{19-16} = addr{12-9}; // Rn
1703 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1704 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1706 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1707 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1709 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1712 let Inst{23} = offset{8}; // U bit
1713 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1714 let Inst{19-16} = Rn;
1715 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1716 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1720 let mayLoad = 1, neverHasSideEffects = 1 in {
1721 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1722 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1723 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1724 let hasExtraDefRegAllocReq = 1 in {
1725 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1726 (ins addrmode3:$addr), IndexModePre,
1727 LdMiscFrm, IIC_iLoad_d_ru,
1728 "ldrd", "\t$Rt, $Rt2, $addr!",
1729 "$addr.base = $Rn_wb", []> {
1731 let Inst{23} = addr{8}; // U bit
1732 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1733 let Inst{19-16} = addr{12-9}; // Rn
1734 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1735 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1737 def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
1738 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1739 LdMiscFrm, IIC_iLoad_d_ru,
1740 "ldrd", "\t$Rt, $Rt2, [$Rn], $offset",
1741 "$Rn = $Rn_wb", []> {
1744 let Inst{23} = offset{8}; // U bit
1745 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1746 let Inst{19-16} = Rn;
1747 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1748 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1750 } // hasExtraDefRegAllocReq = 1
1751 } // mayLoad = 1, neverHasSideEffects = 1
1753 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1754 let mayLoad = 1, neverHasSideEffects = 1 in {
1755 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
1756 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
1757 "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1759 // {13} 1 == Rm, 0 == imm12
1763 let Inst{25} = addr{13};
1764 let Inst{23} = addr{12};
1765 let Inst{21} = 1; // overwrite
1766 let Inst{19-16} = addr{17-14};
1767 let Inst{11-0} = addr{11-0};
1768 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1770 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1771 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
1772 "ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1774 // {13} 1 == Rm, 0 == imm12
1778 let Inst{25} = addr{13};
1779 let Inst{23} = addr{12};
1780 let Inst{21} = 1; // overwrite
1781 let Inst{19-16} = addr{17-14};
1782 let Inst{11-0} = addr{11-0};
1783 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1785 def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1786 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1787 "ldrsbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1788 let Inst{21} = 1; // overwrite
1790 def LDRHT : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1791 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1792 "ldrht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1793 let Inst{21} = 1; // overwrite
1795 def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1796 (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
1797 "ldrsht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1798 let Inst{21} = 1; // overwrite
1804 // Stores with truncate
1805 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1806 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1807 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1810 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
1811 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
1812 StMiscFrm, IIC_iStore_d_r,
1813 "strd", "\t$Rt, $src2, $addr", []>, Requires<[IsARM, HasV5TE]>;
1816 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1817 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1818 IndexModePre, StFrm, IIC_iStore_ru,
1819 "str", "\t$Rt, [$Rn, $offset]!",
1820 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1822 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1824 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1825 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1826 IndexModePost, StFrm, IIC_iStore_ru,
1827 "str", "\t$Rt, [$Rn], $offset",
1828 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1830 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1832 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1833 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1834 IndexModePre, StFrm, IIC_iStore_bh_ru,
1835 "strb", "\t$Rt, [$Rn, $offset]!",
1836 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1837 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1838 GPR:$Rn, am2offset:$offset))]>;
1839 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1840 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1841 IndexModePost, StFrm, IIC_iStore_bh_ru,
1842 "strb", "\t$Rt, [$Rn], $offset",
1843 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1844 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1845 GPR:$Rn, am2offset:$offset))]>;
1847 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1848 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1849 IndexModePre, StMiscFrm, IIC_iStore_ru,
1850 "strh", "\t$Rt, [$Rn, $offset]!",
1851 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1853 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1855 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1856 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1857 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1858 "strh", "\t$Rt, [$Rn], $offset",
1859 "$Rn = $Rn_wb,@earlyclobber $Rn_wb",
1860 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1861 GPR:$Rn, am3offset:$offset))]>;
1863 // For disassembly only
1864 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1865 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1866 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1867 StMiscFrm, IIC_iStore_d_ru,
1868 "strd", "\t$src1, $src2, [$base, $offset]!",
1869 "$base = $base_wb", []>;
1871 // For disassembly only
1872 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1873 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1874 StMiscFrm, IIC_iStore_d_ru,
1875 "strd", "\t$src1, $src2, [$base], $offset",
1876 "$base = $base_wb", []>;
1877 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1879 // STRT, STRBT, and STRHT are for disassembly only.
1881 def STRT : AI2stridxT<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1882 IndexModePost, StFrm, IIC_iStore_ru,
1883 "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1884 [/* For disassembly only; pattern left blank */]> {
1885 let Inst{21} = 1; // overwrite
1886 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1889 def STRBT : AI2stridxT<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1890 IndexModePost, StFrm, IIC_iStore_bh_ru,
1891 "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1892 [/* For disassembly only; pattern left blank */]> {
1893 let Inst{21} = 1; // overwrite
1894 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1897 def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
1898 StMiscFrm, IIC_iStore_bh_ru,
1899 "strht", "\t$Rt, $addr", "$addr.base = $base_wb",
1900 [/* For disassembly only; pattern left blank */]> {
1901 let Inst{21} = 1; // overwrite
1902 let AsmMatchConverter = "CvtStWriteBackRegAddrMode3";
1905 //===----------------------------------------------------------------------===//
1906 // Load / store multiple Instructions.
1909 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1910 InstrItinClass itin, InstrItinClass itin_upd> {
1912 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1913 IndexModeNone, f, itin,
1914 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1915 let Inst{24-23} = 0b01; // Increment After
1916 let Inst{21} = 0; // No writeback
1917 let Inst{20} = L_bit;
1920 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1921 IndexModeUpd, f, itin_upd,
1922 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1923 let Inst{24-23} = 0b01; // Increment After
1924 let Inst{21} = 1; // Writeback
1925 let Inst{20} = L_bit;
1928 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1929 IndexModeNone, f, itin,
1930 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1931 let Inst{24-23} = 0b00; // Decrement After
1932 let Inst{21} = 0; // No writeback
1933 let Inst{20} = L_bit;
1936 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1937 IndexModeUpd, f, itin_upd,
1938 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1939 let Inst{24-23} = 0b00; // Decrement After
1940 let Inst{21} = 1; // Writeback
1941 let Inst{20} = L_bit;
1944 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1945 IndexModeNone, f, itin,
1946 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1947 let Inst{24-23} = 0b10; // Decrement Before
1948 let Inst{21} = 0; // No writeback
1949 let Inst{20} = L_bit;
1952 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1953 IndexModeUpd, f, itin_upd,
1954 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1955 let Inst{24-23} = 0b10; // Decrement Before
1956 let Inst{21} = 1; // Writeback
1957 let Inst{20} = L_bit;
1960 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1961 IndexModeNone, f, itin,
1962 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1963 let Inst{24-23} = 0b11; // Increment Before
1964 let Inst{21} = 0; // No writeback
1965 let Inst{20} = L_bit;
1968 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1969 IndexModeUpd, f, itin_upd,
1970 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1971 let Inst{24-23} = 0b11; // Increment Before
1972 let Inst{21} = 1; // Writeback
1973 let Inst{20} = L_bit;
1977 let neverHasSideEffects = 1 in {
1979 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1980 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1982 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1983 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1985 } // neverHasSideEffects
1987 // Load / Store Multiple Mnemonic Aliases
1988 def : MnemonicAlias<"ldm", "ldmia">;
1989 def : MnemonicAlias<"stm", "stmia">;
1991 // FIXME: remove when we have a way to marking a MI with these properties.
1992 // FIXME: Should pc be an implicit operand like PICADD, etc?
1993 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1994 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1995 def LDMIA_RET : ARMPseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1996 reglist:$regs, variable_ops),
1997 Size4Bytes, IIC_iLoad_mBr, []>,
1998 RegConstraint<"$Rn = $wb">;
2000 //===----------------------------------------------------------------------===//
2001 // Move Instructions.
2004 let neverHasSideEffects = 1 in
2005 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2006 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2010 let Inst{19-16} = 0b0000;
2011 let Inst{11-4} = 0b00000000;
2014 let Inst{15-12} = Rd;
2017 // A version for the smaller set of tail call registers.
2018 let neverHasSideEffects = 1 in
2019 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2020 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2024 let Inst{11-4} = 0b00000000;
2027 let Inst{15-12} = Rd;
2030 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
2031 DPSoRegFrm, IIC_iMOVsr,
2032 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
2036 let Inst{15-12} = Rd;
2037 let Inst{19-16} = 0b0000;
2038 let Inst{11-0} = src;
2042 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2043 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2044 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2048 let Inst{15-12} = Rd;
2049 let Inst{19-16} = 0b0000;
2050 let Inst{11-0} = imm;
2053 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2054 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm),
2056 "movw", "\t$Rd, $imm",
2057 [(set GPR:$Rd, imm0_65535:$imm)]>,
2058 Requires<[IsARM, HasV6T2]>, UnaryDP {
2061 let Inst{15-12} = Rd;
2062 let Inst{11-0} = imm{11-0};
2063 let Inst{19-16} = imm{15-12};
2068 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2069 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2071 let Constraints = "$src = $Rd" in {
2072 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm),
2074 "movt", "\t$Rd, $imm",
2076 (or (and GPR:$src, 0xffff),
2077 lo16AllZero:$imm))]>, UnaryDP,
2078 Requires<[IsARM, HasV6T2]> {
2081 let Inst{15-12} = Rd;
2082 let Inst{11-0} = imm{11-0};
2083 let Inst{19-16} = imm{15-12};
2088 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
2089 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
2093 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
2094 Requires<[IsARM, HasV6T2]>;
2096 let Uses = [CPSR] in
2097 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
2098 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
2101 // These aren't really mov instructions, but we have to define them this way
2102 // due to flag operands.
2104 let Defs = [CPSR] in {
2105 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2106 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
2108 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
2109 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
2113 //===----------------------------------------------------------------------===//
2114 // Extend Instructions.
2119 defm SXTB : AI_ext_rrot<0b01101010,
2120 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
2121 defm SXTH : AI_ext_rrot<0b01101011,
2122 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
2124 defm SXTAB : AI_exta_rrot<0b01101010,
2125 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
2126 defm SXTAH : AI_exta_rrot<0b01101011,
2127 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2129 // For disassembly only
2130 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2132 // For disassembly only
2133 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2137 let AddedComplexity = 16 in {
2138 defm UXTB : AI_ext_rrot<0b01101110,
2139 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2140 defm UXTH : AI_ext_rrot<0b01101111,
2141 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2142 defm UXTB16 : AI_ext_rrot<0b01101100,
2143 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2145 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2146 // The transformation should probably be done as a combiner action
2147 // instead so we can include a check for masking back in the upper
2148 // eight bits of the source into the lower eight bits of the result.
2149 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2150 // (UXTB16r_rot GPR:$Src, 24)>;
2151 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2152 (UXTB16r_rot GPR:$Src, 8)>;
2154 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2155 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2156 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2157 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2160 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2161 // For disassembly only
2162 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2165 def SBFX : I<(outs GPR:$Rd),
2166 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2167 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2168 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2169 Requires<[IsARM, HasV6T2]> {
2174 let Inst{27-21} = 0b0111101;
2175 let Inst{6-4} = 0b101;
2176 let Inst{20-16} = width;
2177 let Inst{15-12} = Rd;
2178 let Inst{11-7} = lsb;
2182 def UBFX : I<(outs GPR:$Rd),
2183 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2184 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2185 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2186 Requires<[IsARM, HasV6T2]> {
2191 let Inst{27-21} = 0b0111111;
2192 let Inst{6-4} = 0b101;
2193 let Inst{20-16} = width;
2194 let Inst{15-12} = Rd;
2195 let Inst{11-7} = lsb;
2199 //===----------------------------------------------------------------------===//
2200 // Arithmetic Instructions.
2203 defm ADD : AsI1_bin_irs<0b0100, "add",
2204 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2205 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2206 defm SUB : AsI1_bin_irs<0b0010, "sub",
2207 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2208 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2210 // ADD and SUB with 's' bit set.
2211 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2212 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2213 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2214 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2215 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2216 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2218 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2219 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2220 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2221 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2223 // ADC and SUBC with 's' bit set.
2224 let usesCustomInserter = 1 in {
2225 defm ADCS : AI1_adde_sube_s_irs<
2226 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2227 defm SBCS : AI1_adde_sube_s_irs<
2228 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2231 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2232 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2233 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2238 let Inst{15-12} = Rd;
2239 let Inst{19-16} = Rn;
2240 let Inst{11-0} = imm;
2243 // The reg/reg form is only defined for the disassembler; for codegen it is
2244 // equivalent to SUBrr.
2245 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2246 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2247 [/* For disassembly only; pattern left blank */]> {
2251 let Inst{11-4} = 0b00000000;
2254 let Inst{15-12} = Rd;
2255 let Inst{19-16} = Rn;
2258 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2259 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2260 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2265 let Inst{11-0} = shift;
2266 let Inst{15-12} = Rd;
2267 let Inst{19-16} = Rn;
2270 // RSB with 's' bit set.
2271 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2272 let usesCustomInserter = 1 in {
2273 def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2274 Size4Bytes, IIC_iALUi,
2275 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
2276 def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2277 Size4Bytes, IIC_iALUr,
2278 [/* For disassembly only; pattern left blank */]>;
2279 def RSBSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2280 Size4Bytes, IIC_iALUsr,
2281 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]>;
2284 let Uses = [CPSR] in {
2285 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2286 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2287 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2293 let Inst{15-12} = Rd;
2294 let Inst{19-16} = Rn;
2295 let Inst{11-0} = imm;
2297 // The reg/reg form is only defined for the disassembler; for codegen it is
2298 // equivalent to SUBrr.
2299 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2300 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2301 [/* For disassembly only; pattern left blank */]> {
2305 let Inst{11-4} = 0b00000000;
2308 let Inst{15-12} = Rd;
2309 let Inst{19-16} = Rn;
2311 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2312 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2313 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2319 let Inst{11-0} = shift;
2320 let Inst{15-12} = Rd;
2321 let Inst{19-16} = Rn;
2325 // NOTE: CPSR def omitted because it will be handled by the custom inserter.
2326 let usesCustomInserter = 1, Uses = [CPSR] in {
2327 def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2328 Size4Bytes, IIC_iALUi,
2329 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>;
2330 def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2331 Size4Bytes, IIC_iALUsr,
2332 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>;
2335 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2336 // The assume-no-carry-in form uses the negation of the input since add/sub
2337 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2338 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2340 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2341 (SUBri GPR:$src, so_imm_neg:$imm)>;
2342 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2343 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2344 // The with-carry-in form matches bitwise not instead of the negation.
2345 // Effectively, the inverse interpretation of the carry flag already accounts
2346 // for part of the negation.
2347 def : ARMPat<(adde_dead_carry GPR:$src, so_imm_not:$imm),
2348 (SBCri GPR:$src, so_imm_not:$imm)>;
2349 def : ARMPat<(adde_live_carry GPR:$src, so_imm_not:$imm),
2350 (SBCSri GPR:$src, so_imm_not:$imm)>;
2352 // Note: These are implemented in C++ code, because they have to generate
2353 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2355 // (mul X, 2^n+1) -> (add (X << n), X)
2356 // (mul X, 2^n-1) -> (rsb X, (X << n))
2358 // ARM Arithmetic Instruction -- for disassembly only
2359 // GPR:$dst = GPR:$a op GPR:$b
2360 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2361 list<dag> pattern = [/* For disassembly only; pattern left blank */],
2362 dag iops = (ins GPR:$Rn, GPR:$Rm), string asm = "\t$Rd, $Rn, $Rm">
2363 : AI<(outs GPR:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
2367 let Inst{27-20} = op27_20;
2368 let Inst{11-4} = op11_4;
2369 let Inst{19-16} = Rn;
2370 let Inst{15-12} = Rd;
2374 // Saturating add/subtract -- for disassembly only
2376 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2377 [(set GPR:$Rd, (int_arm_qadd GPR:$Rm, GPR:$Rn))],
2378 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2379 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2380 [(set GPR:$Rd, (int_arm_qsub GPR:$Rm, GPR:$Rn))],
2381 (ins GPR:$Rm, GPR:$Rn), "\t$Rd, $Rm, $Rn">;
2382 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [], (ins GPR:$Rm, GPR:$Rn),
2384 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [], (ins GPR:$Rm, GPR:$Rn),
2387 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2388 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2389 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2390 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2391 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2392 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2393 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2394 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2395 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2396 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2397 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2398 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2400 // Signed/Unsigned add/subtract -- for disassembly only
2402 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2403 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2404 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2405 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2406 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2407 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2408 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2409 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2410 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2411 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2412 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2413 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2415 // Signed/Unsigned halving add/subtract -- for disassembly only
2417 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2418 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2419 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2420 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2421 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2422 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2423 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2424 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2425 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2426 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2427 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2428 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2430 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2432 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2433 MulFrm /* for convenience */, NoItinerary, "usad8",
2434 "\t$Rd, $Rn, $Rm", []>,
2435 Requires<[IsARM, HasV6]> {
2439 let Inst{27-20} = 0b01111000;
2440 let Inst{15-12} = 0b1111;
2441 let Inst{7-4} = 0b0001;
2442 let Inst{19-16} = Rd;
2443 let Inst{11-8} = Rm;
2446 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2447 MulFrm /* for convenience */, NoItinerary, "usada8",
2448 "\t$Rd, $Rn, $Rm, $Ra", []>,
2449 Requires<[IsARM, HasV6]> {
2454 let Inst{27-20} = 0b01111000;
2455 let Inst{7-4} = 0b0001;
2456 let Inst{19-16} = Rd;
2457 let Inst{15-12} = Ra;
2458 let Inst{11-8} = Rm;
2462 // Signed/Unsigned saturate -- for disassembly only
2464 def SSAT : AI<(outs GPR:$Rd), (ins ssat_imm:$sat_imm, GPR:$a, shift_imm:$sh),
2465 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2466 [/* For disassembly only; pattern left blank */]> {
2471 let Inst{27-21} = 0b0110101;
2472 let Inst{5-4} = 0b01;
2473 let Inst{20-16} = sat_imm;
2474 let Inst{15-12} = Rd;
2475 let Inst{11-7} = sh{7-3};
2476 let Inst{6} = sh{0};
2480 def SSAT16 : AI<(outs GPR:$Rd), (ins ssat_imm:$sat_imm, GPR:$Rn), SatFrm,
2481 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2482 [/* For disassembly only; pattern left blank */]> {
2486 let Inst{27-20} = 0b01101010;
2487 let Inst{11-4} = 0b11110011;
2488 let Inst{15-12} = Rd;
2489 let Inst{19-16} = sat_imm;
2493 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2494 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2495 [/* For disassembly only; pattern left blank */]> {
2500 let Inst{27-21} = 0b0110111;
2501 let Inst{5-4} = 0b01;
2502 let Inst{15-12} = Rd;
2503 let Inst{11-7} = sh{7-3};
2504 let Inst{6} = sh{0};
2505 let Inst{20-16} = sat_imm;
2509 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2510 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2511 [/* For disassembly only; pattern left blank */]> {
2515 let Inst{27-20} = 0b01101110;
2516 let Inst{11-4} = 0b11110011;
2517 let Inst{15-12} = Rd;
2518 let Inst{19-16} = sat_imm;
2522 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2523 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2525 //===----------------------------------------------------------------------===//
2526 // Bitwise Instructions.
2529 defm AND : AsI1_bin_irs<0b0000, "and",
2530 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2531 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2532 defm ORR : AsI1_bin_irs<0b1100, "orr",
2533 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2534 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2535 defm EOR : AsI1_bin_irs<0b0001, "eor",
2536 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2537 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2538 defm BIC : AsI1_bin_irs<0b1110, "bic",
2539 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2540 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2542 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2543 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2544 "bfc", "\t$Rd, $imm", "$src = $Rd",
2545 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2546 Requires<[IsARM, HasV6T2]> {
2549 let Inst{27-21} = 0b0111110;
2550 let Inst{6-0} = 0b0011111;
2551 let Inst{15-12} = Rd;
2552 let Inst{11-7} = imm{4-0}; // lsb
2553 let Inst{20-16} = imm{9-5}; // width
2556 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2557 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2558 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2559 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2560 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2561 bf_inv_mask_imm:$imm))]>,
2562 Requires<[IsARM, HasV6T2]> {
2566 let Inst{27-21} = 0b0111110;
2567 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2568 let Inst{15-12} = Rd;
2569 let Inst{11-7} = imm{4-0}; // lsb
2570 let Inst{20-16} = imm{9-5}; // width
2574 // GNU as only supports this form of bfi (w/ 4 arguments)
2575 let isAsmParserOnly = 1 in
2576 def BFI4p : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn,
2577 lsb_pos_imm:$lsb, width_imm:$width),
2578 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2579 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
2580 []>, Requires<[IsARM, HasV6T2]> {
2585 let Inst{27-21} = 0b0111110;
2586 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2587 let Inst{15-12} = Rd;
2588 let Inst{11-7} = lsb;
2589 let Inst{20-16} = width; // Custom encoder => lsb+width-1
2593 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2594 "mvn", "\t$Rd, $Rm",
2595 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2599 let Inst{19-16} = 0b0000;
2600 let Inst{11-4} = 0b00000000;
2601 let Inst{15-12} = Rd;
2604 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2605 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2606 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2610 let Inst{19-16} = 0b0000;
2611 let Inst{15-12} = Rd;
2612 let Inst{11-0} = shift;
2614 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2615 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2616 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2617 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2621 let Inst{19-16} = 0b0000;
2622 let Inst{15-12} = Rd;
2623 let Inst{11-0} = imm;
2626 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2627 (BICri GPR:$src, so_imm_not:$imm)>;
2629 //===----------------------------------------------------------------------===//
2630 // Multiply Instructions.
2632 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2633 string opc, string asm, list<dag> pattern>
2634 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2638 let Inst{19-16} = Rd;
2639 let Inst{11-8} = Rm;
2642 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2643 string opc, string asm, list<dag> pattern>
2644 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2649 let Inst{19-16} = RdHi;
2650 let Inst{15-12} = RdLo;
2651 let Inst{11-8} = Rm;
2655 let isCommutable = 1 in {
2656 let Constraints = "@earlyclobber $Rd" in
2657 def MULv5: ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
2658 pred:$p, cc_out:$s),
2659 Size4Bytes, IIC_iMUL32,
2660 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2661 Requires<[IsARM, NoV6]>;
2663 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2664 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2665 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
2666 Requires<[IsARM, HasV6]> {
2667 let Inst{15-12} = 0b0000;
2671 let Constraints = "@earlyclobber $Rd" in
2672 def MLAv5: ARMPseudoInst<(outs GPR:$Rd),
2673 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
2674 Size4Bytes, IIC_iMAC32,
2675 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2676 Requires<[IsARM, NoV6]> {
2678 let Inst{15-12} = Ra;
2680 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2681 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2682 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2683 Requires<[IsARM, HasV6]> {
2685 let Inst{15-12} = Ra;
2688 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2689 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2690 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2691 Requires<[IsARM, HasV6T2]> {
2696 let Inst{19-16} = Rd;
2697 let Inst{15-12} = Ra;
2698 let Inst{11-8} = Rm;
2702 // Extra precision multiplies with low / high results
2704 let neverHasSideEffects = 1 in {
2705 let isCommutable = 1 in {
2706 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2707 def SMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2708 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2709 Size4Bytes, IIC_iMUL64, []>,
2710 Requires<[IsARM, NoV6]>;
2712 def UMULLv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2713 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2714 Size4Bytes, IIC_iMUL64, []>,
2715 Requires<[IsARM, NoV6]>;
2718 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2719 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2720 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2721 Requires<[IsARM, HasV6]>;
2723 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2724 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2725 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2726 Requires<[IsARM, HasV6]>;
2729 // Multiply + accumulate
2730 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
2731 def SMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2732 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2733 Size4Bytes, IIC_iMAC64, []>,
2734 Requires<[IsARM, NoV6]>;
2735 def UMLALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2736 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2737 Size4Bytes, IIC_iMAC64, []>,
2738 Requires<[IsARM, NoV6]>;
2739 def UMAALv5 : ARMPseudoInst<(outs GPR:$RdLo, GPR:$RdHi),
2740 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
2741 Size4Bytes, IIC_iMAC64, []>,
2742 Requires<[IsARM, NoV6]>;
2746 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2747 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2748 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2749 Requires<[IsARM, HasV6]>;
2750 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2751 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2752 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2753 Requires<[IsARM, HasV6]>;
2755 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2756 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2757 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2758 Requires<[IsARM, HasV6]> {
2763 let Inst{19-16} = RdLo;
2764 let Inst{15-12} = RdHi;
2765 let Inst{11-8} = Rm;
2768 } // neverHasSideEffects
2770 // Most significant word multiply
2771 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2772 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2773 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2774 Requires<[IsARM, HasV6]> {
2775 let Inst{15-12} = 0b1111;
2778 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2779 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2780 [/* For disassembly only; pattern left blank */]>,
2781 Requires<[IsARM, HasV6]> {
2782 let Inst{15-12} = 0b1111;
2785 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2786 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2787 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2788 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2789 Requires<[IsARM, HasV6]>;
2791 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2792 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2793 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2794 [/* For disassembly only; pattern left blank */]>,
2795 Requires<[IsARM, HasV6]>;
2797 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2798 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2799 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2800 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2801 Requires<[IsARM, HasV6]>;
2803 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2804 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2805 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2806 [/* For disassembly only; pattern left blank */]>,
2807 Requires<[IsARM, HasV6]>;
2809 multiclass AI_smul<string opc, PatFrag opnode> {
2810 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2811 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2812 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2813 (sext_inreg GPR:$Rm, i16)))]>,
2814 Requires<[IsARM, HasV5TE]>;
2816 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2817 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2818 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2819 (sra GPR:$Rm, (i32 16))))]>,
2820 Requires<[IsARM, HasV5TE]>;
2822 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2823 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2824 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2825 (sext_inreg GPR:$Rm, i16)))]>,
2826 Requires<[IsARM, HasV5TE]>;
2828 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2829 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2830 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2831 (sra GPR:$Rm, (i32 16))))]>,
2832 Requires<[IsARM, HasV5TE]>;
2834 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2835 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2836 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2837 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2838 Requires<[IsARM, HasV5TE]>;
2840 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2841 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2842 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2843 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2844 Requires<[IsARM, HasV5TE]>;
2848 multiclass AI_smla<string opc, PatFrag opnode> {
2849 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2850 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2851 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2852 [(set GPR:$Rd, (add GPR:$Ra,
2853 (opnode (sext_inreg GPR:$Rn, i16),
2854 (sext_inreg GPR:$Rm, i16))))]>,
2855 Requires<[IsARM, HasV5TE]>;
2857 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2858 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2859 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2860 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2861 (sra GPR:$Rm, (i32 16)))))]>,
2862 Requires<[IsARM, HasV5TE]>;
2864 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2865 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2866 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2867 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2868 (sext_inreg GPR:$Rm, i16))))]>,
2869 Requires<[IsARM, HasV5TE]>;
2871 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2872 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2873 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2874 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2875 (sra GPR:$Rm, (i32 16)))))]>,
2876 Requires<[IsARM, HasV5TE]>;
2878 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2879 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2880 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2881 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2882 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2883 Requires<[IsARM, HasV5TE]>;
2885 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2886 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2887 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2888 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2889 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2890 Requires<[IsARM, HasV5TE]>;
2893 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2894 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2896 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2897 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2898 (ins GPR:$Rn, GPR:$Rm),
2899 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2900 [/* For disassembly only; pattern left blank */]>,
2901 Requires<[IsARM, HasV5TE]>;
2903 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2904 (ins GPR:$Rn, GPR:$Rm),
2905 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2906 [/* For disassembly only; pattern left blank */]>,
2907 Requires<[IsARM, HasV5TE]>;
2909 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2910 (ins GPR:$Rn, GPR:$Rm),
2911 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2912 [/* For disassembly only; pattern left blank */]>,
2913 Requires<[IsARM, HasV5TE]>;
2915 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2916 (ins GPR:$Rn, GPR:$Rm),
2917 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2918 [/* For disassembly only; pattern left blank */]>,
2919 Requires<[IsARM, HasV5TE]>;
2921 // Helper class for AI_smld -- for disassembly only
2922 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2923 InstrItinClass itin, string opc, string asm>
2924 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2931 let Inst{21-20} = 0b00;
2932 let Inst{22} = long;
2933 let Inst{27-23} = 0b01110;
2934 let Inst{11-8} = Rm;
2937 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2938 InstrItinClass itin, string opc, string asm>
2939 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2941 let Inst{15-12} = 0b1111;
2942 let Inst{19-16} = Rd;
2944 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2945 InstrItinClass itin, string opc, string asm>
2946 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2948 let Inst{15-12} = Ra;
2950 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2951 InstrItinClass itin, string opc, string asm>
2952 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2955 let Inst{19-16} = RdHi;
2956 let Inst{15-12} = RdLo;
2959 multiclass AI_smld<bit sub, string opc> {
2961 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2962 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2964 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2965 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2967 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2968 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2969 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2971 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2972 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2973 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2977 defm SMLA : AI_smld<0, "smla">;
2978 defm SMLS : AI_smld<1, "smls">;
2980 multiclass AI_sdml<bit sub, string opc> {
2982 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2983 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2984 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2985 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2988 defm SMUA : AI_sdml<0, "smua">;
2989 defm SMUS : AI_sdml<1, "smus">;
2991 //===----------------------------------------------------------------------===//
2992 // Misc. Arithmetic Instructions.
2995 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2996 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2997 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2999 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3000 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3001 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3002 Requires<[IsARM, HasV6T2]>;
3004 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3005 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3006 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3008 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3009 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3011 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
3012 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
3013 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
3014 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
3015 Requires<[IsARM, HasV6]>;
3017 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3018 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3021 (or (srl GPR:$Rm, (i32 8)),
3022 (shl GPR:$Rm, (i32 8))), i16))]>,
3023 Requires<[IsARM, HasV6]>;
3025 def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
3026 (shl GPR:$Rm, (i32 8))), i16),
3029 // Need the AddedComplexity or else MOVs + REV would be chosen.
3030 let AddedComplexity = 5 in
3031 def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;
3033 def lsl_shift_imm : SDNodeXForm<imm, [{
3034 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
3035 return CurDAG->getTargetConstant(Sh, MVT::i32);
3038 def lsl_amt : ImmLeaf<i32, [{
3039 return Imm > 0 && Imm < 32;
3042 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3043 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3044 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3045 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3046 (and (shl GPR:$Rm, lsl_amt:$sh),
3048 Requires<[IsARM, HasV6]>;
3050 // Alternate cases for PKHBT where identities eliminate some nodes.
3051 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3052 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3053 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3054 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
3056 def asr_shift_imm : SDNodeXForm<imm, [{
3057 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
3058 return CurDAG->getTargetConstant(Sh, MVT::i32);
3061 def asr_amt : ImmLeaf<i32, [{
3062 return Imm > 0 && Imm <= 32;
3065 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3066 // will match the pattern below.
3067 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3068 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
3069 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3070 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3071 (and (sra GPR:$Rm, asr_amt:$sh),
3073 Requires<[IsARM, HasV6]>;
3075 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3076 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3077 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3078 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
3079 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3080 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3081 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
3083 //===----------------------------------------------------------------------===//
3084 // Comparison Instructions...
3087 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3088 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3089 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3091 // ARMcmpZ can re-use the above instruction definitions.
3092 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3093 (CMPri GPR:$src, so_imm:$imm)>;
3094 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3095 (CMPrr GPR:$src, GPR:$rhs)>;
3096 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
3097 (CMPrs GPR:$src, so_reg:$rhs)>;
3099 // FIXME: We have to be careful when using the CMN instruction and comparison
3100 // with 0. One would expect these two pieces of code should give identical
3116 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3117 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3118 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3119 // value of r0 and the carry bit (because the "carry bit" parameter to
3120 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3121 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3122 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3123 // parameter to AddWithCarry is defined as 0).
3125 // When x is 0 and unsigned:
3129 // ~x + 1 = 0x1 0000 0000
3130 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3132 // Therefore, we should disable CMN when comparing against zero, until we can
3133 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3134 // when it's a comparison which doesn't look at the 'carry' flag).
3136 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3138 // This is related to <rdar://problem/7569620>.
3140 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3141 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
3143 // Note that TST/TEQ don't set all the same flags that CMP does!
3144 defm TST : AI1_cmp_irs<0b1000, "tst",
3145 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3146 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
3147 defm TEQ : AI1_cmp_irs<0b1001, "teq",
3148 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
3149 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
3151 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
3152 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3153 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
3155 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
3156 // (CMNri GPR:$src, so_imm_neg:$imm)>;
3158 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
3159 (CMNzri GPR:$src, so_imm_neg:$imm)>;
3161 // Pseudo i64 compares for some floating point compares.
3162 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
3164 def BCCi64 : PseudoInst<(outs),
3165 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
3167 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
3169 def BCCZi64 : PseudoInst<(outs),
3170 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
3171 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
3172 } // usesCustomInserter
3175 // Conditional moves
3176 // FIXME: should be able to write a pattern for ARMcmov, but can't use
3177 // a two-value operand where a dag node expects two operands. :(
3178 let neverHasSideEffects = 1 in {
3179 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
3180 Size4Bytes, IIC_iCMOVr,
3181 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3182 RegConstraint<"$false = $Rd">;
3183 def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
3184 (ins GPR:$false, so_reg:$shift, pred:$p),
3185 Size4Bytes, IIC_iCMOVsr,
3186 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3187 RegConstraint<"$false = $Rd">;
3189 let isMoveImm = 1 in
3190 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
3191 (ins GPR:$false, i32imm_hilo16:$imm, pred:$p),
3192 Size4Bytes, IIC_iMOVi,
3194 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
3196 let isMoveImm = 1 in
3197 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
3198 (ins GPR:$false, so_imm:$imm, pred:$p),
3199 Size4Bytes, IIC_iCMOVi,
3200 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3201 RegConstraint<"$false = $Rd">;
3203 // Two instruction predicate mov immediate.
3204 let isMoveImm = 1 in
3205 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
3206 (ins GPR:$false, i32imm:$src, pred:$p),
3207 Size8Bytes, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3209 let isMoveImm = 1 in
3210 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
3211 (ins GPR:$false, so_imm:$imm, pred:$p),
3212 Size4Bytes, IIC_iCMOVi,
3213 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3214 RegConstraint<"$false = $Rd">;
3215 } // neverHasSideEffects
3217 //===----------------------------------------------------------------------===//
3218 // Atomic operations intrinsics
3221 def memb_opt : Operand<i32> {
3222 let PrintMethod = "printMemBOption";
3223 let ParserMatchClass = MemBarrierOptOperand;
3226 // memory barriers protect the atomic sequences
3227 let hasSideEffects = 1 in {
3228 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3229 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3230 Requires<[IsARM, HasDB]> {
3232 let Inst{31-4} = 0xf57ff05;
3233 let Inst{3-0} = opt;
3237 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3239 [/* For disassembly only; pattern left blank */]>,
3240 Requires<[IsARM, HasDB]> {
3242 let Inst{31-4} = 0xf57ff04;
3243 let Inst{3-0} = opt;
3246 // ISB has only full system option -- for disassembly only
3247 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3248 Requires<[IsARM, HasDB]> {
3249 let Inst{31-4} = 0xf57ff06;
3250 let Inst{3-0} = 0b1111;
3253 let usesCustomInserter = 1 in {
3254 let Uses = [CPSR] in {
3255 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3256 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3257 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3258 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3259 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3260 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3261 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3262 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3263 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3264 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3265 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3266 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3267 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3268 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3269 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3270 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3271 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3272 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3273 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
3274 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3275 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3276 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
3277 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3278 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3279 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
3280 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3281 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
3282 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
3283 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3284 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
3285 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3286 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3287 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3288 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3289 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3290 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3291 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3292 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3293 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3294 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3295 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3296 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3297 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3298 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3299 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3300 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3301 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3302 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3303 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
3304 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3305 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3306 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
3307 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3308 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3309 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
3310 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3311 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
3312 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
3313 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3314 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
3315 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3316 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3317 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3318 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3319 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3320 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3321 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3322 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3323 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3324 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3325 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3326 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3327 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3328 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3329 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3330 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3331 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3332 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3333 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
3334 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3335 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3336 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
3337 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3338 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3339 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
3340 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3341 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
3342 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
3343 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
3344 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
3346 def ATOMIC_SWAP_I8 : PseudoInst<
3347 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3348 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3349 def ATOMIC_SWAP_I16 : PseudoInst<
3350 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3351 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3352 def ATOMIC_SWAP_I32 : PseudoInst<
3353 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3354 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3356 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3357 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3358 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3359 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3360 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3361 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3362 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3363 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3364 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3368 let mayLoad = 1 in {
3369 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3370 "ldrexb", "\t$Rt, $addr", []>;
3371 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3372 "ldrexh", "\t$Rt, $addr", []>;
3373 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
3374 "ldrex", "\t$Rt, $addr", []>;
3375 let hasExtraDefRegAllocReq = 1 in
3376 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
3377 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
3380 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3381 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3382 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
3383 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3384 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
3385 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
3386 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
3389 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
3390 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3391 (ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
3392 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
3394 // Clear-Exclusive is for disassembly only.
3395 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3396 [/* For disassembly only; pattern left blank */]>,
3397 Requires<[IsARM, HasV7]> {
3398 let Inst{31-0} = 0b11110101011111111111000000011111;
3401 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3402 let mayLoad = 1 in {
3403 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3404 [/* For disassembly only; pattern left blank */]>;
3405 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3406 [/* For disassembly only; pattern left blank */]>;
3409 //===----------------------------------------------------------------------===//
3410 // Coprocessor Instructions.
3413 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3414 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3415 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3416 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3417 imm:$CRm, imm:$opc2)]> {
3425 let Inst{3-0} = CRm;
3427 let Inst{7-5} = opc2;
3428 let Inst{11-8} = cop;
3429 let Inst{15-12} = CRd;
3430 let Inst{19-16} = CRn;
3431 let Inst{23-20} = opc1;
3434 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
3435 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
3436 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
3437 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
3438 imm:$CRm, imm:$opc2)]> {
3439 let Inst{31-28} = 0b1111;
3447 let Inst{3-0} = CRm;
3449 let Inst{7-5} = opc2;
3450 let Inst{11-8} = cop;
3451 let Inst{15-12} = CRd;
3452 let Inst{19-16} = CRn;
3453 let Inst{23-20} = opc1;
3456 class ACI<dag oops, dag iops, string opc, string asm,
3457 IndexMode im = IndexModeNone>
3458 : InoP<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
3459 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3460 let Inst{27-25} = 0b110;
3463 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
3465 def _OFFSET : ACI<(outs),
3466 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3467 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
3468 let Inst{31-28} = op31_28;
3469 let Inst{24} = 1; // P = 1
3470 let Inst{21} = 0; // W = 0
3471 let Inst{22} = 0; // D = 0
3472 let Inst{20} = load;
3475 def _PRE : ACI<(outs),
3476 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3477 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
3478 let Inst{31-28} = op31_28;
3479 let Inst{24} = 1; // P = 1
3480 let Inst{21} = 1; // W = 1
3481 let Inst{22} = 0; // D = 0
3482 let Inst{20} = load;
3485 def _POST : ACI<(outs),
3486 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3487 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
3488 let Inst{31-28} = op31_28;
3489 let Inst{24} = 0; // P = 0
3490 let Inst{21} = 1; // W = 1
3491 let Inst{22} = 0; // D = 0
3492 let Inst{20} = load;
3495 def _OPTION : ACI<(outs),
3496 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
3498 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3499 let Inst{31-28} = op31_28;
3500 let Inst{24} = 0; // P = 0
3501 let Inst{23} = 1; // U = 1
3502 let Inst{21} = 0; // W = 0
3503 let Inst{22} = 0; // D = 0
3504 let Inst{20} = load;
3507 def L_OFFSET : ACI<(outs),
3508 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3509 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
3510 let Inst{31-28} = op31_28;
3511 let Inst{24} = 1; // P = 1
3512 let Inst{21} = 0; // W = 0
3513 let Inst{22} = 1; // D = 1
3514 let Inst{20} = load;
3517 def L_PRE : ACI<(outs),
3518 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3519 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
3521 let Inst{31-28} = op31_28;
3522 let Inst{24} = 1; // P = 1
3523 let Inst{21} = 1; // W = 1
3524 let Inst{22} = 1; // D = 1
3525 let Inst{20} = load;
3528 def L_POST : ACI<(outs),
3529 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
3530 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr",
3532 let Inst{31-28} = op31_28;
3533 let Inst{24} = 0; // P = 0
3534 let Inst{21} = 1; // W = 1
3535 let Inst{22} = 1; // D = 1
3536 let Inst{20} = load;
3539 def L_OPTION : ACI<(outs),
3540 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
3542 !strconcat(!strconcat(opc, "l"), cond),
3543 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
3544 let Inst{31-28} = op31_28;
3545 let Inst{24} = 0; // P = 0
3546 let Inst{23} = 1; // U = 1
3547 let Inst{21} = 0; // W = 0
3548 let Inst{22} = 1; // D = 1
3549 let Inst{20} = load;
3553 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
3554 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
3555 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
3556 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
3558 //===----------------------------------------------------------------------===//
3559 // Move between coprocessor and ARM core register -- for disassembly only
3562 class MovRCopro<string opc, bit direction, dag oops, dag iops,
3564 : ABI<0b1110, oops, iops, NoItinerary, opc,
3565 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
3566 let Inst{20} = direction;
3576 let Inst{15-12} = Rt;
3577 let Inst{11-8} = cop;
3578 let Inst{23-21} = opc1;
3579 let Inst{7-5} = opc2;
3580 let Inst{3-0} = CRm;
3581 let Inst{19-16} = CRn;
3584 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
3586 (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
3587 c_imm:$CRm, i32imm:$opc2),
3588 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3589 imm:$CRm, imm:$opc2)]>;
3590 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
3592 (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm,
3595 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
3596 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3598 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
3600 : ABXI<0b1110, oops, iops, NoItinerary,
3601 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
3602 let Inst{31-28} = 0b1111;
3603 let Inst{20} = direction;
3613 let Inst{15-12} = Rt;
3614 let Inst{11-8} = cop;
3615 let Inst{23-21} = opc1;
3616 let Inst{7-5} = opc2;
3617 let Inst{3-0} = CRm;
3618 let Inst{19-16} = CRn;
3621 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
3623 (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
3624 c_imm:$CRm, i32imm:$opc2),
3625 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3626 imm:$CRm, imm:$opc2)]>;
3627 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
3629 (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm,
3632 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
3633 imm:$CRm, imm:$opc2),
3634 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
3636 class MovRRCopro<string opc, bit direction,
3637 list<dag> pattern = [/* For disassembly only */]>
3638 : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3639 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3640 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
3641 let Inst{23-21} = 0b010;
3642 let Inst{20} = direction;
3650 let Inst{15-12} = Rt;
3651 let Inst{19-16} = Rt2;
3652 let Inst{11-8} = cop;
3653 let Inst{7-4} = opc1;
3654 let Inst{3-0} = CRm;
3657 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
3658 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3660 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
3662 class MovRRCopro2<string opc, bit direction,
3663 list<dag> pattern = [/* For disassembly only */]>
3664 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
3665 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
3666 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3667 let Inst{31-28} = 0b1111;
3668 let Inst{23-21} = 0b010;
3669 let Inst{20} = direction;
3677 let Inst{15-12} = Rt;
3678 let Inst{19-16} = Rt2;
3679 let Inst{11-8} = cop;
3680 let Inst{7-4} = opc1;
3681 let Inst{3-0} = CRm;
3684 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
3685 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
3687 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
3689 //===----------------------------------------------------------------------===//
3690 // Move between special register and ARM core register -- for disassembly only
3693 // Move to ARM core register from Special Register
3694 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, cpsr",
3695 [/* For disassembly only; pattern left blank */]> {
3697 let Inst{23-16} = 0b00001111;
3698 let Inst{15-12} = Rd;
3699 let Inst{7-4} = 0b0000;
3702 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,"mrs","\t$Rd, spsr",
3703 [/* For disassembly only; pattern left blank */]> {
3705 let Inst{23-16} = 0b01001111;
3706 let Inst{15-12} = Rd;
3707 let Inst{7-4} = 0b0000;
3710 // Move from ARM core register to Special Register
3712 // No need to have both system and application versions, the encodings are the
3713 // same and the assembly parser has no way to distinguish between them. The mask
3714 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
3715 // the mask with the fields to be accessed in the special register.
3716 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
3717 "msr", "\t$mask, $Rn",
3718 [/* For disassembly only; pattern left blank */]> {
3723 let Inst{22} = mask{4}; // R bit
3724 let Inst{21-20} = 0b10;
3725 let Inst{19-16} = mask{3-0};
3726 let Inst{15-12} = 0b1111;
3727 let Inst{11-4} = 0b00000000;
3731 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
3732 "msr", "\t$mask, $a",
3733 [/* For disassembly only; pattern left blank */]> {
3738 let Inst{22} = mask{4}; // R bit
3739 let Inst{21-20} = 0b10;
3740 let Inst{19-16} = mask{3-0};
3741 let Inst{15-12} = 0b1111;
3745 //===----------------------------------------------------------------------===//
3749 // __aeabi_read_tp preserves the registers r1-r3.
3750 // This is a pseudo inst so that we can get the encoding right,
3751 // complete with fixup for the aeabi_read_tp function.
3753 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3754 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3755 [(set R0, ARMthread_pointer)]>;
3758 //===----------------------------------------------------------------------===//
3759 // SJLJ Exception handling intrinsics
3760 // eh_sjlj_setjmp() is an instruction sequence to store the return
3761 // address and save #0 in R0 for the non-longjmp case.
3762 // Since by its nature we may be coming from some other function to get
3763 // here, and we're using the stack frame for the containing function to
3764 // save/restore registers, we can't keep anything live in regs across
3765 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3766 // when we get here from a longjmp(). We force everything out of registers
3767 // except for our own input by listing the relevant registers in Defs. By
3768 // doing so, we also cause the prologue/epilogue code to actively preserve
3769 // all of the callee-saved resgisters, which is exactly what we want.
3770 // A constant value is passed in $val, and we use the location as a scratch.
3772 // These are pseudo-instructions and are lowered to individual MC-insts, so
3773 // no encoding information is necessary.
3775 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
3776 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1 in {
3777 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3779 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3780 Requires<[IsARM, HasVFP2]>;
3784 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
3785 hasSideEffects = 1, isBarrier = 1 in {
3786 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3788 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3789 Requires<[IsARM, NoVFP]>;
3792 // FIXME: Non-Darwin version(s)
3793 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3794 Defs = [ R7, LR, SP ] in {
3795 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3797 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3798 Requires<[IsARM, IsDarwin]>;
3801 // eh.sjlj.dispatchsetup pseudo-instruction.
3802 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3803 // handled when the pseudo is expanded (which happens before any passes
3804 // that need the instruction size).
3805 let isBarrier = 1, hasSideEffects = 1 in
3806 def Int_eh_sjlj_dispatchsetup :
3807 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3808 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3809 Requires<[IsDarwin]>;
3811 //===----------------------------------------------------------------------===//
3812 // Non-Instruction Patterns
3815 // Large immediate handling.
3817 // 32-bit immediate using two piece so_imms or movw + movt.
3818 // This is a single pseudo instruction, the benefit is that it can be remat'd
3819 // as a single unit instead of having to handle reg inputs.
3820 // FIXME: Remove this when we can do generalized remat.
3821 let isReMaterializable = 1, isMoveImm = 1 in
3822 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3823 [(set GPR:$dst, (arm_i32imm:$src))]>,
3826 // Pseudo instruction that combines movw + movt + add pc (if PIC).
3827 // It also makes it possible to rematerialize the instructions.
3828 // FIXME: Remove this when we can do generalized remat and when machine licm
3829 // can properly the instructions.
3830 let isReMaterializable = 1 in {
3831 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3833 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
3834 Requires<[IsARM, UseMovt]>;
3836 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3838 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
3839 Requires<[IsARM, UseMovt]>;
3841 let AddedComplexity = 10 in
3842 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
3844 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
3845 Requires<[IsARM, UseMovt]>;
3846 } // isReMaterializable
3848 // ConstantPool, GlobalAddress, and JumpTable
3849 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3850 Requires<[IsARM, DontUseMovt]>;
3851 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3852 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3853 Requires<[IsARM, UseMovt]>;
3854 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3855 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3857 // TODO: add,sub,and, 3-instr forms?
3860 def : ARMPat<(ARMtcret tcGPR:$dst),
3861 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3863 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3864 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3866 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3867 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3869 def : ARMPat<(ARMtcret tcGPR:$dst),
3870 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3872 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3873 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3875 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3876 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3879 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3880 Requires<[IsARM, IsNotDarwin]>;
3881 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3882 Requires<[IsARM, IsDarwin]>;
3884 // zextload i1 -> zextload i8
3885 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3886 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3888 // extload -> zextload
3889 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3890 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3891 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3892 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3894 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3896 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3897 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3900 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3901 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3902 (SMULBB GPR:$a, GPR:$b)>;
3903 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3904 (SMULBB GPR:$a, GPR:$b)>;
3905 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3906 (sra GPR:$b, (i32 16))),
3907 (SMULBT GPR:$a, GPR:$b)>;
3908 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3909 (SMULBT GPR:$a, GPR:$b)>;
3910 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3911 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3912 (SMULTB GPR:$a, GPR:$b)>;
3913 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3914 (SMULTB GPR:$a, GPR:$b)>;
3915 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3917 (SMULWB GPR:$a, GPR:$b)>;
3918 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3919 (SMULWB GPR:$a, GPR:$b)>;
3921 def : ARMV5TEPat<(add GPR:$acc,
3922 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3923 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3924 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3925 def : ARMV5TEPat<(add GPR:$acc,
3926 (mul sext_16_node:$a, sext_16_node:$b)),
3927 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3928 def : ARMV5TEPat<(add GPR:$acc,
3929 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3930 (sra GPR:$b, (i32 16)))),
3931 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3932 def : ARMV5TEPat<(add GPR:$acc,
3933 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3934 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3935 def : ARMV5TEPat<(add GPR:$acc,
3936 (mul (sra GPR:$a, (i32 16)),
3937 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3938 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3939 def : ARMV5TEPat<(add GPR:$acc,
3940 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3941 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3942 def : ARMV5TEPat<(add GPR:$acc,
3943 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3945 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3946 def : ARMV5TEPat<(add GPR:$acc,
3947 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3948 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3951 // Pre-v7 uses MCR for synchronization barriers.
3952 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
3953 Requires<[IsARM, HasV6]>;
3956 //===----------------------------------------------------------------------===//
3960 include "ARMInstrThumb.td"
3962 //===----------------------------------------------------------------------===//
3966 include "ARMInstrThumb2.td"
3968 //===----------------------------------------------------------------------===//
3969 // Floating Point Support
3972 include "ARMInstrVFP.td"
3974 //===----------------------------------------------------------------------===//
3975 // Advanced SIMD (NEON) Support
3978 include "ARMInstrNEON.td"