1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the "Instituto Nokia de Tecnologia" and
6 // is distributed under the University of Illinois Open Source
7 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
11 // This file describes the ARM instructions in TableGen format.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // ARM specific DAG Nodes.
20 def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
39 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
40 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
42 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
45 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
46 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
48 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
49 [SDNPHasChain, SDNPOutFlag]>;
50 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
51 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
53 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
54 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
55 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
59 [SDNPHasChain, SDNPOptInFlag]>;
61 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
63 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
66 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
67 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
69 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
72 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
75 def ARMcmpNZ : SDNode<"ARMISD::CMPNZ", SDT_ARMCmp,
78 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
80 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
81 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
82 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
84 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
86 //===----------------------------------------------------------------------===//
87 // ARM Instruction Predicate Definitions.
89 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
90 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
91 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
92 def IsThumb : Predicate<"Subtarget->isThumb()">;
93 def IsARM : Predicate<"!Subtarget->isThumb()">;
95 //===----------------------------------------------------------------------===//
96 // ARM Flag Definitions.
98 class RegConstraint<string C> {
99 string Constraints = C;
102 //===----------------------------------------------------------------------===//
103 // ARM specific transformation functions and pattern fragments.
106 // so_imm_XFORM - Return a so_imm value packed into the format described for
108 def so_imm_XFORM : SDNodeXForm<imm, [{
109 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(N->getValue()),
113 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
114 // so_imm_neg def below.
115 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
116 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(-(int)N->getValue()),
120 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
121 // so_imm_not def below.
122 def so_imm_not_XFORM : SDNodeXForm<imm, [{
123 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(~(int)N->getValue()),
127 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
128 def rot_imm : PatLeaf<(i32 imm), [{
129 int32_t v = (int32_t)N->getValue();
130 return v == 8 || v == 16 || v == 24;
133 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
134 def imm1_15 : PatLeaf<(i32 imm), [{
135 return (int32_t)N->getValue() >= 1 && (int32_t)N->getValue() < 16;
138 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
139 def imm16_31 : PatLeaf<(i32 imm), [{
140 return (int32_t)N->getValue() >= 16 && (int32_t)N->getValue() < 32;
144 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(-(int)N->getValue()) != -1; }],
148 PatLeaf<(imm), [{ return ARM_AM::getSOImmVal(~(int)N->getValue()) != -1; }],
151 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
152 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
153 return TLI.ComputeNumSignBits(SDOperand(N,0)) >= 17;
158 //===----------------------------------------------------------------------===//
159 // Operand Definitions.
163 def brtarget : Operand<OtherVT>;
165 // Operand for printing out a condition code.
166 def CCOp : Operand<i32> {
167 let PrintMethod = "printCCOperand";
170 // A list of registers separated by comma. Used by load/store multiple.
171 def reglist : Operand<i32> {
172 let PrintMethod = "printRegisterList";
175 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
176 def cpinst_operand : Operand<i32> {
177 let PrintMethod = "printCPInstOperand";
180 def jtblock_operand : Operand<i32> {
181 let PrintMethod = "printJTBlockOperand";
185 def pclabel : Operand<i32> {
186 let PrintMethod = "printPCLabel";
189 // shifter_operand operands: so_reg and so_imm.
190 def so_reg : Operand<i32>, // reg reg imm
191 ComplexPattern<i32, 3, "SelectShifterOperandReg",
192 [shl,srl,sra,rotr]> {
193 let PrintMethod = "printSORegOperand";
194 let MIOperandInfo = (ops GPR, GPR, i32imm);
197 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
198 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
199 // represented in the imm field in the same 12-bit form that they are encoded
200 // into so_imm instructions: the 8-bit immediate is the least significant bits
201 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
202 def so_imm : Operand<i32>,
204 [{ return ARM_AM::getSOImmVal(N->getValue()) != -1; }],
206 let PrintMethod = "printSOImmOperand";
209 // Break so_imm's up into two pieces. This handles immediates with up to 16
210 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
211 // get the first/second pieces.
212 def so_imm2part : Operand<i32>,
214 [{ return ARM_AM::isSOImmTwoPartVal((unsigned)N->getValue()); }]> {
215 let PrintMethod = "printSOImm2PartOperand";
218 def so_imm2part_1 : SDNodeXForm<imm, [{
219 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getValue());
220 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
223 def so_imm2part_2 : SDNodeXForm<imm, [{
224 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getValue());
225 return CurDAG->getTargetConstant(ARM_AM::getSOImmVal(V), MVT::i32);
229 // Define ARM specific addressing modes.
231 // addrmode2 := reg +/- reg shop imm
232 // addrmode2 := reg +/- imm12
234 def addrmode2 : Operand<i32>,
235 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
236 let PrintMethod = "printAddrMode2Operand";
237 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
240 def am2offset : Operand<i32>,
241 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
242 let PrintMethod = "printAddrMode2OffsetOperand";
243 let MIOperandInfo = (ops GPR, i32imm);
246 // addrmode3 := reg +/- reg
247 // addrmode3 := reg +/- imm8
249 def addrmode3 : Operand<i32>,
250 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
251 let PrintMethod = "printAddrMode3Operand";
252 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
255 def am3offset : Operand<i32>,
256 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
257 let PrintMethod = "printAddrMode3OffsetOperand";
258 let MIOperandInfo = (ops GPR, i32imm);
261 // addrmode4 := reg, <mode|W>
263 def addrmode4 : Operand<i32>,
264 ComplexPattern<i32, 2, "", []> {
265 let PrintMethod = "printAddrMode4Operand";
266 let MIOperandInfo = (ops GPR, i32imm);
269 // addrmode5 := reg +/- imm8*4
271 def addrmode5 : Operand<i32>,
272 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
273 let PrintMethod = "printAddrMode5Operand";
274 let MIOperandInfo = (ops GPR, i32imm);
277 // addrmodepc := pc + reg
279 def addrmodepc : Operand<i32>,
280 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
281 let PrintMethod = "printAddrModePCOperand";
282 let MIOperandInfo = (ops GPR, i32imm);
285 //===----------------------------------------------------------------------===//
286 // ARM Instruction flags. These need to match ARMInstrInfo.h.
290 class AddrMode<bits<4> val> {
293 def AddrModeNone : AddrMode<0>;
294 def AddrMode1 : AddrMode<1>;
295 def AddrMode2 : AddrMode<2>;
296 def AddrMode3 : AddrMode<3>;
297 def AddrMode4 : AddrMode<4>;
298 def AddrMode5 : AddrMode<5>;
299 def AddrModeT1 : AddrMode<6>;
300 def AddrModeT2 : AddrMode<7>;
301 def AddrModeT4 : AddrMode<8>;
302 def AddrModeTs : AddrMode<9>;
305 class SizeFlagVal<bits<3> val> {
308 def SizeInvalid : SizeFlagVal<0>; // Unset.
309 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
310 def Size8Bytes : SizeFlagVal<2>;
311 def Size4Bytes : SizeFlagVal<3>;
312 def Size2Bytes : SizeFlagVal<4>;
314 // Load / store index mode.
315 class IndexMode<bits<2> val> {
318 def IndexModeNone : IndexMode<0>;
319 def IndexModePre : IndexMode<1>;
320 def IndexModePost : IndexMode<2>;
322 //===----------------------------------------------------------------------===//
323 // ARM Instruction templates.
326 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
327 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
328 list<Predicate> Predicates = [IsARM];
330 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
331 list<Predicate> Predicates = [IsARM, HasV5TE];
333 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
334 list<Predicate> Predicates = [IsARM, HasV6];
337 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
338 dag ops, string asmstr, string cstr>
340 let Namespace = "ARM";
342 bits<4> Opcode = opcod;
344 bits<4> AddrModeBits = AM.Value;
347 bits<3> SizeFlag = SZ.Value;
350 bits<2> IndexModeBits = IM.Value;
352 dag OperandList = ops;
353 let AsmString = asmstr;
354 let Constraints = cstr;
357 class PseudoInst<dag ops, string asm, list<dag> pattern>
358 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, ops, asm, ""> {
359 let Pattern = pattern;
362 class I<dag ops, AddrMode am, SizeFlagVal sz, IndexMode im,
363 string asm, string cstr, list<dag> pattern>
364 // FIXME: Set all opcodes to 0 for now.
365 : InstARM<0, am, sz, im, ops, asm, cstr> {
366 let Pattern = pattern;
367 list<Predicate> Predicates = [IsARM];
370 class AI<dag ops, string asm, list<dag> pattern>
371 : I<ops, AddrModeNone, Size4Bytes, IndexModeNone, asm, "", pattern>;
372 class AI1<dag ops, string asm, list<dag> pattern>
373 : I<ops, AddrMode1, Size4Bytes, IndexModeNone, asm, "", pattern>;
374 class AI2<dag ops, string asm, list<dag> pattern>
375 : I<ops, AddrMode2, Size4Bytes, IndexModeNone, asm, "", pattern>;
376 class AI3<dag ops, string asm, list<dag> pattern>
377 : I<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
378 class AI4<dag ops, string asm, list<dag> pattern>
379 : I<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
380 class AIx2<dag ops, string asm, list<dag> pattern>
381 : I<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
382 class AI1x2<dag ops, string asm, list<dag> pattern>
383 : I<ops, AddrMode1, Size8Bytes, IndexModeNone, asm, "", pattern>;
386 class AI2pr<dag ops, string asm, string cstr, list<dag> pattern>
387 : I<ops, AddrMode2, Size4Bytes, IndexModePre, asm, cstr, pattern>;
388 class AI3pr<dag ops, string asm, string cstr, list<dag> pattern>
389 : I<ops, AddrMode3, Size4Bytes, IndexModePre, asm, cstr, pattern>;
392 class AI2po<dag ops, string asm, string cstr, list<dag> pattern>
393 : I<ops, AddrMode2, Size4Bytes, IndexModePost, asm, cstr, pattern>;
394 class AI3po<dag ops, string asm, string cstr, list<dag> pattern>
395 : I<ops, AddrMode3, Size4Bytes, IndexModePost, asm, cstr, pattern>;
397 // BR_JT instructions
398 class JTI<dag ops, string asm, list<dag> pattern>
399 : I<ops, AddrModeNone, SizeSpecial, IndexModeNone, asm, "", pattern>;
400 class JTI1<dag ops, string asm, list<dag> pattern>
401 : I<ops, AddrMode1, SizeSpecial, IndexModeNone, asm, "", pattern>;
402 class JTI2<dag ops, string asm, list<dag> pattern>
403 : I<ops, AddrMode2, SizeSpecial, IndexModeNone, asm, "", pattern>;
406 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
407 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
410 /// AI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
411 /// binop that produces a value.
412 multiclass AI1_bin_irs<string opc, PatFrag opnode> {
413 def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
414 !strconcat(opc, " $dst, $a, $b"),
415 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
416 def rr : AI1<(ops GPR:$dst, GPR:$a, GPR:$b),
417 !strconcat(opc, " $dst, $a, $b"),
418 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
419 def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
420 !strconcat(opc, " $dst, $a, $b"),
421 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
424 /// AI1_bin0_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns.
425 /// Similar to AI1_bin_irs except the instruction does not produce a result.
426 multiclass AI1_bin0_irs<string opc, PatFrag opnode> {
427 def ri : AI1<(ops GPR:$a, so_imm:$b),
428 !strconcat(opc, " $a, $b"),
429 [(opnode GPR:$a, so_imm:$b)]>;
430 def rr : AI1<(ops GPR:$a, GPR:$b),
431 !strconcat(opc, " $a, $b"),
432 [(opnode GPR:$a, GPR:$b)]>;
433 def rs : AI1<(ops GPR:$a, so_reg:$b),
434 !strconcat(opc, " $a, $b"),
435 [(opnode GPR:$a, so_reg:$b)]>;
438 /// AI1_bin_is - Defines a set of (op r, {so_imm|so_reg}) patterns for a binop.
439 multiclass AI1_bin_is<string opc, PatFrag opnode> {
440 def ri : AI1<(ops GPR:$dst, GPR:$a, so_imm:$b),
441 !strconcat(opc, " $dst, $a, $b"),
442 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
443 def rs : AI1<(ops GPR:$dst, GPR:$a, so_reg:$b),
444 !strconcat(opc, " $dst, $a, $b"),
445 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
448 /// AI1_unary_irs - Defines a set of (op {so_imm|r|so_reg}) patterns for unary
450 multiclass AI1_unary_irs<string opc, PatFrag opnode> {
451 def i : AI1<(ops GPR:$dst, so_imm:$a),
452 !strconcat(opc, " $dst, $a"),
453 [(set GPR:$dst, (opnode so_imm:$a))]>;
454 def r : AI1<(ops GPR:$dst, GPR:$a),
455 !strconcat(opc, " $dst, $a"),
456 [(set GPR:$dst, (opnode GPR:$a))]>;
457 def s : AI1<(ops GPR:$dst, so_reg:$a),
458 !strconcat(opc, " $dst, $a"),
459 [(set GPR:$dst, (opnode so_reg:$a))]>;
462 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
463 /// register and one whose operand is a register rotated by 8/16/24.
464 multiclass AI_unary_rrot<string opc, PatFrag opnode> {
465 def r : AI<(ops GPR:$dst, GPR:$Src),
466 !strconcat(opc, " $dst, $Src"),
467 [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
468 def r_rot : AI<(ops GPR:$dst, GPR:$Src, i32imm:$rot),
469 !strconcat(opc, " $dst, $Src, ror $rot"),
470 [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
471 Requires<[IsARM, HasV6]>;
474 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
475 /// register and one whose operand is a register rotated by 8/16/24.
476 multiclass AI_bin_rrot<string opc, PatFrag opnode> {
477 def rr : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS),
478 !strconcat(opc, " $dst, $LHS, $RHS"),
479 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
480 Requires<[IsARM, HasV6]>;
481 def rr_rot : AI<(ops GPR:$dst, GPR:$LHS, GPR:$RHS, i32imm:$rot),
482 !strconcat(opc, " $dst, $LHS, $RHS, ror $rot"),
483 [(set GPR:$dst, (opnode GPR:$LHS,
484 (rotr GPR:$RHS, rot_imm:$rot)))]>,
485 Requires<[IsARM, HasV6]>;
489 //===----------------------------------------------------------------------===//
491 //===----------------------------------------------------------------------===//
493 //===----------------------------------------------------------------------===//
494 // Miscellaneous Instructions.
496 def IMPLICIT_DEF_GPR :
497 PseudoInst<(ops GPR:$rD),
498 "@ IMPLICIT_DEF_GPR $rD",
499 [(set GPR:$rD, (undef))]>;
502 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
503 /// the function. The first operand is the ID# for this instruction, the second
504 /// is the index into the MachineConstantPool that this is, the third is the
505 /// size in bytes of this constant pool entry.
506 def CONSTPOOL_ENTRY :
507 PseudoInst<(ops cpinst_operand:$instid, cpinst_operand:$cpidx, i32imm:$size),
508 "${instid:label} ${cpidx:cpentry}", []>;
511 PseudoInst<(ops i32imm:$amt),
512 "@ ADJCALLSTACKUP $amt",
513 [(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>;
515 def ADJCALLSTACKDOWN :
516 PseudoInst<(ops i32imm:$amt),
517 "@ ADJCALLSTACKDOWN $amt",
518 [(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>;
521 PseudoInst<(ops i32imm:$line, i32imm:$col, i32imm:$file),
522 ".loc $file, $line, $col",
523 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
525 def PICADD : AI1<(ops GPR:$dst, GPR:$a, pclabel:$cp),
526 "$cp:\n\tadd $dst, pc, $a",
527 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
528 let AddedComplexity = 10 in
529 def PICLD : AI2<(ops GPR:$dst, addrmodepc:$addr),
530 "${addr:label}:\n\tldr $dst, $addr",
531 [(set GPR:$dst, (load addrmodepc:$addr))]>;
533 //===----------------------------------------------------------------------===//
534 // Control Flow Instructions.
537 let isReturn = 1, isTerminator = 1 in
538 def BX_RET : AI<(ops), "bx lr", [(ARMretflag)]>;
540 // FIXME: remove when we have a way to marking a MI with these properties.
541 let isLoad = 1, isReturn = 1, isTerminator = 1 in
542 def LDM_RET : AI4<(ops addrmode4:$addr, reglist:$dst1, variable_ops),
543 "ldm${addr:submode} $addr, $dst1",
546 let isCall = 1, noResults = 1,
547 Defs = [R0, R1, R2, R3, R12, LR,
548 D0, D1, D2, D3, D4, D5, D6, D7] in {
549 def BL : AI<(ops i32imm:$func, variable_ops),
551 [(ARMcall tglobaladdr:$func)]>;
553 def BLX : AI<(ops GPR:$dst, variable_ops),
555 [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
558 def BX : AIx2<(ops GPR:$dst, variable_ops),
559 "mov lr, pc\n\tbx $dst",
560 [(ARMcall_nolink GPR:$dst)]>;
564 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
565 def B : AI<(ops brtarget:$dst), "b $dst",
568 def BR_JTr : JTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
569 "mov pc, $dst \n$jt",
570 [(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>;
571 def BR_JTm : JTI2<(ops addrmode2:$dst, jtblock_operand:$jt, i32imm:$id),
572 "ldr pc, $dst \n$jt",
573 [(ARMbrjt (i32 (load addrmode2:$dst)), tjumptable:$jt,
575 def BR_JTadd : JTI1<(ops GPR:$dst, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
576 "add pc, $dst, $idx \n$jt",
577 [(ARMbrjt (add GPR:$dst, GPR:$idx), tjumptable:$jt,
581 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in
582 def Bcc : AI<(ops brtarget:$dst, CCOp:$cc), "b$cc $dst",
583 [(ARMbrcond bb:$dst, imm:$cc)]>;
585 //===----------------------------------------------------------------------===//
586 // Load / store Instructions.
591 def LDR : AI2<(ops GPR:$dst, addrmode2:$addr),
593 [(set GPR:$dst, (load addrmode2:$addr))]>;
595 // Special LDR for loads from non-pc-relative constpools.
596 let isReMaterializable = 1 in
597 def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr),
598 "ldr $dst, $addr", []>;
600 // Loads with zero extension
601 def LDRH : AI3<(ops GPR:$dst, addrmode3:$addr),
603 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
605 def LDRB : AI2<(ops GPR:$dst, addrmode2:$addr),
607 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
609 // Loads with sign extension
610 def LDRSH : AI3<(ops GPR:$dst, addrmode3:$addr),
612 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
614 def LDRSB : AI3<(ops GPR:$dst, addrmode3:$addr),
616 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
619 def LDRD : AI3<(ops GPR:$dst, addrmode3:$addr),
621 []>, Requires<[IsARM, HasV5T]>;
624 def LDR_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr),
625 "ldr $dst, $addr!", "$addr.base = $base_wb", []>;
627 def LDR_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base, am2offset:$offset),
628 "ldr $dst, [$base], $offset", "$base = $base_wb", []>;
630 def LDRH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
631 "ldrh $dst, $addr!", "$addr.base = $base_wb", []>;
633 def LDRH_POST : AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
634 "ldrh $dst, [$base], $offset", "$base = $base_wb", []>;
636 def LDRB_PRE : AI2pr<(ops GPR:$dst, GPR:$base_wb, addrmode2:$addr),
637 "ldrb $dst, $addr!", "$addr.base = $base_wb", []>;
639 def LDRB_POST : AI2po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am2offset:$offset),
640 "ldrb $dst, [$base], $offset", "$base = $base_wb", []>;
642 def LDRSH_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
643 "ldrsh $dst, $addr!", "$addr.base = $base_wb", []>;
645 def LDRSH_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
646 "ldrsh $dst, [$base], $offset", "$base = $base_wb", []>;
648 def LDRSB_PRE : AI3pr<(ops GPR:$dst, GPR:$base_wb, addrmode3:$addr),
649 "ldrsb $dst, $addr!", "$addr.base = $base_wb", []>;
651 def LDRSB_POST: AI3po<(ops GPR:$dst, GPR:$base_wb, GPR:$base,am3offset:$offset),
652 "ldrsb $dst, [$base], $offset", "$base = $base_wb", []>;
657 def STR : AI2<(ops GPR:$src, addrmode2:$addr),
659 [(store GPR:$src, addrmode2:$addr)]>;
661 // Stores with truncate
662 def STRH : AI3<(ops GPR:$src, addrmode3:$addr),
664 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
666 def STRB : AI2<(ops GPR:$src, addrmode2:$addr),
668 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
671 def STRD : AI3<(ops GPR:$src, addrmode3:$addr),
673 []>, Requires<[IsARM, HasV5T]>;
676 def STR_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base, am2offset:$offset),
677 "str $src, [$base, $offset]!", "$base = $base_wb",
679 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
681 def STR_POST : AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
682 "str $src, [$base], $offset", "$base = $base_wb",
684 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
686 def STRH_PRE : AI3pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset),
687 "strh $src, [$base, $offset]!", "$base = $base_wb",
689 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
691 def STRH_POST: AI3po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am3offset:$offset),
692 "strh $src, [$base], $offset", "$base = $base_wb",
693 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
694 GPR:$base, am3offset:$offset))]>;
696 def STRB_PRE : AI2pr<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
697 "strb $src, [$base, $offset]!", "$base = $base_wb",
698 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
699 GPR:$base, am2offset:$offset))]>;
701 def STRB_POST: AI2po<(ops GPR:$base_wb, GPR:$src, GPR:$base,am2offset:$offset),
702 "strb $src, [$base], $offset", "$base = $base_wb",
703 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
704 GPR:$base, am2offset:$offset))]>;
707 //===----------------------------------------------------------------------===//
708 // Load / store multiple Instructions.
712 def LDM : AI4<(ops addrmode4:$addr, reglist:$dst1, variable_ops),
713 "ldm${addr:submode} $addr, $dst1",
717 def STM : AI4<(ops addrmode4:$addr, reglist:$src1, variable_ops),
718 "stm${addr:submode} $addr, $src1",
721 //===----------------------------------------------------------------------===//
722 // Move Instructions.
725 def MOVr : AI1<(ops GPR:$dst, GPR:$src),
726 "mov $dst, $src", []>;
727 def MOVs : AI1<(ops GPR:$dst, so_reg:$src),
728 "mov $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
730 let isReMaterializable = 1 in
731 def MOVi : AI1<(ops GPR:$dst, so_imm:$src),
732 "mov $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
734 // These aren't really mov instructions, but we have to define them this way
735 // due to flag operands.
737 def MOVsrl_flag : AI1<(ops GPR:$dst, GPR:$src),
738 "movs $dst, $src, lsr #1",
739 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
740 def MOVsra_flag : AI1<(ops GPR:$dst, GPR:$src),
741 "movs $dst, $src, asr #1",
742 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
743 def MOVrx : AI1<(ops GPR:$dst, GPR:$src),
744 "mov $dst, $src, rrx",
745 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
748 //===----------------------------------------------------------------------===//
749 // Extend Instructions.
754 defm SXTB : AI_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
755 defm SXTH : AI_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
757 defm SXTAB : AI_bin_rrot<"sxtab",
758 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
759 defm SXTAH : AI_bin_rrot<"sxtah",
760 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
762 // TODO: SXT(A){B|H}16
766 let AddedComplexity = 16 in {
767 defm UXTB : AI_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
768 defm UXTH : AI_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
769 defm UXTB16 : AI_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
771 def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
772 (UXTB16r_rot GPR:$Src, 24)>;
773 def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
774 (UXTB16r_rot GPR:$Src, 8)>;
776 defm UXTAB : AI_bin_rrot<"uxtab",
777 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
778 defm UXTAH : AI_bin_rrot<"uxtah",
779 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
782 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
783 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
785 // TODO: UXT(A){B|H}16
787 //===----------------------------------------------------------------------===//
788 // Arithmetic Instructions.
791 defm ADD : AI1_bin_irs<"add" , BinOpFrag<(add node:$LHS, node:$RHS)>>;
792 defm ADDS : AI1_bin_irs<"adds", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
793 defm ADC : AI1_bin_irs<"adc" , BinOpFrag<(adde node:$LHS, node:$RHS)>>;
794 defm SUB : AI1_bin_irs<"sub" , BinOpFrag<(sub node:$LHS, node:$RHS)>>;
795 defm SUBS : AI1_bin_irs<"subs", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
796 defm SBC : AI1_bin_irs<"sbc" , BinOpFrag<(sube node:$LHS, node:$RHS)>>;
798 // These don't define reg/reg forms, because they are handled above.
799 defm RSB : AI1_bin_is <"rsb" , BinOpFrag<(sub node:$RHS, node:$LHS)>>;
800 defm RSBS : AI1_bin_is <"rsbs", BinOpFrag<(subc node:$RHS, node:$LHS)>>;
801 defm RSC : AI1_bin_is <"rsc" , BinOpFrag<(sube node:$RHS, node:$LHS)>>;
803 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
804 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
805 (SUBri GPR:$src, so_imm_neg:$imm)>;
807 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
808 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
809 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
810 // (SBCri GPR:$src, so_imm_neg:$imm)>;
812 // Note: These are implemented in C++ code, because they have to generate
813 // ADD/SUBrs instructions, which use a complex pattern that a xform function
815 // (mul X, 2^n+1) -> (add (X << n), X)
816 // (mul X, 2^n-1) -> (rsb X, (X << n))
819 //===----------------------------------------------------------------------===//
820 // Bitwise Instructions.
823 defm AND : AI1_bin_irs<"and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
824 defm ORR : AI1_bin_irs<"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
825 defm EOR : AI1_bin_irs<"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
826 defm BIC : AI1_bin_irs<"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
828 def MVNr : AI<(ops GPR:$dst, GPR:$src),
829 "mvn $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
830 def MVNs : AI<(ops GPR:$dst, so_reg:$src),
831 "mvn $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
832 let isReMaterializable = 1 in
833 def MVNi : AI<(ops GPR:$dst, so_imm:$imm),
834 "mvn $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
836 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
837 (BICri GPR:$src, so_imm_not:$imm)>;
839 //===----------------------------------------------------------------------===//
840 // Multiply Instructions.
843 // AI_orr - Defines a (op r, r) pattern.
844 class AI_orr<string opc, SDNode opnode>
845 : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
846 !strconcat(opc, " $dst, $a, $b"),
847 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
849 // AI_oorr - Defines a (op (op r, r), r) pattern.
850 class AI_oorr<string opc, SDNode opnode1, SDNode opnode2>
851 : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
852 !strconcat(opc, " $dst, $a, $b, $c"),
853 [(set GPR:$dst, (opnode1 (opnode2 GPR:$a, GPR:$b), GPR:$c))]>;
855 def MUL : AI_orr<"mul", mul>;
856 def MLA : AI_oorr<"mla", add, mul>;
858 // Extra precision multiplies with low / high results
859 def SMULL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
860 "smull $ldst, $hdst, $a, $b",
863 def UMULL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
864 "umull $ldst, $hdst, $a, $b",
867 // Multiply + accumulate
868 def SMLAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
869 "smlal $ldst, $hdst, $a, $b",
872 def UMLAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
873 "umlal $ldst, $hdst, $a, $b",
876 def UMAAL : AI<(ops GPR:$ldst, GPR:$hdst, GPR:$a, GPR:$b),
877 "umaal $ldst, $hdst, $a, $b",
878 []>, Requires<[IsARM, HasV6]>;
880 // Most significant word multiply
881 def SMMUL : AI_orr<"smmul", mulhs>, Requires<[IsARM, HasV6]>;
882 def SMMLA : AI_oorr<"smmla", add, mulhs>, Requires<[IsARM, HasV6]>;
885 def SMMLS : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$c),
886 "smmls $dst, $a, $b, $c",
887 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
888 Requires<[IsARM, HasV6]>;
890 multiclass AI_smul<string opc, PatFrag opnode> {
891 def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
892 !strconcat(opc, "bb $dst, $a, $b"),
893 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
894 (sext_inreg GPR:$b, i16)))]>,
895 Requires<[IsARM, HasV5TE]>;
896 def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
897 !strconcat(opc, "bt $dst, $a, $b"),
898 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
899 (sra GPR:$b, 16)))]>,
900 Requires<[IsARM, HasV5TE]>;
901 def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
902 !strconcat(opc, "tb $dst, $a, $b"),
903 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
904 (sext_inreg GPR:$b, i16)))]>,
905 Requires<[IsARM, HasV5TE]>;
906 def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
907 !strconcat(opc, "tt $dst, $a, $b"),
908 [(set GPR:$dst, (opnode (sra GPR:$a, 16),
909 (sra GPR:$b, 16)))]>,
910 Requires<[IsARM, HasV5TE]>;
911 def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
912 !strconcat(opc, "wb $dst, $a, $b"),
913 [(set GPR:$dst, (sra (opnode GPR:$a,
914 (sext_inreg GPR:$b, i16)), 16))]>,
915 Requires<[IsARM, HasV5TE]>;
916 def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b),
917 !strconcat(opc, "wt $dst, $a, $b"),
918 [(set GPR:$dst, (sra (opnode GPR:$a,
919 (sra GPR:$b, 16)), 16))]>,
920 Requires<[IsARM, HasV5TE]>;
923 multiclass AI_smla<string opc, PatFrag opnode> {
924 def BB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
925 !strconcat(opc, "bb $dst, $a, $b, $acc"),
926 [(set GPR:$dst, (add GPR:$acc,
927 (opnode (sext_inreg GPR:$a, i16),
928 (sext_inreg GPR:$b, i16))))]>,
929 Requires<[IsARM, HasV5TE]>;
930 def BT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
931 !strconcat(opc, "bt $dst, $a, $b, $acc"),
932 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
933 (sra GPR:$b, 16))))]>,
934 Requires<[IsARM, HasV5TE]>;
935 def TB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
936 !strconcat(opc, "tb $dst, $a, $b, $acc"),
937 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
938 (sext_inreg GPR:$b, i16))))]>,
939 Requires<[IsARM, HasV5TE]>;
940 def TT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
941 !strconcat(opc, "tt $dst, $a, $b, $acc"),
942 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, 16),
943 (sra GPR:$b, 16))))]>,
944 Requires<[IsARM, HasV5TE]>;
946 def WB : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
947 !strconcat(opc, "wb $dst, $a, $b, $acc"),
948 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
949 (sext_inreg GPR:$b, i16)), 16)))]>,
950 Requires<[IsARM, HasV5TE]>;
951 def WT : AI<(ops GPR:$dst, GPR:$a, GPR:$b, GPR:$acc),
952 !strconcat(opc, "wt $dst, $a, $b, $acc"),
953 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
954 (sra GPR:$b, 16)), 16)))]>,
955 Requires<[IsARM, HasV5TE]>;
958 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
959 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
961 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
962 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
964 //===----------------------------------------------------------------------===//
965 // Misc. Arithmetic Instructions.
968 def CLZ : AI<(ops GPR:$dst, GPR:$src),
970 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
972 def REV : AI<(ops GPR:$dst, GPR:$src),
974 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
976 def REV16 : AI<(ops GPR:$dst, GPR:$src),
979 (or (and (srl GPR:$src, 8), 0xFF),
980 (or (and (shl GPR:$src, 8), 0xFF00),
981 (or (and (srl GPR:$src, 8), 0xFF0000),
982 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
983 Requires<[IsARM, HasV6]>;
985 def REVSH : AI<(ops GPR:$dst, GPR:$src),
989 (or (srl (and GPR:$src, 0xFF00), 8),
990 (shl GPR:$src, 8)), i16))]>,
991 Requires<[IsARM, HasV6]>;
993 def PKHBT : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt),
994 "pkhbt $dst, $src1, $src2, LSL $shamt",
995 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
996 (and (shl GPR:$src2, (i32 imm:$shamt)),
998 Requires<[IsARM, HasV6]>;
1000 // Alternate cases for PKHBT where identities eliminate some nodes.
1001 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1002 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1003 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1004 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1007 def PKHTB : AI<(ops GPR:$dst, GPR:$src1, GPR:$src2, i32imm:$shamt),
1008 "pkhtb $dst, $src1, $src2, ASR $shamt",
1009 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1010 (and (sra GPR:$src2, imm16_31:$shamt),
1011 0xFFFF)))]>, Requires<[IsARM, HasV6]>;
1013 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1014 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1015 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, 16)),
1016 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1017 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1018 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1019 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1022 //===----------------------------------------------------------------------===//
1023 // Comparison Instructions...
1026 defm CMP : AI1_bin0_irs<"cmp", BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1027 defm CMN : AI1_bin0_irs<"cmn", BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1029 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1030 (CMNri GPR:$src, so_imm_neg:$imm)>;
1032 // Note that TST/TEQ don't set all the same flags that CMP does!
1033 defm TST : AI1_bin0_irs<"tst", BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
1034 defm TEQ : AI1_bin0_irs<"teq", BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
1036 defm CMPnz : AI1_bin0_irs<"cmp", BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
1037 defm CMNnz : AI1_bin0_irs<"cmn", BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
1039 def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
1040 (CMNri GPR:$src, so_imm_neg:$imm)>;
1043 // Conditional moves
1044 def MOVCCr : AI<(ops GPR:$dst, GPR:$false, GPR:$true, CCOp:$cc),
1045 "mov$cc $dst, $true",
1046 [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>,
1047 RegConstraint<"$false = $dst">;
1049 def MOVCCs : AI<(ops GPR:$dst, GPR:$false, so_reg:$true, CCOp:$cc),
1050 "mov$cc $dst, $true",
1051 [(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true,imm:$cc))]>,
1052 RegConstraint<"$false = $dst">;
1054 def MOVCCi : AI<(ops GPR:$dst, GPR:$false, so_imm:$true, CCOp:$cc),
1055 "mov$cc $dst, $true",
1056 [(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true,imm:$cc))]>,
1057 RegConstraint<"$false = $dst">;
1060 // LEApcrel - Load a pc-relative address into a register without offending the
1062 def LEApcrel : AI1<(ops GPR:$dst, i32imm:$label),
1063 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
1064 "${:private}PCRELL${:uid}+8))\n"),
1065 !strconcat("${:private}PCRELL${:uid}:\n\t",
1066 "add $dst, pc, #PCRELV${:uid}")),
1069 def LEApcrelJT : AI1<(ops GPR:$dst, i32imm:$label, i32imm:$id),
1070 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
1071 "${:private}PCRELL${:uid}+8))\n"),
1072 !strconcat("${:private}PCRELL${:uid}:\n\t",
1073 "add $dst, pc, #PCRELV${:uid}")),
1075 //===----------------------------------------------------------------------===//
1079 // __aeabi_read_tp preserves the registers r1-r3.
1081 Defs = [R0, R12, LR] in {
1082 def TPsoft : AI<(ops),
1083 "bl __aeabi_read_tp",
1084 [(set R0, ARMthread_pointer)]>;
1087 //===----------------------------------------------------------------------===//
1088 // Non-Instruction Patterns
1091 // ConstantPool, GlobalAddress, and JumpTable
1092 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1093 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1094 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1095 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1097 // Large immediate handling.
1099 // Two piece so_imms.
1100 let isReMaterializable = 1 in
1101 def MOVi2pieces : AI1x2<(ops GPR:$dst, so_imm2part:$src),
1103 [(set GPR:$dst, so_imm2part:$src)]>;
1105 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1106 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1107 (so_imm2part_2 imm:$RHS))>;
1108 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1109 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1110 (so_imm2part_2 imm:$RHS))>;
1112 // TODO: add,sub,and, 3-instr forms?
1116 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
1118 // zextload i1 -> zextload i8
1119 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1121 // extload -> zextload
1122 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1123 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1124 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1126 // truncstore i1 -> truncstore i8
1127 def : Pat<(truncstorei1 GPR:$src, addrmode2:$dst),
1128 (STRB GPR:$src, addrmode2:$dst)>;
1129 def : Pat<(pre_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
1130 (STRB_PRE GPR:$src, GPR:$base, am2offset:$offset)>;
1131 def : Pat<(post_truncsti1 GPR:$src, GPR:$base, am2offset:$offset),
1132 (STRB_POST GPR:$src, GPR:$base, am2offset:$offset)>;
1135 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra (shl GPR:$b, 16), 16)),
1136 (SMULBB GPR:$a, GPR:$b)>;
1137 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1138 (SMULBB GPR:$a, GPR:$b)>;
1139 def : ARMV5TEPat<(mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16)),
1140 (SMULBT GPR:$a, GPR:$b)>;
1141 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, 16)),
1142 (SMULBT GPR:$a, GPR:$b)>;
1143 def : ARMV5TEPat<(mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16)),
1144 (SMULTB GPR:$a, GPR:$b)>;
1145 def : ARMV5TEPat<(mul (sra GPR:$a, 16), sext_16_node:$b),
1146 (SMULTB GPR:$a, GPR:$b)>;
1147 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16),
1148 (SMULWB GPR:$a, GPR:$b)>;
1149 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), 16),
1150 (SMULWB GPR:$a, GPR:$b)>;
1152 def : ARMV5TEPat<(add GPR:$acc,
1153 (mul (sra (shl GPR:$a, 16), 16),
1154 (sra (shl GPR:$b, 16), 16))),
1155 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1156 def : ARMV5TEPat<(add GPR:$acc,
1157 (mul sext_16_node:$a, sext_16_node:$b)),
1158 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1159 def : ARMV5TEPat<(add GPR:$acc,
1160 (mul (sra (shl GPR:$a, 16), 16), (sra GPR:$b, 16))),
1161 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1162 def : ARMV5TEPat<(add GPR:$acc,
1163 (mul sext_16_node:$a, (sra GPR:$b, 16))),
1164 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1165 def : ARMV5TEPat<(add GPR:$acc,
1166 (mul (sra GPR:$a, 16), (sra (shl GPR:$b, 16), 16))),
1167 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1168 def : ARMV5TEPat<(add GPR:$acc,
1169 (mul (sra GPR:$a, 16), sext_16_node:$b)),
1170 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1171 def : ARMV5TEPat<(add GPR:$acc,
1172 (sra (mul GPR:$a, (sra (shl GPR:$b, 16), 16)), 16)),
1173 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1174 def : ARMV5TEPat<(add GPR:$acc,
1175 (sra (mul GPR:$a, sext_16_node:$b), 16)),
1176 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1178 //===----------------------------------------------------------------------===//
1182 include "ARMInstrThumb.td"
1184 //===----------------------------------------------------------------------===//
1185 // Floating Point Support
1188 include "ARMInstrVFP.td"