1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
67 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
68 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
71 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
72 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
74 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
75 [SDNPHasChain, SDNPOutFlag]>;
76 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
77 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
79 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
80 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
82 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
83 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
85 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
86 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
89 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
90 [SDNPHasChain, SDNPOptInFlag]>;
92 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
94 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
97 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
98 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
100 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
102 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
105 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
108 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
111 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
112 [SDNPOutFlag, SDNPCommutative]>;
114 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
116 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
117 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
118 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
120 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
121 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
122 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
123 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
124 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
125 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
126 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
129 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
131 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
133 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
134 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
136 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
138 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
139 [SDNPHasChain, SDNPOptInFlag, SDNPVariadic]>;
142 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
144 //===----------------------------------------------------------------------===//
145 // ARM Instruction Predicate Definitions.
147 def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate;
148 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
149 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
150 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate;
151 def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate;
152 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate;
153 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
154 def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate;
155 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
156 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">, AssemblerPredicate;
157 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate;
158 def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate;
159 def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate;
160 def HasDivide : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
161 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
163 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
165 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
167 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
168 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
169 def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate;
170 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
171 def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate;
172 def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate;
173 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
174 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
176 // FIXME: Eventually this will be just "hasV6T2Ops".
177 def UseMovt : Predicate<"Subtarget->useMovt()">;
178 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
179 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
181 //===----------------------------------------------------------------------===//
182 // ARM Flag Definitions.
184 class RegConstraint<string C> {
185 string Constraints = C;
188 //===----------------------------------------------------------------------===//
189 // ARM specific transformation functions and pattern fragments.
192 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
193 // so_imm_neg def below.
194 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
195 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
198 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
199 // so_imm_not def below.
200 def so_imm_not_XFORM : SDNodeXForm<imm, [{
201 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
204 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
205 def imm1_15 : PatLeaf<(i32 imm), [{
206 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
209 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
210 def imm16_31 : PatLeaf<(i32 imm), [{
211 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
216 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
217 }], so_imm_neg_XFORM>;
221 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
222 }], so_imm_not_XFORM>;
224 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
225 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
226 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
229 /// Split a 32-bit immediate into two 16 bit parts.
230 def hi16 : SDNodeXForm<imm, [{
231 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
234 def lo16AllZero : PatLeaf<(i32 imm), [{
235 // Returns true if all low 16-bits are 0.
236 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
239 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
241 def imm0_65535 : PatLeaf<(i32 imm), [{
242 return (uint32_t)N->getZExtValue() < 65536;
245 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
246 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
248 /// adde and sube predicates - True based on whether the carry flag output
249 /// will be needed or not.
250 def adde_dead_carry :
251 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
252 [{return !N->hasAnyUseOfValue(1);}]>;
253 def sube_dead_carry :
254 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
255 [{return !N->hasAnyUseOfValue(1);}]>;
256 def adde_live_carry :
257 PatFrag<(ops node:$LHS, node:$RHS), (adde node:$LHS, node:$RHS),
258 [{return N->hasAnyUseOfValue(1);}]>;
259 def sube_live_carry :
260 PatFrag<(ops node:$LHS, node:$RHS), (sube node:$LHS, node:$RHS),
261 [{return N->hasAnyUseOfValue(1);}]>;
263 // An 'and' node with a single use.
264 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
265 return N->hasOneUse();
268 // An 'xor' node with a single use.
269 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
270 return N->hasOneUse();
273 // An 'fmul' node with a single use.
274 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
275 return N->hasOneUse();
278 // An 'fadd' node which checks for single non-hazardous use.
279 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
280 return hasNoVMLxHazardUse(N);
283 // An 'fsub' node which checks for single non-hazardous use.
284 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
285 return hasNoVMLxHazardUse(N);
288 //===----------------------------------------------------------------------===//
289 // Operand Definitions.
293 def brtarget : Operand<OtherVT> {
294 let EncoderMethod = "getBranchTargetOpValue";
297 def uncondbrtarget : Operand<OtherVT> {
298 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
302 def bltarget : Operand<i32> {
303 // Encoded the same as branch targets.
304 let EncoderMethod = "getBranchTargetOpValue";
307 // A list of registers separated by comma. Used by load/store multiple.
308 def RegListAsmOperand : AsmOperandClass {
309 let Name = "RegList";
310 let SuperClasses = [];
313 def DPRRegListAsmOperand : AsmOperandClass {
314 let Name = "DPRRegList";
315 let SuperClasses = [];
318 def SPRRegListAsmOperand : AsmOperandClass {
319 let Name = "SPRRegList";
320 let SuperClasses = [];
323 def reglist : Operand<i32> {
324 let EncoderMethod = "getRegisterListOpValue";
325 let ParserMatchClass = RegListAsmOperand;
326 let PrintMethod = "printRegisterList";
329 def dpr_reglist : Operand<i32> {
330 let EncoderMethod = "getRegisterListOpValue";
331 let ParserMatchClass = DPRRegListAsmOperand;
332 let PrintMethod = "printRegisterList";
335 def spr_reglist : Operand<i32> {
336 let EncoderMethod = "getRegisterListOpValue";
337 let ParserMatchClass = SPRRegListAsmOperand;
338 let PrintMethod = "printRegisterList";
341 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
342 def cpinst_operand : Operand<i32> {
343 let PrintMethod = "printCPInstOperand";
347 def pclabel : Operand<i32> {
348 let PrintMethod = "printPCLabel";
351 // ADR instruction labels.
352 def adrlabel : Operand<i32> {
353 let EncoderMethod = "getAdrLabelOpValue";
356 def neon_vcvt_imm32 : Operand<i32> {
357 let EncoderMethod = "getNEONVcvtImm32OpValue";
360 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
361 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
362 int32_t v = (int32_t)N->getZExtValue();
363 return v == 8 || v == 16 || v == 24; }]> {
364 let EncoderMethod = "getRotImmOpValue";
367 // shift_imm: An integer that encodes a shift amount and the type of shift
368 // (currently either asr or lsl) using the same encoding used for the
369 // immediates in so_reg operands.
370 def shift_imm : Operand<i32> {
371 let PrintMethod = "printShiftImmOperand";
374 // shifter_operand operands: so_reg and so_imm.
375 def so_reg : Operand<i32>, // reg reg imm
376 ComplexPattern<i32, 3, "SelectShifterOperandReg",
377 [shl,srl,sra,rotr]> {
378 let EncoderMethod = "getSORegOpValue";
379 let PrintMethod = "printSORegOperand";
380 let MIOperandInfo = (ops GPR, GPR, i32imm);
382 def shift_so_reg : Operand<i32>, // reg reg imm
383 ComplexPattern<i32, 3, "SelectShiftShifterOperandReg",
384 [shl,srl,sra,rotr]> {
385 let EncoderMethod = "getSORegOpValue";
386 let PrintMethod = "printSORegOperand";
387 let MIOperandInfo = (ops GPR, GPR, i32imm);
390 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
391 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
392 // represented in the imm field in the same 12-bit form that they are encoded
393 // into so_imm instructions: the 8-bit immediate is the least significant bits
394 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
395 def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> {
396 let EncoderMethod = "getSOImmOpValue";
397 let PrintMethod = "printSOImmOperand";
400 // Break so_imm's up into two pieces. This handles immediates with up to 16
401 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
402 // get the first/second pieces.
403 def so_imm2part : PatLeaf<(imm), [{
404 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
407 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
409 def arm_i32imm : PatLeaf<(imm), [{
410 if (Subtarget->hasV6T2Ops())
412 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
415 def so_imm2part_1 : SDNodeXForm<imm, [{
416 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
417 return CurDAG->getTargetConstant(V, MVT::i32);
420 def so_imm2part_2 : SDNodeXForm<imm, [{
421 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
422 return CurDAG->getTargetConstant(V, MVT::i32);
425 def so_neg_imm2part : Operand<i32>, PatLeaf<(imm), [{
426 return ARM_AM::isSOImmTwoPartVal(-(int)N->getZExtValue());
428 let PrintMethod = "printSOImm2PartOperand";
431 def so_neg_imm2part_1 : SDNodeXForm<imm, [{
432 unsigned V = ARM_AM::getSOImmTwoPartFirst(-(int)N->getZExtValue());
433 return CurDAG->getTargetConstant(V, MVT::i32);
436 def so_neg_imm2part_2 : SDNodeXForm<imm, [{
437 unsigned V = ARM_AM::getSOImmTwoPartSecond(-(int)N->getZExtValue());
438 return CurDAG->getTargetConstant(V, MVT::i32);
441 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
442 def imm0_31 : Operand<i32>, PatLeaf<(imm), [{
443 return (int32_t)N->getZExtValue() < 32;
446 /// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
447 def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{
448 return (int32_t)N->getZExtValue() < 32;
450 let EncoderMethod = "getImmMinusOneOpValue";
453 // For movt/movw - sets the MC Encoder method.
454 // The imm is split into imm{15-12}, imm{11-0}
456 def movt_imm : Operand<i32> {
457 let EncoderMethod = "getMovtImmOpValue";
460 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
462 def bf_inv_mask_imm : Operand<i32>,
464 return ARM::isBitFieldInvertedMask(N->getZExtValue());
466 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
467 let PrintMethod = "printBitfieldInvMaskImmOperand";
470 // Define ARM specific addressing modes.
473 // addrmode_imm12 := reg +/- imm12
475 def addrmode_imm12 : Operand<i32>,
476 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
477 // 12-bit immediate operand. Note that instructions using this encode
478 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
479 // immediate values are as normal.
481 let EncoderMethod = "getAddrModeImm12OpValue";
482 let PrintMethod = "printAddrModeImm12Operand";
483 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
485 // ldst_so_reg := reg +/- reg shop imm
487 def ldst_so_reg : Operand<i32>,
488 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
489 let EncoderMethod = "getLdStSORegOpValue";
490 // FIXME: Simplify the printer
491 let PrintMethod = "printAddrMode2Operand";
492 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
495 // addrmode2 := reg +/- imm12
496 // := reg +/- reg shop imm
498 def addrmode2 : Operand<i32>,
499 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
500 let EncoderMethod = "getAddrMode2OpValue";
501 let PrintMethod = "printAddrMode2Operand";
502 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
505 def am2offset : Operand<i32>,
506 ComplexPattern<i32, 2, "SelectAddrMode2Offset",
507 [], [SDNPWantRoot]> {
508 let EncoderMethod = "getAddrMode2OffsetOpValue";
509 let PrintMethod = "printAddrMode2OffsetOperand";
510 let MIOperandInfo = (ops GPR, i32imm);
513 // addrmode3 := reg +/- reg
514 // addrmode3 := reg +/- imm8
516 def addrmode3 : Operand<i32>,
517 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
518 let EncoderMethod = "getAddrMode3OpValue";
519 let PrintMethod = "printAddrMode3Operand";
520 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
523 def am3offset : Operand<i32>,
524 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
525 [], [SDNPWantRoot]> {
526 let EncoderMethod = "getAddrMode3OffsetOpValue";
527 let PrintMethod = "printAddrMode3OffsetOperand";
528 let MIOperandInfo = (ops GPR, i32imm);
531 // ldstm_mode := {ia, ib, da, db}
533 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
534 let EncoderMethod = "getLdStmModeOpValue";
535 let PrintMethod = "printLdStmModeOperand";
538 def MemMode5AsmOperand : AsmOperandClass {
539 let Name = "MemMode5";
540 let SuperClasses = [];
543 // addrmode5 := reg +/- imm8*4
545 def addrmode5 : Operand<i32>,
546 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
547 let PrintMethod = "printAddrMode5Operand";
548 let MIOperandInfo = (ops GPR:$base, i32imm);
549 let ParserMatchClass = MemMode5AsmOperand;
550 let EncoderMethod = "getAddrMode5OpValue";
553 // addrmode6 := reg with optional writeback
555 def addrmode6 : Operand<i32>,
556 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
557 let PrintMethod = "printAddrMode6Operand";
558 let MIOperandInfo = (ops GPR:$addr, i32imm);
559 let EncoderMethod = "getAddrMode6AddressOpValue";
562 def am6offset : Operand<i32> {
563 let PrintMethod = "printAddrMode6OffsetOperand";
564 let MIOperandInfo = (ops GPR);
565 let EncoderMethod = "getAddrMode6OffsetOpValue";
568 // Special version of addrmode6 to handle alignment encoding for VLD-dup
569 // instructions, specifically VLD4-dup.
570 def addrmode6dup : Operand<i32>,
571 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
572 let PrintMethod = "printAddrMode6Operand";
573 let MIOperandInfo = (ops GPR:$addr, i32imm);
574 let EncoderMethod = "getAddrMode6DupAddressOpValue";
577 // addrmodepc := pc + reg
579 def addrmodepc : Operand<i32>,
580 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
581 let PrintMethod = "printAddrModePCOperand";
582 let MIOperandInfo = (ops GPR, i32imm);
585 def nohash_imm : Operand<i32> {
586 let PrintMethod = "printNoHashImmediate";
589 //===----------------------------------------------------------------------===//
591 include "ARMInstrFormats.td"
593 //===----------------------------------------------------------------------===//
594 // Multiclass helpers...
597 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
598 /// binop that produces a value.
599 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
600 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
601 PatFrag opnode, bit Commutable = 0> {
602 // The register-immediate version is re-materializable. This is useful
603 // in particular for taking the address of a local.
604 let isReMaterializable = 1 in {
605 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
606 iii, opc, "\t$Rd, $Rn, $imm",
607 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
612 let Inst{19-16} = Rn;
613 let Inst{15-12} = Rd;
614 let Inst{11-0} = imm;
617 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
618 iir, opc, "\t$Rd, $Rn, $Rm",
619 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
624 let isCommutable = Commutable;
625 let Inst{19-16} = Rn;
626 let Inst{15-12} = Rd;
627 let Inst{11-4} = 0b00000000;
630 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
631 iis, opc, "\t$Rd, $Rn, $shift",
632 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
637 let Inst{19-16} = Rn;
638 let Inst{15-12} = Rd;
639 let Inst{11-0} = shift;
643 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
644 /// instruction modifies the CPSR register.
645 let Defs = [CPSR] in {
646 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
647 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
648 PatFrag opnode, bit Commutable = 0> {
649 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
650 iii, opc, "\t$Rd, $Rn, $imm",
651 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
657 let Inst{19-16} = Rn;
658 let Inst{15-12} = Rd;
659 let Inst{11-0} = imm;
661 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
662 iir, opc, "\t$Rd, $Rn, $Rm",
663 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
667 let isCommutable = Commutable;
670 let Inst{19-16} = Rn;
671 let Inst{15-12} = Rd;
672 let Inst{11-4} = 0b00000000;
675 def rs : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm,
676 iis, opc, "\t$Rd, $Rn, $shift",
677 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]> {
683 let Inst{19-16} = Rn;
684 let Inst{15-12} = Rd;
685 let Inst{11-0} = shift;
690 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
691 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
692 /// a explicit result, only implicitly set CPSR.
693 let isCompare = 1, Defs = [CPSR] in {
694 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
695 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
696 PatFrag opnode, bit Commutable = 0> {
697 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
699 [(opnode GPR:$Rn, so_imm:$imm)]> {
704 let Inst{19-16} = Rn;
705 let Inst{15-12} = 0b0000;
706 let Inst{11-0} = imm;
708 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
710 [(opnode GPR:$Rn, GPR:$Rm)]> {
713 let isCommutable = Commutable;
716 let Inst{19-16} = Rn;
717 let Inst{15-12} = 0b0000;
718 let Inst{11-4} = 0b00000000;
721 def rs : AI1<opcod, (outs), (ins GPR:$Rn, so_reg:$shift), DPSoRegFrm, iis,
722 opc, "\t$Rn, $shift",
723 [(opnode GPR:$Rn, so_reg:$shift)]> {
728 let Inst{19-16} = Rn;
729 let Inst{15-12} = 0b0000;
730 let Inst{11-0} = shift;
735 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
736 /// register and one whose operand is a register rotated by 8/16/24.
737 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
738 multiclass AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode> {
739 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
740 IIC_iEXTr, opc, "\t$Rd, $Rm",
741 [(set GPR:$Rd, (opnode GPR:$Rm))]>,
742 Requires<[IsARM, HasV6]> {
745 let Inst{19-16} = 0b1111;
746 let Inst{15-12} = Rd;
747 let Inst{11-10} = 0b00;
750 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
751 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
752 [(set GPR:$Rd, (opnode (rotr GPR:$Rm, rot_imm:$rot)))]>,
753 Requires<[IsARM, HasV6]> {
757 let Inst{19-16} = 0b1111;
758 let Inst{15-12} = Rd;
759 let Inst{11-10} = rot;
764 multiclass AI_ext_rrot_np<bits<8> opcod, string opc> {
765 def r : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm),
766 IIC_iEXTr, opc, "\t$Rd, $Rm",
767 [/* For disassembly only; pattern left blank */]>,
768 Requires<[IsARM, HasV6]> {
769 let Inst{19-16} = 0b1111;
770 let Inst{11-10} = 0b00;
772 def r_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rm, rot_imm:$rot),
773 IIC_iEXTr, opc, "\t$Rd, $Rm, ror $rot",
774 [/* For disassembly only; pattern left blank */]>,
775 Requires<[IsARM, HasV6]> {
777 let Inst{19-16} = 0b1111;
778 let Inst{11-10} = rot;
782 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
783 /// register and one whose operand is a register rotated by 8/16/24.
784 multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
785 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
786 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
787 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
788 Requires<[IsARM, HasV6]> {
792 let Inst{19-16} = Rn;
793 let Inst{15-12} = Rd;
794 let Inst{11-10} = 0b00;
795 let Inst{9-4} = 0b000111;
798 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
800 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
801 [(set GPR:$Rd, (opnode GPR:$Rn,
802 (rotr GPR:$Rm, rot_imm:$rot)))]>,
803 Requires<[IsARM, HasV6]> {
808 let Inst{19-16} = Rn;
809 let Inst{15-12} = Rd;
810 let Inst{11-10} = rot;
811 let Inst{9-4} = 0b000111;
816 // For disassembly only.
817 multiclass AI_exta_rrot_np<bits<8> opcod, string opc> {
818 def rr : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
819 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
820 [/* For disassembly only; pattern left blank */]>,
821 Requires<[IsARM, HasV6]> {
822 let Inst{11-10} = 0b00;
824 def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
826 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm, ror $rot",
827 [/* For disassembly only; pattern left blank */]>,
828 Requires<[IsARM, HasV6]> {
831 let Inst{19-16} = Rn;
832 let Inst{11-10} = rot;
836 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
837 let Uses = [CPSR] in {
838 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
839 bit Commutable = 0> {
840 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
841 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
842 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
848 let Inst{15-12} = Rd;
849 let Inst{19-16} = Rn;
850 let Inst{11-0} = imm;
852 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
853 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
854 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
859 let Inst{11-4} = 0b00000000;
861 let isCommutable = Commutable;
863 let Inst{15-12} = Rd;
864 let Inst{19-16} = Rn;
866 def rs : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
867 DPSoRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
868 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
874 let Inst{11-0} = shift;
875 let Inst{15-12} = Rd;
876 let Inst{19-16} = Rn;
879 // Carry setting variants
880 let Defs = [CPSR] in {
881 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
882 bit Commutable = 0> {
883 def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
884 DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
885 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
890 let Inst{15-12} = Rd;
891 let Inst{19-16} = Rn;
892 let Inst{11-0} = imm;
896 def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
897 DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
898 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
903 let Inst{11-4} = 0b00000000;
904 let isCommutable = Commutable;
906 let Inst{15-12} = Rd;
907 let Inst{19-16} = Rn;
911 def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
912 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
913 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
918 let Inst{11-0} = shift;
919 let Inst{15-12} = Rd;
920 let Inst{19-16} = Rn;
928 let canFoldAsLoad = 1, isReMaterializable = 1 in {
929 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
930 InstrItinClass iir, PatFrag opnode> {
931 // Note: We use the complex addrmode_imm12 rather than just an input
932 // GPR and a constrained immediate so that we can use this to match
933 // frame index references and avoid matching constant pool references.
934 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
935 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
936 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
939 let Inst{23} = addr{12}; // U (add = ('U' == 1))
940 let Inst{19-16} = addr{16-13}; // Rn
941 let Inst{15-12} = Rt;
942 let Inst{11-0} = addr{11-0}; // imm12
944 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
945 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
946 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
949 let Inst{23} = shift{12}; // U (add = ('U' == 1))
950 let Inst{19-16} = shift{16-13}; // Rn
951 let Inst{15-12} = Rt;
952 let Inst{11-0} = shift{11-0};
957 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
958 InstrItinClass iir, PatFrag opnode> {
959 // Note: We use the complex addrmode_imm12 rather than just an input
960 // GPR and a constrained immediate so that we can use this to match
961 // frame index references and avoid matching constant pool references.
962 def i12 : AI2ldst<0b010, 0, isByte, (outs),
963 (ins GPR:$Rt, addrmode_imm12:$addr),
964 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
965 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
968 let Inst{23} = addr{12}; // U (add = ('U' == 1))
969 let Inst{19-16} = addr{16-13}; // Rn
970 let Inst{15-12} = Rt;
971 let Inst{11-0} = addr{11-0}; // imm12
973 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
974 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
975 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
978 let Inst{23} = shift{12}; // U (add = ('U' == 1))
979 let Inst{19-16} = shift{16-13}; // Rn
980 let Inst{15-12} = Rt;
981 let Inst{11-0} = shift{11-0};
984 //===----------------------------------------------------------------------===//
986 //===----------------------------------------------------------------------===//
988 //===----------------------------------------------------------------------===//
989 // Miscellaneous Instructions.
992 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
993 /// the function. The first operand is the ID# for this instruction, the second
994 /// is the index into the MachineConstantPool that this is, the third is the
995 /// size in bytes of this constant pool entry.
996 let neverHasSideEffects = 1, isNotDuplicable = 1 in
997 def CONSTPOOL_ENTRY :
998 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
999 i32imm:$size), NoItinerary, []>;
1001 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1002 // from removing one half of the matched pairs. That breaks PEI, which assumes
1003 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1004 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1005 def ADJCALLSTACKUP :
1006 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1007 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1009 def ADJCALLSTACKDOWN :
1010 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1011 [(ARMcallseq_start timm:$amt)]>;
1014 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "",
1015 [/* For disassembly only; pattern left blank */]>,
1016 Requires<[IsARM, HasV6T2]> {
1017 let Inst{27-16} = 0b001100100000;
1018 let Inst{15-8} = 0b11110000;
1019 let Inst{7-0} = 0b00000000;
1022 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "",
1023 [/* For disassembly only; pattern left blank */]>,
1024 Requires<[IsARM, HasV6T2]> {
1025 let Inst{27-16} = 0b001100100000;
1026 let Inst{15-8} = 0b11110000;
1027 let Inst{7-0} = 0b00000001;
1030 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "",
1031 [/* For disassembly only; pattern left blank */]>,
1032 Requires<[IsARM, HasV6T2]> {
1033 let Inst{27-16} = 0b001100100000;
1034 let Inst{15-8} = 0b11110000;
1035 let Inst{7-0} = 0b00000010;
1038 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "",
1039 [/* For disassembly only; pattern left blank */]>,
1040 Requires<[IsARM, HasV6T2]> {
1041 let Inst{27-16} = 0b001100100000;
1042 let Inst{15-8} = 0b11110000;
1043 let Inst{7-0} = 0b00000011;
1046 def SEL : AI<(outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm, NoItinerary, "sel",
1048 [/* For disassembly only; pattern left blank */]>,
1049 Requires<[IsARM, HasV6]> {
1054 let Inst{15-12} = Rd;
1055 let Inst{19-16} = Rn;
1056 let Inst{27-20} = 0b01101000;
1057 let Inst{7-4} = 0b1011;
1058 let Inst{11-8} = 0b1111;
1061 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1062 [/* For disassembly only; pattern left blank */]>,
1063 Requires<[IsARM, HasV6T2]> {
1064 let Inst{27-16} = 0b001100100000;
1065 let Inst{15-8} = 0b11110000;
1066 let Inst{7-0} = 0b00000100;
1069 // The i32imm operand $val can be used by a debugger to store more information
1070 // about the breakpoint.
1071 def BKPT : AI<(outs), (ins i32imm:$val), MiscFrm, NoItinerary, "bkpt", "\t$val",
1072 [/* For disassembly only; pattern left blank */]>,
1075 let Inst{3-0} = val{3-0};
1076 let Inst{19-8} = val{15-4};
1077 let Inst{27-20} = 0b00010010;
1078 let Inst{7-4} = 0b0111;
1081 // Change Processor State is a system instruction -- for disassembly only.
1082 // The singleton $opt operand contains the following information:
1083 // opt{4-0} = mode from Inst{4-0}
1084 // opt{5} = changemode from Inst{17}
1085 // opt{8-6} = AIF from Inst{8-6}
1086 // opt{10-9} = imod from Inst{19-18} with 0b10 as enable and 0b11 as disable
1087 // FIXME: Integrated assembler will need these split out.
1088 def CPS : AXI<(outs), (ins cps_opt:$opt), MiscFrm, NoItinerary, "cps$opt",
1089 [/* For disassembly only; pattern left blank */]>,
1091 let Inst{31-28} = 0b1111;
1092 let Inst{27-20} = 0b00010000;
1097 // Preload signals the memory system of possible future data/instruction access.
1098 // These are for disassembly only.
1099 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1101 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1102 !strconcat(opc, "\t$addr"),
1103 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1106 let Inst{31-26} = 0b111101;
1107 let Inst{25} = 0; // 0 for immediate form
1108 let Inst{24} = data;
1109 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1110 let Inst{22} = read;
1111 let Inst{21-20} = 0b01;
1112 let Inst{19-16} = addr{16-13}; // Rn
1113 let Inst{15-12} = Rt;
1114 let Inst{11-0} = addr{11-0}; // imm12
1117 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1118 !strconcat(opc, "\t$shift"),
1119 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1122 let Inst{31-26} = 0b111101;
1123 let Inst{25} = 1; // 1 for register form
1124 let Inst{24} = data;
1125 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1126 let Inst{22} = read;
1127 let Inst{21-20} = 0b01;
1128 let Inst{19-16} = shift{16-13}; // Rn
1129 let Inst{11-0} = shift{11-0};
1133 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1134 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1135 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1137 def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary,
1139 [/* For disassembly only; pattern left blank */]>,
1142 let Inst{31-10} = 0b1111000100000001000000;
1147 def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1148 [/* For disassembly only; pattern left blank */]>,
1149 Requires<[IsARM, HasV7]> {
1151 let Inst{27-4} = 0b001100100000111100001111;
1152 let Inst{3-0} = opt;
1155 // A5.4 Permanently UNDEFINED instructions.
1156 let isBarrier = 1, isTerminator = 1 in
1157 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1160 let Inst = 0xe7ffdefe;
1163 // Address computation and loads and stores in PIC mode.
1164 let isNotDuplicable = 1 in {
1165 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1166 Size4Bytes, IIC_iALUr,
1167 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1169 let AddedComplexity = 10 in {
1170 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1171 Size4Bytes, IIC_iLoad_r,
1172 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1174 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1175 Size4Bytes, IIC_iLoad_bh_r,
1176 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1178 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1179 Size4Bytes, IIC_iLoad_bh_r,
1180 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1182 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1183 Size4Bytes, IIC_iLoad_bh_r,
1184 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1186 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1187 Size4Bytes, IIC_iLoad_bh_r,
1188 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1190 let AddedComplexity = 10 in {
1191 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1192 Size4Bytes, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1194 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1195 Size4Bytes, IIC_iStore_bh_r, [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
1197 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1198 Size4Bytes, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1200 } // isNotDuplicable = 1
1203 // LEApcrel - Load a pc-relative address into a register without offending the
1205 let neverHasSideEffects = 1, isReMaterializable = 1 in
1206 // The 'adr' mnemonic encodes differently if the label is before or after
1207 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1208 // know until then which form of the instruction will be used.
1209 def ADR : AI1<0, (outs GPR:$Rd), (ins adrlabel:$label),
1210 MiscFrm, IIC_iALUi, "adr", "\t$Rd, #$label", []> {
1213 let Inst{27-25} = 0b001;
1215 let Inst{19-16} = 0b1111;
1216 let Inst{15-12} = Rd;
1217 let Inst{11-0} = label;
1219 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1220 Size4Bytes, IIC_iALUi, []>;
1222 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1223 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1224 Size4Bytes, IIC_iALUi, []>;
1226 //===----------------------------------------------------------------------===//
1227 // Control Flow Instructions.
1230 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1232 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1233 "bx", "\tlr", [(ARMretflag)]>,
1234 Requires<[IsARM, HasV4T]> {
1235 let Inst{27-0} = 0b0001001011111111111100011110;
1239 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1240 "mov", "\tpc, lr", [(ARMretflag)]>,
1241 Requires<[IsARM, NoV4T]> {
1242 let Inst{27-0} = 0b0001101000001111000000001110;
1246 // Indirect branches
1247 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1249 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1250 [(brind GPR:$dst)]>,
1251 Requires<[IsARM, HasV4T]> {
1253 let Inst{31-4} = 0b1110000100101111111111110001;
1254 let Inst{3-0} = dst;
1258 // FIXME: We would really like to define this as a vanilla ARMPat like:
1259 // ARMPat<(brind GPR:$dst), (MOVr PC, GPR:$dst)>
1260 // With that, however, we can't set isBranch, isTerminator, etc..
1261 def MOVPCRX : ARMPseudoInst<(outs), (ins GPR:$dst),
1262 Size4Bytes, IIC_Br, [(brind GPR:$dst)]>,
1263 Requires<[IsARM, NoV4T]>;
1266 // All calls clobber the non-callee saved registers. SP is marked as
1267 // a use to prevent stack-pointer assignments that appear immediately
1268 // before calls from potentially appearing dead.
1270 // On non-Darwin platforms R9 is callee-saved.
1271 Defs = [R0, R1, R2, R3, R12, LR,
1272 D0, D1, D2, D3, D4, D5, D6, D7,
1273 D16, D17, D18, D19, D20, D21, D22, D23,
1274 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1276 def BL : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1277 IIC_Br, "bl\t$func",
1278 [(ARMcall tglobaladdr:$func)]>,
1279 Requires<[IsARM, IsNotDarwin]> {
1280 let Inst{31-28} = 0b1110;
1282 let Inst{23-0} = func;
1285 def BL_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1286 IIC_Br, "bl", "\t$func",
1287 [(ARMcall_pred tglobaladdr:$func)]>,
1288 Requires<[IsARM, IsNotDarwin]> {
1290 let Inst{23-0} = func;
1294 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1295 IIC_Br, "blx\t$func",
1296 [(ARMcall GPR:$func)]>,
1297 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1299 let Inst{31-4} = 0b1110000100101111111111110011;
1300 let Inst{3-0} = func;
1304 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1305 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1306 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1307 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1310 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1311 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1312 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1316 // On Darwin R9 is call-clobbered.
1317 // R7 is marked as a use to prevent frame-pointer assignments from being
1318 // moved above / below calls.
1319 Defs = [R0, R1, R2, R3, R9, R12, LR,
1320 D0, D1, D2, D3, D4, D5, D6, D7,
1321 D16, D17, D18, D19, D20, D21, D22, D23,
1322 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
1323 Uses = [R7, SP] in {
1324 def BLr9 : ABXI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1325 IIC_Br, "bl\t$func",
1326 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
1327 let Inst{31-28} = 0b1110;
1329 let Inst{23-0} = func;
1332 def BLr9_pred : ABI<0b1011, (outs), (ins bltarget:$func, variable_ops),
1333 IIC_Br, "bl", "\t$func",
1334 [(ARMcall_pred tglobaladdr:$func)]>,
1335 Requires<[IsARM, IsDarwin]> {
1337 let Inst{23-0} = func;
1341 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1342 IIC_Br, "blx\t$func",
1343 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
1345 let Inst{31-4} = 0b1110000100101111111111110011;
1346 let Inst{3-0} = func;
1350 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1351 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1352 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1353 Requires<[IsARM, HasV4T, IsDarwin]>;
1356 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1357 Size8Bytes, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1358 Requires<[IsARM, NoV4T, IsDarwin]>;
1363 // FIXME: These should probably be xformed into the non-TC versions of the
1364 // instructions as part of MC lowering.
1365 // FIXME: These seem to be used for both Thumb and ARM instruction selection.
1366 // Thumb should have its own version since the instruction is actually
1367 // different, even though the mnemonic is the same.
1368 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1370 let Defs = [R0, R1, R2, R3, R9, R12,
1371 D0, D1, D2, D3, D4, D5, D6, D7,
1372 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1373 D27, D28, D29, D30, D31, PC],
1375 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1376 IIC_Br, []>, Requires<[IsDarwin]>;
1378 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1379 IIC_Br, []>, Requires<[IsDarwin]>;
1381 def TAILJMPd : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1382 IIC_Br, "b\t$dst @ TAILCALL",
1383 []>, Requires<[IsARM, IsDarwin]>;
1385 def TAILJMPdt: ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1386 IIC_Br, "b.w\t$dst @ TAILCALL",
1387 []>, Requires<[IsThumb, IsDarwin]>;
1389 def TAILJMPr : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1390 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1391 []>, Requires<[IsDarwin]> {
1393 let Inst{31-4} = 0b1110000100101111111111110001;
1394 let Inst{3-0} = dst;
1398 // Non-Darwin versions (the difference is R9).
1399 let Defs = [R0, R1, R2, R3, R12,
1400 D0, D1, D2, D3, D4, D5, D6, D7,
1401 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26,
1402 D27, D28, D29, D30, D31, PC],
1404 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
1405 IIC_Br, []>, Requires<[IsNotDarwin]>;
1407 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
1408 IIC_Br, []>, Requires<[IsNotDarwin]>;
1410 def TAILJMPdND : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1411 IIC_Br, "b\t$dst @ TAILCALL",
1412 []>, Requires<[IsARM, IsNotDarwin]>;
1414 def TAILJMPdNDt : ABXI<0b1010, (outs), (ins brtarget:$dst, variable_ops),
1415 IIC_Br, "b.w\t$dst @ TAILCALL",
1416 []>, Requires<[IsThumb, IsNotDarwin]>;
1418 def TAILJMPrND : AXI<(outs), (ins tcGPR:$dst, variable_ops),
1419 BrMiscFrm, IIC_Br, "bx\t$dst @ TAILCALL",
1420 []>, Requires<[IsNotDarwin]> {
1422 let Inst{31-4} = 0b1110000100101111111111110001;
1423 let Inst{3-0} = dst;
1428 let isBranch = 1, isTerminator = 1 in {
1429 // B is "predicable" since it can be xformed into a Bcc.
1430 let isBarrier = 1 in {
1431 let isPredicable = 1 in
1432 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
1433 "b\t$target", [(br bb:$target)]> {
1435 let Inst{31-28} = 0b1110;
1436 let Inst{23-0} = target;
1439 let isNotDuplicable = 1, isIndirectBranch = 1 in {
1440 def BR_JTr : ARMPseudoInst<(outs),
1441 (ins GPR:$target, i32imm:$jt, i32imm:$id),
1442 SizeSpecial, IIC_Br,
1443 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
1444 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
1445 // into i12 and rs suffixed versions.
1446 def BR_JTm : ARMPseudoInst<(outs),
1447 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
1448 SizeSpecial, IIC_Br,
1449 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
1451 def BR_JTadd : ARMPseudoInst<(outs),
1452 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
1453 SizeSpecial, IIC_Br,
1454 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
1456 } // isNotDuplicable = 1, isIndirectBranch = 1
1459 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
1460 // a two-value operand where a dag node expects two operands. :(
1461 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
1462 IIC_Br, "b", "\t$target",
1463 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
1465 let Inst{23-0} = target;
1469 // Branch and Exchange Jazelle -- for disassembly only
1470 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
1471 [/* For disassembly only; pattern left blank */]> {
1472 let Inst{23-20} = 0b0010;
1473 //let Inst{19-8} = 0xfff;
1474 let Inst{7-4} = 0b0010;
1477 // Secure Monitor Call is a system instruction -- for disassembly only
1478 def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
1479 [/* For disassembly only; pattern left blank */]> {
1481 let Inst{23-4} = 0b01100000000000000111;
1482 let Inst{3-0} = opt;
1485 // Supervisor Call (Software Interrupt) -- for disassembly only
1486 let isCall = 1, Uses = [SP] in {
1487 def SVC : ABI<0b1111, (outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc",
1488 [/* For disassembly only; pattern left blank */]> {
1490 let Inst{23-0} = svc;
1494 // Store Return State is a system instruction -- for disassembly only
1495 let isCodeGenOnly = 1 in { // FIXME: This should not use submode!
1496 def SRSW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1497 NoItinerary, "srs${amode}\tsp!, $mode",
1498 [/* For disassembly only; pattern left blank */]> {
1499 let Inst{31-28} = 0b1111;
1500 let Inst{22-20} = 0b110; // W = 1
1503 def SRS : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
1504 NoItinerary, "srs${amode}\tsp, $mode",
1505 [/* For disassembly only; pattern left blank */]> {
1506 let Inst{31-28} = 0b1111;
1507 let Inst{22-20} = 0b100; // W = 0
1510 // Return From Exception is a system instruction -- for disassembly only
1511 def RFEW : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1512 NoItinerary, "rfe${amode}\t$base!",
1513 [/* For disassembly only; pattern left blank */]> {
1514 let Inst{31-28} = 0b1111;
1515 let Inst{22-20} = 0b011; // W = 1
1518 def RFE : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
1519 NoItinerary, "rfe${amode}\t$base",
1520 [/* For disassembly only; pattern left blank */]> {
1521 let Inst{31-28} = 0b1111;
1522 let Inst{22-20} = 0b001; // W = 0
1524 } // isCodeGenOnly = 1
1526 //===----------------------------------------------------------------------===//
1527 // Load / store Instructions.
1533 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
1534 UnOpFrag<(load node:$Src)>>;
1535 defm LDRB : AI_ldr1<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
1536 UnOpFrag<(zextloadi8 node:$Src)>>;
1537 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
1538 BinOpFrag<(store node:$LHS, node:$RHS)>>;
1539 defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
1540 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
1542 // Special LDR for loads from non-pc-relative constpools.
1543 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
1544 isReMaterializable = 1 in
1545 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1546 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
1550 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1551 let Inst{19-16} = 0b1111;
1552 let Inst{15-12} = Rt;
1553 let Inst{11-0} = addr{11-0}; // imm12
1556 // Loads with zero extension
1557 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1558 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
1559 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
1561 // Loads with sign extension
1562 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1563 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
1564 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
1566 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
1567 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
1568 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
1570 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
1571 isCodeGenOnly = 1 in { // $dst2 doesn't exist in asmstring?
1572 // FIXME: $dst2 isn't in the asm string as it's implied by $Rd (dst2 = Rd+1)
1573 // how to represent that such that tblgen is happy and we don't
1574 // mark this codegen only?
1576 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
1577 (ins addrmode3:$addr), LdMiscFrm,
1578 IIC_iLoad_d_r, "ldrd", "\t$Rd, $addr",
1579 []>, Requires<[IsARM, HasV5TE]>;
1583 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
1584 def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1585 (ins addrmode2:$addr), IndexModePre, LdFrm, itin,
1586 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1588 // {13} 1 == Rm, 0 == imm12
1592 let Inst{25} = addr{13};
1593 let Inst{23} = addr{12};
1594 let Inst{19-16} = addr{17-14};
1595 let Inst{11-0} = addr{11-0};
1597 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1598 (ins GPR:$Rn, am2offset:$offset),
1599 IndexModePost, LdFrm, itin,
1600 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1601 // {13} 1 == Rm, 0 == imm12
1606 let Inst{25} = offset{13};
1607 let Inst{23} = offset{12};
1608 let Inst{19-16} = Rn;
1609 let Inst{11-0} = offset{11-0};
1613 let mayLoad = 1, neverHasSideEffects = 1 in {
1614 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
1615 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
1618 multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> {
1619 def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1620 (ins addrmode3:$addr), IndexModePre,
1622 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
1624 let Inst{23} = addr{8}; // U bit
1625 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
1626 let Inst{19-16} = addr{12-9}; // Rn
1627 let Inst{11-8} = addr{7-4}; // imm7_4/zero
1628 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
1630 def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1631 (ins GPR:$Rn, am3offset:$offset), IndexModePost,
1633 opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
1636 let Inst{23} = offset{8}; // U bit
1637 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
1638 let Inst{19-16} = Rn;
1639 let Inst{11-8} = offset{7-4}; // imm7_4/zero
1640 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
1644 let mayLoad = 1, neverHasSideEffects = 1 in {
1645 defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
1646 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
1647 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
1648 let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1649 defm LDRD : AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
1650 } // mayLoad = 1, neverHasSideEffects = 1
1652 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
1653 let mayLoad = 1, neverHasSideEffects = 1 in {
1654 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1655 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1656 LdFrm, IIC_iLoad_ru,
1657 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1658 let Inst{21} = 1; // overwrite
1660 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1661 (ins GPR:$base, am2offset:$offset), IndexModeNone,
1662 LdFrm, IIC_iLoad_bh_ru,
1663 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1664 let Inst{21} = 1; // overwrite
1666 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1667 (ins GPR:$base, am3offset:$offset), IndexModePost,
1668 LdMiscFrm, IIC_iLoad_bh_ru,
1669 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1670 let Inst{21} = 1; // overwrite
1672 def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1673 (ins GPR:$base, am3offset:$offset), IndexModePost,
1674 LdMiscFrm, IIC_iLoad_bh_ru,
1675 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1676 let Inst{21} = 1; // overwrite
1678 def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1679 (ins GPR:$base, am3offset:$offset), IndexModePost,
1680 LdMiscFrm, IIC_iLoad_bh_ru,
1681 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
1682 let Inst{21} = 1; // overwrite
1688 // Stores with truncate
1689 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
1690 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
1691 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
1694 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
1695 isCodeGenOnly = 1 in // $src2 doesn't exist in asm string
1696 def STRD : AI3str<0b1111, (outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
1697 StMiscFrm, IIC_iStore_d_r,
1698 "strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
1701 def STR_PRE : AI2stridx<0, 1, (outs GPR:$Rn_wb),
1702 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1703 IndexModePre, StFrm, IIC_iStore_ru,
1704 "str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1706 (pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1708 def STR_POST : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1709 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1710 IndexModePost, StFrm, IIC_iStore_ru,
1711 "str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1713 (post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]>;
1715 def STRB_PRE : AI2stridx<1, 1, (outs GPR:$Rn_wb),
1716 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1717 IndexModePre, StFrm, IIC_iStore_bh_ru,
1718 "strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1719 [(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
1720 GPR:$Rn, am2offset:$offset))]>;
1721 def STRB_POST: AI2stridx<1, 0, (outs GPR:$Rn_wb),
1722 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1723 IndexModePost, StFrm, IIC_iStore_bh_ru,
1724 "strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1725 [(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
1726 GPR:$Rn, am2offset:$offset))]>;
1728 def STRH_PRE : AI3stridx<0b1011, 0, 1, (outs GPR:$Rn_wb),
1729 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1730 IndexModePre, StMiscFrm, IIC_iStore_ru,
1731 "strh", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
1733 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
1735 def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb),
1736 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset),
1737 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
1738 "strh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1739 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
1740 GPR:$Rn, am3offset:$offset))]>;
1742 // For disassembly only
1743 def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
1744 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1745 StMiscFrm, IIC_iStore_d_ru,
1746 "strd", "\t$src1, $src2, [$base, $offset]!",
1747 "$base = $base_wb", []>;
1749 // For disassembly only
1750 def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
1751 (ins GPR:$src1, GPR:$src2, GPR:$base, am3offset:$offset),
1752 StMiscFrm, IIC_iStore_d_ru,
1753 "strd", "\t$src1, $src2, [$base], $offset",
1754 "$base = $base_wb", []>;
1756 // STRT, STRBT, and STRHT are for disassembly only.
1758 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1759 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
1760 IndexModeNone, StFrm, IIC_iStore_ru,
1761 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1762 [/* For disassembly only; pattern left blank */]> {
1763 let Inst{21} = 1; // overwrite
1766 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1767 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
1768 IndexModeNone, StFrm, IIC_iStore_bh_ru,
1769 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
1770 [/* For disassembly only; pattern left blank */]> {
1771 let Inst{21} = 1; // overwrite
1774 def STRHT: AI3sthpo<(outs GPR:$base_wb),
1775 (ins GPR:$src, GPR:$base,am3offset:$offset),
1776 StMiscFrm, IIC_iStore_bh_ru,
1777 "strht", "\t$src, [$base], $offset", "$base = $base_wb",
1778 [/* For disassembly only; pattern left blank */]> {
1779 let Inst{21} = 1; // overwrite
1782 //===----------------------------------------------------------------------===//
1783 // Load / store multiple Instructions.
1786 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
1787 InstrItinClass itin, InstrItinClass itin_upd> {
1789 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1790 IndexModeNone, f, itin,
1791 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
1792 let Inst{24-23} = 0b01; // Increment After
1793 let Inst{21} = 0; // No writeback
1794 let Inst{20} = L_bit;
1797 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1798 IndexModeUpd, f, itin_upd,
1799 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1800 let Inst{24-23} = 0b01; // Increment After
1801 let Inst{21} = 1; // Writeback
1802 let Inst{20} = L_bit;
1805 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1806 IndexModeNone, f, itin,
1807 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
1808 let Inst{24-23} = 0b00; // Decrement After
1809 let Inst{21} = 0; // No writeback
1810 let Inst{20} = L_bit;
1813 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1814 IndexModeUpd, f, itin_upd,
1815 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1816 let Inst{24-23} = 0b00; // Decrement After
1817 let Inst{21} = 1; // Writeback
1818 let Inst{20} = L_bit;
1821 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1822 IndexModeNone, f, itin,
1823 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
1824 let Inst{24-23} = 0b10; // Decrement Before
1825 let Inst{21} = 0; // No writeback
1826 let Inst{20} = L_bit;
1829 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1830 IndexModeUpd, f, itin_upd,
1831 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1832 let Inst{24-23} = 0b10; // Decrement Before
1833 let Inst{21} = 1; // Writeback
1834 let Inst{20} = L_bit;
1837 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1838 IndexModeNone, f, itin,
1839 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
1840 let Inst{24-23} = 0b11; // Increment Before
1841 let Inst{21} = 0; // No writeback
1842 let Inst{20} = L_bit;
1845 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
1846 IndexModeUpd, f, itin_upd,
1847 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
1848 let Inst{24-23} = 0b11; // Increment Before
1849 let Inst{21} = 1; // Writeback
1850 let Inst{20} = L_bit;
1854 let neverHasSideEffects = 1 in {
1856 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
1857 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
1859 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
1860 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
1862 } // neverHasSideEffects
1864 // Load / Store Multiple Mnemnoic Aliases
1865 def : MnemonicAlias<"ldm", "ldmia">;
1866 def : MnemonicAlias<"stm", "stmia">;
1868 // FIXME: remove when we have a way to marking a MI with these properties.
1869 // FIXME: Should pc be an implicit operand like PICADD, etc?
1870 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1871 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1872 // FIXME: Should be a pseudo-instruction.
1873 def LDMIA_RET : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1874 reglist:$regs, variable_ops),
1875 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1876 "ldmia${p}\t$Rn!, $regs",
1878 let Inst{24-23} = 0b01; // Increment After
1879 let Inst{21} = 1; // Writeback
1880 let Inst{20} = 1; // Load
1883 //===----------------------------------------------------------------------===//
1884 // Move Instructions.
1887 let neverHasSideEffects = 1 in
1888 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
1889 "mov", "\t$Rd, $Rm", []>, UnaryDP {
1893 let Inst{11-4} = 0b00000000;
1896 let Inst{15-12} = Rd;
1899 // A version for the smaller set of tail call registers.
1900 let neverHasSideEffects = 1 in
1901 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
1902 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
1906 let Inst{11-4} = 0b00000000;
1909 let Inst{15-12} = Rd;
1912 def MOVs : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg:$src),
1913 DPSoRegFrm, IIC_iMOVsr,
1914 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg:$src)]>,
1918 let Inst{15-12} = Rd;
1919 let Inst{11-0} = src;
1923 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1924 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
1925 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
1929 let Inst{15-12} = Rd;
1930 let Inst{19-16} = 0b0000;
1931 let Inst{11-0} = imm;
1934 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
1935 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins movt_imm:$imm),
1937 "movw", "\t$Rd, $imm",
1938 [(set GPR:$Rd, imm0_65535:$imm)]>,
1939 Requires<[IsARM, HasV6T2]>, UnaryDP {
1942 let Inst{15-12} = Rd;
1943 let Inst{11-0} = imm{11-0};
1944 let Inst{19-16} = imm{15-12};
1949 let Constraints = "$src = $Rd" in
1950 def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, movt_imm:$imm),
1952 "movt", "\t$Rd, $imm",
1954 (or (and GPR:$src, 0xffff),
1955 lo16AllZero:$imm))]>, UnaryDP,
1956 Requires<[IsARM, HasV6T2]> {
1959 let Inst{15-12} = Rd;
1960 let Inst{11-0} = imm{11-0};
1961 let Inst{19-16} = imm{15-12};
1966 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
1967 Requires<[IsARM, HasV6T2]>;
1969 let Uses = [CPSR] in
1970 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
1971 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
1974 // These aren't really mov instructions, but we have to define them this way
1975 // due to flag operands.
1977 let Defs = [CPSR] in {
1978 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1979 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
1981 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
1982 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
1986 //===----------------------------------------------------------------------===//
1987 // Extend Instructions.
1992 defm SXTB : AI_ext_rrot<0b01101010,
1993 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
1994 defm SXTH : AI_ext_rrot<0b01101011,
1995 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
1997 defm SXTAB : AI_exta_rrot<0b01101010,
1998 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
1999 defm SXTAH : AI_exta_rrot<0b01101011,
2000 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
2002 // For disassembly only
2003 defm SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
2005 // For disassembly only
2006 defm SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
2010 let AddedComplexity = 16 in {
2011 defm UXTB : AI_ext_rrot<0b01101110,
2012 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
2013 defm UXTH : AI_ext_rrot<0b01101111,
2014 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
2015 defm UXTB16 : AI_ext_rrot<0b01101100,
2016 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
2018 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
2019 // The transformation should probably be done as a combiner action
2020 // instead so we can include a check for masking back in the upper
2021 // eight bits of the source into the lower eight bits of the result.
2022 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
2023 // (UXTB16r_rot GPR:$Src, 24)>;
2024 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
2025 (UXTB16r_rot GPR:$Src, 8)>;
2027 defm UXTAB : AI_exta_rrot<0b01101110, "uxtab",
2028 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
2029 defm UXTAH : AI_exta_rrot<0b01101111, "uxtah",
2030 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
2033 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
2034 // For disassembly only
2035 defm UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
2038 def SBFX : I<(outs GPR:$Rd),
2039 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2040 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2041 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2042 Requires<[IsARM, HasV6T2]> {
2047 let Inst{27-21} = 0b0111101;
2048 let Inst{6-4} = 0b101;
2049 let Inst{20-16} = width;
2050 let Inst{15-12} = Rd;
2051 let Inst{11-7} = lsb;
2055 def UBFX : I<(outs GPR:$Rd),
2056 (ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
2057 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2058 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
2059 Requires<[IsARM, HasV6T2]> {
2064 let Inst{27-21} = 0b0111111;
2065 let Inst{6-4} = 0b101;
2066 let Inst{20-16} = width;
2067 let Inst{15-12} = Rd;
2068 let Inst{11-7} = lsb;
2072 //===----------------------------------------------------------------------===//
2073 // Arithmetic Instructions.
2076 defm ADD : AsI1_bin_irs<0b0100, "add",
2077 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2078 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
2079 defm SUB : AsI1_bin_irs<0b0010, "sub",
2080 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2081 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
2083 // ADD and SUB with 's' bit set.
2084 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
2085 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2086 BinOpFrag<(addc node:$LHS, node:$RHS)>, 1>;
2087 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
2088 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
2089 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
2091 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
2092 BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
2093 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
2094 BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
2095 defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
2096 BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
2097 defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
2098 BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
2100 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2101 IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",
2102 [(set GPR:$Rd, (sub so_imm:$imm, GPR:$Rn))]> {
2107 let Inst{15-12} = Rd;
2108 let Inst{19-16} = Rn;
2109 let Inst{11-0} = imm;
2112 // The reg/reg form is only defined for the disassembler; for codegen it is
2113 // equivalent to SUBrr.
2114 def RSBrr : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
2115 IIC_iALUr, "rsb", "\t$Rd, $Rn, $Rm",
2116 [/* For disassembly only; pattern left blank */]> {
2120 let Inst{11-4} = 0b00000000;
2123 let Inst{15-12} = Rd;
2124 let Inst{19-16} = Rn;
2127 def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2128 DPSoRegFrm, IIC_iALUsr, "rsb", "\t$Rd, $Rn, $shift",
2129 [(set GPR:$Rd, (sub so_reg:$shift, GPR:$Rn))]> {
2134 let Inst{11-0} = shift;
2135 let Inst{15-12} = Rd;
2136 let Inst{19-16} = Rn;
2139 // RSB with 's' bit set.
2140 let Defs = [CPSR] in {
2141 def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
2142 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
2143 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
2149 let Inst{15-12} = Rd;
2150 let Inst{19-16} = Rn;
2151 let Inst{11-0} = imm;
2153 def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2154 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
2155 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
2161 let Inst{11-0} = shift;
2162 let Inst{15-12} = Rd;
2163 let Inst{19-16} = Rn;
2167 let Uses = [CPSR] in {
2168 def RSCri : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2169 DPFrm, IIC_iALUi, "rsc", "\t$Rd, $Rn, $imm",
2170 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2176 let Inst{15-12} = Rd;
2177 let Inst{19-16} = Rn;
2178 let Inst{11-0} = imm;
2180 // The reg/reg form is only defined for the disassembler; for codegen it is
2181 // equivalent to SUBrr.
2182 def RSCrr : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2183 DPFrm, IIC_iALUr, "rsc", "\t$Rd, $Rn, $Rm",
2184 [/* For disassembly only; pattern left blank */]> {
2188 let Inst{11-4} = 0b00000000;
2191 let Inst{15-12} = Rd;
2192 let Inst{19-16} = Rn;
2194 def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2195 DPSoRegFrm, IIC_iALUsr, "rsc", "\t$Rd, $Rn, $shift",
2196 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2202 let Inst{11-0} = shift;
2203 let Inst{15-12} = Rd;
2204 let Inst{19-16} = Rn;
2208 // FIXME: Allow these to be predicated.
2209 let Defs = [CPSR], Uses = [CPSR] in {
2210 def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
2211 DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
2212 [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
2219 let Inst{15-12} = Rd;
2220 let Inst{19-16} = Rn;
2221 let Inst{11-0} = imm;
2223 def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
2224 DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
2225 [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
2232 let Inst{11-0} = shift;
2233 let Inst{15-12} = Rd;
2234 let Inst{19-16} = Rn;
2238 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
2239 // The assume-no-carry-in form uses the negation of the input since add/sub
2240 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
2241 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
2243 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
2244 (SUBri GPR:$src, so_imm_neg:$imm)>;
2245 def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
2246 (SUBSri GPR:$src, so_imm_neg:$imm)>;
2247 // The with-carry-in form matches bitwise not instead of the negation.
2248 // Effectively, the inverse interpretation of the carry flag already accounts
2249 // for part of the negation.
2250 def : ARMPat<(adde GPR:$src, so_imm_not:$imm),
2251 (SBCri GPR:$src, so_imm_not:$imm)>;
2253 // Note: These are implemented in C++ code, because they have to generate
2254 // ADD/SUBrs instructions, which use a complex pattern that a xform function
2256 // (mul X, 2^n+1) -> (add (X << n), X)
2257 // (mul X, 2^n-1) -> (rsb X, (X << n))
2259 // ARM Arithmetic Instruction -- for disassembly only
2260 // GPR:$dst = GPR:$a op GPR:$b
2261 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
2262 list<dag> pattern = [/* For disassembly only; pattern left blank */]>
2263 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iALUr,
2264 opc, "\t$Rd, $Rn, $Rm", pattern> {
2268 let Inst{27-20} = op27_20;
2269 let Inst{11-4} = op11_4;
2270 let Inst{19-16} = Rn;
2271 let Inst{15-12} = Rd;
2275 // Saturating add/subtract -- for disassembly only
2277 def QADD : AAI<0b00010000, 0b00000101, "qadd",
2278 [(set GPR:$Rd, (int_arm_qadd GPR:$Rn, GPR:$Rm))]>;
2279 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
2280 [(set GPR:$Rd, (int_arm_qsub GPR:$Rn, GPR:$Rm))]>;
2281 def QDADD : AAI<0b00010100, 0b00000101, "qdadd">;
2282 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub">;
2284 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
2285 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
2286 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
2287 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
2288 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
2289 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
2290 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
2291 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
2292 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
2293 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
2294 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
2295 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
2297 // Signed/Unsigned add/subtract -- for disassembly only
2299 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
2300 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
2301 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
2302 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
2303 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
2304 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
2305 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
2306 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
2307 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
2308 def USAX : AAI<0b01100101, 0b11110101, "usax">;
2309 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
2310 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
2312 // Signed/Unsigned halving add/subtract -- for disassembly only
2314 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
2315 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
2316 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
2317 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
2318 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
2319 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
2320 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
2321 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
2322 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
2323 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
2324 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
2325 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
2327 // Unsigned Sum of Absolute Differences [and Accumulate] -- for disassembly only
2329 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2330 MulFrm /* for convenience */, NoItinerary, "usad8",
2331 "\t$Rd, $Rn, $Rm", []>,
2332 Requires<[IsARM, HasV6]> {
2336 let Inst{27-20} = 0b01111000;
2337 let Inst{15-12} = 0b1111;
2338 let Inst{7-4} = 0b0001;
2339 let Inst{19-16} = Rd;
2340 let Inst{11-8} = Rm;
2343 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2344 MulFrm /* for convenience */, NoItinerary, "usada8",
2345 "\t$Rd, $Rn, $Rm, $Ra", []>,
2346 Requires<[IsARM, HasV6]> {
2351 let Inst{27-20} = 0b01111000;
2352 let Inst{7-4} = 0b0001;
2353 let Inst{19-16} = Rd;
2354 let Inst{15-12} = Ra;
2355 let Inst{11-8} = Rm;
2359 // Signed/Unsigned saturate -- for disassembly only
2361 def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2362 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh",
2363 [/* For disassembly only; pattern left blank */]> {
2368 let Inst{27-21} = 0b0110101;
2369 let Inst{5-4} = 0b01;
2370 let Inst{20-16} = sat_imm;
2371 let Inst{15-12} = Rd;
2372 let Inst{11-7} = sh{7-3};
2373 let Inst{6} = sh{0};
2377 def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm,
2378 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn",
2379 [/* For disassembly only; pattern left blank */]> {
2383 let Inst{27-20} = 0b01101010;
2384 let Inst{11-4} = 0b11110011;
2385 let Inst{15-12} = Rd;
2386 let Inst{19-16} = sat_imm;
2390 def USAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh),
2391 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $a$sh",
2392 [/* For disassembly only; pattern left blank */]> {
2397 let Inst{27-21} = 0b0110111;
2398 let Inst{5-4} = 0b01;
2399 let Inst{15-12} = Rd;
2400 let Inst{11-7} = sh{7-3};
2401 let Inst{6} = sh{0};
2402 let Inst{20-16} = sat_imm;
2406 def USAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a), SatFrm,
2407 NoItinerary, "usat16", "\t$Rd, $sat_imm, $a",
2408 [/* For disassembly only; pattern left blank */]> {
2412 let Inst{27-20} = 0b01101110;
2413 let Inst{11-4} = 0b11110011;
2414 let Inst{15-12} = Rd;
2415 let Inst{19-16} = sat_imm;
2419 def : ARMV6Pat<(int_arm_ssat GPR:$a, imm:$pos), (SSAT imm:$pos, GPR:$a, 0)>;
2420 def : ARMV6Pat<(int_arm_usat GPR:$a, imm:$pos), (USAT imm:$pos, GPR:$a, 0)>;
2422 //===----------------------------------------------------------------------===//
2423 // Bitwise Instructions.
2426 defm AND : AsI1_bin_irs<0b0000, "and",
2427 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2428 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
2429 defm ORR : AsI1_bin_irs<0b1100, "orr",
2430 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2431 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
2432 defm EOR : AsI1_bin_irs<0b0001, "eor",
2433 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2434 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
2435 defm BIC : AsI1_bin_irs<0b1110, "bic",
2436 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
2437 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
2439 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
2440 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2441 "bfc", "\t$Rd, $imm", "$src = $Rd",
2442 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
2443 Requires<[IsARM, HasV6T2]> {
2446 let Inst{27-21} = 0b0111110;
2447 let Inst{6-0} = 0b0011111;
2448 let Inst{15-12} = Rd;
2449 let Inst{11-7} = imm{4-0}; // lsb
2450 let Inst{20-16} = imm{9-5}; // width
2453 // A8.6.18 BFI - Bitfield insert (Encoding A1)
2454 def BFI : I<(outs GPR:$Rd), (ins GPR:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
2455 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi,
2456 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
2457 [(set GPR:$Rd, (ARMbfi GPR:$src, GPR:$Rn,
2458 bf_inv_mask_imm:$imm))]>,
2459 Requires<[IsARM, HasV6T2]> {
2463 let Inst{27-21} = 0b0111110;
2464 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
2465 let Inst{15-12} = Rd;
2466 let Inst{11-7} = imm{4-0}; // lsb
2467 let Inst{20-16} = imm{9-5}; // width
2471 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
2472 "mvn", "\t$Rd, $Rm",
2473 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
2477 let Inst{19-16} = 0b0000;
2478 let Inst{11-4} = 0b00000000;
2479 let Inst{15-12} = Rd;
2482 def MVNs : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg:$shift), DPSoRegFrm,
2483 IIC_iMVNsr, "mvn", "\t$Rd, $shift",
2484 [(set GPR:$Rd, (not so_reg:$shift))]>, UnaryDP {
2488 let Inst{19-16} = 0b0000;
2489 let Inst{15-12} = Rd;
2490 let Inst{11-0} = shift;
2492 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2493 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
2494 IIC_iMVNi, "mvn", "\t$Rd, $imm",
2495 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
2499 let Inst{19-16} = 0b0000;
2500 let Inst{15-12} = Rd;
2501 let Inst{11-0} = imm;
2504 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
2505 (BICri GPR:$src, so_imm_not:$imm)>;
2507 //===----------------------------------------------------------------------===//
2508 // Multiply Instructions.
2510 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2511 string opc, string asm, list<dag> pattern>
2512 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2516 let Inst{19-16} = Rd;
2517 let Inst{11-8} = Rm;
2520 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
2521 string opc, string asm, list<dag> pattern>
2522 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
2527 let Inst{19-16} = RdHi;
2528 let Inst{15-12} = RdLo;
2529 let Inst{11-8} = Rm;
2533 let isCommutable = 1 in
2534 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2535 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
2536 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>;
2538 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2539 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
2540 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]> {
2542 let Inst{15-12} = Ra;
2545 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2546 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
2547 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
2548 Requires<[IsARM, HasV6T2]> {
2553 let Inst{19-16} = Rd;
2554 let Inst{15-12} = Ra;
2555 let Inst{11-8} = Rm;
2559 // Extra precision multiplies with low / high results
2561 let neverHasSideEffects = 1 in {
2562 let isCommutable = 1 in {
2563 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
2564 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2565 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2567 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
2568 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
2569 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2572 // Multiply + accumulate
2573 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
2574 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2575 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2577 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
2578 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2579 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
2581 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
2582 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
2583 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
2584 Requires<[IsARM, HasV6]> {
2589 let Inst{19-16} = RdLo;
2590 let Inst{15-12} = RdHi;
2591 let Inst{11-8} = Rm;
2594 } // neverHasSideEffects
2596 // Most significant word multiply
2597 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2598 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
2599 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
2600 Requires<[IsARM, HasV6]> {
2601 let Inst{15-12} = 0b1111;
2604 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2605 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
2606 [/* For disassembly only; pattern left blank */]>,
2607 Requires<[IsARM, HasV6]> {
2608 let Inst{15-12} = 0b1111;
2611 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
2612 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2613 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
2614 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
2615 Requires<[IsARM, HasV6]>;
2617 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
2618 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2619 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
2620 [/* For disassembly only; pattern left blank */]>,
2621 Requires<[IsARM, HasV6]>;
2623 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
2624 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2625 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
2626 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
2627 Requires<[IsARM, HasV6]>;
2629 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
2630 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2631 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
2632 [/* For disassembly only; pattern left blank */]>,
2633 Requires<[IsARM, HasV6]>;
2635 multiclass AI_smul<string opc, PatFrag opnode> {
2636 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2637 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
2638 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2639 (sext_inreg GPR:$Rm, i16)))]>,
2640 Requires<[IsARM, HasV5TE]>;
2642 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2643 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
2644 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
2645 (sra GPR:$Rm, (i32 16))))]>,
2646 Requires<[IsARM, HasV5TE]>;
2648 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2649 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
2650 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2651 (sext_inreg GPR:$Rm, i16)))]>,
2652 Requires<[IsARM, HasV5TE]>;
2654 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2655 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
2656 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
2657 (sra GPR:$Rm, (i32 16))))]>,
2658 Requires<[IsARM, HasV5TE]>;
2660 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2661 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
2662 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2663 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
2664 Requires<[IsARM, HasV5TE]>;
2666 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2667 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
2668 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
2669 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
2670 Requires<[IsARM, HasV5TE]>;
2674 multiclass AI_smla<string opc, PatFrag opnode> {
2675 def BB : AMulxyIa<0b0001000, 0b00, (outs GPR:$Rd),
2676 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2677 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
2678 [(set GPR:$Rd, (add GPR:$Ra,
2679 (opnode (sext_inreg GPR:$Rn, i16),
2680 (sext_inreg GPR:$Rm, i16))))]>,
2681 Requires<[IsARM, HasV5TE]>;
2683 def BT : AMulxyIa<0b0001000, 0b10, (outs GPR:$Rd),
2684 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2685 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
2686 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sext_inreg GPR:$Rn, i16),
2687 (sra GPR:$Rm, (i32 16)))))]>,
2688 Requires<[IsARM, HasV5TE]>;
2690 def TB : AMulxyIa<0b0001000, 0b01, (outs GPR:$Rd),
2691 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2692 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
2693 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2694 (sext_inreg GPR:$Rm, i16))))]>,
2695 Requires<[IsARM, HasV5TE]>;
2697 def TT : AMulxyIa<0b0001000, 0b11, (outs GPR:$Rd),
2698 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2699 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
2700 [(set GPR:$Rd, (add GPR:$Ra, (opnode (sra GPR:$Rn, (i32 16)),
2701 (sra GPR:$Rm, (i32 16)))))]>,
2702 Requires<[IsARM, HasV5TE]>;
2704 def WB : AMulxyIa<0b0001001, 0b00, (outs GPR:$Rd),
2705 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2706 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
2707 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2708 (sext_inreg GPR:$Rm, i16)), (i32 16))))]>,
2709 Requires<[IsARM, HasV5TE]>;
2711 def WT : AMulxyIa<0b0001001, 0b10, (outs GPR:$Rd),
2712 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2713 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
2714 [(set GPR:$Rd, (add GPR:$Ra, (sra (opnode GPR:$Rn,
2715 (sra GPR:$Rm, (i32 16))), (i32 16))))]>,
2716 Requires<[IsARM, HasV5TE]>;
2719 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2720 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
2722 // Halfword multiply accumulate long: SMLAL<x><y> -- for disassembly only
2723 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPR:$RdLo, GPR:$RdHi),
2724 (ins GPR:$Rn, GPR:$Rm),
2725 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm",
2726 [/* For disassembly only; pattern left blank */]>,
2727 Requires<[IsARM, HasV5TE]>;
2729 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPR:$RdLo, GPR:$RdHi),
2730 (ins GPR:$Rn, GPR:$Rm),
2731 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm",
2732 [/* For disassembly only; pattern left blank */]>,
2733 Requires<[IsARM, HasV5TE]>;
2735 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPR:$RdLo, GPR:$RdHi),
2736 (ins GPR:$Rn, GPR:$Rm),
2737 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm",
2738 [/* For disassembly only; pattern left blank */]>,
2739 Requires<[IsARM, HasV5TE]>;
2741 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPR:$RdLo, GPR:$RdHi),
2742 (ins GPR:$Rn, GPR:$Rm),
2743 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm",
2744 [/* For disassembly only; pattern left blank */]>,
2745 Requires<[IsARM, HasV5TE]>;
2747 // Helper class for AI_smld -- for disassembly only
2748 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
2749 InstrItinClass itin, string opc, string asm>
2750 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
2757 let Inst{21-20} = 0b00;
2758 let Inst{22} = long;
2759 let Inst{27-23} = 0b01110;
2760 let Inst{11-8} = Rm;
2763 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
2764 InstrItinClass itin, string opc, string asm>
2765 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2767 let Inst{15-12} = 0b1111;
2768 let Inst{19-16} = Rd;
2770 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
2771 InstrItinClass itin, string opc, string asm>
2772 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2774 let Inst{15-12} = Ra;
2776 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
2777 InstrItinClass itin, string opc, string asm>
2778 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
2781 let Inst{19-16} = RdHi;
2782 let Inst{15-12} = RdLo;
2785 multiclass AI_smld<bit sub, string opc> {
2787 def D : AMulDualIa<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2788 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
2790 def DX: AMulDualIa<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
2791 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
2793 def LD: AMulDualI64<1, sub, 0, (outs GPR:$RdLo,GPR:$RdHi),
2794 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2795 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
2797 def LDX : AMulDualI64<1, sub, 1, (outs GPR:$RdLo,GPR:$RdHi),
2798 (ins GPR:$Rn, GPR:$Rm), NoItinerary,
2799 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
2803 defm SMLA : AI_smld<0, "smla">;
2804 defm SMLS : AI_smld<1, "smls">;
2806 multiclass AI_sdml<bit sub, string opc> {
2808 def D : AMulDualI<0, sub, 0, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2809 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
2810 def DX : AMulDualI<0, sub, 1, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2811 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
2814 defm SMUA : AI_sdml<0, "smua">;
2815 defm SMUS : AI_sdml<1, "smus">;
2817 //===----------------------------------------------------------------------===//
2818 // Misc. Arithmetic Instructions.
2821 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
2822 IIC_iUNAr, "clz", "\t$Rd, $Rm",
2823 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
2825 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2826 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
2827 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
2828 Requires<[IsARM, HasV6T2]>;
2830 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
2831 IIC_iUNAr, "rev", "\t$Rd, $Rm",
2832 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
2834 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2835 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
2837 (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
2838 (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
2839 (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
2840 (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
2841 Requires<[IsARM, HasV6]>;
2843 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
2844 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
2847 (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
2848 (shl GPR:$Rm, (i32 8))), i16))]>,
2849 Requires<[IsARM, HasV6]>;
2851 def lsl_shift_imm : SDNodeXForm<imm, [{
2852 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2853 return CurDAG->getTargetConstant(Sh, MVT::i32);
2856 def lsl_amt : PatLeaf<(i32 imm), [{
2857 return (N->getZExtValue() < 32);
2860 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
2861 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2862 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
2863 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
2864 (and (shl GPR:$Rm, lsl_amt:$sh),
2866 Requires<[IsARM, HasV6]>;
2868 // Alternate cases for PKHBT where identities eliminate some nodes.
2869 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
2870 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
2871 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
2872 (PKHBT GPR:$Rn, GPR:$Rm, (lsl_shift_imm imm16_31:$sh))>;
2874 def asr_shift_imm : SDNodeXForm<imm, [{
2875 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2876 return CurDAG->getTargetConstant(Sh, MVT::i32);
2879 def asr_amt : PatLeaf<(i32 imm), [{
2880 return (N->getZExtValue() <= 32);
2883 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2884 // will match the pattern below.
2885 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
2886 (ins GPR:$Rn, GPR:$Rm, shift_imm:$sh),
2887 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
2888 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
2889 (and (sra GPR:$Rm, asr_amt:$sh),
2891 Requires<[IsARM, HasV6]>;
2893 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
2894 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2895 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2896 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
2897 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2898 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2899 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
2901 //===----------------------------------------------------------------------===//
2902 // Comparison Instructions...
2905 defm CMP : AI1_cmp_irs<0b1010, "cmp",
2906 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2907 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
2909 // ARMcmpZ can re-use the above instruction definitions.
2910 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
2911 (CMPri GPR:$src, so_imm:$imm)>;
2912 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
2913 (CMPrr GPR:$src, GPR:$rhs)>;
2914 def : ARMPat<(ARMcmpZ GPR:$src, so_reg:$rhs),
2915 (CMPrs GPR:$src, so_reg:$rhs)>;
2917 // FIXME: We have to be careful when using the CMN instruction and comparison
2918 // with 0. One would expect these two pieces of code should give identical
2934 // However, the CMN gives the *opposite* result when r1 is 0. This is because
2935 // the carry flag is set in the CMP case but not in the CMN case. In short, the
2936 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
2937 // value of r0 and the carry bit (because the "carry bit" parameter to
2938 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
2939 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
2940 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
2941 // parameter to AddWithCarry is defined as 0).
2943 // When x is 0 and unsigned:
2947 // ~x + 1 = 0x1 0000 0000
2948 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
2950 // Therefore, we should disable CMN when comparing against zero, until we can
2951 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
2952 // when it's a comparison which doesn't look at the 'carry' flag).
2954 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
2956 // This is related to <rdar://problem/7569620>.
2958 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
2959 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
2961 // Note that TST/TEQ don't set all the same flags that CMP does!
2962 defm TST : AI1_cmp_irs<0b1000, "tst",
2963 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2964 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
2965 defm TEQ : AI1_cmp_irs<0b1001, "teq",
2966 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
2967 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
2969 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
2970 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
2971 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
2973 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
2974 // (CMNri GPR:$src, so_imm_neg:$imm)>;
2976 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
2977 (CMNzri GPR:$src, so_imm_neg:$imm)>;
2979 // Pseudo i64 compares for some floating point compares.
2980 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
2982 def BCCi64 : PseudoInst<(outs),
2983 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
2985 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
2987 def BCCZi64 : PseudoInst<(outs),
2988 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
2989 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
2990 } // usesCustomInserter
2993 // Conditional moves
2994 // FIXME: should be able to write a pattern for ARMcmov, but can't use
2995 // a two-value operand where a dag node expects two operands. :(
2996 // FIXME: These should all be pseudo-instructions that get expanded to
2997 // the normal MOV instructions. That would fix the dependency on
2998 // special casing them in tblgen.
2999 let neverHasSideEffects = 1 in {
3000 def MOVCCr : AI1<0b1101, (outs GPR:$Rd), (ins GPR:$false, GPR:$Rm), DPFrm,
3001 IIC_iCMOVr, "mov", "\t$Rd, $Rm",
3002 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
3003 RegConstraint<"$false = $Rd">, UnaryDP {
3008 let Inst{15-12} = Rd;
3009 let Inst{11-4} = 0b00000000;
3013 def MOVCCs : AI1<0b1101, (outs GPR:$Rd),
3014 (ins GPR:$false, so_reg:$shift), DPSoRegFrm, IIC_iCMOVsr,
3015 "mov", "\t$Rd, $shift",
3016 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg:$shift, imm:$cc, CCR:$ccr))*/]>,
3017 RegConstraint<"$false = $Rd">, UnaryDP {
3022 let Inst{19-16} = 0;
3023 let Inst{15-12} = Rd;
3024 let Inst{11-0} = shift;
3027 let isMoveImm = 1 in
3028 def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, movt_imm:$imm),
3030 "movw", "\t$Rd, $imm",
3032 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
3038 let Inst{19-16} = imm{15-12};
3039 let Inst{15-12} = Rd;
3040 let Inst{11-0} = imm{11-0};
3043 let isMoveImm = 1 in
3044 def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
3045 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3046 "mov", "\t$Rd, $imm",
3047 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
3048 RegConstraint<"$false = $Rd">, UnaryDP {
3053 let Inst{19-16} = 0b0000;
3054 let Inst{15-12} = Rd;
3055 let Inst{11-0} = imm;
3058 // Two instruction predicate mov immediate.
3059 let isMoveImm = 1 in
3060 def MOVCCi32imm : PseudoInst<(outs GPR:$Rd),
3061 (ins GPR:$false, i32imm:$src, pred:$p),
3062 IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
3064 let isMoveImm = 1 in
3065 def MVNCCi : AI1<0b1111, (outs GPR:$Rd),
3066 (ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
3067 "mvn", "\t$Rd, $imm",
3068 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
3069 RegConstraint<"$false = $Rd">, UnaryDP {
3074 let Inst{19-16} = 0b0000;
3075 let Inst{15-12} = Rd;
3076 let Inst{11-0} = imm;
3078 } // neverHasSideEffects
3080 //===----------------------------------------------------------------------===//
3081 // Atomic operations intrinsics
3084 def memb_opt : Operand<i32> {
3085 let PrintMethod = "printMemBOption";
3088 // memory barriers protect the atomic sequences
3089 let hasSideEffects = 1 in {
3090 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3091 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
3092 Requires<[IsARM, HasDB]> {
3094 let Inst{31-4} = 0xf57ff05;
3095 let Inst{3-0} = opt;
3098 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
3099 "mcr", "\tp15, 0, $zero, c7, c10, 5",
3100 [(ARMMemBarrierMCR GPR:$zero)]>,
3101 Requires<[IsARM, HasV6]> {
3102 // FIXME: add encoding
3106 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
3108 [/* For disassembly only; pattern left blank */]>,
3109 Requires<[IsARM, HasDB]> {
3111 let Inst{31-4} = 0xf57ff04;
3112 let Inst{3-0} = opt;
3115 // ISB has only full system option -- for disassembly only
3116 def ISB : AInoP<(outs), (ins), MiscFrm, NoItinerary, "isb", "", []>,
3117 Requires<[IsARM, HasDB]> {
3118 let Inst{31-4} = 0xf57ff06;
3119 let Inst{3-0} = 0b1111;
3122 let usesCustomInserter = 1 in {
3123 let Uses = [CPSR] in {
3124 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
3125 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3126 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
3127 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
3128 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3129 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
3130 def ATOMIC_LOAD_AND_I8 : PseudoInst<
3131 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3132 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
3133 def ATOMIC_LOAD_OR_I8 : PseudoInst<
3134 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3135 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
3136 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
3137 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3138 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
3139 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
3140 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3141 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
3142 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
3143 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3144 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
3145 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
3146 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3147 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
3148 def ATOMIC_LOAD_AND_I16 : PseudoInst<
3149 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3150 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
3151 def ATOMIC_LOAD_OR_I16 : PseudoInst<
3152 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3153 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
3154 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
3155 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3156 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
3157 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
3158 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3159 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
3160 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
3161 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3162 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
3163 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
3164 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3165 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
3166 def ATOMIC_LOAD_AND_I32 : PseudoInst<
3167 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3168 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
3169 def ATOMIC_LOAD_OR_I32 : PseudoInst<
3170 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3171 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
3172 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
3173 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3174 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
3175 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
3176 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
3177 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
3179 def ATOMIC_SWAP_I8 : PseudoInst<
3180 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3181 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
3182 def ATOMIC_SWAP_I16 : PseudoInst<
3183 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3184 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
3185 def ATOMIC_SWAP_I32 : PseudoInst<
3186 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
3187 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
3189 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
3190 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3191 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
3192 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
3193 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3194 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
3195 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
3196 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
3197 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
3201 let mayLoad = 1 in {
3202 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3203 "ldrexb", "\t$Rt, [$Rn]",
3205 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3206 "ldrexh", "\t$Rt, [$Rn]",
3208 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins GPR:$Rn), NoItinerary,
3209 "ldrex", "\t$Rt, [$Rn]",
3211 def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins GPR:$Rn),
3213 "ldrexd", "\t$Rt, $Rt2, [$Rn]",
3217 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3218 def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$src, GPR:$Rn),
3220 "strexb", "\t$Rd, $src, [$Rn]",
3222 def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3224 "strexh", "\t$Rd, $Rt, [$Rn]",
3226 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, GPR:$Rn),
3228 "strex", "\t$Rd, $Rt, [$Rn]",
3230 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
3231 (ins GPR:$Rt, GPR:$Rt2, GPR:$Rn),
3233 "strexd", "\t$Rd, $Rt, $Rt2, [$Rn]",
3237 // Clear-Exclusive is for disassembly only.
3238 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
3239 [/* For disassembly only; pattern left blank */]>,
3240 Requires<[IsARM, HasV7]> {
3241 let Inst{31-0} = 0b11110101011111111111000000011111;
3244 // SWP/SWPB are deprecated in V6/V7 and for disassembly only.
3245 let mayLoad = 1 in {
3246 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swp",
3247 [/* For disassembly only; pattern left blank */]>;
3248 def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
3249 [/* For disassembly only; pattern left blank */]>;
3252 //===----------------------------------------------------------------------===//
3256 // __aeabi_read_tp preserves the registers r1-r3.
3257 // This is a pseudo inst so that we can get the encoding right,
3258 // complete with fixup for the aeabi_read_tp function.
3260 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
3261 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
3262 [(set R0, ARMthread_pointer)]>;
3265 //===----------------------------------------------------------------------===//
3266 // SJLJ Exception handling intrinsics
3267 // eh_sjlj_setjmp() is an instruction sequence to store the return
3268 // address and save #0 in R0 for the non-longjmp case.
3269 // Since by its nature we may be coming from some other function to get
3270 // here, and we're using the stack frame for the containing function to
3271 // save/restore registers, we can't keep anything live in regs across
3272 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
3273 // when we get here from a longjmp(). We force everthing out of registers
3274 // except for our own input by listing the relevant registers in Defs. By
3275 // doing so, we also cause the prologue/epilogue code to actively preserve
3276 // all of the callee-saved resgisters, which is exactly what we want.
3277 // A constant value is passed in $val, and we use the location as a scratch.
3279 // These are pseudo-instructions and are lowered to individual MC-insts, so
3280 // no encoding information is necessary.
3282 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
3283 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
3284 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
3285 D31 ], hasSideEffects = 1, isBarrier = 1 in {
3286 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3288 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3289 Requires<[IsARM, HasVFP2]>;
3293 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR ],
3294 hasSideEffects = 1, isBarrier = 1 in {
3295 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
3297 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
3298 Requires<[IsARM, NoVFP]>;
3301 // FIXME: Non-Darwin version(s)
3302 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
3303 Defs = [ R7, LR, SP ] in {
3304 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
3306 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
3307 Requires<[IsARM, IsDarwin]>;
3310 // eh.sjlj.dispatchsetup pseudo-instruction.
3311 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
3312 // handled when the pseudo is expanded (which happens before any passes
3313 // that need the instruction size).
3314 let isBarrier = 1, hasSideEffects = 1 in
3315 def Int_eh_sjlj_dispatchsetup :
3316 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
3317 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
3318 Requires<[IsDarwin]>;
3320 //===----------------------------------------------------------------------===//
3321 // Non-Instruction Patterns
3324 // Large immediate handling.
3326 // 32-bit immediate using two piece so_imms or movw + movt.
3327 // This is a single pseudo instruction, the benefit is that it can be remat'd
3328 // as a single unit instead of having to handle reg inputs.
3329 // FIXME: Remove this when we can do generalized remat.
3330 let isReMaterializable = 1, isMoveImm = 1 in
3331 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
3332 [(set GPR:$dst, (arm_i32imm:$src))]>,
3335 // ConstantPool, GlobalAddress, and JumpTable
3336 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
3337 Requires<[IsARM, DontUseMovt]>;
3338 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
3339 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
3340 Requires<[IsARM, UseMovt]>;
3341 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
3342 (LEApcrelJT tjumptable:$dst, imm:$id)>;
3344 // TODO: add,sub,and, 3-instr forms?
3347 def : ARMPat<(ARMtcret tcGPR:$dst),
3348 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
3350 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3351 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3353 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3354 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
3356 def : ARMPat<(ARMtcret tcGPR:$dst),
3357 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
3359 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
3360 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3362 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
3363 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
3366 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
3367 Requires<[IsARM, IsNotDarwin]>;
3368 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
3369 Requires<[IsARM, IsDarwin]>;
3371 // zextload i1 -> zextload i8
3372 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3373 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3375 // extload -> zextload
3376 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3377 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3378 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
3379 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
3381 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
3383 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
3384 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
3387 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3388 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3389 (SMULBB GPR:$a, GPR:$b)>;
3390 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
3391 (SMULBB GPR:$a, GPR:$b)>;
3392 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3393 (sra GPR:$b, (i32 16))),
3394 (SMULBT GPR:$a, GPR:$b)>;
3395 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
3396 (SMULBT GPR:$a, GPR:$b)>;
3397 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
3398 (sra (shl GPR:$b, (i32 16)), (i32 16))),
3399 (SMULTB GPR:$a, GPR:$b)>;
3400 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
3401 (SMULTB GPR:$a, GPR:$b)>;
3402 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3404 (SMULWB GPR:$a, GPR:$b)>;
3405 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
3406 (SMULWB GPR:$a, GPR:$b)>;
3408 def : ARMV5TEPat<(add GPR:$acc,
3409 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3410 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3411 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3412 def : ARMV5TEPat<(add GPR:$acc,
3413 (mul sext_16_node:$a, sext_16_node:$b)),
3414 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
3415 def : ARMV5TEPat<(add GPR:$acc,
3416 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
3417 (sra GPR:$b, (i32 16)))),
3418 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3419 def : ARMV5TEPat<(add GPR:$acc,
3420 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
3421 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
3422 def : ARMV5TEPat<(add GPR:$acc,
3423 (mul (sra GPR:$a, (i32 16)),
3424 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
3425 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3426 def : ARMV5TEPat<(add GPR:$acc,
3427 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
3428 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
3429 def : ARMV5TEPat<(add GPR:$acc,
3430 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
3432 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3433 def : ARMV5TEPat<(add GPR:$acc,
3434 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
3435 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
3437 //===----------------------------------------------------------------------===//
3441 include "ARMInstrThumb.td"
3443 //===----------------------------------------------------------------------===//
3447 include "ARMInstrThumb2.td"
3449 //===----------------------------------------------------------------------===//
3450 // Floating Point Support
3453 include "ARMInstrVFP.td"
3455 //===----------------------------------------------------------------------===//
3456 // Advanced SIMD (NEON) Support
3459 include "ARMInstrNEON.td"
3461 //===----------------------------------------------------------------------===//
3462 // Coprocessor Instructions. For disassembly only.
3465 def CDP : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3466 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3467 NoItinerary, "cdp", "\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3468 [/* For disassembly only; pattern left blank */]> {
3472 def CDP2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3473 nohash_imm:$CRd, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3474 NoItinerary, "cdp2\tp$cop, $opc1, cr$CRd, cr$CRn, cr$CRm, $opc2",
3475 [/* For disassembly only; pattern left blank */]> {
3476 let Inst{31-28} = 0b1111;
3480 class ACI<dag oops, dag iops, string opc, string asm>
3481 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, NoItinerary,
3482 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
3483 let Inst{27-25} = 0b110;
3486 multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
3488 def _OFFSET : ACI<(outs),
3489 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3490 opc, "\tp$cop, cr$CRd, $addr"> {
3491 let Inst{31-28} = op31_28;
3492 let Inst{24} = 1; // P = 1
3493 let Inst{21} = 0; // W = 0
3494 let Inst{22} = 0; // D = 0
3495 let Inst{20} = load;
3498 def _PRE : ACI<(outs),
3499 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3500 opc, "\tp$cop, cr$CRd, $addr!"> {
3501 let Inst{31-28} = op31_28;
3502 let Inst{24} = 1; // P = 1
3503 let Inst{21} = 1; // W = 1
3504 let Inst{22} = 0; // D = 0
3505 let Inst{20} = load;
3508 def _POST : ACI<(outs),
3509 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3510 opc, "\tp$cop, cr$CRd, [$base], $offset"> {
3511 let Inst{31-28} = op31_28;
3512 let Inst{24} = 0; // P = 0
3513 let Inst{21} = 1; // W = 1
3514 let Inst{22} = 0; // D = 0
3515 let Inst{20} = load;
3518 def _OPTION : ACI<(outs),
3519 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, i32imm:$option),
3520 opc, "\tp$cop, cr$CRd, [$base], $option"> {
3521 let Inst{31-28} = op31_28;
3522 let Inst{24} = 0; // P = 0
3523 let Inst{23} = 1; // U = 1
3524 let Inst{21} = 0; // W = 0
3525 let Inst{22} = 0; // D = 0
3526 let Inst{20} = load;
3529 def L_OFFSET : ACI<(outs),
3530 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3531 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
3532 let Inst{31-28} = op31_28;
3533 let Inst{24} = 1; // P = 1
3534 let Inst{21} = 0; // W = 0
3535 let Inst{22} = 1; // D = 1
3536 let Inst{20} = load;
3539 def L_PRE : ACI<(outs),
3540 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3541 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
3542 let Inst{31-28} = op31_28;
3543 let Inst{24} = 1; // P = 1
3544 let Inst{21} = 1; // W = 1
3545 let Inst{22} = 1; // D = 1
3546 let Inst{20} = load;
3549 def L_POST : ACI<(outs),
3550 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, am2offset:$offset),
3551 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $offset"> {
3552 let Inst{31-28} = op31_28;
3553 let Inst{24} = 0; // P = 0
3554 let Inst{21} = 1; // W = 1
3555 let Inst{22} = 1; // D = 1
3556 let Inst{20} = load;
3559 def L_OPTION : ACI<(outs),
3560 (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
3561 !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], $option"> {
3562 let Inst{31-28} = op31_28;
3563 let Inst{24} = 0; // P = 0
3564 let Inst{23} = 1; // U = 1
3565 let Inst{21} = 0; // W = 0
3566 let Inst{22} = 1; // D = 1
3567 let Inst{20} = load;
3571 defm LDC : LdStCop<{?,?,?,?}, 1, "ldc">;
3572 defm LDC2 : LdStCop<0b1111, 1, "ldc2">;
3573 defm STC : LdStCop<{?,?,?,?}, 0, "stc">;
3574 defm STC2 : LdStCop<0b1111, 0, "stc2">;
3576 def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3577 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3578 NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3579 [/* For disassembly only; pattern left blank */]> {
3584 def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3585 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3586 NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3587 [/* For disassembly only; pattern left blank */]> {
3588 let Inst{31-28} = 0b1111;
3593 def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3594 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3595 NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3596 [/* For disassembly only; pattern left blank */]> {
3601 def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1,
3602 GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2),
3603 NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2",
3604 [/* For disassembly only; pattern left blank */]> {
3605 let Inst{31-28} = 0b1111;
3610 def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3611 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3612 NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3613 [/* For disassembly only; pattern left blank */]> {
3614 let Inst{23-20} = 0b0100;
3617 def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3618 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3619 NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3620 [/* For disassembly only; pattern left blank */]> {
3621 let Inst{31-28} = 0b1111;
3622 let Inst{23-20} = 0b0100;
3625 def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3626 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3627 NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3628 [/* For disassembly only; pattern left blank */]> {
3629 let Inst{23-20} = 0b0101;
3632 def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc,
3633 GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm),
3634 NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm",
3635 [/* For disassembly only; pattern left blank */]> {
3636 let Inst{31-28} = 0b1111;
3637 let Inst{23-20} = 0b0101;
3640 //===----------------------------------------------------------------------===//
3641 // Move between special register and ARM core register -- for disassembly only
3644 def MRS : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary, "mrs", "\t$dst, cpsr",
3645 [/* For disassembly only; pattern left blank */]> {
3646 let Inst{23-20} = 0b0000;
3647 let Inst{7-4} = 0b0000;
3650 def MRSsys : ABI<0b0001,(outs GPR:$dst),(ins), NoItinerary,"mrs","\t$dst, spsr",
3651 [/* For disassembly only; pattern left blank */]> {
3652 let Inst{23-20} = 0b0100;
3653 let Inst{7-4} = 0b0000;
3656 def MSR : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3657 "msr", "\tcpsr$mask, $src",
3658 [/* For disassembly only; pattern left blank */]> {
3659 let Inst{23-20} = 0b0010;
3660 let Inst{7-4} = 0b0000;
3663 def MSRi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3664 "msr", "\tcpsr$mask, $a",
3665 [/* For disassembly only; pattern left blank */]> {
3666 let Inst{23-20} = 0b0010;
3667 let Inst{7-4} = 0b0000;
3670 def MSRsys : ABI<0b0001, (outs), (ins GPR:$src, msr_mask:$mask), NoItinerary,
3671 "msr", "\tspsr$mask, $src",
3672 [/* For disassembly only; pattern left blank */]> {
3673 let Inst{23-20} = 0b0110;
3674 let Inst{7-4} = 0b0000;
3677 def MSRsysi : ABI<0b0011, (outs), (ins so_imm:$a, msr_mask:$mask), NoItinerary,
3678 "msr", "\tspsr$mask, $a",
3679 [/* For disassembly only; pattern left blank */]> {
3680 let Inst{23-20} = 0b0110;
3681 let Inst{7-4} = 0b0000;