1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
43 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
44 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
46 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
47 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
50 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
51 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
53 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
54 [SDNPHasChain, SDNPOutFlag]>;
55 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
58 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
59 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
60 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
61 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
62 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
63 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
65 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
66 [SDNPHasChain, SDNPOptInFlag]>;
68 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
70 def ARMcneg : SDNode<"ARMISD::CNEG", SDT_ARMCMov,
73 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
74 [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
76 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
78 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
81 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
84 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
85 [SDNPOutFlag,SDNPCommutative]>;
87 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
89 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
90 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutFlag]>;
91 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInFlag ]>;
93 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
94 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP", SDT_ARMEH_SJLJ_Setjmp>;
96 //===----------------------------------------------------------------------===//
97 // ARM Instruction Predicate Definitions.
99 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
100 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">;
101 def HasV6 : Predicate<"Subtarget->hasV6Ops()">;
102 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">;
103 def HasV7 : Predicate<"Subtarget->hasV7Ops()">;
104 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
105 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
106 def HasNEON : Predicate<"Subtarget->hasNEON()">;
107 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
108 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
109 def IsThumb : Predicate<"Subtarget->isThumb()">;
110 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
111 def IsThumb2 : Predicate<"Subtarget->isThumb2()">;
112 def IsARM : Predicate<"!Subtarget->isThumb()">;
113 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
114 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
115 def CarryDefIsUnused : Predicate<"!N.getNode()->hasAnyUseOfValue(1)">;
116 def CarryDefIsUsed : Predicate<"N.getNode()->hasAnyUseOfValue(1)">;
118 //===----------------------------------------------------------------------===//
119 // ARM Flag Definitions.
121 class RegConstraint<string C> {
122 string Constraints = C;
125 //===----------------------------------------------------------------------===//
126 // ARM specific transformation functions and pattern fragments.
129 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
130 // so_imm_neg def below.
131 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
132 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
135 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
136 // so_imm_not def below.
137 def so_imm_not_XFORM : SDNodeXForm<imm, [{
138 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
141 // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24.
142 def rot_imm : PatLeaf<(i32 imm), [{
143 int32_t v = (int32_t)N->getZExtValue();
144 return v == 8 || v == 16 || v == 24;
147 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
148 def imm1_15 : PatLeaf<(i32 imm), [{
149 return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 16;
152 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
153 def imm16_31 : PatLeaf<(i32 imm), [{
154 return (int32_t)N->getZExtValue() >= 16 && (int32_t)N->getZExtValue() < 32;
159 return ARM_AM::getSOImmVal(-(int)N->getZExtValue()) != -1;
160 }], so_imm_neg_XFORM>;
164 return ARM_AM::getSOImmVal(~(int)N->getZExtValue()) != -1;
165 }], so_imm_not_XFORM>;
167 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
168 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
169 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
172 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
174 def bf_inv_mask_imm : Operand<i32>,
176 uint32_t v = (uint32_t)N->getZExtValue();
179 // there can be 1's on either or both "outsides", all the "inside"
181 unsigned int lsb = 0, msb = 31;
182 while (v & (1 << msb)) --msb;
183 while (v & (1 << lsb)) ++lsb;
184 for (unsigned int i = lsb; i <= msb; ++i) {
190 let PrintMethod = "printBitfieldInvMaskImmOperand";
193 /// Split a 32-bit immediate into two 16 bit parts.
194 def lo16 : SDNodeXForm<imm, [{
195 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
199 def hi16 : SDNodeXForm<imm, [{
200 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
203 def lo16AllZero : PatLeaf<(i32 imm), [{
204 // Returns true if all low 16-bits are 0.
205 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
208 /// imm0_65535 predicate - True if the 32-bit immediate is in the range
210 def imm0_65535 : PatLeaf<(i32 imm), [{
211 return (uint32_t)N->getZExtValue() < 65536;
214 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
215 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
217 //===----------------------------------------------------------------------===//
218 // Operand Definitions.
222 def brtarget : Operand<OtherVT>;
224 // A list of registers separated by comma. Used by load/store multiple.
225 def reglist : Operand<i32> {
226 let PrintMethod = "printRegisterList";
229 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
230 def cpinst_operand : Operand<i32> {
231 let PrintMethod = "printCPInstOperand";
234 def jtblock_operand : Operand<i32> {
235 let PrintMethod = "printJTBlockOperand";
237 def jt2block_operand : Operand<i32> {
238 let PrintMethod = "printJT2BlockOperand";
242 def pclabel : Operand<i32> {
243 let PrintMethod = "printPCLabel";
246 // shifter_operand operands: so_reg and so_imm.
247 def so_reg : Operand<i32>, // reg reg imm
248 ComplexPattern<i32, 3, "SelectShifterOperandReg",
249 [shl,srl,sra,rotr]> {
250 let PrintMethod = "printSORegOperand";
251 let MIOperandInfo = (ops GPR, GPR, i32imm);
254 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
255 // 8-bit immediate rotated by an arbitrary number of bits. so_imm values are
256 // represented in the imm field in the same 12-bit form that they are encoded
257 // into so_imm instructions: the 8-bit immediate is the least significant bits
258 // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11].
259 def so_imm : Operand<i32>,
261 return ARM_AM::getSOImmVal(N->getZExtValue()) != -1;
263 let PrintMethod = "printSOImmOperand";
266 // Break so_imm's up into two pieces. This handles immediates with up to 16
267 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
268 // get the first/second pieces.
269 def so_imm2part : Operand<i32>,
271 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
273 let PrintMethod = "printSOImm2PartOperand";
276 def so_imm2part_1 : SDNodeXForm<imm, [{
277 unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue());
278 return CurDAG->getTargetConstant(V, MVT::i32);
281 def so_imm2part_2 : SDNodeXForm<imm, [{
282 unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue());
283 return CurDAG->getTargetConstant(V, MVT::i32);
287 // Define ARM specific addressing modes.
289 // addrmode2 := reg +/- reg shop imm
290 // addrmode2 := reg +/- imm12
292 def addrmode2 : Operand<i32>,
293 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
294 let PrintMethod = "printAddrMode2Operand";
295 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
298 def am2offset : Operand<i32>,
299 ComplexPattern<i32, 2, "SelectAddrMode2Offset", []> {
300 let PrintMethod = "printAddrMode2OffsetOperand";
301 let MIOperandInfo = (ops GPR, i32imm);
304 // addrmode3 := reg +/- reg
305 // addrmode3 := reg +/- imm8
307 def addrmode3 : Operand<i32>,
308 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
309 let PrintMethod = "printAddrMode3Operand";
310 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
313 def am3offset : Operand<i32>,
314 ComplexPattern<i32, 2, "SelectAddrMode3Offset", []> {
315 let PrintMethod = "printAddrMode3OffsetOperand";
316 let MIOperandInfo = (ops GPR, i32imm);
319 // addrmode4 := reg, <mode|W>
321 def addrmode4 : Operand<i32>,
322 ComplexPattern<i32, 2, "SelectAddrMode4", []> {
323 let PrintMethod = "printAddrMode4Operand";
324 let MIOperandInfo = (ops GPR, i32imm);
327 // addrmode5 := reg +/- imm8*4
329 def addrmode5 : Operand<i32>,
330 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
331 let PrintMethod = "printAddrMode5Operand";
332 let MIOperandInfo = (ops GPR, i32imm);
335 // addrmode6 := reg with optional writeback
337 def addrmode6 : Operand<i32>,
338 ComplexPattern<i32, 3, "SelectAddrMode6", []> {
339 let PrintMethod = "printAddrMode6Operand";
340 let MIOperandInfo = (ops GPR:$addr, GPR:$upd, i32imm);
343 // addrmodepc := pc + reg
345 def addrmodepc : Operand<i32>,
346 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
347 let PrintMethod = "printAddrModePCOperand";
348 let MIOperandInfo = (ops GPR, i32imm);
351 def nohash_imm : Operand<i32> {
352 let PrintMethod = "printNoHashImmediate";
355 //===----------------------------------------------------------------------===//
357 include "ARMInstrFormats.td"
359 //===----------------------------------------------------------------------===//
360 // Multiclass helpers...
363 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
364 /// binop that produces a value.
365 multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode,
366 bit Commutable = 0> {
367 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
368 IIC_iALUi, opc, " $dst, $a, $b",
369 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
372 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
373 IIC_iALUr, opc, " $dst, $a, $b",
374 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
376 let isCommutable = Commutable;
378 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
379 IIC_iALUsr, opc, " $dst, $a, $b",
380 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
385 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
386 /// instruction modifies the CSPR register.
387 let Defs = [CPSR] in {
388 multiclass AI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode,
389 bit Commutable = 0> {
390 def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
391 IIC_iALUi, opc, "s $dst, $a, $b",
392 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]> {
395 def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPFrm,
396 IIC_iALUr, opc, "s $dst, $a, $b",
397 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]> {
398 let isCommutable = Commutable;
401 def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
402 IIC_iALUsr, opc, "s $dst, $a, $b",
403 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]> {
409 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
410 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
411 /// a explicit result, only implicitly set CPSR.
412 let Defs = [CPSR] in {
413 multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode,
414 bit Commutable = 0> {
415 def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPFrm, IIC_iCMPi,
417 [(opnode GPR:$a, so_imm:$b)]> {
420 def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPFrm, IIC_iCMPr,
422 [(opnode GPR:$a, GPR:$b)]> {
424 let isCommutable = Commutable;
426 def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPSoRegFrm, IIC_iCMPsr,
428 [(opnode GPR:$a, so_reg:$b)]> {
434 /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
435 /// register and one whose operand is a register rotated by 8/16/24.
436 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
437 multiclass AI_unary_rrot<bits<8> opcod, string opc, PatFrag opnode> {
438 def r : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src),
439 IIC_iUNAr, opc, " $dst, $src",
440 [(set GPR:$dst, (opnode GPR:$src))]>,
441 Requires<[IsARM, HasV6]> {
442 let Inst{19-16} = 0b1111;
444 def r_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$src, i32imm:$rot),
445 IIC_iUNAsi, opc, " $dst, $src, ror $rot",
446 [(set GPR:$dst, (opnode (rotr GPR:$src, rot_imm:$rot)))]>,
447 Requires<[IsARM, HasV6]> {
448 let Inst{19-16} = 0b1111;
452 /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
453 /// register and one whose operand is a register rotated by 8/16/24.
454 multiclass AI_bin_rrot<bits<8> opcod, string opc, PatFrag opnode> {
455 def rr : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
456 IIC_iALUr, opc, " $dst, $LHS, $RHS",
457 [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
458 Requires<[IsARM, HasV6]>;
459 def rr_rot : AExtI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
460 IIC_iALUsi, opc, " $dst, $LHS, $RHS, ror $rot",
461 [(set GPR:$dst, (opnode GPR:$LHS,
462 (rotr GPR:$RHS, rot_imm:$rot)))]>,
463 Requires<[IsARM, HasV6]>;
466 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
467 let Uses = [CPSR] in {
468 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
469 bit Commutable = 0> {
470 def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
471 DPFrm, IIC_iALUi, opc, " $dst, $a, $b",
472 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
473 Requires<[IsARM, CarryDefIsUnused]> {
476 def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
477 DPFrm, IIC_iALUr, opc, " $dst, $a, $b",
478 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
479 Requires<[IsARM, CarryDefIsUnused]> {
480 let isCommutable = Commutable;
483 def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
484 DPSoRegFrm, IIC_iALUsr, opc, " $dst, $a, $b",
485 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
486 Requires<[IsARM, CarryDefIsUnused]> {
489 // Carry setting variants
490 def Sri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
491 DPFrm, IIC_iALUi, !strconcat(opc, "s $dst, $a, $b"),
492 [(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>,
493 Requires<[IsARM, CarryDefIsUsed]> {
497 def Srr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
498 DPFrm, IIC_iALUr, !strconcat(opc, "s $dst, $a, $b"),
499 [(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
500 Requires<[IsARM, CarryDefIsUsed]> {
504 def Srs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
505 DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "s $dst, $a, $b"),
506 [(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>,
507 Requires<[IsARM, CarryDefIsUsed]> {
514 //===----------------------------------------------------------------------===//
516 //===----------------------------------------------------------------------===//
518 //===----------------------------------------------------------------------===//
519 // Miscellaneous Instructions.
522 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
523 /// the function. The first operand is the ID# for this instruction, the second
524 /// is the index into the MachineConstantPool that this is, the third is the
525 /// size in bytes of this constant pool entry.
526 let neverHasSideEffects = 1, isNotDuplicable = 1 in
527 def CONSTPOOL_ENTRY :
528 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
529 i32imm:$size), NoItinerary,
530 "${instid:label} ${cpidx:cpentry}", []>;
532 let Defs = [SP], Uses = [SP] in {
534 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
535 "@ ADJCALLSTACKUP $amt1",
536 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
538 def ADJCALLSTACKDOWN :
539 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
540 "@ ADJCALLSTACKDOWN $amt",
541 [(ARMcallseq_start timm:$amt)]>;
545 PseudoInst<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file), NoItinerary,
546 ".loc $file, $line, $col",
547 [(dwarf_loc (i32 imm:$line), (i32 imm:$col), (i32 imm:$file))]>;
550 // Address computation and loads and stores in PIC mode.
551 let isNotDuplicable = 1 in {
552 def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
553 Pseudo, IIC_iALUr, "\n$cp:\n\tadd$p $dst, pc, $a",
554 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
556 let AddedComplexity = 10 in {
557 let canFoldAsLoad = 1 in
558 def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
559 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p $dst, $addr",
560 [(set GPR:$dst, (load addrmodepc:$addr))]>;
562 def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
563 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}h $dst, $addr",
564 [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
566 def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
567 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}b $dst, $addr",
568 [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
570 def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
571 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sh $dst, $addr",
572 [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
574 def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
575 Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr${p}sb $dst, $addr",
576 [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
578 let AddedComplexity = 10 in {
579 def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
580 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr$p $src, $addr",
581 [(store GPR:$src, addrmodepc:$addr)]>;
583 def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
584 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}h $src, $addr",
585 [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
587 def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
588 Pseudo, IIC_iStorer, "\n${addr:label}:\n\tstr${p}b $src, $addr",
589 [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
591 } // isNotDuplicable = 1
594 // LEApcrel - Load a pc-relative address into a register without offending the
596 def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p),
598 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
599 "${:private}PCRELL${:uid}+8))\n"),
600 !strconcat("${:private}PCRELL${:uid}:\n\t",
601 "add$p $dst, pc, #${:private}PCRELV${:uid}")),
604 def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
605 (ins i32imm:$label, nohash_imm:$id, pred:$p),
607 !strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
609 "${:private}PCRELL${:uid}+8))\n"),
610 !strconcat("${:private}PCRELL${:uid}:\n\t",
611 "add$p $dst, pc, #${:private}PCRELV${:uid}")),
616 //===----------------------------------------------------------------------===//
617 // Control Flow Instructions.
620 let isReturn = 1, isTerminator = 1 in
621 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
622 "bx", " lr", [(ARMretflag)]> {
623 let Inst{7-4} = 0b0001;
624 let Inst{19-8} = 0b111111111111;
625 let Inst{27-20} = 0b00010010;
628 // FIXME: remove when we have a way to marking a MI with these properties.
629 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
631 // FIXME: Should pc be an implicit operand like PICADD, etc?
632 let isReturn = 1, isTerminator = 1, mayLoad = 1 in
633 def LDM_RET : AXI4ld<(outs),
634 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
635 LdStMulFrm, IIC_Br, "ldm${p}${addr:submode} $addr, $dst1",
638 // On non-Darwin platforms R9 is callee-saved.
640 Defs = [R0, R1, R2, R3, R12, LR,
641 D0, D1, D2, D3, D4, D5, D6, D7,
642 D16, D17, D18, D19, D20, D21, D22, D23,
643 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
644 def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
645 IIC_Br, "bl ${func:call}",
646 [(ARMcall tglobaladdr:$func)]>,
647 Requires<[IsARM, IsNotDarwin]>;
649 def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
650 IIC_Br, "bl", " ${func:call}",
651 [(ARMcall_pred tglobaladdr:$func)]>,
652 Requires<[IsARM, IsNotDarwin]>;
655 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
657 [(ARMcall GPR:$func)]>,
658 Requires<[IsARM, HasV5T, IsNotDarwin]> {
659 let Inst{7-4} = 0b0011;
660 let Inst{19-8} = 0b111111111111;
661 let Inst{27-20} = 0b00010010;
665 def BX : ABXIx2<(outs), (ins GPR:$func, variable_ops),
666 IIC_Br, "mov lr, pc\n\tbx $func",
667 [(ARMcall_nolink GPR:$func)]>,
668 Requires<[IsARM, IsNotDarwin]> {
669 let Inst{7-4} = 0b0001;
670 let Inst{19-8} = 0b111111111111;
671 let Inst{27-20} = 0b00010010;
675 // On Darwin R9 is call-clobbered.
677 Defs = [R0, R1, R2, R3, R9, R12, LR,
678 D0, D1, D2, D3, D4, D5, D6, D7,
679 D16, D17, D18, D19, D20, D21, D22, D23,
680 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
681 def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
682 IIC_Br, "bl ${func:call}",
683 [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
685 def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
686 IIC_Br, "bl", " ${func:call}",
687 [(ARMcall_pred tglobaladdr:$func)]>,
688 Requires<[IsARM, IsDarwin]>;
691 def BLXr9 : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
693 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
694 let Inst{7-4} = 0b0011;
695 let Inst{19-8} = 0b111111111111;
696 let Inst{27-20} = 0b00010010;
700 def BXr9 : ABXIx2<(outs), (ins GPR:$func, variable_ops),
701 IIC_Br, "mov lr, pc\n\tbx $func",
702 [(ARMcall_nolink GPR:$func)]>, Requires<[IsARM, IsDarwin]> {
703 let Inst{7-4} = 0b0001;
704 let Inst{19-8} = 0b111111111111;
705 let Inst{27-20} = 0b00010010;
709 let isBranch = 1, isTerminator = 1 in {
710 // B is "predicable" since it can be xformed into a Bcc.
711 let isBarrier = 1 in {
712 let isPredicable = 1 in
713 def B : ABXI<0b1010, (outs), (ins brtarget:$target), IIC_Br,
714 "b $target", [(br bb:$target)]>;
716 let isNotDuplicable = 1, isIndirectBranch = 1 in {
717 def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
718 IIC_Br, "mov pc, $target \n$jt",
719 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
720 let Inst{20} = 0; // S Bit
721 let Inst{24-21} = 0b1101;
722 let Inst{27-25} = 0b000;
724 def BR_JTm : JTI<(outs),
725 (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
726 IIC_Br, "ldr pc, $target \n$jt",
727 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
729 let Inst{20} = 1; // L bit
730 let Inst{21} = 0; // W bit
731 let Inst{22} = 0; // B bit
732 let Inst{24} = 1; // P bit
733 let Inst{27-25} = 0b011;
735 def BR_JTadd : JTI<(outs),
736 (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
737 IIC_Br, "add pc, $target, $idx \n$jt",
738 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
740 let Inst{20} = 0; // S bit
741 let Inst{24-21} = 0b0100;
742 let Inst{27-25} = 0b000;
744 } // isNotDuplicable = 1, isIndirectBranch = 1
747 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
748 // a two-value operand where a dag node expects two operands. :(
749 def Bcc : ABI<0b1010, (outs), (ins brtarget:$target),
750 IIC_Br, "b", " $target",
751 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
754 //===----------------------------------------------------------------------===//
755 // Load / store Instructions.
759 let canFoldAsLoad = 1 in
760 def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
761 "ldr", " $dst, $addr",
762 [(set GPR:$dst, (load addrmode2:$addr))]>;
764 // Special LDR for loads from non-pc-relative constpools.
765 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
766 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
767 "ldr", " $dst, $addr", []>;
769 // Loads with zero extension
770 def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
771 IIC_iLoadr, "ldr", "h $dst, $addr",
772 [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
774 def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
775 IIC_iLoadr, "ldr", "b $dst, $addr",
776 [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
778 // Loads with sign extension
779 def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
780 IIC_iLoadr, "ldr", "sh $dst, $addr",
781 [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
783 def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
784 IIC_iLoadr, "ldr", "sb $dst, $addr",
785 [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
789 def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
790 IIC_iLoadr, "ldr", "d $dst1, $addr",
791 []>, Requires<[IsARM, HasV5TE]>;
794 def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
795 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
796 "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
798 def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
799 (ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoadru,
800 "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
802 def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
803 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
804 "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
806 def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
807 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
808 "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
810 def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
811 (ins addrmode2:$addr), LdFrm, IIC_iLoadru,
812 "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
814 def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
815 (ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoadru,
816 "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
818 def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
819 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
820 "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
822 def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
823 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
824 "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
826 def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
827 (ins addrmode3:$addr), LdMiscFrm, IIC_iLoadru,
828 "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
830 def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
831 (ins GPR:$base,am3offset:$offset), LdMiscFrm, IIC_iLoadru,
832 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
836 def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
837 "str", " $src, $addr",
838 [(store GPR:$src, addrmode2:$addr)]>;
840 // Stores with truncate
841 def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, IIC_iStorer,
842 "str", "h $src, $addr",
843 [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
845 def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
846 "str", "b $src, $addr",
847 [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
851 def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
852 StMiscFrm, IIC_iStorer,
853 "str", "d $src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
856 def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
857 (ins GPR:$src, GPR:$base, am2offset:$offset),
859 "str", " $src, [$base, $offset]!", "$base = $base_wb",
861 (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
863 def STR_POST : AI2stwpo<(outs GPR:$base_wb),
864 (ins GPR:$src, GPR:$base,am2offset:$offset),
866 "str", " $src, [$base], $offset", "$base = $base_wb",
868 (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
870 def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
871 (ins GPR:$src, GPR:$base,am3offset:$offset),
872 StMiscFrm, IIC_iStoreru,
873 "str", "h $src, [$base, $offset]!", "$base = $base_wb",
875 (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
877 def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
878 (ins GPR:$src, GPR:$base,am3offset:$offset),
879 StMiscFrm, IIC_iStoreru,
880 "str", "h $src, [$base], $offset", "$base = $base_wb",
881 [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
882 GPR:$base, am3offset:$offset))]>;
884 def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
885 (ins GPR:$src, GPR:$base,am2offset:$offset),
887 "str", "b $src, [$base, $offset]!", "$base = $base_wb",
888 [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
889 GPR:$base, am2offset:$offset))]>;
891 def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
892 (ins GPR:$src, GPR:$base,am2offset:$offset),
894 "str", "b $src, [$base], $offset", "$base = $base_wb",
895 [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
896 GPR:$base, am2offset:$offset))]>;
898 //===----------------------------------------------------------------------===//
899 // Load / store multiple Instructions.
902 // FIXME: $dst1 should be a def.
904 def LDM : AXI4ld<(outs),
905 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
906 LdStMulFrm, IIC_iLoadm, "ldm${p}${addr:submode} $addr, $dst1",
910 def STM : AXI4st<(outs),
911 (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
912 LdStMulFrm, IIC_iStorem, "stm${p}${addr:submode} $addr, $src1",
915 //===----------------------------------------------------------------------===//
916 // Move Instructions.
919 let neverHasSideEffects = 1 in
920 def MOVr : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
921 "mov", " $dst, $src", []>, UnaryDP;
922 def MOVs : AsI1<0b1101, (outs GPR:$dst), (ins so_reg:$src),
923 DPSoRegFrm, IIC_iMOVsr,
924 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>, UnaryDP;
926 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
927 def MOVi : AsI1<0b1101, (outs GPR:$dst), (ins so_imm:$src), DPFrm, IIC_iMOVi,
928 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>, UnaryDP {
932 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
933 def MOVi16 : AI1<0b1000, (outs GPR:$dst), (ins i32imm:$src),
935 "movw", " $dst, $src",
936 [(set GPR:$dst, imm0_65535:$src)]>,
937 Requires<[IsARM, HasV6T2]> {
941 let isReMaterializable = 1, isAsCheapAsAMove = 1,
942 Constraints = "$src = $dst" in
943 def MOVTi16 : AI1<0b1010, (outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
945 "movt", " $dst, $imm",
947 (or (and GPR:$src, 0xffff),
948 lo16AllZero:$imm))]>, UnaryDP,
949 Requires<[IsARM, HasV6T2]> {
954 def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
955 "mov", " $dst, $src, rrx",
956 [(set GPR:$dst, (ARMrrx GPR:$src))]>, UnaryDP;
958 // These aren't really mov instructions, but we have to define them this way
959 // due to flag operands.
961 let Defs = [CPSR] in {
962 def MOVsrl_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
963 IIC_iMOVsi, "mov", "s $dst, $src, lsr #1",
964 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP;
965 def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo,
966 IIC_iMOVsi, "mov", "s $dst, $src, asr #1",
967 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP;
970 //===----------------------------------------------------------------------===//
971 // Extend Instructions.
976 defm SXTB : AI_unary_rrot<0b01101010,
977 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
978 defm SXTH : AI_unary_rrot<0b01101011,
979 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
981 defm SXTAB : AI_bin_rrot<0b01101010,
982 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
983 defm SXTAH : AI_bin_rrot<0b01101011,
984 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
986 // TODO: SXT(A){B|H}16
990 let AddedComplexity = 16 in {
991 defm UXTB : AI_unary_rrot<0b01101110,
992 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
993 defm UXTH : AI_unary_rrot<0b01101111,
994 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
995 defm UXTB16 : AI_unary_rrot<0b01101100,
996 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
998 def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
999 (UXTB16r_rot GPR:$Src, 24)>;
1000 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
1001 (UXTB16r_rot GPR:$Src, 8)>;
1003 defm UXTAB : AI_bin_rrot<0b01101110, "uxtab",
1004 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
1005 defm UXTAH : AI_bin_rrot<0b01101111, "uxtah",
1006 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
1009 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
1010 //defm UXTAB16 : xxx<"uxtab16", 0xff00ff>;
1012 // TODO: UXT(A){B|H}16
1014 //===----------------------------------------------------------------------===//
1015 // Arithmetic Instructions.
1018 defm ADD : AsI1_bin_irs<0b0100, "add",
1019 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
1020 defm SUB : AsI1_bin_irs<0b0010, "sub",
1021 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
1023 // ADD and SUB with 's' bit set.
1024 defm ADDS : AI1_bin_s_irs<0b0100, "add",
1025 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
1026 defm SUBS : AI1_bin_s_irs<0b0010, "sub",
1027 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
1029 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
1030 BinOpFrag<(adde node:$LHS, node:$RHS)>, 1>;
1031 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
1032 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
1034 // These don't define reg/reg forms, because they are handled above.
1035 def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1036 IIC_iALUi, "rsb", " $dst, $a, $b",
1037 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
1041 def RSBrs : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1042 IIC_iALUsr, "rsb", " $dst, $a, $b",
1043 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
1045 // RSB with 's' bit set.
1046 let Defs = [CPSR] in {
1047 def RSBSri : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
1048 IIC_iALUi, "rsb", "s $dst, $a, $b",
1049 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]> {
1052 def RSBSrs : AI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPSoRegFrm,
1053 IIC_iALUsr, "rsb", "s $dst, $a, $b",
1054 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
1057 let Uses = [CPSR] in {
1058 def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1059 DPFrm, IIC_iALUi, "rsc", " $dst, $a, $b",
1060 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1061 Requires<[IsARM, CarryDefIsUnused]> {
1064 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1065 DPSoRegFrm, IIC_iALUsr, "rsc", " $dst, $a, $b",
1066 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1067 Requires<[IsARM, CarryDefIsUnused]>;
1070 // FIXME: Allow these to be predicated.
1071 let Defs = [CPSR], Uses = [CPSR] in {
1072 def RSCSri : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
1073 DPFrm, IIC_iALUi, "rscs $dst, $a, $b",
1074 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>,
1075 Requires<[IsARM, CarryDefIsUnused]> {
1078 def RSCSrs : AXI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
1079 DPSoRegFrm, IIC_iALUsr, "rscs $dst, $a, $b",
1080 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>,
1081 Requires<[IsARM, CarryDefIsUnused]>;
1084 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1085 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
1086 (SUBri GPR:$src, so_imm_neg:$imm)>;
1088 //def : ARMPat<(addc GPR:$src, so_imm_neg:$imm),
1089 // (SUBSri GPR:$src, so_imm_neg:$imm)>;
1090 //def : ARMPat<(adde GPR:$src, so_imm_neg:$imm),
1091 // (SBCri GPR:$src, so_imm_neg:$imm)>;
1093 // Note: These are implemented in C++ code, because they have to generate
1094 // ADD/SUBrs instructions, which use a complex pattern that a xform function
1096 // (mul X, 2^n+1) -> (add (X << n), X)
1097 // (mul X, 2^n-1) -> (rsb X, (X << n))
1100 //===----------------------------------------------------------------------===//
1101 // Bitwise Instructions.
1104 defm AND : AsI1_bin_irs<0b0000, "and",
1105 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
1106 defm ORR : AsI1_bin_irs<0b1100, "orr",
1107 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
1108 defm EOR : AsI1_bin_irs<0b0001, "eor",
1109 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
1110 defm BIC : AsI1_bin_irs<0b1110, "bic",
1111 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
1113 def BFC : I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
1114 AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iALUi,
1115 "bfc", " $dst, $imm", "$src = $dst",
1116 [(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
1117 Requires<[IsARM, HasV6T2]> {
1118 let Inst{27-21} = 0b0111110;
1119 let Inst{6-0} = 0b0011111;
1122 def MVNr : AsI1<0b1111, (outs GPR:$dst), (ins GPR:$src), DPFrm, IIC_iMOVr,
1123 "mvn", " $dst, $src",
1124 [(set GPR:$dst, (not GPR:$src))]>, UnaryDP;
1125 def MVNs : AsI1<0b1111, (outs GPR:$dst), (ins so_reg:$src), DPSoRegFrm,
1126 IIC_iMOVsr, "mvn", " $dst, $src",
1127 [(set GPR:$dst, (not so_reg:$src))]>, UnaryDP;
1128 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1129 def MVNi : AsI1<0b1111, (outs GPR:$dst), (ins so_imm:$imm), DPFrm,
1130 IIC_iMOVi, "mvn", " $dst, $imm",
1131 [(set GPR:$dst, so_imm_not:$imm)]>,UnaryDP {
1135 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
1136 (BICri GPR:$src, so_imm_not:$imm)>;
1138 //===----------------------------------------------------------------------===//
1139 // Multiply Instructions.
1142 let isCommutable = 1 in
1143 def MUL : AsMul1I<0b0000000, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1144 IIC_iMUL32, "mul", " $dst, $a, $b",
1145 [(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
1147 def MLA : AsMul1I<0b0000001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1148 IIC_iMAC32, "mla", " $dst, $a, $b, $c",
1149 [(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
1151 def MLS : AMul1I<0b0000011, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1152 IIC_iMAC32, "mls", " $dst, $a, $b, $c",
1153 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
1154 Requires<[IsARM, HasV6T2]>;
1156 // Extra precision multiplies with low / high results
1157 let neverHasSideEffects = 1 in {
1158 let isCommutable = 1 in {
1159 def SMULL : AsMul1I<0b0000110, (outs GPR:$ldst, GPR:$hdst),
1160 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1161 "smull", " $ldst, $hdst, $a, $b", []>;
1163 def UMULL : AsMul1I<0b0000100, (outs GPR:$ldst, GPR:$hdst),
1164 (ins GPR:$a, GPR:$b), IIC_iMUL64,
1165 "umull", " $ldst, $hdst, $a, $b", []>;
1168 // Multiply + accumulate
1169 def SMLAL : AsMul1I<0b0000111, (outs GPR:$ldst, GPR:$hdst),
1170 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1171 "smlal", " $ldst, $hdst, $a, $b", []>;
1173 def UMLAL : AsMul1I<0b0000101, (outs GPR:$ldst, GPR:$hdst),
1174 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1175 "umlal", " $ldst, $hdst, $a, $b", []>;
1177 def UMAAL : AMul1I <0b0000010, (outs GPR:$ldst, GPR:$hdst),
1178 (ins GPR:$a, GPR:$b), IIC_iMAC64,
1179 "umaal", " $ldst, $hdst, $a, $b", []>,
1180 Requires<[IsARM, HasV6]>;
1181 } // neverHasSideEffects
1183 // Most significant word multiply
1184 def SMMUL : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1185 IIC_iMUL32, "smmul", " $dst, $a, $b",
1186 [(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
1187 Requires<[IsARM, HasV6]> {
1188 let Inst{7-4} = 0b0001;
1189 let Inst{15-12} = 0b1111;
1192 def SMMLA : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1193 IIC_iMAC32, "smmla", " $dst, $a, $b, $c",
1194 [(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
1195 Requires<[IsARM, HasV6]> {
1196 let Inst{7-4} = 0b0001;
1200 def SMMLS : AMul2I <0b0111010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
1201 IIC_iMAC32, "smmls", " $dst, $a, $b, $c",
1202 [(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
1203 Requires<[IsARM, HasV6]> {
1204 let Inst{7-4} = 0b1101;
1207 multiclass AI_smul<string opc, PatFrag opnode> {
1208 def BB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1209 IIC_iMUL32, !strconcat(opc, "bb"), " $dst, $a, $b",
1210 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1211 (sext_inreg GPR:$b, i16)))]>,
1212 Requires<[IsARM, HasV5TE]> {
1217 def BT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1218 IIC_iMUL32, !strconcat(opc, "bt"), " $dst, $a, $b",
1219 [(set GPR:$dst, (opnode (sext_inreg GPR:$a, i16),
1220 (sra GPR:$b, (i32 16))))]>,
1221 Requires<[IsARM, HasV5TE]> {
1226 def TB : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1227 IIC_iMUL32, !strconcat(opc, "tb"), " $dst, $a, $b",
1228 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1229 (sext_inreg GPR:$b, i16)))]>,
1230 Requires<[IsARM, HasV5TE]> {
1235 def TT : AMulxyI<0b0001011, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1236 IIC_iMUL32, !strconcat(opc, "tt"), " $dst, $a, $b",
1237 [(set GPR:$dst, (opnode (sra GPR:$a, (i32 16)),
1238 (sra GPR:$b, (i32 16))))]>,
1239 Requires<[IsARM, HasV5TE]> {
1244 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1245 IIC_iMUL16, !strconcat(opc, "wb"), " $dst, $a, $b",
1246 [(set GPR:$dst, (sra (opnode GPR:$a,
1247 (sext_inreg GPR:$b, i16)), (i32 16)))]>,
1248 Requires<[IsARM, HasV5TE]> {
1253 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
1254 IIC_iMUL16, !strconcat(opc, "wt"), " $dst, $a, $b",
1255 [(set GPR:$dst, (sra (opnode GPR:$a,
1256 (sra GPR:$b, (i32 16))), (i32 16)))]>,
1257 Requires<[IsARM, HasV5TE]> {
1264 multiclass AI_smla<string opc, PatFrag opnode> {
1265 def BB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1266 IIC_iMAC16, !strconcat(opc, "bb"), " $dst, $a, $b, $acc",
1267 [(set GPR:$dst, (add GPR:$acc,
1268 (opnode (sext_inreg GPR:$a, i16),
1269 (sext_inreg GPR:$b, i16))))]>,
1270 Requires<[IsARM, HasV5TE]> {
1275 def BT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1276 IIC_iMAC16, !strconcat(opc, "bt"), " $dst, $a, $b, $acc",
1277 [(set GPR:$dst, (add GPR:$acc, (opnode (sext_inreg GPR:$a, i16),
1278 (sra GPR:$b, (i32 16)))))]>,
1279 Requires<[IsARM, HasV5TE]> {
1284 def TB : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1285 IIC_iMAC16, !strconcat(opc, "tb"), " $dst, $a, $b, $acc",
1286 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1287 (sext_inreg GPR:$b, i16))))]>,
1288 Requires<[IsARM, HasV5TE]> {
1293 def TT : AMulxyI<0b0001000, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1294 IIC_iMAC16, !strconcat(opc, "tt"), " $dst, $a, $b, $acc",
1295 [(set GPR:$dst, (add GPR:$acc, (opnode (sra GPR:$a, (i32 16)),
1296 (sra GPR:$b, (i32 16)))))]>,
1297 Requires<[IsARM, HasV5TE]> {
1302 def WB : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1303 IIC_iMAC16, !strconcat(opc, "wb"), " $dst, $a, $b, $acc",
1304 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1305 (sext_inreg GPR:$b, i16)), (i32 16))))]>,
1306 Requires<[IsARM, HasV5TE]> {
1311 def WT : AMulxyI<0b0001001, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc),
1312 IIC_iMAC16, !strconcat(opc, "wt"), " $dst, $a, $b, $acc",
1313 [(set GPR:$dst, (add GPR:$acc, (sra (opnode GPR:$a,
1314 (sra GPR:$b, (i32 16))), (i32 16))))]>,
1315 Requires<[IsARM, HasV5TE]> {
1321 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1322 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
1324 // TODO: Halfword multiple accumulate long: SMLAL<x><y>
1325 // TODO: Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
1327 //===----------------------------------------------------------------------===//
1328 // Misc. Arithmetic Instructions.
1331 def CLZ : AMiscA1I<0b000010110, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1332 "clz", " $dst, $src",
1333 [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]> {
1334 let Inst{7-4} = 0b0001;
1335 let Inst{11-8} = 0b1111;
1336 let Inst{19-16} = 0b1111;
1339 def REV : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1340 "rev", " $dst, $src",
1341 [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]> {
1342 let Inst{7-4} = 0b0011;
1343 let Inst{11-8} = 0b1111;
1344 let Inst{19-16} = 0b1111;
1347 def REV16 : AMiscA1I<0b01101011, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1348 "rev16", " $dst, $src",
1350 (or (and (srl GPR:$src, (i32 8)), 0xFF),
1351 (or (and (shl GPR:$src, (i32 8)), 0xFF00),
1352 (or (and (srl GPR:$src, (i32 8)), 0xFF0000),
1353 (and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>,
1354 Requires<[IsARM, HasV6]> {
1355 let Inst{7-4} = 0b1011;
1356 let Inst{11-8} = 0b1111;
1357 let Inst{19-16} = 0b1111;
1360 def REVSH : AMiscA1I<0b01101111, (outs GPR:$dst), (ins GPR:$src), IIC_iUNAr,
1361 "revsh", " $dst, $src",
1364 (or (srl (and GPR:$src, 0xFF00), (i32 8)),
1365 (shl GPR:$src, (i32 8))), i16))]>,
1366 Requires<[IsARM, HasV6]> {
1367 let Inst{7-4} = 0b1011;
1368 let Inst{11-8} = 0b1111;
1369 let Inst{19-16} = 0b1111;
1372 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
1373 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1374 IIC_iALUsi, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
1375 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
1376 (and (shl GPR:$src2, (i32 imm:$shamt)),
1378 Requires<[IsARM, HasV6]> {
1379 let Inst{6-4} = 0b001;
1382 // Alternate cases for PKHBT where identities eliminate some nodes.
1383 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
1384 (PKHBT GPR:$src1, GPR:$src2, 0)>;
1385 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
1386 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
1389 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
1390 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
1391 IIC_iALUsi, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
1392 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
1393 (and (sra GPR:$src2, imm16_31:$shamt),
1394 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
1395 let Inst{6-4} = 0b101;
1398 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
1399 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
1400 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
1401 (PKHTB GPR:$src1, GPR:$src2, 16)>;
1402 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
1403 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
1404 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
1406 //===----------------------------------------------------------------------===//
1407 // Comparison Instructions...
1410 defm CMP : AI1_cmp_irs<0b1010, "cmp",
1411 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
1412 defm CMN : AI1_cmp_irs<0b1011, "cmn",
1413 BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
1415 // Note that TST/TEQ don't set all the same flags that CMP does!
1416 defm TST : AI1_cmp_irs<0b1000, "tst",
1417 BinOpFrag<(ARMcmpZ (and node:$LHS, node:$RHS), 0)>, 1>;
1418 defm TEQ : AI1_cmp_irs<0b1001, "teq",
1419 BinOpFrag<(ARMcmpZ (xor node:$LHS, node:$RHS), 0)>, 1>;
1421 defm CMPz : AI1_cmp_irs<0b1010, "cmp",
1422 BinOpFrag<(ARMcmpZ node:$LHS, node:$RHS)>>;
1423 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
1424 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
1426 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
1427 (CMNri GPR:$src, so_imm_neg:$imm)>;
1429 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
1430 (CMNri GPR:$src, so_imm_neg:$imm)>;
1433 // Conditional moves
1434 // FIXME: should be able to write a pattern for ARMcmov, but can't use
1435 // a two-value operand where a dag node expects two operands. :(
1436 def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
1437 IIC_iCMOVr, "mov", " $dst, $true",
1438 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
1439 RegConstraint<"$false = $dst">, UnaryDP;
1441 def MOVCCs : AI1<0b1101, (outs GPR:$dst),
1442 (ins GPR:$false, so_reg:$true), DPSoRegFrm, IIC_iCMOVsr,
1443 "mov", " $dst, $true",
1444 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
1445 RegConstraint<"$false = $dst">, UnaryDP;
1447 def MOVCCi : AI1<0b1101, (outs GPR:$dst),
1448 (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
1449 "mov", " $dst, $true",
1450 [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
1451 RegConstraint<"$false = $dst">, UnaryDP {
1456 //===----------------------------------------------------------------------===//
1460 // __aeabi_read_tp preserves the registers r1-r3.
1462 Defs = [R0, R12, LR, CPSR] in {
1463 def TPsoft : ABXI<0b1011, (outs), (ins), IIC_Br,
1464 "bl __aeabi_read_tp",
1465 [(set R0, ARMthread_pointer)]>;
1468 //===----------------------------------------------------------------------===//
1469 // SJLJ Exception handling intrinsics
1470 // eh_sjlj_setjmp() is an instruction sequence to store the return
1471 // address and save #0 in R0 for the non-longjmp case.
1472 // Since by its nature we may be coming from some other function to get
1473 // here, and we're using the stack frame for the containing function to
1474 // save/restore registers, we can't keep anything live in regs across
1475 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1476 // when we get here from a longjmp(). We force everthing out of registers
1477 // except for our own input by listing the relevant registers in Defs. By
1478 // doing so, we also cause the prologue/epilogue code to actively preserve
1479 // all of the callee-saved resgisters, which is exactly what we want.
1481 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, D0,
1482 D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15,
1483 D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, D29, D30,
1485 def Int_eh_sjlj_setjmp : XI<(outs), (ins GPR:$src),
1486 AddrModeNone, SizeSpecial, IndexModeNone,
1487 Pseudo, NoItinerary,
1488 "str sp, [$src, #+8] @ eh_setjmp begin\n\t"
1489 "add r12, pc, #8\n\t"
1490 "str r12, [$src, #+4]\n\t"
1492 "add pc, pc, #0\n\t"
1493 "mov r0, #1 @ eh_setjmp end", "",
1494 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
1497 //===----------------------------------------------------------------------===//
1498 // Non-Instruction Patterns
1501 // ConstantPool, GlobalAddress, and JumpTable
1502 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>;
1503 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
1504 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1505 (LEApcrelJT tjumptable:$dst, imm:$id)>;
1507 // Large immediate handling.
1509 // Two piece so_imms.
1510 let isReMaterializable = 1 in
1511 def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src),
1513 "mov", " $dst, $src",
1514 [(set GPR:$dst, so_imm2part:$src)]>;
1516 def : ARMPat<(or GPR:$LHS, so_imm2part:$RHS),
1517 (ORRri (ORRri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1518 (so_imm2part_2 imm:$RHS))>;
1519 def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
1520 (EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
1521 (so_imm2part_2 imm:$RHS))>;
1523 def : ARMPat<(i32 imm:$src),
1524 (MOVTi16 (MOVi16 (lo16 imm:$src)), (hi16 imm:$src))>,
1525 Requires<[IsARM, HasV6T2]>;
1527 // TODO: add,sub,and, 3-instr forms?
1531 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
1532 Requires<[IsARM, IsNotDarwin]>;
1533 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
1534 Requires<[IsARM, IsDarwin]>;
1536 // zextload i1 -> zextload i8
1537 def : ARMPat<(zextloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1539 // extload -> zextload
1540 def : ARMPat<(extloadi1 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1541 def : ARMPat<(extloadi8 addrmode2:$addr), (LDRB addrmode2:$addr)>;
1542 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
1544 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
1545 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
1548 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1549 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1550 (SMULBB GPR:$a, GPR:$b)>;
1551 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
1552 (SMULBB GPR:$a, GPR:$b)>;
1553 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1554 (sra GPR:$b, (i32 16))),
1555 (SMULBT GPR:$a, GPR:$b)>;
1556 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
1557 (SMULBT GPR:$a, GPR:$b)>;
1558 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
1559 (sra (shl GPR:$b, (i32 16)), (i32 16))),
1560 (SMULTB GPR:$a, GPR:$b)>;
1561 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
1562 (SMULTB GPR:$a, GPR:$b)>;
1563 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1565 (SMULWB GPR:$a, GPR:$b)>;
1566 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
1567 (SMULWB GPR:$a, GPR:$b)>;
1569 def : ARMV5TEPat<(add GPR:$acc,
1570 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1571 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1572 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1573 def : ARMV5TEPat<(add GPR:$acc,
1574 (mul sext_16_node:$a, sext_16_node:$b)),
1575 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
1576 def : ARMV5TEPat<(add GPR:$acc,
1577 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
1578 (sra GPR:$b, (i32 16)))),
1579 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1580 def : ARMV5TEPat<(add GPR:$acc,
1581 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
1582 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
1583 def : ARMV5TEPat<(add GPR:$acc,
1584 (mul (sra GPR:$a, (i32 16)),
1585 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
1586 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1587 def : ARMV5TEPat<(add GPR:$acc,
1588 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
1589 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
1590 def : ARMV5TEPat<(add GPR:$acc,
1591 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
1593 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1594 def : ARMV5TEPat<(add GPR:$acc,
1595 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
1596 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
1598 //===----------------------------------------------------------------------===//
1602 include "ARMInstrThumb.td"
1604 //===----------------------------------------------------------------------===//
1608 include "ARMInstrThumb2.td"
1610 //===----------------------------------------------------------------------===//
1611 // Floating Point Support
1614 include "ARMInstrVFP.td"
1616 //===----------------------------------------------------------------------===//
1617 // Advanced SIMD (NEON) Support
1620 include "ARMInstrNEON.td"