1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
21 def SDT_ARMStructByVal : SDTypeProfile<0, 4,
22 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
23 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
25 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
27 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
29 def SDT_ARMCMov : SDTypeProfile<1, 3,
30 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
33 def SDT_ARMBrcond : SDTypeProfile<0, 2,
34 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
36 def SDT_ARMBrJT : SDTypeProfile<0, 3,
37 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
40 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
41 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
42 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
44 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
46 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
47 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
48 SDTCisVT<5, OtherVT>]>;
50 def SDT_ARMAnd : SDTypeProfile<1, 2,
51 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
54 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
56 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
57 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
59 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
60 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
62 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
64 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
66 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
69 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
71 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
72 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
74 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
77 SDTCisInt<0>, SDTCisVT<1, i32>]>;
79 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
80 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
87 def SDT_ARM64bitmlal : SDTypeProfile<2,4, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>,
88 SDTCisVT<2, i32>, SDTCisVT<3, i32>,
89 SDTCisVT<4, i32>, SDTCisVT<5, i32> ] >;
90 def ARMUmlal : SDNode<"ARMISD::UMLAL", SDT_ARM64bitmlal>;
91 def ARMSmlal : SDNode<"ARMISD::SMLAL", SDT_ARM64bitmlal>;
94 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
95 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
96 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
97 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
99 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
100 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
101 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
102 [SDNPHasChain, SDNPSideEffect,
103 SDNPOptInGlue, SDNPOutGlue]>;
104 def ARMcopystructbyval : SDNode<"ARMISD::COPY_STRUCT_BYVAL" ,
106 [SDNPHasChain, SDNPInGlue, SDNPOutGlue,
107 SDNPMayStore, SDNPMayLoad]>;
109 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
112 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
115 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
116 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
120 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
122 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
125 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
126 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
128 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
130 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
133 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
136 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
139 def ARMcmn : SDNode<"ARMISD::CMN", SDT_ARMCmp,
142 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
143 [SDNPOutGlue, SDNPCommutative]>;
145 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
147 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
148 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
149 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
151 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
153 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
154 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
155 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
157 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
158 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
159 SDT_ARMEH_SJLJ_Setjmp,
160 [SDNPHasChain, SDNPSideEffect]>;
161 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
162 SDT_ARMEH_SJLJ_Longjmp,
163 [SDNPHasChain, SDNPSideEffect]>;
165 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
166 [SDNPHasChain, SDNPSideEffect]>;
167 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
168 [SDNPHasChain, SDNPSideEffect]>;
169 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
170 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
172 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
174 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
175 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
178 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
180 //===----------------------------------------------------------------------===//
181 // ARM Instruction Predicate Definitions.
183 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
184 AssemblerPredicate<"HasV4TOps", "armv4t">;
185 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
186 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
187 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
188 AssemblerPredicate<"HasV5TEOps", "armv5te">;
189 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
190 AssemblerPredicate<"HasV6Ops", "armv6">;
191 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
192 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
193 AssemblerPredicate<"HasV6T2Ops", "armv6t2">;
194 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
195 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
196 AssemblerPredicate<"HasV7Ops", "armv7">;
197 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
198 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
199 AssemblerPredicate<"FeatureVFP2", "VFP2">;
200 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
201 AssemblerPredicate<"FeatureVFP3", "VFP3">;
202 def HasVFP4 : Predicate<"Subtarget->hasVFP4()">,
203 AssemblerPredicate<"FeatureVFP4", "VFP4">;
204 def HasNEON : Predicate<"Subtarget->hasNEON()">,
205 AssemblerPredicate<"FeatureNEON", "NEON">;
206 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
207 AssemblerPredicate<"FeatureFP16","half-float">;
208 def HasDivide : Predicate<"Subtarget->hasDivide()">,
209 AssemblerPredicate<"FeatureHWDiv", "divide">;
210 def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">,
211 AssemblerPredicate<"FeatureHWDivARM">;
212 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
213 AssemblerPredicate<"FeatureT2XtPk",
215 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
216 AssemblerPredicate<"FeatureDSPThumb2",
218 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
219 AssemblerPredicate<"FeatureDB",
221 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
222 AssemblerPredicate<"FeatureMP",
224 def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">,
225 AssemblerPredicate<"FeatureTrustZone",
227 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
228 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
229 def IsThumb : Predicate<"Subtarget->isThumb()">,
230 AssemblerPredicate<"ModeThumb", "thumb">;
231 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
232 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
233 AssemblerPredicate<"ModeThumb,FeatureThumb2",
235 def IsMClass : Predicate<"Subtarget->isMClass()">,
236 AssemblerPredicate<"FeatureMClass", "armv7m">;
237 def IsARClass : Predicate<"!Subtarget->isMClass()">,
238 AssemblerPredicate<"!FeatureMClass",
240 def IsARM : Predicate<"!Subtarget->isThumb()">,
241 AssemblerPredicate<"!ModeThumb", "arm-mode">;
242 def IsIOS : Predicate<"Subtarget->isTargetIOS()">;
243 def IsNotIOS : Predicate<"!Subtarget->isTargetIOS()">;
244 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">;
245 def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">,
246 AssemblerPredicate<"FeatureNaClTrap", "NaCl">;
247 def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">;
249 // FIXME: Eventually this will be just "hasV6T2Ops".
250 def UseMovt : Predicate<"Subtarget->useMovt()">;
251 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
252 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
253 def UseMulOps : Predicate<"Subtarget->useMulOps()">;
255 // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available.
256 // But only select them if more precision in FP computation is allowed.
257 // Do not use them for Darwin platforms.
258 def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion =="
259 " FPOpFusion::Fast) && "
260 "!Subtarget->isTargetDarwin()">;
261 def DontUseFusedMAC : Predicate<"!Subtarget->hasVFP4() || "
262 "Subtarget->isTargetDarwin()">;
264 // VGETLNi32 is microcoded on Swift - prefer VMOV.
265 def HasFastVGETLNi32 : Predicate<"!Subtarget->isSwift()">;
266 def HasSlowVGETLNi32 : Predicate<"Subtarget->isSwift()">;
268 // VDUP.32 is microcoded on Swift - prefer VMOV.
269 def HasFastVDUP32 : Predicate<"!Subtarget->isSwift()">;
270 def HasSlowVDUP32 : Predicate<"Subtarget->isSwift()">;
272 // Cortex-A9 prefers VMOVSR to VMOVDRR even when using NEON for scalar FP, as
273 // this allows more effective execution domain optimization. See
274 // setExecutionDomain().
275 def UseVMOVSR : Predicate<"Subtarget->isCortexA9() || !Subtarget->useNEONForSinglePrecisionFP()">;
276 def DontUseVMOVSR : Predicate<"!Subtarget->isCortexA9() && Subtarget->useNEONForSinglePrecisionFP()">;
278 def IsLE : Predicate<"TLI.isLittleEndian()">;
279 def IsBE : Predicate<"TLI.isBigEndian()">;
281 //===----------------------------------------------------------------------===//
282 // ARM Flag Definitions.
284 class RegConstraint<string C> {
285 string Constraints = C;
288 //===----------------------------------------------------------------------===//
289 // ARM specific transformation functions and pattern fragments.
292 // imm_neg_XFORM - Return the negation of an i32 immediate value.
293 def imm_neg_XFORM : SDNodeXForm<imm, [{
294 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
297 // imm_not_XFORM - Return the complement of a i32 immediate value.
298 def imm_not_XFORM : SDNodeXForm<imm, [{
299 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
302 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
303 def imm16_31 : ImmLeaf<i32, [{
304 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
307 def so_imm_neg_asmoperand : AsmOperandClass { let Name = "ARMSOImmNeg"; }
308 def so_imm_neg : Operand<i32>, PatLeaf<(imm), [{
309 unsigned Value = -(unsigned)N->getZExtValue();
310 return Value && ARM_AM::getSOImmVal(Value) != -1;
312 let ParserMatchClass = so_imm_neg_asmoperand;
315 // Note: this pattern doesn't require an encoder method and such, as it's
316 // only used on aliases (Pat<> and InstAlias<>). The actual encoding
317 // is handled by the destination instructions, which use so_imm.
318 def so_imm_not_asmoperand : AsmOperandClass { let Name = "ARMSOImmNot"; }
319 def so_imm_not : Operand<i32>, PatLeaf<(imm), [{
320 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
322 let ParserMatchClass = so_imm_not_asmoperand;
325 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
326 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
327 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
330 /// Split a 32-bit immediate into two 16 bit parts.
331 def hi16 : SDNodeXForm<imm, [{
332 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
335 def lo16AllZero : PatLeaf<(i32 imm), [{
336 // Returns true if all low 16-bits are 0.
337 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
340 class BinOpWithFlagFrag<dag res> :
341 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
342 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
343 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
345 // An 'and' node with a single use.
346 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
347 return N->hasOneUse();
350 // An 'xor' node with a single use.
351 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
352 return N->hasOneUse();
355 // An 'fmul' node with a single use.
356 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
357 return N->hasOneUse();
360 // An 'fadd' node which checks for single non-hazardous use.
361 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
362 return hasNoVMLxHazardUse(N);
365 // An 'fsub' node which checks for single non-hazardous use.
366 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
367 return hasNoVMLxHazardUse(N);
370 //===----------------------------------------------------------------------===//
371 // Operand Definitions.
374 // Immediate operands with a shared generic asm render method.
375 class ImmAsmOperand : AsmOperandClass { let RenderMethod = "addImmOperands"; }
378 // FIXME: rename brtarget to t2_brtarget
379 def brtarget : Operand<OtherVT> {
380 let EncoderMethod = "getBranchTargetOpValue";
381 let OperandType = "OPERAND_PCREL";
382 let DecoderMethod = "DecodeT2BROperand";
385 // FIXME: get rid of this one?
386 def uncondbrtarget : Operand<OtherVT> {
387 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
388 let OperandType = "OPERAND_PCREL";
391 // Branch target for ARM. Handles conditional/unconditional
392 def br_target : Operand<OtherVT> {
393 let EncoderMethod = "getARMBranchTargetOpValue";
394 let OperandType = "OPERAND_PCREL";
398 // FIXME: rename bltarget to t2_bl_target?
399 def bltarget : Operand<i32> {
400 // Encoded the same as branch targets.
401 let EncoderMethod = "getBranchTargetOpValue";
402 let OperandType = "OPERAND_PCREL";
405 // Call target for ARM. Handles conditional/unconditional
406 // FIXME: rename bl_target to t2_bltarget?
407 def bl_target : Operand<i32> {
408 let EncoderMethod = "getARMBLTargetOpValue";
409 let OperandType = "OPERAND_PCREL";
412 def blx_target : Operand<i32> {
413 let EncoderMethod = "getARMBLXTargetOpValue";
414 let OperandType = "OPERAND_PCREL";
417 // A list of registers separated by comma. Used by load/store multiple.
418 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
419 def reglist : Operand<i32> {
420 let EncoderMethod = "getRegisterListOpValue";
421 let ParserMatchClass = RegListAsmOperand;
422 let PrintMethod = "printRegisterList";
423 let DecoderMethod = "DecodeRegListOperand";
426 def GPRPairOp : RegisterOperand<GPRPair, "printGPRPairOperand">;
428 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
429 def dpr_reglist : Operand<i32> {
430 let EncoderMethod = "getRegisterListOpValue";
431 let ParserMatchClass = DPRRegListAsmOperand;
432 let PrintMethod = "printRegisterList";
433 let DecoderMethod = "DecodeDPRRegListOperand";
436 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
437 def spr_reglist : Operand<i32> {
438 let EncoderMethod = "getRegisterListOpValue";
439 let ParserMatchClass = SPRRegListAsmOperand;
440 let PrintMethod = "printRegisterList";
441 let DecoderMethod = "DecodeSPRRegListOperand";
444 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
445 def cpinst_operand : Operand<i32> {
446 let PrintMethod = "printCPInstOperand";
450 def pclabel : Operand<i32> {
451 let PrintMethod = "printPCLabel";
454 // ADR instruction labels.
455 def AdrLabelAsmOperand : AsmOperandClass { let Name = "AdrLabel"; }
456 def adrlabel : Operand<i32> {
457 let EncoderMethod = "getAdrLabelOpValue";
458 let ParserMatchClass = AdrLabelAsmOperand;
459 let PrintMethod = "printAdrLabelOperand";
462 def neon_vcvt_imm32 : Operand<i32> {
463 let EncoderMethod = "getNEONVcvtImm32OpValue";
464 let DecoderMethod = "DecodeVCVTImmOperand";
467 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
468 def rot_imm_XFORM: SDNodeXForm<imm, [{
469 switch (N->getZExtValue()){
471 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
472 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
473 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
474 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
477 def RotImmAsmOperand : AsmOperandClass {
479 let ParserMethod = "parseRotImm";
481 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
482 int32_t v = N->getZExtValue();
483 return v == 8 || v == 16 || v == 24; }],
485 let PrintMethod = "printRotImmOperand";
486 let ParserMatchClass = RotImmAsmOperand;
489 // shift_imm: An integer that encodes a shift amount and the type of shift
490 // (asr or lsl). The 6-bit immediate encodes as:
493 // {4-0} imm5 shift amount.
494 // asr #32 encoded as imm5 == 0.
495 def ShifterImmAsmOperand : AsmOperandClass {
496 let Name = "ShifterImm";
497 let ParserMethod = "parseShifterImm";
499 def shift_imm : Operand<i32> {
500 let PrintMethod = "printShiftImmOperand";
501 let ParserMatchClass = ShifterImmAsmOperand;
504 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
505 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
506 def so_reg_reg : Operand<i32>, // reg reg imm
507 ComplexPattern<i32, 3, "SelectRegShifterOperand",
508 [shl, srl, sra, rotr]> {
509 let EncoderMethod = "getSORegRegOpValue";
510 let PrintMethod = "printSORegRegOperand";
511 let DecoderMethod = "DecodeSORegRegOperand";
512 let ParserMatchClass = ShiftedRegAsmOperand;
513 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
516 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
517 def so_reg_imm : Operand<i32>, // reg imm
518 ComplexPattern<i32, 2, "SelectImmShifterOperand",
519 [shl, srl, sra, rotr]> {
520 let EncoderMethod = "getSORegImmOpValue";
521 let PrintMethod = "printSORegImmOperand";
522 let DecoderMethod = "DecodeSORegImmOperand";
523 let ParserMatchClass = ShiftedImmAsmOperand;
524 let MIOperandInfo = (ops GPR, i32imm);
527 // FIXME: Does this need to be distinct from so_reg?
528 def shift_so_reg_reg : Operand<i32>, // reg reg imm
529 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
530 [shl,srl,sra,rotr]> {
531 let EncoderMethod = "getSORegRegOpValue";
532 let PrintMethod = "printSORegRegOperand";
533 let DecoderMethod = "DecodeSORegRegOperand";
534 let ParserMatchClass = ShiftedRegAsmOperand;
535 let MIOperandInfo = (ops GPR, GPR, i32imm);
538 // FIXME: Does this need to be distinct from so_reg?
539 def shift_so_reg_imm : Operand<i32>, // reg reg imm
540 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
541 [shl,srl,sra,rotr]> {
542 let EncoderMethod = "getSORegImmOpValue";
543 let PrintMethod = "printSORegImmOperand";
544 let DecoderMethod = "DecodeSORegImmOperand";
545 let ParserMatchClass = ShiftedImmAsmOperand;
546 let MIOperandInfo = (ops GPR, i32imm);
550 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
551 // 8-bit immediate rotated by an arbitrary number of bits.
552 def SOImmAsmOperand: ImmAsmOperand { let Name = "ARMSOImm"; }
553 def so_imm : Operand<i32>, ImmLeaf<i32, [{
554 return ARM_AM::getSOImmVal(Imm) != -1;
556 let EncoderMethod = "getSOImmOpValue";
557 let ParserMatchClass = SOImmAsmOperand;
558 let DecoderMethod = "DecodeSOImmOperand";
561 // Break so_imm's up into two pieces. This handles immediates with up to 16
562 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
563 // get the first/second pieces.
564 def so_imm2part : PatLeaf<(imm), [{
565 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
568 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
570 def arm_i32imm : PatLeaf<(imm), [{
571 if (Subtarget->hasV6T2Ops())
573 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
576 /// imm0_1 predicate - Immediate in the range [0,1].
577 def Imm0_1AsmOperand: ImmAsmOperand { let Name = "Imm0_1"; }
578 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
580 /// imm0_3 predicate - Immediate in the range [0,3].
581 def Imm0_3AsmOperand: ImmAsmOperand { let Name = "Imm0_3"; }
582 def imm0_3 : Operand<i32> { let ParserMatchClass = Imm0_3AsmOperand; }
584 /// imm0_4 predicate - Immediate in the range [0,4].
585 def Imm0_4AsmOperand : ImmAsmOperand
588 let DiagnosticType = "ImmRange0_4";
590 def imm0_4 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 5; }]> {
591 let ParserMatchClass = Imm0_4AsmOperand;
592 let DecoderMethod = "DecodeImm0_4";
595 /// imm0_7 predicate - Immediate in the range [0,7].
596 def Imm0_7AsmOperand: ImmAsmOperand { let Name = "Imm0_7"; }
597 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
598 return Imm >= 0 && Imm < 8;
600 let ParserMatchClass = Imm0_7AsmOperand;
603 /// imm8 predicate - Immediate is exactly 8.
604 def Imm8AsmOperand: ImmAsmOperand { let Name = "Imm8"; }
605 def imm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 8; }]> {
606 let ParserMatchClass = Imm8AsmOperand;
609 /// imm16 predicate - Immediate is exactly 16.
610 def Imm16AsmOperand: ImmAsmOperand { let Name = "Imm16"; }
611 def imm16 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 16; }]> {
612 let ParserMatchClass = Imm16AsmOperand;
615 /// imm32 predicate - Immediate is exactly 32.
616 def Imm32AsmOperand: ImmAsmOperand { let Name = "Imm32"; }
617 def imm32 : Operand<i32>, ImmLeaf<i32, [{ return Imm == 32; }]> {
618 let ParserMatchClass = Imm32AsmOperand;
621 /// imm1_7 predicate - Immediate in the range [1,7].
622 def Imm1_7AsmOperand: ImmAsmOperand { let Name = "Imm1_7"; }
623 def imm1_7 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 8; }]> {
624 let ParserMatchClass = Imm1_7AsmOperand;
627 /// imm1_15 predicate - Immediate in the range [1,15].
628 def Imm1_15AsmOperand: ImmAsmOperand { let Name = "Imm1_15"; }
629 def imm1_15 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 16; }]> {
630 let ParserMatchClass = Imm1_15AsmOperand;
633 /// imm1_31 predicate - Immediate in the range [1,31].
634 def Imm1_31AsmOperand: ImmAsmOperand { let Name = "Imm1_31"; }
635 def imm1_31 : Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm < 32; }]> {
636 let ParserMatchClass = Imm1_31AsmOperand;
639 /// imm0_15 predicate - Immediate in the range [0,15].
640 def Imm0_15AsmOperand: ImmAsmOperand {
641 let Name = "Imm0_15";
642 let DiagnosticType = "ImmRange0_15";
644 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
645 return Imm >= 0 && Imm < 16;
647 let ParserMatchClass = Imm0_15AsmOperand;
650 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
651 def Imm0_31AsmOperand: ImmAsmOperand { let Name = "Imm0_31"; }
652 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
653 return Imm >= 0 && Imm < 32;
655 let ParserMatchClass = Imm0_31AsmOperand;
658 /// imm0_32 predicate - True if the 32-bit immediate is in the range [0,32].
659 def Imm0_32AsmOperand: ImmAsmOperand { let Name = "Imm0_32"; }
660 def imm0_32 : Operand<i32>, ImmLeaf<i32, [{
661 return Imm >= 0 && Imm < 32;
663 let ParserMatchClass = Imm0_32AsmOperand;
666 /// imm0_63 predicate - True if the 32-bit immediate is in the range [0,63].
667 def Imm0_63AsmOperand: ImmAsmOperand { let Name = "Imm0_63"; }
668 def imm0_63 : Operand<i32>, ImmLeaf<i32, [{
669 return Imm >= 0 && Imm < 64;
671 let ParserMatchClass = Imm0_63AsmOperand;
674 /// imm0_255 predicate - Immediate in the range [0,255].
675 def Imm0_255AsmOperand : ImmAsmOperand { let Name = "Imm0_255"; }
676 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
677 let ParserMatchClass = Imm0_255AsmOperand;
680 /// imm0_65535 - An immediate is in the range [0.65535].
681 def Imm0_65535AsmOperand: ImmAsmOperand { let Name = "Imm0_65535"; }
682 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
683 return Imm >= 0 && Imm < 65536;
685 let ParserMatchClass = Imm0_65535AsmOperand;
688 // imm0_65535_neg - An immediate whose negative value is in the range [0.65535].
689 def imm0_65535_neg : Operand<i32>, ImmLeaf<i32, [{
690 return -Imm >= 0 && -Imm < 65536;
693 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
694 // a relocatable expression.
696 // FIXME: This really needs a Thumb version separate from the ARM version.
697 // While the range is the same, and can thus use the same match class,
698 // the encoding is different so it should have a different encoder method.
699 def Imm0_65535ExprAsmOperand: ImmAsmOperand { let Name = "Imm0_65535Expr"; }
700 def imm0_65535_expr : Operand<i32> {
701 let EncoderMethod = "getHiLo16ImmOpValue";
702 let ParserMatchClass = Imm0_65535ExprAsmOperand;
705 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
706 def Imm24bitAsmOperand: ImmAsmOperand { let Name = "Imm24bit"; }
707 def imm24b : Operand<i32>, ImmLeaf<i32, [{
708 return Imm >= 0 && Imm <= 0xffffff;
710 let ParserMatchClass = Imm24bitAsmOperand;
714 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
716 def BitfieldAsmOperand : AsmOperandClass {
717 let Name = "Bitfield";
718 let ParserMethod = "parseBitfield";
721 def bf_inv_mask_imm : Operand<i32>,
723 return ARM::isBitFieldInvertedMask(N->getZExtValue());
725 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
726 let PrintMethod = "printBitfieldInvMaskImmOperand";
727 let DecoderMethod = "DecodeBitfieldMaskOperand";
728 let ParserMatchClass = BitfieldAsmOperand;
731 def imm1_32_XFORM: SDNodeXForm<imm, [{
732 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
734 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
735 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
736 uint64_t Imm = N->getZExtValue();
737 return Imm > 0 && Imm <= 32;
740 let PrintMethod = "printImmPlusOneOperand";
741 let ParserMatchClass = Imm1_32AsmOperand;
744 def imm1_16_XFORM: SDNodeXForm<imm, [{
745 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
747 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
748 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
750 let PrintMethod = "printImmPlusOneOperand";
751 let ParserMatchClass = Imm1_16AsmOperand;
754 // Define ARM specific addressing modes.
755 // addrmode_imm12 := reg +/- imm12
757 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
758 class AddrMode_Imm12 : Operand<i32>,
759 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
760 // 12-bit immediate operand. Note that instructions using this encode
761 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
762 // immediate values are as normal.
764 let EncoderMethod = "getAddrModeImm12OpValue";
765 let DecoderMethod = "DecodeAddrModeImm12Operand";
766 let ParserMatchClass = MemImm12OffsetAsmOperand;
767 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
770 def addrmode_imm12 : AddrMode_Imm12 {
771 let PrintMethod = "printAddrModeImm12Operand<false>";
774 def addrmode_imm12_pre : AddrMode_Imm12 {
775 let PrintMethod = "printAddrModeImm12Operand<true>";
778 // ldst_so_reg := reg +/- reg shop imm
780 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
781 def ldst_so_reg : Operand<i32>,
782 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
783 let EncoderMethod = "getLdStSORegOpValue";
784 // FIXME: Simplify the printer
785 let PrintMethod = "printAddrMode2Operand";
786 let DecoderMethod = "DecodeSORegMemOperand";
787 let ParserMatchClass = MemRegOffsetAsmOperand;
788 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
791 // postidx_imm8 := +/- [0,255]
794 // {8} 1 is imm8 is non-negative. 0 otherwise.
795 // {7-0} [0,255] imm8 value.
796 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
797 def postidx_imm8 : Operand<i32> {
798 let PrintMethod = "printPostIdxImm8Operand";
799 let ParserMatchClass = PostIdxImm8AsmOperand;
800 let MIOperandInfo = (ops i32imm);
803 // postidx_imm8s4 := +/- [0,1020]
806 // {8} 1 is imm8 is non-negative. 0 otherwise.
807 // {7-0} [0,255] imm8 value, scaled by 4.
808 def PostIdxImm8s4AsmOperand : AsmOperandClass { let Name = "PostIdxImm8s4"; }
809 def postidx_imm8s4 : Operand<i32> {
810 let PrintMethod = "printPostIdxImm8s4Operand";
811 let ParserMatchClass = PostIdxImm8s4AsmOperand;
812 let MIOperandInfo = (ops i32imm);
816 // postidx_reg := +/- reg
818 def PostIdxRegAsmOperand : AsmOperandClass {
819 let Name = "PostIdxReg";
820 let ParserMethod = "parsePostIdxReg";
822 def postidx_reg : Operand<i32> {
823 let EncoderMethod = "getPostIdxRegOpValue";
824 let DecoderMethod = "DecodePostIdxReg";
825 let PrintMethod = "printPostIdxRegOperand";
826 let ParserMatchClass = PostIdxRegAsmOperand;
827 let MIOperandInfo = (ops GPRnopc, i32imm);
831 // addrmode2 := reg +/- imm12
832 // := reg +/- reg shop imm
834 // FIXME: addrmode2 should be refactored the rest of the way to always
835 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
836 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
837 def addrmode2 : Operand<i32>,
838 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
839 let EncoderMethod = "getAddrMode2OpValue";
840 let PrintMethod = "printAddrMode2Operand";
841 let ParserMatchClass = AddrMode2AsmOperand;
842 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
845 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
846 let Name = "PostIdxRegShifted";
847 let ParserMethod = "parsePostIdxReg";
849 def am2offset_reg : Operand<i32>,
850 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
851 [], [SDNPWantRoot]> {
852 let EncoderMethod = "getAddrMode2OffsetOpValue";
853 let PrintMethod = "printAddrMode2OffsetOperand";
854 // When using this for assembly, it's always as a post-index offset.
855 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
856 let MIOperandInfo = (ops GPRnopc, i32imm);
859 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
860 // the GPR is purely vestigal at this point.
861 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
862 def am2offset_imm : Operand<i32>,
863 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
864 [], [SDNPWantRoot]> {
865 let EncoderMethod = "getAddrMode2OffsetOpValue";
866 let PrintMethod = "printAddrMode2OffsetOperand";
867 let ParserMatchClass = AM2OffsetImmAsmOperand;
868 let MIOperandInfo = (ops GPRnopc, i32imm);
872 // addrmode3 := reg +/- reg
873 // addrmode3 := reg +/- imm8
875 // FIXME: split into imm vs. reg versions.
876 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
877 class AddrMode3 : Operand<i32>,
878 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
879 let EncoderMethod = "getAddrMode3OpValue";
880 let ParserMatchClass = AddrMode3AsmOperand;
881 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
884 def addrmode3 : AddrMode3
886 let PrintMethod = "printAddrMode3Operand<false>";
889 def addrmode3_pre : AddrMode3
891 let PrintMethod = "printAddrMode3Operand<true>";
894 // FIXME: split into imm vs. reg versions.
895 // FIXME: parser method to handle +/- register.
896 def AM3OffsetAsmOperand : AsmOperandClass {
897 let Name = "AM3Offset";
898 let ParserMethod = "parseAM3Offset";
900 def am3offset : Operand<i32>,
901 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
902 [], [SDNPWantRoot]> {
903 let EncoderMethod = "getAddrMode3OffsetOpValue";
904 let PrintMethod = "printAddrMode3OffsetOperand";
905 let ParserMatchClass = AM3OffsetAsmOperand;
906 let MIOperandInfo = (ops GPR, i32imm);
909 // ldstm_mode := {ia, ib, da, db}
911 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
912 let EncoderMethod = "getLdStmModeOpValue";
913 let PrintMethod = "printLdStmModeOperand";
916 // addrmode5 := reg +/- imm8*4
918 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
919 class AddrMode5 : Operand<i32>,
920 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
921 let EncoderMethod = "getAddrMode5OpValue";
922 let DecoderMethod = "DecodeAddrMode5Operand";
923 let ParserMatchClass = AddrMode5AsmOperand;
924 let MIOperandInfo = (ops GPR:$base, i32imm);
927 def addrmode5 : AddrMode5 {
928 let PrintMethod = "printAddrMode5Operand<false>";
931 def addrmode5_pre : AddrMode5 {
932 let PrintMethod = "printAddrMode5Operand<true>";
935 // addrmode6 := reg with optional alignment
937 def AddrMode6AsmOperand : AsmOperandClass { let Name = "AlignedMemory"; }
938 def addrmode6 : Operand<i32>,
939 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
940 let PrintMethod = "printAddrMode6Operand";
941 let MIOperandInfo = (ops GPR:$addr, i32imm:$align);
942 let EncoderMethod = "getAddrMode6AddressOpValue";
943 let DecoderMethod = "DecodeAddrMode6Operand";
944 let ParserMatchClass = AddrMode6AsmOperand;
947 def am6offset : Operand<i32>,
948 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
949 [], [SDNPWantRoot]> {
950 let PrintMethod = "printAddrMode6OffsetOperand";
951 let MIOperandInfo = (ops GPR);
952 let EncoderMethod = "getAddrMode6OffsetOpValue";
953 let DecoderMethod = "DecodeGPRRegisterClass";
956 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
957 // (single element from one lane) for size 32.
958 def addrmode6oneL32 : Operand<i32>,
959 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
960 let PrintMethod = "printAddrMode6Operand";
961 let MIOperandInfo = (ops GPR:$addr, i32imm);
962 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
965 // Special version of addrmode6 to handle alignment encoding for VLD-dup
966 // instructions, specifically VLD4-dup.
967 def addrmode6dup : Operand<i32>,
968 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
969 let PrintMethod = "printAddrMode6Operand";
970 let MIOperandInfo = (ops GPR:$addr, i32imm);
971 let EncoderMethod = "getAddrMode6DupAddressOpValue";
972 // FIXME: This is close, but not quite right. The alignment specifier is
974 let ParserMatchClass = AddrMode6AsmOperand;
977 // addrmodepc := pc + reg
979 def addrmodepc : Operand<i32>,
980 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
981 let PrintMethod = "printAddrModePCOperand";
982 let MIOperandInfo = (ops GPR, i32imm);
985 // addr_offset_none := reg
987 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
988 def addr_offset_none : Operand<i32>,
989 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
990 let PrintMethod = "printAddrMode7Operand";
991 let DecoderMethod = "DecodeAddrMode7Operand";
992 let ParserMatchClass = MemNoOffsetAsmOperand;
993 let MIOperandInfo = (ops GPR:$base);
996 def nohash_imm : Operand<i32> {
997 let PrintMethod = "printNoHashImmediate";
1000 def CoprocNumAsmOperand : AsmOperandClass {
1001 let Name = "CoprocNum";
1002 let ParserMethod = "parseCoprocNumOperand";
1004 def p_imm : Operand<i32> {
1005 let PrintMethod = "printPImmediate";
1006 let ParserMatchClass = CoprocNumAsmOperand;
1007 let DecoderMethod = "DecodeCoprocessor";
1010 def pf_imm : Operand<i32> {
1011 let PrintMethod = "printPImmediate";
1012 let ParserMatchClass = CoprocNumAsmOperand;
1015 def CoprocRegAsmOperand : AsmOperandClass {
1016 let Name = "CoprocReg";
1017 let ParserMethod = "parseCoprocRegOperand";
1019 def c_imm : Operand<i32> {
1020 let PrintMethod = "printCImmediate";
1021 let ParserMatchClass = CoprocRegAsmOperand;
1023 def CoprocOptionAsmOperand : AsmOperandClass {
1024 let Name = "CoprocOption";
1025 let ParserMethod = "parseCoprocOptionOperand";
1027 def coproc_option_imm : Operand<i32> {
1028 let PrintMethod = "printCoprocOptionImm";
1029 let ParserMatchClass = CoprocOptionAsmOperand;
1032 //===----------------------------------------------------------------------===//
1034 include "ARMInstrFormats.td"
1036 //===----------------------------------------------------------------------===//
1037 // Multiclass helpers...
1040 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
1041 /// binop that produces a value.
1042 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1043 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
1044 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1045 PatFrag opnode, bit Commutable = 0> {
1046 // The register-immediate version is re-materializable. This is useful
1047 // in particular for taking the address of a local.
1048 let isReMaterializable = 1 in {
1049 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1050 iii, opc, "\t$Rd, $Rn, $imm",
1051 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1052 Sched<[WriteALU, ReadALU]> {
1057 let Inst{19-16} = Rn;
1058 let Inst{15-12} = Rd;
1059 let Inst{11-0} = imm;
1062 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1063 iir, opc, "\t$Rd, $Rn, $Rm",
1064 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1065 Sched<[WriteALU, ReadALU, ReadALU]> {
1070 let isCommutable = Commutable;
1071 let Inst{19-16} = Rn;
1072 let Inst{15-12} = Rd;
1073 let Inst{11-4} = 0b00000000;
1077 def rsi : AsI1<opcod, (outs GPR:$Rd),
1078 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1079 iis, opc, "\t$Rd, $Rn, $shift",
1080 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1081 Sched<[WriteALUsi, ReadALU]> {
1086 let Inst{19-16} = Rn;
1087 let Inst{15-12} = Rd;
1088 let Inst{11-5} = shift{11-5};
1090 let Inst{3-0} = shift{3-0};
1093 def rsr : AsI1<opcod, (outs GPR:$Rd),
1094 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1095 iis, opc, "\t$Rd, $Rn, $shift",
1096 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1097 Sched<[WriteALUsr, ReadALUsr]> {
1102 let Inst{19-16} = Rn;
1103 let Inst{15-12} = Rd;
1104 let Inst{11-8} = shift{11-8};
1106 let Inst{6-5} = shift{6-5};
1108 let Inst{3-0} = shift{3-0};
1112 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
1113 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
1114 /// it is equivalent to the AsI1_bin_irs counterpart.
1115 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1116 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
1117 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1118 PatFrag opnode, bit Commutable = 0> {
1119 // The register-immediate version is re-materializable. This is useful
1120 // in particular for taking the address of a local.
1121 let isReMaterializable = 1 in {
1122 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1123 iii, opc, "\t$Rd, $Rn, $imm",
1124 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1125 Sched<[WriteALU, ReadALU]> {
1130 let Inst{19-16} = Rn;
1131 let Inst{15-12} = Rd;
1132 let Inst{11-0} = imm;
1135 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1136 iir, opc, "\t$Rd, $Rn, $Rm",
1137 [/* pattern left blank */]>,
1138 Sched<[WriteALU, ReadALU, ReadALU]> {
1142 let Inst{11-4} = 0b00000000;
1145 let Inst{15-12} = Rd;
1146 let Inst{19-16} = Rn;
1149 def rsi : AsI1<opcod, (outs GPR:$Rd),
1150 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1151 iis, opc, "\t$Rd, $Rn, $shift",
1152 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1153 Sched<[WriteALUsi, ReadALU]> {
1158 let Inst{19-16} = Rn;
1159 let Inst{15-12} = Rd;
1160 let Inst{11-5} = shift{11-5};
1162 let Inst{3-0} = shift{3-0};
1165 def rsr : AsI1<opcod, (outs GPR:$Rd),
1166 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1167 iis, opc, "\t$Rd, $Rn, $shift",
1168 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1169 Sched<[WriteALUsr, ReadALUsr]> {
1174 let Inst{19-16} = Rn;
1175 let Inst{15-12} = Rd;
1176 let Inst{11-8} = shift{11-8};
1178 let Inst{6-5} = shift{6-5};
1180 let Inst{3-0} = shift{3-0};
1184 /// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
1186 /// These opcodes will be converted to the real non-S opcodes by
1187 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1188 let hasPostISelHook = 1, Defs = [CPSR] in {
1189 multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
1190 InstrItinClass iis, PatFrag opnode,
1191 bit Commutable = 0> {
1192 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1194 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1195 Sched<[WriteALU, ReadALU]>;
1197 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1199 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1200 Sched<[WriteALU, ReadALU, ReadALU]> {
1201 let isCommutable = Commutable;
1203 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1204 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1206 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1207 so_reg_imm:$shift))]>,
1208 Sched<[WriteALUsi, ReadALU]>;
1210 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1211 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1213 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1214 so_reg_reg:$shift))]>,
1215 Sched<[WriteALUSsr, ReadALUsr]>;
1219 /// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
1220 /// operands are reversed.
1221 let hasPostISelHook = 1, Defs = [CPSR] in {
1222 multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
1223 InstrItinClass iis, PatFrag opnode,
1224 bit Commutable = 0> {
1225 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1227 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1228 Sched<[WriteALU, ReadALU]>;
1230 def rsi : ARMPseudoInst<(outs GPR:$Rd),
1231 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1233 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
1235 Sched<[WriteALUsi, ReadALU]>;
1237 def rsr : ARMPseudoInst<(outs GPR:$Rd),
1238 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1240 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
1242 Sched<[WriteALUSsr, ReadALUsr]>;
1246 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1247 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1248 /// a explicit result, only implicitly set CPSR.
1249 let isCompare = 1, Defs = [CPSR] in {
1250 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1251 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1252 PatFrag opnode, bit Commutable = 0> {
1253 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1255 [(opnode GPR:$Rn, so_imm:$imm)]>,
1256 Sched<[WriteCMP, ReadALU]> {
1261 let Inst{19-16} = Rn;
1262 let Inst{15-12} = 0b0000;
1263 let Inst{11-0} = imm;
1265 let Unpredictable{15-12} = 0b1111;
1267 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1269 [(opnode GPR:$Rn, GPR:$Rm)]>,
1270 Sched<[WriteCMP, ReadALU, ReadALU]> {
1273 let isCommutable = Commutable;
1276 let Inst{19-16} = Rn;
1277 let Inst{15-12} = 0b0000;
1278 let Inst{11-4} = 0b00000000;
1281 let Unpredictable{15-12} = 0b1111;
1283 def rsi : AI1<opcod, (outs),
1284 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1285 opc, "\t$Rn, $shift",
1286 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1287 Sched<[WriteCMPsi, ReadALU]> {
1292 let Inst{19-16} = Rn;
1293 let Inst{15-12} = 0b0000;
1294 let Inst{11-5} = shift{11-5};
1296 let Inst{3-0} = shift{3-0};
1298 let Unpredictable{15-12} = 0b1111;
1300 def rsr : AI1<opcod, (outs),
1301 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1302 opc, "\t$Rn, $shift",
1303 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1304 Sched<[WriteCMPsr, ReadALU]> {
1309 let Inst{19-16} = Rn;
1310 let Inst{15-12} = 0b0000;
1311 let Inst{11-8} = shift{11-8};
1313 let Inst{6-5} = shift{6-5};
1315 let Inst{3-0} = shift{3-0};
1317 let Unpredictable{15-12} = 0b1111;
1323 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1324 /// register and one whose operand is a register rotated by 8/16/24.
1325 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1326 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1327 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1328 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1329 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1330 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1334 let Inst{19-16} = 0b1111;
1335 let Inst{15-12} = Rd;
1336 let Inst{11-10} = rot;
1340 class AI_ext_rrot_np<bits<8> opcod, string opc>
1341 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1342 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1343 Requires<[IsARM, HasV6]>, Sched<[WriteALUsi]> {
1345 let Inst{19-16} = 0b1111;
1346 let Inst{11-10} = rot;
1349 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1350 /// register and one whose operand is a register rotated by 8/16/24.
1351 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1352 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1353 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1354 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1355 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1356 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1361 let Inst{19-16} = Rn;
1362 let Inst{15-12} = Rd;
1363 let Inst{11-10} = rot;
1364 let Inst{9-4} = 0b000111;
1368 class AI_exta_rrot_np<bits<8> opcod, string opc>
1369 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1370 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1371 Requires<[IsARM, HasV6]>, Sched<[WriteALUsr]> {
1374 let Inst{19-16} = Rn;
1375 let Inst{11-10} = rot;
1378 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1379 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1380 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1381 bit Commutable = 0> {
1382 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1383 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1384 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1385 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1387 Sched<[WriteALU, ReadALU]> {
1392 let Inst{15-12} = Rd;
1393 let Inst{19-16} = Rn;
1394 let Inst{11-0} = imm;
1396 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1397 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1398 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1400 Sched<[WriteALU, ReadALU, ReadALU]> {
1404 let Inst{11-4} = 0b00000000;
1406 let isCommutable = Commutable;
1408 let Inst{15-12} = Rd;
1409 let Inst{19-16} = Rn;
1411 def rsi : AsI1<opcod, (outs GPR:$Rd),
1412 (ins GPR:$Rn, so_reg_imm:$shift),
1413 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1414 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1416 Sched<[WriteALUsi, ReadALU]> {
1421 let Inst{19-16} = Rn;
1422 let Inst{15-12} = Rd;
1423 let Inst{11-5} = shift{11-5};
1425 let Inst{3-0} = shift{3-0};
1427 def rsr : AsI1<opcod, (outs GPRnopc:$Rd),
1428 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1429 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1430 [(set GPRnopc:$Rd, CPSR,
1431 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1433 Sched<[WriteALUsr, ReadALUsr]> {
1438 let Inst{19-16} = Rn;
1439 let Inst{15-12} = Rd;
1440 let Inst{11-8} = shift{11-8};
1442 let Inst{6-5} = shift{6-5};
1444 let Inst{3-0} = shift{3-0};
1449 /// AI1_rsc_irs - Define instructions and patterns for rsc
1450 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1451 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
1452 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1453 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1454 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1455 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1457 Sched<[WriteALU, ReadALU]> {
1462 let Inst{15-12} = Rd;
1463 let Inst{19-16} = Rn;
1464 let Inst{11-0} = imm;
1466 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1467 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1468 [/* pattern left blank */]>,
1469 Sched<[WriteALU, ReadALU, ReadALU]> {
1473 let Inst{11-4} = 0b00000000;
1476 let Inst{15-12} = Rd;
1477 let Inst{19-16} = Rn;
1479 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1480 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1481 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1483 Sched<[WriteALUsi, ReadALU]> {
1488 let Inst{19-16} = Rn;
1489 let Inst{15-12} = Rd;
1490 let Inst{11-5} = shift{11-5};
1492 let Inst{3-0} = shift{3-0};
1494 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1495 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1496 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1498 Sched<[WriteALUsr, ReadALUsr]> {
1503 let Inst{19-16} = Rn;
1504 let Inst{15-12} = Rd;
1505 let Inst{11-8} = shift{11-8};
1507 let Inst{6-5} = shift{6-5};
1509 let Inst{3-0} = shift{3-0};
1514 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1515 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1516 InstrItinClass iir, PatFrag opnode> {
1517 // Note: We use the complex addrmode_imm12 rather than just an input
1518 // GPR and a constrained immediate so that we can use this to match
1519 // frame index references and avoid matching constant pool references.
1520 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1521 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1522 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1525 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1526 let Inst{19-16} = addr{16-13}; // Rn
1527 let Inst{15-12} = Rt;
1528 let Inst{11-0} = addr{11-0}; // imm12
1530 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1531 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1532 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1535 let shift{4} = 0; // Inst{4} = 0
1536 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1537 let Inst{19-16} = shift{16-13}; // Rn
1538 let Inst{15-12} = Rt;
1539 let Inst{11-0} = shift{11-0};
1544 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1545 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1546 InstrItinClass iir, PatFrag opnode> {
1547 // Note: We use the complex addrmode_imm12 rather than just an input
1548 // GPR and a constrained immediate so that we can use this to match
1549 // frame index references and avoid matching constant pool references.
1550 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt),
1551 (ins addrmode_imm12:$addr),
1552 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1553 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1556 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1557 let Inst{19-16} = addr{16-13}; // Rn
1558 let Inst{15-12} = Rt;
1559 let Inst{11-0} = addr{11-0}; // imm12
1561 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt),
1562 (ins ldst_so_reg:$shift),
1563 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1564 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1567 let shift{4} = 0; // Inst{4} = 0
1568 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1569 let Inst{19-16} = shift{16-13}; // Rn
1570 let Inst{15-12} = Rt;
1571 let Inst{11-0} = shift{11-0};
1577 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1578 InstrItinClass iir, PatFrag opnode> {
1579 // Note: We use the complex addrmode_imm12 rather than just an input
1580 // GPR and a constrained immediate so that we can use this to match
1581 // frame index references and avoid matching constant pool references.
1582 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1583 (ins GPR:$Rt, addrmode_imm12:$addr),
1584 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1585 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1588 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1589 let Inst{19-16} = addr{16-13}; // Rn
1590 let Inst{15-12} = Rt;
1591 let Inst{11-0} = addr{11-0}; // imm12
1593 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1594 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1595 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1598 let shift{4} = 0; // Inst{4} = 0
1599 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1600 let Inst{19-16} = shift{16-13}; // Rn
1601 let Inst{15-12} = Rt;
1602 let Inst{11-0} = shift{11-0};
1606 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1607 InstrItinClass iir, PatFrag opnode> {
1608 // Note: We use the complex addrmode_imm12 rather than just an input
1609 // GPR and a constrained immediate so that we can use this to match
1610 // frame index references and avoid matching constant pool references.
1611 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1612 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1613 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1614 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1617 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1618 let Inst{19-16} = addr{16-13}; // Rn
1619 let Inst{15-12} = Rt;
1620 let Inst{11-0} = addr{11-0}; // imm12
1622 def rs : AI2ldst<0b011, 0, isByte, (outs),
1623 (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1624 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1625 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1628 let shift{4} = 0; // Inst{4} = 0
1629 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1630 let Inst{19-16} = shift{16-13}; // Rn
1631 let Inst{15-12} = Rt;
1632 let Inst{11-0} = shift{11-0};
1637 //===----------------------------------------------------------------------===//
1639 //===----------------------------------------------------------------------===//
1641 //===----------------------------------------------------------------------===//
1642 // Miscellaneous Instructions.
1645 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1646 /// the function. The first operand is the ID# for this instruction, the second
1647 /// is the index into the MachineConstantPool that this is, the third is the
1648 /// size in bytes of this constant pool entry.
1649 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1650 def CONSTPOOL_ENTRY :
1651 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1652 i32imm:$size), NoItinerary, []>;
1654 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1655 // from removing one half of the matched pairs. That breaks PEI, which assumes
1656 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1657 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1658 def ADJCALLSTACKUP :
1659 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1660 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1662 def ADJCALLSTACKDOWN :
1663 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1664 [(ARMcallseq_start timm:$amt)]>;
1667 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1668 // (These pseudos use a hand-written selection code).
1669 let usesCustomInserter = 1, Defs = [CPSR], mayLoad = 1, mayStore = 1 in {
1670 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1671 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1673 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1674 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1676 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1677 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1679 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1680 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1682 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1683 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1685 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1686 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1688 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1689 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1691 def ATOMCMPXCHG6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1692 (ins GPR:$addr, GPR:$cmp1, GPR:$cmp2,
1693 GPR:$set1, GPR:$set2),
1695 def ATOMMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1696 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1698 def ATOMUMIN6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1699 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1701 def ATOMMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1702 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1704 def ATOMUMAX6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1705 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1709 def HINT : AI<(outs), (ins imm0_4:$imm), MiscFrm, NoItinerary,
1710 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1712 let Inst{27-3} = 0b0011001000001111000000000;
1713 let Inst{2-0} = imm;
1716 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1717 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1718 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1719 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1720 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1722 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1723 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1728 let Inst{15-12} = Rd;
1729 let Inst{19-16} = Rn;
1730 let Inst{27-20} = 0b01101000;
1731 let Inst{7-4} = 0b1011;
1732 let Inst{11-8} = 0b1111;
1733 let Unpredictable{11-8} = 0b1111;
1736 // The 16-bit operand $val can be used by a debugger to store more information
1737 // about the breakpoint.
1738 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1739 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1741 let Inst{3-0} = val{3-0};
1742 let Inst{19-8} = val{15-4};
1743 let Inst{27-20} = 0b00010010;
1744 let Inst{7-4} = 0b0111;
1747 // Change Processor State
1748 // FIXME: We should use InstAlias to handle the optional operands.
1749 class CPS<dag iops, string asm_ops>
1750 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1751 []>, Requires<[IsARM]> {
1757 let Inst{31-28} = 0b1111;
1758 let Inst{27-20} = 0b00010000;
1759 let Inst{19-18} = imod;
1760 let Inst{17} = M; // Enabled if mode is set;
1761 let Inst{16-9} = 0b00000000;
1762 let Inst{8-6} = iflags;
1764 let Inst{4-0} = mode;
1767 let DecoderMethod = "DecodeCPSInstruction" in {
1769 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1770 "$imod\t$iflags, $mode">;
1771 let mode = 0, M = 0 in
1772 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1774 let imod = 0, iflags = 0, M = 1 in
1775 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1778 // Preload signals the memory system of possible future data/instruction access.
1779 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1781 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1782 !strconcat(opc, "\t$addr"),
1783 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]>,
1784 Sched<[WritePreLd]> {
1787 let Inst{31-26} = 0b111101;
1788 let Inst{25} = 0; // 0 for immediate form
1789 let Inst{24} = data;
1790 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1791 let Inst{22} = read;
1792 let Inst{21-20} = 0b01;
1793 let Inst{19-16} = addr{16-13}; // Rn
1794 let Inst{15-12} = 0b1111;
1795 let Inst{11-0} = addr{11-0}; // imm12
1798 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1799 !strconcat(opc, "\t$shift"),
1800 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]>,
1801 Sched<[WritePreLd]> {
1803 let Inst{31-26} = 0b111101;
1804 let Inst{25} = 1; // 1 for register form
1805 let Inst{24} = data;
1806 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1807 let Inst{22} = read;
1808 let Inst{21-20} = 0b01;
1809 let Inst{19-16} = shift{16-13}; // Rn
1810 let Inst{15-12} = 0b1111;
1811 let Inst{11-0} = shift{11-0};
1816 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1817 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1818 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1820 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1821 "setend\t$end", []>, Requires<[IsARM]> {
1823 let Inst{31-10} = 0b1111000100000001000000;
1828 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1829 []>, Requires<[IsARM, HasV7]> {
1831 let Inst{27-4} = 0b001100100000111100001111;
1832 let Inst{3-0} = opt;
1836 * A5.4 Permanently UNDEFINED instructions.
1838 * For most targets use UDF #65006, for which the OS will generate SIGTRAP.
1839 * Other UDF encodings generate SIGILL.
1841 * NaCl's OS instead chooses an ARM UDF encoding that's also a UDF in Thumb.
1843 * 1110 0111 1111 iiii iiii iiii 1111 iiii
1845 * 1101 1110 iiii iiii
1846 * It uses the following encoding:
1847 * 1110 0111 1111 1110 1101 1110 1111 0000
1848 * - In ARM: UDF #60896;
1849 * - In Thumb: UDF #254 followed by a branch-to-self.
1851 let isBarrier = 1, isTerminator = 1 in
1852 def TRAPNaCl : AXI<(outs), (ins), MiscFrm, NoItinerary,
1854 Requires<[IsARM,UseNaClTrap]> {
1855 let Inst = 0xe7fedef0;
1857 let isBarrier = 1, isTerminator = 1 in
1858 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1860 Requires<[IsARM,DontUseNaClTrap]> {
1861 let Inst = 0xe7ffdefe;
1864 // Address computation and loads and stores in PIC mode.
1865 let isNotDuplicable = 1 in {
1866 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1868 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>,
1869 Sched<[WriteALU, ReadALU]>;
1871 let AddedComplexity = 10 in {
1872 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1874 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1876 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1878 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1880 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1882 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1884 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1886 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1888 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1890 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1892 let AddedComplexity = 10 in {
1893 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1894 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1896 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1897 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1898 addrmodepc:$addr)]>;
1900 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1901 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1903 } // isNotDuplicable = 1
1906 // LEApcrel - Load a pc-relative address into a register without offending the
1908 let neverHasSideEffects = 1, isReMaterializable = 1 in
1909 // The 'adr' mnemonic encodes differently if the label is before or after
1910 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1911 // know until then which form of the instruction will be used.
1912 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1913 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
1914 Sched<[WriteALU, ReadALU]> {
1917 let Inst{27-25} = 0b001;
1919 let Inst{23-22} = label{13-12};
1922 let Inst{19-16} = 0b1111;
1923 let Inst{15-12} = Rd;
1924 let Inst{11-0} = label{11-0};
1927 let hasSideEffects = 1 in {
1928 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1929 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1931 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1932 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1933 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>;
1936 //===----------------------------------------------------------------------===//
1937 // Control Flow Instructions.
1940 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1942 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1943 "bx", "\tlr", [(ARMretflag)]>,
1944 Requires<[IsARM, HasV4T]> {
1945 let Inst{27-0} = 0b0001001011111111111100011110;
1949 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1950 "mov", "\tpc, lr", [(ARMretflag)]>,
1951 Requires<[IsARM, NoV4T]> {
1952 let Inst{27-0} = 0b0001101000001111000000001110;
1956 // Indirect branches
1957 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1959 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1960 [(brind GPR:$dst)]>,
1961 Requires<[IsARM, HasV4T]> {
1963 let Inst{31-4} = 0b1110000100101111111111110001;
1964 let Inst{3-0} = dst;
1967 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1968 "bx", "\t$dst", [/* pattern left blank */]>,
1969 Requires<[IsARM, HasV4T]> {
1971 let Inst{27-4} = 0b000100101111111111110001;
1972 let Inst{3-0} = dst;
1976 // SP is marked as a use to prevent stack-pointer assignments that appear
1977 // immediately before calls from potentially appearing dead.
1979 // FIXME: Do we really need a non-predicated version? If so, it should
1980 // at least be a pseudo instruction expanding to the predicated version
1981 // at MC lowering time.
1982 Defs = [LR], Uses = [SP] in {
1983 def BL : ABXI<0b1011, (outs), (ins bl_target:$func),
1984 IIC_Br, "bl\t$func",
1985 [(ARMcall tglobaladdr:$func)]>,
1987 let Inst{31-28} = 0b1110;
1989 let Inst{23-0} = func;
1990 let DecoderMethod = "DecodeBranchImmInstruction";
1993 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func),
1994 IIC_Br, "bl", "\t$func",
1995 [(ARMcall_pred tglobaladdr:$func)]>,
1998 let Inst{23-0} = func;
1999 let DecoderMethod = "DecodeBranchImmInstruction";
2003 def BLX : AXI<(outs), (ins GPR:$func), BrMiscFrm,
2004 IIC_Br, "blx\t$func",
2005 [(ARMcall GPR:$func)]>,
2006 Requires<[IsARM, HasV5T]> {
2008 let Inst{31-4} = 0b1110000100101111111111110011;
2009 let Inst{3-0} = func;
2012 def BLX_pred : AI<(outs), (ins GPR:$func), BrMiscFrm,
2013 IIC_Br, "blx", "\t$func",
2014 [(ARMcall_pred GPR:$func)]>,
2015 Requires<[IsARM, HasV5T]> {
2017 let Inst{27-4} = 0b000100101111111111110011;
2018 let Inst{3-0} = func;
2022 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2023 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2024 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2025 Requires<[IsARM, HasV4T]>;
2028 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func),
2029 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2030 Requires<[IsARM, NoV4T]>;
2032 // mov lr, pc; b if callee is marked noreturn to avoid confusing the
2033 // return stack predictor.
2034 def BMOVPCB_CALL : ARMPseudoInst<(outs), (ins bl_target:$func),
2035 8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
2039 let isBranch = 1, isTerminator = 1 in {
2040 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2041 // a two-value operand where a dag node expects two operands. :(
2042 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2043 IIC_Br, "b", "\t$target",
2044 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
2046 let Inst{23-0} = target;
2047 let DecoderMethod = "DecodeBranchImmInstruction";
2050 let isBarrier = 1 in {
2051 // B is "predicable" since it's just a Bcc with an 'always' condition.
2052 let isPredicable = 1 in
2053 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2054 // should be sufficient.
2055 // FIXME: Is B really a Barrier? That doesn't seem right.
2056 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2057 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
2059 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2060 def BR_JTr : ARMPseudoInst<(outs),
2061 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2063 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
2064 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2065 // into i12 and rs suffixed versions.
2066 def BR_JTm : ARMPseudoInst<(outs),
2067 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2069 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2071 def BR_JTadd : ARMPseudoInst<(outs),
2072 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2074 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2076 } // isNotDuplicable = 1, isIndirectBranch = 1
2082 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2083 "blx\t$target", []>,
2084 Requires<[IsARM, HasV5T]> {
2085 let Inst{31-25} = 0b1111101;
2087 let Inst{23-0} = target{24-1};
2088 let Inst{24} = target{0};
2091 // Branch and Exchange Jazelle
2092 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2093 [/* pattern left blank */]> {
2095 let Inst{23-20} = 0b0010;
2096 let Inst{19-8} = 0xfff;
2097 let Inst{7-4} = 0b0010;
2098 let Inst{3-0} = func;
2103 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
2104 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst), IIC_Br, []>;
2106 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst), IIC_Br, []>;
2108 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst),
2110 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2113 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst),
2119 // Secure Monitor Call is a system instruction.
2120 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2121 []>, Requires<[IsARM, HasTrustZone]> {
2123 let Inst{23-4} = 0b01100000000000000111;
2124 let Inst{3-0} = opt;
2127 // Supervisor Call (Software Interrupt)
2128 let isCall = 1, Uses = [SP] in {
2129 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2131 let Inst{23-0} = svc;
2135 // Store Return State
2136 class SRSI<bit wb, string asm>
2137 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2138 NoItinerary, asm, "", []> {
2140 let Inst{31-28} = 0b1111;
2141 let Inst{27-25} = 0b100;
2145 let Inst{19-16} = 0b1101; // SP
2146 let Inst{15-5} = 0b00000101000;
2147 let Inst{4-0} = mode;
2150 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2151 let Inst{24-23} = 0;
2153 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2154 let Inst{24-23} = 0;
2156 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2157 let Inst{24-23} = 0b10;
2159 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2160 let Inst{24-23} = 0b10;
2162 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2163 let Inst{24-23} = 0b01;
2165 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2166 let Inst{24-23} = 0b01;
2168 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2169 let Inst{24-23} = 0b11;
2171 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2172 let Inst{24-23} = 0b11;
2175 def : ARMInstAlias<"srsda $mode", (SRSDA imm0_31:$mode)>;
2176 def : ARMInstAlias<"srsda $mode!", (SRSDA_UPD imm0_31:$mode)>;
2178 def : ARMInstAlias<"srsdb $mode", (SRSDB imm0_31:$mode)>;
2179 def : ARMInstAlias<"srsdb $mode!", (SRSDB_UPD imm0_31:$mode)>;
2181 def : ARMInstAlias<"srsia $mode", (SRSIA imm0_31:$mode)>;
2182 def : ARMInstAlias<"srsia $mode!", (SRSIA_UPD imm0_31:$mode)>;
2184 def : ARMInstAlias<"srsib $mode", (SRSIB imm0_31:$mode)>;
2185 def : ARMInstAlias<"srsib $mode!", (SRSIB_UPD imm0_31:$mode)>;
2187 // Return From Exception
2188 class RFEI<bit wb, string asm>
2189 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2190 NoItinerary, asm, "", []> {
2192 let Inst{31-28} = 0b1111;
2193 let Inst{27-25} = 0b100;
2197 let Inst{19-16} = Rn;
2198 let Inst{15-0} = 0xa00;
2201 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2202 let Inst{24-23} = 0;
2204 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2205 let Inst{24-23} = 0;
2207 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2208 let Inst{24-23} = 0b10;
2210 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2211 let Inst{24-23} = 0b10;
2213 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2214 let Inst{24-23} = 0b01;
2216 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2217 let Inst{24-23} = 0b01;
2219 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2220 let Inst{24-23} = 0b11;
2222 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2223 let Inst{24-23} = 0b11;
2226 //===----------------------------------------------------------------------===//
2227 // Load / Store Instructions.
2233 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2234 UnOpFrag<(load node:$Src)>>;
2235 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2236 UnOpFrag<(zextloadi8 node:$Src)>>;
2237 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2238 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2239 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2240 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2242 // Special LDR for loads from non-pc-relative constpools.
2243 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2244 isReMaterializable = 1, isCodeGenOnly = 1 in
2245 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2246 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2250 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2251 let Inst{19-16} = 0b1111;
2252 let Inst{15-12} = Rt;
2253 let Inst{11-0} = addr{11-0}; // imm12
2256 // Loads with zero extension
2257 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2258 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2259 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2261 // Loads with sign extension
2262 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2263 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2264 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2266 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2267 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2268 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2270 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2272 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2273 (ins addrmode3:$addr), LdMiscFrm,
2274 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2275 []>, Requires<[IsARM, HasV5TE]>;
2279 multiclass AI2_ldridx<bit isByte, string opc,
2280 InstrItinClass iii, InstrItinClass iir> {
2281 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2282 (ins addrmode_imm12_pre:$addr), IndexModePre, LdFrm, iii,
2283 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2286 let Inst{23} = addr{12};
2287 let Inst{19-16} = addr{16-13};
2288 let Inst{11-0} = addr{11-0};
2289 let DecoderMethod = "DecodeLDRPreImm";
2290 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2293 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2294 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, iir,
2295 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2298 let Inst{23} = addr{12};
2299 let Inst{19-16} = addr{16-13};
2300 let Inst{11-0} = addr{11-0};
2302 let DecoderMethod = "DecodeLDRPreReg";
2303 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2306 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2307 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2308 IndexModePost, LdFrm, iir,
2309 opc, "\t$Rt, $addr, $offset",
2310 "$addr.base = $Rn_wb", []> {
2316 let Inst{23} = offset{12};
2317 let Inst{19-16} = addr;
2318 let Inst{11-0} = offset{11-0};
2321 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2324 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2325 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2326 IndexModePost, LdFrm, iii,
2327 opc, "\t$Rt, $addr, $offset",
2328 "$addr.base = $Rn_wb", []> {
2334 let Inst{23} = offset{12};
2335 let Inst{19-16} = addr;
2336 let Inst{11-0} = offset{11-0};
2338 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2343 let mayLoad = 1, neverHasSideEffects = 1 in {
2344 // FIXME: for LDR_PRE_REG etc. the itineray should be either IIC_iLoad_ru or
2345 // IIC_iLoad_siu depending on whether it the offset register is shifted.
2346 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_iu, IIC_iLoad_ru>;
2347 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_iu, IIC_iLoad_bh_ru>;
2350 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2351 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2352 (ins addrmode3_pre:$addr), IndexModePre,
2354 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2356 let Inst{23} = addr{8}; // U bit
2357 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2358 let Inst{19-16} = addr{12-9}; // Rn
2359 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2360 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2361 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2362 let DecoderMethod = "DecodeAddrMode3Instruction";
2364 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2365 (ins addr_offset_none:$addr, am3offset:$offset),
2366 IndexModePost, LdMiscFrm, itin,
2367 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2371 let Inst{23} = offset{8}; // U bit
2372 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2373 let Inst{19-16} = addr;
2374 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2375 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2376 let DecoderMethod = "DecodeAddrMode3Instruction";
2380 let mayLoad = 1, neverHasSideEffects = 1 in {
2381 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2382 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2383 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2384 let hasExtraDefRegAllocReq = 1 in {
2385 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2386 (ins addrmode3_pre:$addr), IndexModePre,
2387 LdMiscFrm, IIC_iLoad_d_ru,
2388 "ldrd", "\t$Rt, $Rt2, $addr!",
2389 "$addr.base = $Rn_wb", []> {
2391 let Inst{23} = addr{8}; // U bit
2392 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2393 let Inst{19-16} = addr{12-9}; // Rn
2394 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2395 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2396 let DecoderMethod = "DecodeAddrMode3Instruction";
2397 let AsmMatchConverter = "cvtLdrdPre";
2399 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2400 (ins addr_offset_none:$addr, am3offset:$offset),
2401 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2402 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2403 "$addr.base = $Rn_wb", []> {
2406 let Inst{23} = offset{8}; // U bit
2407 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2408 let Inst{19-16} = addr;
2409 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2410 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2411 let DecoderMethod = "DecodeAddrMode3Instruction";
2413 } // hasExtraDefRegAllocReq = 1
2414 } // mayLoad = 1, neverHasSideEffects = 1
2416 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2417 let mayLoad = 1, neverHasSideEffects = 1 in {
2418 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2419 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2420 IndexModePost, LdFrm, IIC_iLoad_ru,
2421 "ldrt", "\t$Rt, $addr, $offset",
2422 "$addr.base = $Rn_wb", []> {
2428 let Inst{23} = offset{12};
2429 let Inst{21} = 1; // overwrite
2430 let Inst{19-16} = addr;
2431 let Inst{11-5} = offset{11-5};
2433 let Inst{3-0} = offset{3-0};
2434 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2437 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2438 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2439 IndexModePost, LdFrm, IIC_iLoad_ru,
2440 "ldrt", "\t$Rt, $addr, $offset",
2441 "$addr.base = $Rn_wb", []> {
2447 let Inst{23} = offset{12};
2448 let Inst{21} = 1; // overwrite
2449 let Inst{19-16} = addr;
2450 let Inst{11-0} = offset{11-0};
2451 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2454 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2455 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2456 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2457 "ldrbt", "\t$Rt, $addr, $offset",
2458 "$addr.base = $Rn_wb", []> {
2464 let Inst{23} = offset{12};
2465 let Inst{21} = 1; // overwrite
2466 let Inst{19-16} = addr;
2467 let Inst{11-5} = offset{11-5};
2469 let Inst{3-0} = offset{3-0};
2470 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2473 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2474 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2475 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2476 "ldrbt", "\t$Rt, $addr, $offset",
2477 "$addr.base = $Rn_wb", []> {
2483 let Inst{23} = offset{12};
2484 let Inst{21} = 1; // overwrite
2485 let Inst{19-16} = addr;
2486 let Inst{11-0} = offset{11-0};
2487 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2490 multiclass AI3ldrT<bits<4> op, string opc> {
2491 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2492 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2493 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2494 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2496 let Inst{23} = offset{8};
2498 let Inst{11-8} = offset{7-4};
2499 let Inst{3-0} = offset{3-0};
2500 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2502 def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
2503 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2504 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2505 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2507 let Inst{23} = Rm{4};
2510 let Unpredictable{11-8} = 0b1111;
2511 let Inst{3-0} = Rm{3-0};
2512 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2513 let DecoderMethod = "DecodeLDR";
2517 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2518 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2519 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2524 // Stores with truncate
2525 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2526 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2527 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2530 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2531 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2532 StMiscFrm, IIC_iStore_d_r,
2533 "strd", "\t$Rt, $src2, $addr", []>,
2534 Requires<[IsARM, HasV5TE]> {
2539 multiclass AI2_stridx<bit isByte, string opc,
2540 InstrItinClass iii, InstrItinClass iir> {
2541 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2542 (ins GPR:$Rt, addrmode_imm12_pre:$addr), IndexModePre,
2544 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2547 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2548 let Inst{19-16} = addr{16-13}; // Rn
2549 let Inst{11-0} = addr{11-0}; // imm12
2550 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2551 let DecoderMethod = "DecodeSTRPreImm";
2554 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2555 (ins GPR:$Rt, ldst_so_reg:$addr),
2556 IndexModePre, StFrm, iir,
2557 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2560 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2561 let Inst{19-16} = addr{16-13}; // Rn
2562 let Inst{11-0} = addr{11-0};
2563 let Inst{4} = 0; // Inst{4} = 0
2564 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2565 let DecoderMethod = "DecodeSTRPreReg";
2567 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2568 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2569 IndexModePost, StFrm, iir,
2570 opc, "\t$Rt, $addr, $offset",
2571 "$addr.base = $Rn_wb", []> {
2577 let Inst{23} = offset{12};
2578 let Inst{19-16} = addr;
2579 let Inst{11-0} = offset{11-0};
2582 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2585 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2586 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2587 IndexModePost, StFrm, iii,
2588 opc, "\t$Rt, $addr, $offset",
2589 "$addr.base = $Rn_wb", []> {
2595 let Inst{23} = offset{12};
2596 let Inst{19-16} = addr;
2597 let Inst{11-0} = offset{11-0};
2599 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2603 let mayStore = 1, neverHasSideEffects = 1 in {
2604 // FIXME: for STR_PRE_REG etc. the itineray should be either IIC_iStore_ru or
2605 // IIC_iStore_siu depending on whether it the offset register is shifted.
2606 defm STR : AI2_stridx<0, "str", IIC_iStore_iu, IIC_iStore_ru>;
2607 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_iu, IIC_iStore_bh_ru>;
2610 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2611 am2offset_reg:$offset),
2612 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2613 am2offset_reg:$offset)>;
2614 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2615 am2offset_imm:$offset),
2616 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2617 am2offset_imm:$offset)>;
2618 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2619 am2offset_reg:$offset),
2620 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2621 am2offset_reg:$offset)>;
2622 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2623 am2offset_imm:$offset),
2624 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2625 am2offset_imm:$offset)>;
2627 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2628 // put the patterns on the instruction definitions directly as ISel wants
2629 // the address base and offset to be separate operands, not a single
2630 // complex operand like we represent the instructions themselves. The
2631 // pseudos map between the two.
2632 let usesCustomInserter = 1,
2633 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2634 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2635 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2638 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2639 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2640 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2643 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2644 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2645 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2648 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2649 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2650 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2653 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2654 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2655 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2658 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2663 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2664 (ins GPR:$Rt, addrmode3_pre:$addr), IndexModePre,
2665 StMiscFrm, IIC_iStore_bh_ru,
2666 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2668 let Inst{23} = addr{8}; // U bit
2669 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2670 let Inst{19-16} = addr{12-9}; // Rn
2671 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2672 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2673 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2674 let DecoderMethod = "DecodeAddrMode3Instruction";
2677 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2678 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2679 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2680 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2681 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2682 addr_offset_none:$addr,
2683 am3offset:$offset))]> {
2686 let Inst{23} = offset{8}; // U bit
2687 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2688 let Inst{19-16} = addr;
2689 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2690 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2691 let DecoderMethod = "DecodeAddrMode3Instruction";
2694 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2695 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2696 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
2697 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2698 "strd", "\t$Rt, $Rt2, $addr!",
2699 "$addr.base = $Rn_wb", []> {
2701 let Inst{23} = addr{8}; // U bit
2702 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2703 let Inst{19-16} = addr{12-9}; // Rn
2704 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2705 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2706 let DecoderMethod = "DecodeAddrMode3Instruction";
2707 let AsmMatchConverter = "cvtStrdPre";
2710 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2711 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2713 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2714 "strd", "\t$Rt, $Rt2, $addr, $offset",
2715 "$addr.base = $Rn_wb", []> {
2718 let Inst{23} = offset{8}; // U bit
2719 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2720 let Inst{19-16} = addr;
2721 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2722 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2723 let DecoderMethod = "DecodeAddrMode3Instruction";
2725 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2727 // STRT, STRBT, and STRHT
2729 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2730 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2731 IndexModePost, StFrm, IIC_iStore_bh_ru,
2732 "strbt", "\t$Rt, $addr, $offset",
2733 "$addr.base = $Rn_wb", []> {
2739 let Inst{23} = offset{12};
2740 let Inst{21} = 1; // overwrite
2741 let Inst{19-16} = addr;
2742 let Inst{11-5} = offset{11-5};
2744 let Inst{3-0} = offset{3-0};
2745 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2748 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2749 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2750 IndexModePost, StFrm, IIC_iStore_bh_ru,
2751 "strbt", "\t$Rt, $addr, $offset",
2752 "$addr.base = $Rn_wb", []> {
2758 let Inst{23} = offset{12};
2759 let Inst{21} = 1; // overwrite
2760 let Inst{19-16} = addr;
2761 let Inst{11-0} = offset{11-0};
2762 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2765 let mayStore = 1, neverHasSideEffects = 1 in {
2766 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2767 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2768 IndexModePost, StFrm, IIC_iStore_ru,
2769 "strt", "\t$Rt, $addr, $offset",
2770 "$addr.base = $Rn_wb", []> {
2776 let Inst{23} = offset{12};
2777 let Inst{21} = 1; // overwrite
2778 let Inst{19-16} = addr;
2779 let Inst{11-5} = offset{11-5};
2781 let Inst{3-0} = offset{3-0};
2782 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2785 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2786 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2787 IndexModePost, StFrm, IIC_iStore_ru,
2788 "strt", "\t$Rt, $addr, $offset",
2789 "$addr.base = $Rn_wb", []> {
2795 let Inst{23} = offset{12};
2796 let Inst{21} = 1; // overwrite
2797 let Inst{19-16} = addr;
2798 let Inst{11-0} = offset{11-0};
2799 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2804 multiclass AI3strT<bits<4> op, string opc> {
2805 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2806 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2807 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2808 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2810 let Inst{23} = offset{8};
2812 let Inst{11-8} = offset{7-4};
2813 let Inst{3-0} = offset{3-0};
2814 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2816 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2817 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2818 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2819 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2821 let Inst{23} = Rm{4};
2824 let Inst{3-0} = Rm{3-0};
2825 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2830 defm STRHT : AI3strT<0b1011, "strht">;
2833 //===----------------------------------------------------------------------===//
2834 // Load / store multiple Instructions.
2837 multiclass arm_ldst_mult<string asm, string sfx, bit L_bit, bit P_bit, Format f,
2838 InstrItinClass itin, InstrItinClass itin_upd> {
2839 // IA is the default, so no need for an explicit suffix on the
2840 // mnemonic here. Without it is the canonical spelling.
2842 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2843 IndexModeNone, f, itin,
2844 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
2845 let Inst{24-23} = 0b01; // Increment After
2846 let Inst{22} = P_bit;
2847 let Inst{21} = 0; // No writeback
2848 let Inst{20} = L_bit;
2851 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2852 IndexModeUpd, f, itin_upd,
2853 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2854 let Inst{24-23} = 0b01; // Increment After
2855 let Inst{22} = P_bit;
2856 let Inst{21} = 1; // Writeback
2857 let Inst{20} = L_bit;
2859 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2862 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2863 IndexModeNone, f, itin,
2864 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
2865 let Inst{24-23} = 0b00; // Decrement After
2866 let Inst{22} = P_bit;
2867 let Inst{21} = 0; // No writeback
2868 let Inst{20} = L_bit;
2871 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2872 IndexModeUpd, f, itin_upd,
2873 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2874 let Inst{24-23} = 0b00; // Decrement After
2875 let Inst{22} = P_bit;
2876 let Inst{21} = 1; // Writeback
2877 let Inst{20} = L_bit;
2879 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2882 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2883 IndexModeNone, f, itin,
2884 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
2885 let Inst{24-23} = 0b10; // Decrement Before
2886 let Inst{22} = P_bit;
2887 let Inst{21} = 0; // No writeback
2888 let Inst{20} = L_bit;
2891 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2892 IndexModeUpd, f, itin_upd,
2893 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2894 let Inst{24-23} = 0b10; // Decrement Before
2895 let Inst{22} = P_bit;
2896 let Inst{21} = 1; // Writeback
2897 let Inst{20} = L_bit;
2899 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2902 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2903 IndexModeNone, f, itin,
2904 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
2905 let Inst{24-23} = 0b11; // Increment Before
2906 let Inst{22} = P_bit;
2907 let Inst{21} = 0; // No writeback
2908 let Inst{20} = L_bit;
2911 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2912 IndexModeUpd, f, itin_upd,
2913 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
2914 let Inst{24-23} = 0b11; // Increment Before
2915 let Inst{22} = P_bit;
2916 let Inst{21} = 1; // Writeback
2917 let Inst{20} = L_bit;
2919 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2923 let neverHasSideEffects = 1 in {
2925 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2926 defm LDM : arm_ldst_mult<"ldm", "", 1, 0, LdStMulFrm, IIC_iLoad_m,
2929 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2930 defm STM : arm_ldst_mult<"stm", "", 0, 0, LdStMulFrm, IIC_iStore_m,
2933 } // neverHasSideEffects
2935 // FIXME: remove when we have a way to marking a MI with these properties.
2936 // FIXME: Should pc be an implicit operand like PICADD, etc?
2937 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2938 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2939 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2940 reglist:$regs, variable_ops),
2941 4, IIC_iLoad_mBr, [],
2942 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2943 RegConstraint<"$Rn = $wb">;
2945 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2946 defm sysLDM : arm_ldst_mult<"ldm", " ^", 1, 1, LdStMulFrm, IIC_iLoad_m,
2949 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2950 defm sysSTM : arm_ldst_mult<"stm", " ^", 0, 1, LdStMulFrm, IIC_iStore_m,
2955 //===----------------------------------------------------------------------===//
2956 // Move Instructions.
2959 let neverHasSideEffects = 1 in
2960 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2961 "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2965 let Inst{19-16} = 0b0000;
2966 let Inst{11-4} = 0b00000000;
2969 let Inst{15-12} = Rd;
2972 // A version for the smaller set of tail call registers.
2973 let neverHasSideEffects = 1 in
2974 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2975 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP, Sched<[WriteALU]> {
2979 let Inst{11-4} = 0b00000000;
2982 let Inst{15-12} = Rd;
2985 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2986 DPSoRegRegFrm, IIC_iMOVsr,
2987 "mov", "\t$Rd, $src",
2988 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP,
2992 let Inst{15-12} = Rd;
2993 let Inst{19-16} = 0b0000;
2994 let Inst{11-8} = src{11-8};
2996 let Inst{6-5} = src{6-5};
2998 let Inst{3-0} = src{3-0};
3002 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
3003 DPSoRegImmFrm, IIC_iMOVsr,
3004 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
3005 UnaryDP, Sched<[WriteALU]> {
3008 let Inst{15-12} = Rd;
3009 let Inst{19-16} = 0b0000;
3010 let Inst{11-5} = src{11-5};
3012 let Inst{3-0} = src{3-0};
3016 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3017 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3018 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
3023 let Inst{15-12} = Rd;
3024 let Inst{19-16} = 0b0000;
3025 let Inst{11-0} = imm;
3028 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3029 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3031 "movw", "\t$Rd, $imm",
3032 [(set GPR:$Rd, imm0_65535:$imm)]>,
3033 Requires<[IsARM, HasV6T2]>, UnaryDP, Sched<[WriteALU]> {
3036 let Inst{15-12} = Rd;
3037 let Inst{11-0} = imm{11-0};
3038 let Inst{19-16} = imm{15-12};
3041 let DecoderMethod = "DecodeArmMOVTWInstruction";
3044 def : InstAlias<"mov${p} $Rd, $imm",
3045 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3048 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3049 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3052 let Constraints = "$src = $Rd" in {
3053 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3054 (ins GPR:$src, imm0_65535_expr:$imm),
3056 "movt", "\t$Rd, $imm",
3058 (or (and GPR:$src, 0xffff),
3059 lo16AllZero:$imm))]>, UnaryDP,
3060 Requires<[IsARM, HasV6T2]>, Sched<[WriteALU]> {
3063 let Inst{15-12} = Rd;
3064 let Inst{11-0} = imm{11-0};
3065 let Inst{19-16} = imm{15-12};
3068 let DecoderMethod = "DecodeArmMOVTWInstruction";
3071 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3072 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
3077 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3078 Requires<[IsARM, HasV6T2]>;
3080 let Uses = [CPSR] in
3081 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3082 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3083 Requires<[IsARM]>, Sched<[WriteALU]>;
3085 // These aren't really mov instructions, but we have to define them this way
3086 // due to flag operands.
3088 let Defs = [CPSR] in {
3089 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3090 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3091 Sched<[WriteALU]>, Requires<[IsARM]>;
3092 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3093 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3094 Sched<[WriteALU]>, Requires<[IsARM]>;
3097 //===----------------------------------------------------------------------===//
3098 // Extend Instructions.
3103 def SXTB : AI_ext_rrot<0b01101010,
3104 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3105 def SXTH : AI_ext_rrot<0b01101011,
3106 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3108 def SXTAB : AI_exta_rrot<0b01101010,
3109 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3110 def SXTAH : AI_exta_rrot<0b01101011,
3111 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3113 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3115 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3119 let AddedComplexity = 16 in {
3120 def UXTB : AI_ext_rrot<0b01101110,
3121 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3122 def UXTH : AI_ext_rrot<0b01101111,
3123 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3124 def UXTB16 : AI_ext_rrot<0b01101100,
3125 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3127 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3128 // The transformation should probably be done as a combiner action
3129 // instead so we can include a check for masking back in the upper
3130 // eight bits of the source into the lower eight bits of the result.
3131 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3132 // (UXTB16r_rot GPR:$Src, 3)>;
3133 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3134 (UXTB16 GPR:$Src, 1)>;
3136 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3137 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3138 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3139 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3142 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3143 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3146 def SBFX : I<(outs GPRnopc:$Rd),
3147 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3148 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3149 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3150 Requires<[IsARM, HasV6T2]> {
3155 let Inst{27-21} = 0b0111101;
3156 let Inst{6-4} = 0b101;
3157 let Inst{20-16} = width;
3158 let Inst{15-12} = Rd;
3159 let Inst{11-7} = lsb;
3163 def UBFX : I<(outs GPR:$Rd),
3164 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3165 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3166 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3167 Requires<[IsARM, HasV6T2]> {
3172 let Inst{27-21} = 0b0111111;
3173 let Inst{6-4} = 0b101;
3174 let Inst{20-16} = width;
3175 let Inst{15-12} = Rd;
3176 let Inst{11-7} = lsb;
3180 //===----------------------------------------------------------------------===//
3181 // Arithmetic Instructions.
3184 defm ADD : AsI1_bin_irs<0b0100, "add",
3185 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3186 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>;
3187 defm SUB : AsI1_bin_irs<0b0010, "sub",
3188 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3189 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3191 // ADD and SUB with 's' bit set.
3193 // Currently, ADDS/SUBS are pseudo opcodes that exist only in the
3194 // selection DAG. They are "lowered" to real ADD/SUB opcodes by
3195 // AdjustInstrPostInstrSelection where we determine whether or not to
3196 // set the "s" bit based on CPSR liveness.
3198 // FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
3199 // support for an optional CPSR definition that corresponds to the DAG
3200 // node's second value. We can then eliminate the implicit def of CPSR.
3201 defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3202 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3203 defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3204 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3206 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3207 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>;
3208 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3209 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3211 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3212 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3213 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
3215 // FIXME: Eliminate them if we can write def : Pat patterns which defines
3216 // CPSR and the implicit def of CPSR is not needed.
3217 defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3218 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3220 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3221 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>;
3223 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3224 // The assume-no-carry-in form uses the negation of the input since add/sub
3225 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3226 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3228 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3229 (SUBri GPR:$src, so_imm_neg:$imm)>;
3230 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3231 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3233 def : ARMPat<(add GPR:$src, imm0_65535_neg:$imm),
3234 (SUBrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3235 Requires<[IsARM, HasV6T2]>;
3236 def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$imm),
3237 (SUBSrr GPR:$src, (MOVi16 (imm_neg_XFORM imm:$imm)))>,
3238 Requires<[IsARM, HasV6T2]>;
3240 // The with-carry-in form matches bitwise not instead of the negation.
3241 // Effectively, the inverse interpretation of the carry flag already accounts
3242 // for part of the negation.
3243 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3244 (SBCri GPR:$src, so_imm_not:$imm)>;
3245 def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
3246 (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
3248 // Note: These are implemented in C++ code, because they have to generate
3249 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3251 // (mul X, 2^n+1) -> (add (X << n), X)
3252 // (mul X, 2^n-1) -> (rsb X, (X << n))
3254 // ARM Arithmetic Instruction
3255 // GPR:$dst = GPR:$a op GPR:$b
3256 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3257 list<dag> pattern = [],
3258 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3259 string asm = "\t$Rd, $Rn, $Rm">
3260 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3261 Sched<[WriteALU, ReadALU, ReadALU]> {
3265 let Inst{27-20} = op27_20;
3266 let Inst{11-4} = op11_4;
3267 let Inst{19-16} = Rn;
3268 let Inst{15-12} = Rd;
3271 let Unpredictable{11-8} = 0b1111;
3274 // Saturating add/subtract
3276 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3277 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3278 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3279 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3280 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3281 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3282 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3283 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3285 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3286 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3289 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3290 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3291 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3292 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3293 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3294 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3295 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3296 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3297 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3298 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3299 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3300 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3302 // Signed/Unsigned add/subtract
3304 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3305 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3306 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3307 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3308 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3309 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3310 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3311 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3312 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3313 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3314 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3315 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3317 // Signed/Unsigned halving add/subtract
3319 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3320 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3321 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3322 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3323 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3324 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3325 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3326 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3327 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3328 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3329 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3330 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3332 // Unsigned Sum of Absolute Differences [and Accumulate].
3334 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3335 MulFrm /* for convenience */, NoItinerary, "usad8",
3336 "\t$Rd, $Rn, $Rm", []>,
3337 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]> {
3341 let Inst{27-20} = 0b01111000;
3342 let Inst{15-12} = 0b1111;
3343 let Inst{7-4} = 0b0001;
3344 let Inst{19-16} = Rd;
3345 let Inst{11-8} = Rm;
3348 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3349 MulFrm /* for convenience */, NoItinerary, "usada8",
3350 "\t$Rd, $Rn, $Rm, $Ra", []>,
3351 Requires<[IsARM, HasV6]>, Sched<[WriteALU, ReadALU, ReadALU]>{
3356 let Inst{27-20} = 0b01111000;
3357 let Inst{7-4} = 0b0001;
3358 let Inst{19-16} = Rd;
3359 let Inst{15-12} = Ra;
3360 let Inst{11-8} = Rm;
3364 // Signed/Unsigned saturate
3366 def SSAT : AI<(outs GPRnopc:$Rd),
3367 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3368 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3373 let Inst{27-21} = 0b0110101;
3374 let Inst{5-4} = 0b01;
3375 let Inst{20-16} = sat_imm;
3376 let Inst{15-12} = Rd;
3377 let Inst{11-7} = sh{4-0};
3378 let Inst{6} = sh{5};
3382 def SSAT16 : AI<(outs GPRnopc:$Rd),
3383 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3384 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3388 let Inst{27-20} = 0b01101010;
3389 let Inst{11-4} = 0b11110011;
3390 let Inst{15-12} = Rd;
3391 let Inst{19-16} = sat_imm;
3395 def USAT : AI<(outs GPRnopc:$Rd),
3396 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3397 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3402 let Inst{27-21} = 0b0110111;
3403 let Inst{5-4} = 0b01;
3404 let Inst{15-12} = Rd;
3405 let Inst{11-7} = sh{4-0};
3406 let Inst{6} = sh{5};
3407 let Inst{20-16} = sat_imm;
3411 def USAT16 : AI<(outs GPRnopc:$Rd),
3412 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3413 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3417 let Inst{27-20} = 0b01101110;
3418 let Inst{11-4} = 0b11110011;
3419 let Inst{15-12} = Rd;
3420 let Inst{19-16} = sat_imm;
3424 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3425 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3426 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3427 (USAT imm:$pos, GPRnopc:$a, 0)>;
3429 //===----------------------------------------------------------------------===//
3430 // Bitwise Instructions.
3433 defm AND : AsI1_bin_irs<0b0000, "and",
3434 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3435 BinOpFrag<(and node:$LHS, node:$RHS)>, 1>;
3436 defm ORR : AsI1_bin_irs<0b1100, "orr",
3437 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3438 BinOpFrag<(or node:$LHS, node:$RHS)>, 1>;
3439 defm EOR : AsI1_bin_irs<0b0001, "eor",
3440 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3441 BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>;
3442 defm BIC : AsI1_bin_irs<0b1110, "bic",
3443 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3444 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
3446 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3447 // like in the actual instruction encoding. The complexity of mapping the mask
3448 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3449 // instruction description.
3450 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3451 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3452 "bfc", "\t$Rd, $imm", "$src = $Rd",
3453 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3454 Requires<[IsARM, HasV6T2]> {
3457 let Inst{27-21} = 0b0111110;
3458 let Inst{6-0} = 0b0011111;
3459 let Inst{15-12} = Rd;
3460 let Inst{11-7} = imm{4-0}; // lsb
3461 let Inst{20-16} = imm{9-5}; // msb
3464 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3465 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3466 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3467 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3468 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3469 bf_inv_mask_imm:$imm))]>,
3470 Requires<[IsARM, HasV6T2]> {
3474 let Inst{27-21} = 0b0111110;
3475 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3476 let Inst{15-12} = Rd;
3477 let Inst{11-7} = imm{4-0}; // lsb
3478 let Inst{20-16} = imm{9-5}; // width
3482 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3483 "mvn", "\t$Rd, $Rm",
3484 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP, Sched<[WriteALU]> {
3488 let Inst{19-16} = 0b0000;
3489 let Inst{11-4} = 0b00000000;
3490 let Inst{15-12} = Rd;
3493 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3494 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3495 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP,
3500 let Inst{19-16} = 0b0000;
3501 let Inst{15-12} = Rd;
3502 let Inst{11-5} = shift{11-5};
3504 let Inst{3-0} = shift{3-0};
3506 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3507 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3508 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP,
3513 let Inst{19-16} = 0b0000;
3514 let Inst{15-12} = Rd;
3515 let Inst{11-8} = shift{11-8};
3517 let Inst{6-5} = shift{6-5};
3519 let Inst{3-0} = shift{3-0};
3521 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3522 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3523 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3524 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3528 let Inst{19-16} = 0b0000;
3529 let Inst{15-12} = Rd;
3530 let Inst{11-0} = imm;
3533 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3534 (BICri GPR:$src, so_imm_not:$imm)>;
3536 //===----------------------------------------------------------------------===//
3537 // Multiply Instructions.
3539 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3540 string opc, string asm, list<dag> pattern>
3541 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3545 let Inst{19-16} = Rd;
3546 let Inst{11-8} = Rm;
3549 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3550 string opc, string asm, list<dag> pattern>
3551 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3556 let Inst{19-16} = RdHi;
3557 let Inst{15-12} = RdLo;
3558 let Inst{11-8} = Rm;
3561 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3562 string opc, string asm, list<dag> pattern>
3563 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3568 let Inst{19-16} = RdHi;
3569 let Inst{15-12} = RdLo;
3570 let Inst{11-8} = Rm;
3574 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3575 // property. Remove them when it's possible to add those properties
3576 // on an individual MachineInstr, not just an instruction description.
3577 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
3578 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
3579 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3580 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3581 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3582 Requires<[IsARM, HasV6]> {
3583 let Inst{15-12} = 0b0000;
3584 let Unpredictable{15-12} = 0b1111;
3587 let Constraints = "@earlyclobber $Rd" in
3588 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
3589 pred:$p, cc_out:$s),
3591 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
3592 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3593 Requires<[IsARM, NoV6, UseMulOps]>;
3596 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3597 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3598 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3599 Requires<[IsARM, HasV6, UseMulOps]> {
3601 let Inst{15-12} = Ra;
3604 let Constraints = "@earlyclobber $Rd" in
3605 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3606 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3608 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3609 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3610 Requires<[IsARM, NoV6]>;
3612 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3613 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3614 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3615 Requires<[IsARM, HasV6T2, UseMulOps]> {
3620 let Inst{19-16} = Rd;
3621 let Inst{15-12} = Ra;
3622 let Inst{11-8} = Rm;
3626 // Extra precision multiplies with low / high results
3627 let neverHasSideEffects = 1 in {
3628 let isCommutable = 1 in {
3629 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3630 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3631 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3632 Requires<[IsARM, HasV6]>;
3634 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3635 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3636 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3637 Requires<[IsARM, HasV6]>;
3639 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3640 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3641 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3643 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3644 Requires<[IsARM, NoV6]>;
3646 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3647 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3649 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3650 Requires<[IsARM, NoV6]>;
3654 // Multiply + accumulate
3655 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3656 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3657 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3658 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3659 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3660 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
3661 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3662 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3664 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3665 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3666 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3667 Requires<[IsARM, HasV6]> {
3672 let Inst{19-16} = RdHi;
3673 let Inst{15-12} = RdLo;
3674 let Inst{11-8} = Rm;
3678 let Constraints = "$RLo = $RdLo,$RHi = $RdHi" in {
3679 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3680 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3682 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3683 pred:$p, cc_out:$s)>,
3684 Requires<[IsARM, NoV6]>;
3685 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3686 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
3688 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
3689 pred:$p, cc_out:$s)>,
3690 Requires<[IsARM, NoV6]>;
3693 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3694 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3695 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3697 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3698 Requires<[IsARM, NoV6]>;
3701 } // neverHasSideEffects
3703 // Most significant word multiply
3704 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3705 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3706 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3707 Requires<[IsARM, HasV6]> {
3708 let Inst{15-12} = 0b1111;
3711 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3712 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3713 Requires<[IsARM, HasV6]> {
3714 let Inst{15-12} = 0b1111;
3717 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3718 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3719 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3720 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3721 Requires<[IsARM, HasV6, UseMulOps]>;
3723 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3724 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3725 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3726 Requires<[IsARM, HasV6]>;
3728 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3729 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3730 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
3731 Requires<[IsARM, HasV6, UseMulOps]>;
3733 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3734 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3735 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3736 Requires<[IsARM, HasV6]>;
3738 multiclass AI_smul<string opc, PatFrag opnode> {
3739 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3740 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3741 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3742 (sext_inreg GPR:$Rm, i16)))]>,
3743 Requires<[IsARM, HasV5TE]>;
3745 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3746 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3747 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3748 (sra GPR:$Rm, (i32 16))))]>,
3749 Requires<[IsARM, HasV5TE]>;
3751 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3752 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3753 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3754 (sext_inreg GPR:$Rm, i16)))]>,
3755 Requires<[IsARM, HasV5TE]>;
3757 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3758 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3759 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3760 (sra GPR:$Rm, (i32 16))))]>,
3761 Requires<[IsARM, HasV5TE]>;
3763 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3764 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3765 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3766 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3767 Requires<[IsARM, HasV5TE]>;
3769 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3770 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3771 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3772 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3773 Requires<[IsARM, HasV5TE]>;
3777 multiclass AI_smla<string opc, PatFrag opnode> {
3778 let DecoderMethod = "DecodeSMLAInstruction" in {
3779 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3780 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3781 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3782 [(set GPRnopc:$Rd, (add GPR:$Ra,
3783 (opnode (sext_inreg GPRnopc:$Rn, i16),
3784 (sext_inreg GPRnopc:$Rm, i16))))]>,
3785 Requires<[IsARM, HasV5TE, UseMulOps]>;
3787 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3788 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3789 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3791 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3792 (sra GPRnopc:$Rm, (i32 16)))))]>,
3793 Requires<[IsARM, HasV5TE, UseMulOps]>;
3795 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3796 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3797 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3799 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3800 (sext_inreg GPRnopc:$Rm, i16))))]>,
3801 Requires<[IsARM, HasV5TE, UseMulOps]>;
3803 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3804 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3805 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3807 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3808 (sra GPRnopc:$Rm, (i32 16)))))]>,
3809 Requires<[IsARM, HasV5TE, UseMulOps]>;
3811 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3812 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3813 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3815 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3816 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3817 Requires<[IsARM, HasV5TE, UseMulOps]>;
3819 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3820 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3821 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3823 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3824 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3825 Requires<[IsARM, HasV5TE, UseMulOps]>;
3829 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3830 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3832 // Halfword multiply accumulate long: SMLAL<x><y>.
3833 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3834 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3835 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3836 Requires<[IsARM, HasV5TE]>;
3838 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3839 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3840 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3841 Requires<[IsARM, HasV5TE]>;
3843 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3844 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3845 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3846 Requires<[IsARM, HasV5TE]>;
3848 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3849 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3850 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3851 Requires<[IsARM, HasV5TE]>;
3853 // Helper class for AI_smld.
3854 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3855 InstrItinClass itin, string opc, string asm>
3856 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3859 let Inst{27-23} = 0b01110;
3860 let Inst{22} = long;
3861 let Inst{21-20} = 0b00;
3862 let Inst{11-8} = Rm;
3869 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3870 InstrItinClass itin, string opc, string asm>
3871 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3873 let Inst{15-12} = 0b1111;
3874 let Inst{19-16} = Rd;
3876 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3877 InstrItinClass itin, string opc, string asm>
3878 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3881 let Inst{19-16} = Rd;
3882 let Inst{15-12} = Ra;
3884 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3885 InstrItinClass itin, string opc, string asm>
3886 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3889 let Inst{19-16} = RdHi;
3890 let Inst{15-12} = RdLo;
3893 multiclass AI_smld<bit sub, string opc> {
3895 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3896 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3897 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3899 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3900 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3901 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3903 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3904 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3905 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3907 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3908 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3909 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3913 defm SMLA : AI_smld<0, "smla">;
3914 defm SMLS : AI_smld<1, "smls">;
3916 multiclass AI_sdml<bit sub, string opc> {
3918 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3919 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3920 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3921 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3924 defm SMUA : AI_sdml<0, "smua">;
3925 defm SMUS : AI_sdml<1, "smus">;
3927 //===----------------------------------------------------------------------===//
3928 // Division Instructions (ARMv7-A with virtualization extension)
3930 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3931 "sdiv", "\t$Rd, $Rn, $Rm",
3932 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
3933 Requires<[IsARM, HasDivideInARM]>;
3935 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
3936 "udiv", "\t$Rd, $Rn, $Rm",
3937 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
3938 Requires<[IsARM, HasDivideInARM]>;
3940 //===----------------------------------------------------------------------===//
3941 // Misc. Arithmetic Instructions.
3944 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3945 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3946 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
3949 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3950 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3951 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3952 Requires<[IsARM, HasV6T2]>,
3955 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3956 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3957 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
3960 let AddedComplexity = 5 in
3961 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3962 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3963 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3964 Requires<[IsARM, HasV6]>,
3967 let AddedComplexity = 5 in
3968 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3969 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3970 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3971 Requires<[IsARM, HasV6]>,
3974 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3975 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3978 def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
3979 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
3980 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3981 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
3982 (and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
3984 Requires<[IsARM, HasV6]>,
3985 Sched<[WriteALUsi, ReadALU]>;
3987 // Alternate cases for PKHBT where identities eliminate some nodes.
3988 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
3989 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
3990 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
3991 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
3993 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3994 // will match the pattern below.
3995 def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
3996 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
3997 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3998 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
3999 (and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
4001 Requires<[IsARM, HasV6]>,
4002 Sched<[WriteALUsi, ReadALU]>;
4004 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
4005 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
4006 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4007 (srl GPRnopc:$src2, imm16_31:$sh)),
4008 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm16_31:$sh)>;
4009 def : ARMV6Pat<(or (and GPRnopc:$src1, 0xFFFF0000),
4010 (and (srl GPRnopc:$src2, imm1_15:$sh), 0xFFFF)),
4011 (PKHTB GPRnopc:$src1, GPRnopc:$src2, imm1_15:$sh)>;
4013 //===----------------------------------------------------------------------===//
4014 // Comparison Instructions...
4017 defm CMP : AI1_cmp_irs<0b1010, "cmp",
4018 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4019 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
4021 // ARMcmpZ can re-use the above instruction definitions.
4022 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
4023 (CMPri GPR:$src, so_imm:$imm)>;
4024 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
4025 (CMPrr GPR:$src, GPR:$rhs)>;
4026 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
4027 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
4028 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
4029 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
4031 // CMN register-integer
4032 let isCompare = 1, Defs = [CPSR] in {
4033 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
4034 "cmn", "\t$Rn, $imm",
4035 [(ARMcmn GPR:$Rn, so_imm:$imm)]>,
4036 Sched<[WriteCMP, ReadALU]> {
4041 let Inst{19-16} = Rn;
4042 let Inst{15-12} = 0b0000;
4043 let Inst{11-0} = imm;
4045 let Unpredictable{15-12} = 0b1111;
4048 // CMN register-register/shift
4049 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4050 "cmn", "\t$Rn, $Rm",
4051 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4052 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4055 let isCommutable = 1;
4058 let Inst{19-16} = Rn;
4059 let Inst{15-12} = 0b0000;
4060 let Inst{11-4} = 0b00000000;
4063 let Unpredictable{15-12} = 0b1111;
4066 def CMNzrsi : AI1<0b1011, (outs),
4067 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4068 "cmn", "\t$Rn, $shift",
4069 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4070 GPR:$Rn, so_reg_imm:$shift)]>,
4071 Sched<[WriteCMPsi, ReadALU]> {
4076 let Inst{19-16} = Rn;
4077 let Inst{15-12} = 0b0000;
4078 let Inst{11-5} = shift{11-5};
4080 let Inst{3-0} = shift{3-0};
4082 let Unpredictable{15-12} = 0b1111;
4085 def CMNzrsr : AI1<0b1011, (outs),
4086 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4087 "cmn", "\t$Rn, $shift",
4088 [(BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>
4089 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4090 Sched<[WriteCMPsr, ReadALU]> {
4095 let Inst{19-16} = Rn;
4096 let Inst{15-12} = 0b0000;
4097 let Inst{11-8} = shift{11-8};
4099 let Inst{6-5} = shift{6-5};
4101 let Inst{3-0} = shift{3-0};
4103 let Unpredictable{15-12} = 0b1111;
4108 def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4109 (CMNri GPR:$src, so_imm_neg:$imm)>;
4111 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4112 (CMNri GPR:$src, so_imm_neg:$imm)>;
4114 // Note that TST/TEQ don't set all the same flags that CMP does!
4115 defm TST : AI1_cmp_irs<0b1000, "tst",
4116 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4117 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4118 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4119 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4120 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4122 // Pseudo i64 compares for some floating point compares.
4123 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4125 def BCCi64 : PseudoInst<(outs),
4126 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4128 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
4130 def BCCZi64 : PseudoInst<(outs),
4131 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4132 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
4133 } // usesCustomInserter
4136 // Conditional moves
4137 // FIXME: should be able to write a pattern for ARMcmov, but can't use
4138 // a two-value operand where a dag node expects two operands. :(
4139 let neverHasSideEffects = 1 in {
4141 let isCommutable = 1, isSelect = 1 in
4142 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4144 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4145 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4147 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4148 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
4150 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4151 imm:$cc, CCR:$ccr))*/]>,
4152 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4153 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4154 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4156 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4157 imm:$cc, CCR:$ccr))*/]>,
4158 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4161 let isMoveImm = 1 in
4162 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4163 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4166 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
4169 let isMoveImm = 1 in
4170 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4171 (ins GPR:$false, so_imm:$imm, pred:$p),
4173 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4174 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4176 // Two instruction predicate mov immediate.
4177 let isMoveImm = 1 in
4178 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4179 (ins GPR:$false, i32imm:$src, pred:$p),
4180 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4182 let isMoveImm = 1 in
4183 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4184 (ins GPR:$false, so_imm:$imm, pred:$p),
4186 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4187 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
4189 } // neverHasSideEffects
4192 //===----------------------------------------------------------------------===//
4193 // Atomic operations intrinsics
4196 def MemBarrierOptOperand : AsmOperandClass {
4197 let Name = "MemBarrierOpt";
4198 let ParserMethod = "parseMemBarrierOptOperand";
4200 def memb_opt : Operand<i32> {
4201 let PrintMethod = "printMemBOption";
4202 let ParserMatchClass = MemBarrierOptOperand;
4203 let DecoderMethod = "DecodeMemBarrierOption";
4206 // memory barriers protect the atomic sequences
4207 let hasSideEffects = 1 in {
4208 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4209 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4210 Requires<[IsARM, HasDB]> {
4212 let Inst{31-4} = 0xf57ff05;
4213 let Inst{3-0} = opt;
4217 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4218 "dsb", "\t$opt", []>,
4219 Requires<[IsARM, HasDB]> {
4221 let Inst{31-4} = 0xf57ff04;
4222 let Inst{3-0} = opt;
4225 // ISB has only full system option
4226 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4227 "isb", "\t$opt", []>,
4228 Requires<[IsARM, HasDB]> {
4230 let Inst{31-4} = 0xf57ff06;
4231 let Inst{3-0} = opt;
4234 // Pseudo instruction that combines movs + predicated rsbmi
4235 // to implement integer ABS
4236 let usesCustomInserter = 1, Defs = [CPSR] in
4237 def ABS : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$src), 8, NoItinerary, []>;
4239 let usesCustomInserter = 1 in {
4240 let Defs = [CPSR] in {
4241 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4242 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4243 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4244 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4245 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4246 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4247 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4248 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4249 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4250 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4251 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4252 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4253 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4254 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4255 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4256 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4257 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4258 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4259 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4260 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4261 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4262 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4263 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4264 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4265 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4266 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4267 [(set GPR:$dst, (atomic_load_umin_8 GPR:$ptr, GPR:$val))]>;
4268 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4269 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4270 [(set GPR:$dst, (atomic_load_umax_8 GPR:$ptr, GPR:$val))]>;
4271 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4272 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4273 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4274 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4275 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4276 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4277 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4278 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4279 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4280 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4281 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4282 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4283 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4284 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4285 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4286 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4287 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4288 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4289 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4290 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4291 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4292 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4293 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4294 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4295 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4296 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4297 [(set GPR:$dst, (atomic_load_umin_16 GPR:$ptr, GPR:$val))]>;
4298 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4299 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4300 [(set GPR:$dst, (atomic_load_umax_16 GPR:$ptr, GPR:$val))]>;
4301 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4302 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4303 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4304 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4305 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4306 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4307 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4308 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4309 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4310 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4311 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4312 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4313 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4314 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4315 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4316 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4317 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4318 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4319 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4320 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4321 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4322 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4323 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4324 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4325 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4326 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4327 [(set GPR:$dst, (atomic_load_umin_32 GPR:$ptr, GPR:$val))]>;
4328 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4329 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4330 [(set GPR:$dst, (atomic_load_umax_32 GPR:$ptr, GPR:$val))]>;
4332 def ATOMIC_SWAP_I8 : PseudoInst<
4333 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4334 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4335 def ATOMIC_SWAP_I16 : PseudoInst<
4336 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4337 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4338 def ATOMIC_SWAP_I32 : PseudoInst<
4339 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4340 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4342 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4343 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4344 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4345 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4346 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4347 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4348 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4349 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4350 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4354 let usesCustomInserter = 1 in {
4355 def COPY_STRUCT_BYVAL_I32 : PseudoInst<
4356 (outs), (ins GPR:$dst, GPR:$src, i32imm:$size, i32imm:$alignment),
4358 [(ARMcopystructbyval GPR:$dst, GPR:$src, imm:$size, imm:$alignment)]>;
4361 let mayLoad = 1 in {
4362 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4364 "ldrexb", "\t$Rt, $addr", []>;
4365 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4366 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4367 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4368 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4369 let hasExtraDefRegAllocReq = 1 in
4370 def LDREXD: AIldrex<0b01, (outs GPRPairOp:$Rt),(ins addr_offset_none:$addr),
4371 NoItinerary, "ldrexd", "\t$Rt, $addr", []> {
4372 let DecoderMethod = "DecodeDoubleRegLoad";
4376 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4377 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4378 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4379 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4380 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4381 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4382 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4383 let hasExtraSrcRegAllocReq = 1 in
4384 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4385 (ins GPRPairOp:$Rt, addr_offset_none:$addr),
4386 NoItinerary, "strexd", "\t$Rd, $Rt, $addr", []> {
4387 let DecoderMethod = "DecodeDoubleRegStore";
4392 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4393 Requires<[IsARM, HasV7]> {
4394 let Inst{31-0} = 0b11110101011111111111000000011111;
4397 // SWP/SWPB are deprecated in V6/V7.
4398 let mayLoad = 1, mayStore = 1 in {
4399 def SWP : AIswp<0, (outs GPRnopc:$Rt),
4400 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swp", []>;
4401 def SWPB: AIswp<1, (outs GPRnopc:$Rt),
4402 (ins GPRnopc:$Rt2, addr_offset_none:$addr), "swpb", []>;
4405 //===----------------------------------------------------------------------===//
4406 // Coprocessor Instructions.
4409 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4410 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4411 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4412 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4413 imm:$CRm, imm:$opc2)]> {
4421 let Inst{3-0} = CRm;
4423 let Inst{7-5} = opc2;
4424 let Inst{11-8} = cop;
4425 let Inst{15-12} = CRd;
4426 let Inst{19-16} = CRn;
4427 let Inst{23-20} = opc1;
4430 def CDP2 : ABXI<0b1110, (outs), (ins pf_imm:$cop, imm0_15:$opc1,
4431 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4432 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4433 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4434 imm:$CRm, imm:$opc2)]> {
4435 let Inst{31-28} = 0b1111;
4443 let Inst{3-0} = CRm;
4445 let Inst{7-5} = opc2;
4446 let Inst{11-8} = cop;
4447 let Inst{15-12} = CRd;
4448 let Inst{19-16} = CRn;
4449 let Inst{23-20} = opc1;
4452 class ACI<dag oops, dag iops, string opc, string asm,
4453 IndexMode im = IndexModeNone>
4454 : I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4456 let Inst{27-25} = 0b110;
4458 class ACInoP<dag oops, dag iops, string opc, string asm,
4459 IndexMode im = IndexModeNone>
4460 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4462 let Inst{31-28} = 0b1111;
4463 let Inst{27-25} = 0b110;
4465 multiclass LdStCop<bit load, bit Dbit, string asm> {
4466 def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4467 asm, "\t$cop, $CRd, $addr"> {
4471 let Inst{24} = 1; // P = 1
4472 let Inst{23} = addr{8};
4473 let Inst{22} = Dbit;
4474 let Inst{21} = 0; // W = 0
4475 let Inst{20} = load;
4476 let Inst{19-16} = addr{12-9};
4477 let Inst{15-12} = CRd;
4478 let Inst{11-8} = cop;
4479 let Inst{7-0} = addr{7-0};
4480 let DecoderMethod = "DecodeCopMemInstruction";
4482 def _PRE : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4483 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4487 let Inst{24} = 1; // P = 1
4488 let Inst{23} = addr{8};
4489 let Inst{22} = Dbit;
4490 let Inst{21} = 1; // W = 1
4491 let Inst{20} = load;
4492 let Inst{19-16} = addr{12-9};
4493 let Inst{15-12} = CRd;
4494 let Inst{11-8} = cop;
4495 let Inst{7-0} = addr{7-0};
4496 let DecoderMethod = "DecodeCopMemInstruction";
4498 def _POST: ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4499 postidx_imm8s4:$offset),
4500 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4505 let Inst{24} = 0; // P = 0
4506 let Inst{23} = offset{8};
4507 let Inst{22} = Dbit;
4508 let Inst{21} = 1; // W = 1
4509 let Inst{20} = load;
4510 let Inst{19-16} = addr;
4511 let Inst{15-12} = CRd;
4512 let Inst{11-8} = cop;
4513 let Inst{7-0} = offset{7-0};
4514 let DecoderMethod = "DecodeCopMemInstruction";
4516 def _OPTION : ACI<(outs),
4517 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4518 coproc_option_imm:$option),
4519 asm, "\t$cop, $CRd, $addr, $option"> {
4524 let Inst{24} = 0; // P = 0
4525 let Inst{23} = 1; // U = 1
4526 let Inst{22} = Dbit;
4527 let Inst{21} = 0; // W = 0
4528 let Inst{20} = load;
4529 let Inst{19-16} = addr;
4530 let Inst{15-12} = CRd;
4531 let Inst{11-8} = cop;
4532 let Inst{7-0} = option;
4533 let DecoderMethod = "DecodeCopMemInstruction";
4536 multiclass LdSt2Cop<bit load, bit Dbit, string asm> {
4537 def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
4538 asm, "\t$cop, $CRd, $addr"> {
4542 let Inst{24} = 1; // P = 1
4543 let Inst{23} = addr{8};
4544 let Inst{22} = Dbit;
4545 let Inst{21} = 0; // W = 0
4546 let Inst{20} = load;
4547 let Inst{19-16} = addr{12-9};
4548 let Inst{15-12} = CRd;
4549 let Inst{11-8} = cop;
4550 let Inst{7-0} = addr{7-0};
4551 let DecoderMethod = "DecodeCopMemInstruction";
4553 def _PRE : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5_pre:$addr),
4554 asm, "\t$cop, $CRd, $addr!", IndexModePre> {
4558 let Inst{24} = 1; // P = 1
4559 let Inst{23} = addr{8};
4560 let Inst{22} = Dbit;
4561 let Inst{21} = 1; // W = 1
4562 let Inst{20} = load;
4563 let Inst{19-16} = addr{12-9};
4564 let Inst{15-12} = CRd;
4565 let Inst{11-8} = cop;
4566 let Inst{7-0} = addr{7-0};
4567 let DecoderMethod = "DecodeCopMemInstruction";
4569 def _POST: ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4570 postidx_imm8s4:$offset),
4571 asm, "\t$cop, $CRd, $addr, $offset", IndexModePost> {
4576 let Inst{24} = 0; // P = 0
4577 let Inst{23} = offset{8};
4578 let Inst{22} = Dbit;
4579 let Inst{21} = 1; // W = 1
4580 let Inst{20} = load;
4581 let Inst{19-16} = addr;
4582 let Inst{15-12} = CRd;
4583 let Inst{11-8} = cop;
4584 let Inst{7-0} = offset{7-0};
4585 let DecoderMethod = "DecodeCopMemInstruction";
4587 def _OPTION : ACInoP<(outs),
4588 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr,
4589 coproc_option_imm:$option),
4590 asm, "\t$cop, $CRd, $addr, $option"> {
4595 let Inst{24} = 0; // P = 0
4596 let Inst{23} = 1; // U = 1
4597 let Inst{22} = Dbit;
4598 let Inst{21} = 0; // W = 0
4599 let Inst{20} = load;
4600 let Inst{19-16} = addr;
4601 let Inst{15-12} = CRd;
4602 let Inst{11-8} = cop;
4603 let Inst{7-0} = option;
4604 let DecoderMethod = "DecodeCopMemInstruction";
4608 defm LDC : LdStCop <1, 0, "ldc">;
4609 defm LDCL : LdStCop <1, 1, "ldcl">;
4610 defm STC : LdStCop <0, 0, "stc">;
4611 defm STCL : LdStCop <0, 1, "stcl">;
4612 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4613 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4614 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4615 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4617 //===----------------------------------------------------------------------===//
4618 // Move between coprocessor and ARM core register.
4621 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4623 : ABI<0b1110, oops, iops, NoItinerary, opc,
4624 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4625 let Inst{20} = direction;
4635 let Inst{15-12} = Rt;
4636 let Inst{11-8} = cop;
4637 let Inst{23-21} = opc1;
4638 let Inst{7-5} = opc2;
4639 let Inst{3-0} = CRm;
4640 let Inst{19-16} = CRn;
4643 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4645 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4646 c_imm:$CRm, imm0_7:$opc2),
4647 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4648 imm:$CRm, imm:$opc2)]>;
4649 def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4650 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4651 c_imm:$CRm, 0, pred:$p)>;
4652 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4653 (outs GPRwithAPSR:$Rt),
4654 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4656 def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
4657 (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4658 c_imm:$CRm, 0, pred:$p)>;
4660 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4661 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4663 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4665 : ABXI<0b1110, oops, iops, NoItinerary,
4666 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4667 let Inst{31-24} = 0b11111110;
4668 let Inst{20} = direction;
4678 let Inst{15-12} = Rt;
4679 let Inst{11-8} = cop;
4680 let Inst{23-21} = opc1;
4681 let Inst{7-5} = opc2;
4682 let Inst{3-0} = CRm;
4683 let Inst{19-16} = CRn;
4686 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4688 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4689 c_imm:$CRm, imm0_7:$opc2),
4690 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4691 imm:$CRm, imm:$opc2)]>;
4692 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
4693 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4695 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4696 (outs GPRwithAPSR:$Rt),
4697 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4699 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
4700 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
4703 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4704 imm:$CRm, imm:$opc2),
4705 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4707 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4708 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4709 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
4710 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4711 let Inst{23-21} = 0b010;
4712 let Inst{20} = direction;
4720 let Inst{15-12} = Rt;
4721 let Inst{19-16} = Rt2;
4722 let Inst{11-8} = cop;
4723 let Inst{7-4} = opc1;
4724 let Inst{3-0} = CRm;
4727 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4728 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt,
4729 GPRnopc:$Rt2, imm:$CRm)]>;
4730 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4732 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4733 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4734 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
4735 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4736 let Inst{31-28} = 0b1111;
4737 let Inst{23-21} = 0b010;
4738 let Inst{20} = direction;
4746 let Inst{15-12} = Rt;
4747 let Inst{19-16} = Rt2;
4748 let Inst{11-8} = cop;
4749 let Inst{7-4} = opc1;
4750 let Inst{3-0} = CRm;
4752 let DecoderMethod = "DecodeMRRC2";
4755 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4756 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt,
4757 GPRnopc:$Rt2, imm:$CRm)]>;
4758 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4760 //===----------------------------------------------------------------------===//
4761 // Move between special register and ARM core register
4764 // Move to ARM core register from Special Register
4765 def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4766 "mrs", "\t$Rd, apsr", []> {
4768 let Inst{23-16} = 0b00001111;
4769 let Unpredictable{19-17} = 0b111;
4771 let Inst{15-12} = Rd;
4773 let Inst{11-0} = 0b000000000000;
4774 let Unpredictable{11-0} = 0b110100001111;
4777 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>,
4780 // The MRSsys instruction is the MRS instruction from the ARM ARM,
4781 // section B9.3.9, with the R bit set to 1.
4782 def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
4783 "mrs", "\t$Rd, spsr", []> {
4785 let Inst{23-16} = 0b01001111;
4786 let Unpredictable{19-16} = 0b1111;
4788 let Inst{15-12} = Rd;
4790 let Inst{11-0} = 0b000000000000;
4791 let Unpredictable{11-0} = 0b110100001111;
4794 // Move from ARM core register to Special Register
4796 // No need to have both system and application versions, the encodings are the
4797 // same and the assembly parser has no way to distinguish between them. The mask
4798 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4799 // the mask with the fields to be accessed in the special register.
4800 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4801 "msr", "\t$mask, $Rn", []> {
4806 let Inst{22} = mask{4}; // R bit
4807 let Inst{21-20} = 0b10;
4808 let Inst{19-16} = mask{3-0};
4809 let Inst{15-12} = 0b1111;
4810 let Inst{11-4} = 0b00000000;
4814 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4815 "msr", "\t$mask, $a", []> {
4820 let Inst{22} = mask{4}; // R bit
4821 let Inst{21-20} = 0b10;
4822 let Inst{19-16} = mask{3-0};
4823 let Inst{15-12} = 0b1111;
4827 //===----------------------------------------------------------------------===//
4831 // __aeabi_read_tp preserves the registers r1-r3.
4832 // This is a pseudo inst so that we can get the encoding right,
4833 // complete with fixup for the aeabi_read_tp function.
4835 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4836 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4837 [(set R0, ARMthread_pointer)]>;
4840 //===----------------------------------------------------------------------===//
4841 // SJLJ Exception handling intrinsics
4842 // eh_sjlj_setjmp() is an instruction sequence to store the return
4843 // address and save #0 in R0 for the non-longjmp case.
4844 // Since by its nature we may be coming from some other function to get
4845 // here, and we're using the stack frame for the containing function to
4846 // save/restore registers, we can't keep anything live in regs across
4847 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4848 // when we get here from a longjmp(). We force everything out of registers
4849 // except for our own input by listing the relevant registers in Defs. By
4850 // doing so, we also cause the prologue/epilogue code to actively preserve
4851 // all of the callee-saved resgisters, which is exactly what we want.
4852 // A constant value is passed in $val, and we use the location as a scratch.
4854 // These are pseudo-instructions and are lowered to individual MC-insts, so
4855 // no encoding information is necessary.
4857 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4858 Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15 ],
4859 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4860 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4862 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4863 Requires<[IsARM, HasVFP2]>;
4867 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4868 hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
4869 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4871 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4872 Requires<[IsARM, NoVFP]>;
4875 // FIXME: Non-IOS version(s)
4876 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4877 Defs = [ R7, LR, SP ] in {
4878 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4880 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4881 Requires<[IsARM, IsIOS]>;
4884 // eh.sjlj.dispatchsetup pseudo-instruction.
4885 // This pseudo is used for both ARM and Thumb. Any differences are handled when
4886 // the pseudo is expanded (which happens before any passes that need the
4887 // instruction size).
4888 let isBarrier = 1 in
4889 def Int_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
4892 //===----------------------------------------------------------------------===//
4893 // Non-Instruction Patterns
4896 // ARMv4 indirect branch using (MOVr PC, dst)
4897 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4898 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4899 4, IIC_Br, [(brind GPR:$dst)],
4900 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4901 Requires<[IsARM, NoV4T]>;
4903 // Large immediate handling.
4905 // 32-bit immediate using two piece so_imms or movw + movt.
4906 // This is a single pseudo instruction, the benefit is that it can be remat'd
4907 // as a single unit instead of having to handle reg inputs.
4908 // FIXME: Remove this when we can do generalized remat.
4909 let isReMaterializable = 1, isMoveImm = 1 in
4910 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4911 [(set GPR:$dst, (arm_i32imm:$src))]>,
4914 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4915 // It also makes it possible to rematerialize the instructions.
4916 // FIXME: Remove this when we can do generalized remat and when machine licm
4917 // can properly the instructions.
4918 let isReMaterializable = 1 in {
4919 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4921 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4922 Requires<[IsARM, UseMovt]>;
4924 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4926 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4927 Requires<[IsARM, UseMovt]>;
4929 let AddedComplexity = 10 in
4930 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4932 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4933 Requires<[IsARM, UseMovt]>;
4934 } // isReMaterializable
4936 // ConstantPool, GlobalAddress, and JumpTable
4937 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4938 Requires<[IsARM, DontUseMovt]>;
4939 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4940 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4941 Requires<[IsARM, UseMovt]>;
4942 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4943 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4945 // TODO: add,sub,and, 3-instr forms?
4947 // Tail calls. These patterns also apply to Thumb mode.
4948 def : Pat<(ARMtcret tcGPR:$dst), (TCRETURNri tcGPR:$dst)>;
4949 def : Pat<(ARMtcret (i32 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4950 def : Pat<(ARMtcret (i32 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4953 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>;
4954 def : ARMPat<(ARMcall_nolink texternalsym:$func),
4955 (BMOVPCB_CALL texternalsym:$func)>;
4957 // zextload i1 -> zextload i8
4958 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4959 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4961 // extload -> zextload
4962 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4963 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4964 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4965 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4967 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4969 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4970 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4973 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4974 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4975 (SMULBB GPR:$a, GPR:$b)>;
4976 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4977 (SMULBB GPR:$a, GPR:$b)>;
4978 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4979 (sra GPR:$b, (i32 16))),
4980 (SMULBT GPR:$a, GPR:$b)>;
4981 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4982 (SMULBT GPR:$a, GPR:$b)>;
4983 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4984 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4985 (SMULTB GPR:$a, GPR:$b)>;
4986 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4987 (SMULTB GPR:$a, GPR:$b)>;
4988 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4990 (SMULWB GPR:$a, GPR:$b)>;
4991 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4992 (SMULWB GPR:$a, GPR:$b)>;
4994 def : ARMV5MOPat<(add GPR:$acc,
4995 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4996 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4997 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4998 def : ARMV5MOPat<(add GPR:$acc,
4999 (mul sext_16_node:$a, sext_16_node:$b)),
5000 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
5001 def : ARMV5MOPat<(add GPR:$acc,
5002 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
5003 (sra GPR:$b, (i32 16)))),
5004 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5005 def : ARMV5MOPat<(add GPR:$acc,
5006 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5007 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
5008 def : ARMV5MOPat<(add GPR:$acc,
5009 (mul (sra GPR:$a, (i32 16)),
5010 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
5011 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5012 def : ARMV5MOPat<(add GPR:$acc,
5013 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5014 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
5015 def : ARMV5MOPat<(add GPR:$acc,
5016 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
5018 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5019 def : ARMV5MOPat<(add GPR:$acc,
5020 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
5021 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
5024 // Pre-v7 uses MCR for synchronization barriers.
5025 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
5026 Requires<[IsARM, HasV6]>;
5028 // SXT/UXT with no rotate
5029 let AddedComplexity = 16 in {
5030 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
5031 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
5032 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
5033 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
5034 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
5035 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
5036 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
5039 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
5040 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
5042 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
5043 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
5044 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
5045 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
5047 // Atomic load/store patterns
5048 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
5049 (LDRBrs ldst_so_reg:$src)>;
5050 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
5051 (LDRBi12 addrmode_imm12:$src)>;
5052 def : ARMPat<(atomic_load_16 addrmode3:$src),
5053 (LDRH addrmode3:$src)>;
5054 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
5055 (LDRrs ldst_so_reg:$src)>;
5056 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
5057 (LDRi12 addrmode_imm12:$src)>;
5058 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
5059 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
5060 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
5061 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
5062 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
5063 (STRH GPR:$val, addrmode3:$ptr)>;
5064 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
5065 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
5066 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
5067 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
5070 //===----------------------------------------------------------------------===//
5074 include "ARMInstrThumb.td"
5076 //===----------------------------------------------------------------------===//
5080 include "ARMInstrThumb2.td"
5082 //===----------------------------------------------------------------------===//
5083 // Floating Point Support
5086 include "ARMInstrVFP.td"
5088 //===----------------------------------------------------------------------===//
5089 // Advanced SIMD (NEON) Support
5092 include "ARMInstrNEON.td"
5094 //===----------------------------------------------------------------------===//
5095 // Assembler aliases
5099 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
5100 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
5101 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
5103 // System instructions
5104 def : MnemonicAlias<"swi", "svc">;
5106 // Load / Store Multiple
5107 def : MnemonicAlias<"ldmfd", "ldm">;
5108 def : MnemonicAlias<"ldmia", "ldm">;
5109 def : MnemonicAlias<"ldmea", "ldmdb">;
5110 def : MnemonicAlias<"stmfd", "stmdb">;
5111 def : MnemonicAlias<"stmia", "stm">;
5112 def : MnemonicAlias<"stmea", "stm">;
5114 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
5115 // shift amount is zero (i.e., unspecified).
5116 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
5117 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5118 Requires<[IsARM, HasV6]>;
5119 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
5120 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p)>,
5121 Requires<[IsARM, HasV6]>;
5123 // PUSH/POP aliases for STM/LDM
5124 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
5125 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
5127 // SSAT/USAT optional shift operand.
5128 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5129 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5130 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5131 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
5134 // Extend instruction optional rotate operand.
5135 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5136 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5137 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5138 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5139 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5140 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5141 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
5142 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5143 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
5144 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5145 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
5146 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5148 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5149 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5150 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5151 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5152 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5153 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
5154 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
5155 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5156 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
5157 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5158 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
5159 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
5163 def : MnemonicAlias<"rfefa", "rfeda">;
5164 def : MnemonicAlias<"rfeea", "rfedb">;
5165 def : MnemonicAlias<"rfefd", "rfeia">;
5166 def : MnemonicAlias<"rfeed", "rfeib">;
5167 def : MnemonicAlias<"rfe", "rfeia">;
5170 def : MnemonicAlias<"srsfa", "srsda">;
5171 def : MnemonicAlias<"srsea", "srsdb">;
5172 def : MnemonicAlias<"srsfd", "srsia">;
5173 def : MnemonicAlias<"srsed", "srsib">;
5174 def : MnemonicAlias<"srs", "srsia">;
5177 def : MnemonicAlias<"qsubaddx", "qsax">;
5179 def : MnemonicAlias<"saddsubx", "sasx">;
5180 // SHASX == SHADDSUBX
5181 def : MnemonicAlias<"shaddsubx", "shasx">;
5182 // SHSAX == SHSUBADDX
5183 def : MnemonicAlias<"shsubaddx", "shsax">;
5185 def : MnemonicAlias<"ssubaddx", "ssax">;
5187 def : MnemonicAlias<"uaddsubx", "uasx">;
5188 // UHASX == UHADDSUBX
5189 def : MnemonicAlias<"uhaddsubx", "uhasx">;
5190 // UHSAX == UHSUBADDX
5191 def : MnemonicAlias<"uhsubaddx", "uhsax">;
5192 // UQASX == UQADDSUBX
5193 def : MnemonicAlias<"uqaddsubx", "uqasx">;
5194 // UQSAX == UQSUBADDX
5195 def : MnemonicAlias<"uqsubaddx", "uqsax">;
5197 def : MnemonicAlias<"usubaddx", "usax">;
5199 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
5201 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5202 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5203 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5204 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5205 // Same for AND <--> BIC
5206 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5207 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5208 pred:$p, cc_out:$s)>;
5209 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5210 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5211 pred:$p, cc_out:$s)>;
5212 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5213 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5214 pred:$p, cc_out:$s)>;
5215 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5216 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5217 pred:$p, cc_out:$s)>;
5219 // Likewise, "add Rd, so_imm_neg" -> sub
5220 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5221 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5222 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5223 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5224 // Same for CMP <--> CMN via so_imm_neg
5225 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5226 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5227 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5228 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5230 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
5231 // LSR, ROR, and RRX instructions.
5232 // FIXME: We need C++ parser hooks to map the alias to the MOV
5233 // encoding. It seems we should be able to do that sort of thing
5234 // in tblgen, but it could get ugly.
5235 let TwoOperandAliasConstraint = "$Rm = $Rd" in {
5236 def ASRi : ARMAsmPseudo<"asr${s}${p} $Rd, $Rm, $imm",
5237 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5239 def LSRi : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rm, $imm",
5240 (ins GPR:$Rd, GPR:$Rm, imm0_32:$imm, pred:$p,
5242 def LSLi : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rm, $imm",
5243 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5245 def RORi : ARMAsmPseudo<"ror${s}${p} $Rd, $Rm, $imm",
5246 (ins GPR:$Rd, GPR:$Rm, imm0_31:$imm, pred:$p,
5249 def RRXi : ARMAsmPseudo<"rrx${s}${p} $Rd, $Rm",
5250 (ins GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
5251 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
5252 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
5253 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5255 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
5256 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5258 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
5259 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5261 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
5262 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
5266 // "neg" is and alias for "rsb rd, rn, #0"
5267 def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
5268 (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
5270 // Pre-v6, 'mov r0, r0' was used as a NOP encoding.
5271 def : InstAlias<"nop${p}", (MOVr R0, R0, pred:$p, zero_reg)>,
5272 Requires<[IsARM, NoV6]>;
5274 // UMULL/SMULL are available on all arches, but the instruction definitions
5275 // need difference constraints pre-v6. Use these aliases for the assembly
5276 // parsing on pre-v6.
5277 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5278 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5279 Requires<[IsARM, NoV6]>;
5280 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
5281 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
5282 Requires<[IsARM, NoV6]>;
5284 // 'it' blocks in ARM mode just validate the predicates. The IT itself
5286 def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;