1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM specific DAG Nodes.
19 def SDT_ARMCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
20 def SDT_ARMCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>;
22 def SDT_ARMSaveCallPC : SDTypeProfile<0, 1, []>;
24 def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
26 def SDT_ARMCMov : SDTypeProfile<1, 3,
27 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
30 def SDT_ARMBrcond : SDTypeProfile<0, 2,
31 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
33 def SDT_ARMBrJT : SDTypeProfile<0, 3,
34 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
37 def SDT_ARMBr2JT : SDTypeProfile<0, 4,
38 [SDTCisPtrTy<0>, SDTCisVT<1, i32>,
39 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
41 def SDT_ARMBCC_i64 : SDTypeProfile<0, 6,
43 SDTCisVT<1, i32>, SDTCisVT<2, i32>,
44 SDTCisVT<3, i32>, SDTCisVT<4, i32>,
45 SDTCisVT<5, OtherVT>]>;
47 def SDT_ARMAnd : SDTypeProfile<1, 2,
48 [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
51 def SDT_ARMCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
53 def SDT_ARMPICAdd : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>,
54 SDTCisPtrTy<1>, SDTCisVT<2, i32>]>;
56 def SDT_ARMThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
57 def SDT_ARMEH_SJLJ_Setjmp : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisPtrTy<1>,
59 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
61 def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisInt<0>]>;
63 def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
65 def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
68 def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
70 def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
71 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
72 def SDTARMatomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>,
73 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>;
75 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
78 SDTCisInt<0>, SDTCisVT<1, i32>]>;
80 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
81 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
88 def ARMWrapper : SDNode<"ARMISD::Wrapper", SDTIntUnaryOp>;
89 def ARMWrapperDYN : SDNode<"ARMISD::WrapperDYN", SDTIntUnaryOp>;
90 def ARMWrapperPIC : SDNode<"ARMISD::WrapperPIC", SDTIntUnaryOp>;
91 def ARMWrapperJT : SDNode<"ARMISD::WrapperJT", SDTIntBinOp>;
93 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
94 [SDNPHasChain, SDNPOutGlue]>;
95 def ARMcallseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeqEnd,
96 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
98 def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
99 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
101 def ARMcall_pred : SDNode<"ARMISD::CALL_PRED", SDT_ARMcall,
102 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
104 def ARMcall_nolink : SDNode<"ARMISD::CALL_NOLINK", SDT_ARMcall,
105 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
108 def ARMretflag : SDNode<"ARMISD::RET_FLAG", SDTNone,
109 [SDNPHasChain, SDNPOptInGlue]>;
111 def ARMcmov : SDNode<"ARMISD::CMOV", SDT_ARMCMov,
114 def ARMbrcond : SDNode<"ARMISD::BRCOND", SDT_ARMBrcond,
115 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>;
117 def ARMbrjt : SDNode<"ARMISD::BR_JT", SDT_ARMBrJT,
119 def ARMbr2jt : SDNode<"ARMISD::BR2_JT", SDT_ARMBr2JT,
122 def ARMBcci64 : SDNode<"ARMISD::BCC_i64", SDT_ARMBCC_i64,
125 def ARMcmp : SDNode<"ARMISD::CMP", SDT_ARMCmp,
128 def ARMcmpZ : SDNode<"ARMISD::CMPZ", SDT_ARMCmp,
129 [SDNPOutGlue, SDNPCommutative]>;
131 def ARMpic_add : SDNode<"ARMISD::PIC_ADD", SDT_ARMPICAdd>;
133 def ARMsrl_flag : SDNode<"ARMISD::SRL_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
134 def ARMsra_flag : SDNode<"ARMISD::SRA_FLAG", SDTIntUnaryOp, [SDNPOutGlue]>;
135 def ARMrrx : SDNode<"ARMISD::RRX" , SDTIntUnaryOp, [SDNPInGlue ]>;
137 def ARMaddc : SDNode<"ARMISD::ADDC", SDTBinaryArithWithFlags,
139 def ARMsubc : SDNode<"ARMISD::SUBC", SDTBinaryArithWithFlags>;
140 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
141 def ARMsube : SDNode<"ARMISD::SUBE", SDTBinaryArithWithFlagsInOut>;
143 def ARMthread_pointer: SDNode<"ARMISD::THREAD_POINTER", SDT_ARMThreadPointer>;
144 def ARMeh_sjlj_setjmp: SDNode<"ARMISD::EH_SJLJ_SETJMP",
145 SDT_ARMEH_SJLJ_Setjmp, [SDNPHasChain]>;
146 def ARMeh_sjlj_longjmp: SDNode<"ARMISD::EH_SJLJ_LONGJMP",
147 SDT_ARMEH_SJLJ_Longjmp, [SDNPHasChain]>;
148 def ARMeh_sjlj_dispatchsetup: SDNode<"ARMISD::EH_SJLJ_DISPATCHSETUP",
149 SDT_ARMEH_SJLJ_DispatchSetup, [SDNPHasChain]>;
152 def ARMMemBarrier : SDNode<"ARMISD::MEMBARRIER", SDT_ARMMEMBARRIER,
154 def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
156 def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
157 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
159 def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
161 def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
162 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
165 def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
167 def ARMAtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTARMatomicBinary,
168 [SDNPHasChain, SDNPMayStore,
169 SDNPMayLoad, SDNPMemOperand]>;
170 def ARMAtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTARMatomicBinary,
171 [SDNPHasChain, SDNPMayStore,
172 SDNPMayLoad, SDNPMemOperand]>;
173 def ARMAtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTARMatomicBinary,
174 [SDNPHasChain, SDNPMayStore,
175 SDNPMayLoad, SDNPMemOperand]>;
176 def ARMAtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTARMatomicBinary,
177 [SDNPHasChain, SDNPMayStore,
178 SDNPMayLoad, SDNPMemOperand]>;
179 def ARMAtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTARMatomicBinary,
180 [SDNPHasChain, SDNPMayStore,
181 SDNPMayLoad, SDNPMemOperand]>;
182 def ARMAtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTARMatomicBinary,
183 [SDNPHasChain, SDNPMayStore,
184 SDNPMayLoad, SDNPMemOperand]>;
185 def ARMAtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTARMatomicBinary,
186 [SDNPHasChain, SDNPMayStore,
187 SDNPMayLoad, SDNPMemOperand]>;
189 //===----------------------------------------------------------------------===//
190 // ARM Instruction Predicate Definitions.
192 def HasV4T : Predicate<"Subtarget->hasV4TOps()">,
193 AssemblerPredicate<"HasV4TOps">;
194 def NoV4T : Predicate<"!Subtarget->hasV4TOps()">;
195 def HasV5T : Predicate<"Subtarget->hasV5TOps()">;
196 def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">,
197 AssemblerPredicate<"HasV5TEOps">;
198 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,
199 AssemblerPredicate<"HasV6Ops">;
200 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
201 def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">,
202 AssemblerPredicate<"HasV6T2Ops">;
203 def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">;
204 def HasV7 : Predicate<"Subtarget->hasV7Ops()">,
205 AssemblerPredicate<"HasV7Ops">;
206 def NoVFP : Predicate<"!Subtarget->hasVFP2()">;
207 def HasVFP2 : Predicate<"Subtarget->hasVFP2()">,
208 AssemblerPredicate<"FeatureVFP2">;
209 def HasVFP3 : Predicate<"Subtarget->hasVFP3()">,
210 AssemblerPredicate<"FeatureVFP3">;
211 def HasNEON : Predicate<"Subtarget->hasNEON()">,
212 AssemblerPredicate<"FeatureNEON">;
213 def HasFP16 : Predicate<"Subtarget->hasFP16()">,
214 AssemblerPredicate<"FeatureFP16">;
215 def HasDivide : Predicate<"Subtarget->hasDivide()">,
216 AssemblerPredicate<"FeatureHWDiv">;
217 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
218 AssemblerPredicate<"FeatureT2XtPk">;
219 def HasThumb2DSP : Predicate<"Subtarget->hasThumb2DSP()">,
220 AssemblerPredicate<"FeatureDSPThumb2">;
221 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
222 AssemblerPredicate<"FeatureDB">;
223 def HasMP : Predicate<"Subtarget->hasMPExtension()">,
224 AssemblerPredicate<"FeatureMP">;
225 def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">;
226 def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">;
227 def IsThumb : Predicate<"Subtarget->isThumb()">,
228 AssemblerPredicate<"ModeThumb">;
229 def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
230 def IsThumb2 : Predicate<"Subtarget->isThumb2()">,
231 AssemblerPredicate<"ModeThumb,FeatureThumb2">;
232 def IsARM : Predicate<"!Subtarget->isThumb()">,
233 AssemblerPredicate<"!ModeThumb">;
234 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
235 def IsNotDarwin : Predicate<"!Subtarget->isTargetDarwin()">;
237 // FIXME: Eventually this will be just "hasV6T2Ops".
238 def UseMovt : Predicate<"Subtarget->useMovt()">;
239 def DontUseMovt : Predicate<"!Subtarget->useMovt()">;
240 def UseFPVMLx : Predicate<"Subtarget->useFPVMLx()">;
242 //===----------------------------------------------------------------------===//
243 // ARM Flag Definitions.
245 class RegConstraint<string C> {
246 string Constraints = C;
249 //===----------------------------------------------------------------------===//
250 // ARM specific transformation functions and pattern fragments.
253 // so_imm_neg_XFORM - Return a so_imm value packed into the format described for
254 // so_imm_neg def below.
255 def so_imm_neg_XFORM : SDNodeXForm<imm, [{
256 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
259 // so_imm_not_XFORM - Return a so_imm value packed into the format described for
260 // so_imm_not def below.
261 def so_imm_not_XFORM : SDNodeXForm<imm, [{
262 return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32);
265 /// imm1_15 predicate - True if the 32-bit immediate is in the range [1,15].
266 def imm1_15 : ImmLeaf<i32, [{
267 return (int32_t)Imm >= 1 && (int32_t)Imm < 16;
270 /// imm16_31 predicate - True if the 32-bit immediate is in the range [16,31].
271 def imm16_31 : ImmLeaf<i32, [{
272 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
277 return ARM_AM::getSOImmVal(-(uint32_t)N->getZExtValue()) != -1;
278 }], so_imm_neg_XFORM>;
282 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
283 }], so_imm_not_XFORM>;
285 // sext_16_node predicate - True if the SDNode is sign-extended 16 or more bits.
286 def sext_16_node : PatLeaf<(i32 GPR:$a), [{
287 return CurDAG->ComputeNumSignBits(SDValue(N,0)) >= 17;
290 /// Split a 32-bit immediate into two 16 bit parts.
291 def hi16 : SDNodeXForm<imm, [{
292 return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
295 def lo16AllZero : PatLeaf<(i32 imm), [{
296 // Returns true if all low 16-bits are 0.
297 return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
300 /// imm0_65535 - An immediate is in the range [0.65535].
301 def Imm0_65535AsmOperand: AsmOperandClass { let Name = "Imm0_65535"; }
302 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
303 return Imm >= 0 && Imm < 65536;
305 let ParserMatchClass = Imm0_65535AsmOperand;
308 class BinOpWithFlagFrag<dag res> :
309 PatFrag<(ops node:$LHS, node:$RHS, node:$FLAG), res>;
310 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
311 class UnOpFrag <dag res> : PatFrag<(ops node:$Src), res>;
313 // An 'and' node with a single use.
314 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
315 return N->hasOneUse();
318 // An 'xor' node with a single use.
319 def xor_su : PatFrag<(ops node:$lhs, node:$rhs), (xor node:$lhs, node:$rhs), [{
320 return N->hasOneUse();
323 // An 'fmul' node with a single use.
324 def fmul_su : PatFrag<(ops node:$lhs, node:$rhs), (fmul node:$lhs, node:$rhs),[{
325 return N->hasOneUse();
328 // An 'fadd' node which checks for single non-hazardous use.
329 def fadd_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fadd node:$lhs, node:$rhs),[{
330 return hasNoVMLxHazardUse(N);
333 // An 'fsub' node which checks for single non-hazardous use.
334 def fsub_mlx : PatFrag<(ops node:$lhs, node:$rhs),(fsub node:$lhs, node:$rhs),[{
335 return hasNoVMLxHazardUse(N);
338 //===----------------------------------------------------------------------===//
339 // Operand Definitions.
343 // FIXME: rename brtarget to t2_brtarget
344 def brtarget : Operand<OtherVT> {
345 let EncoderMethod = "getBranchTargetOpValue";
346 let OperandType = "OPERAND_PCREL";
347 let DecoderMethod = "DecodeT2BROperand";
350 // FIXME: get rid of this one?
351 def uncondbrtarget : Operand<OtherVT> {
352 let EncoderMethod = "getUnconditionalBranchTargetOpValue";
353 let OperandType = "OPERAND_PCREL";
356 // Branch target for ARM. Handles conditional/unconditional
357 def br_target : Operand<OtherVT> {
358 let EncoderMethod = "getARMBranchTargetOpValue";
359 let OperandType = "OPERAND_PCREL";
363 // FIXME: rename bltarget to t2_bl_target?
364 def bltarget : Operand<i32> {
365 // Encoded the same as branch targets.
366 let EncoderMethod = "getBranchTargetOpValue";
367 let OperandType = "OPERAND_PCREL";
370 // Call target for ARM. Handles conditional/unconditional
371 // FIXME: rename bl_target to t2_bltarget?
372 def bl_target : Operand<i32> {
373 // Encoded the same as branch targets.
374 let EncoderMethod = "getARMBranchTargetOpValue";
375 let OperandType = "OPERAND_PCREL";
378 def blx_target : Operand<i32> {
379 // Encoded the same as branch targets.
380 let EncoderMethod = "getARMBLXTargetOpValue";
381 let OperandType = "OPERAND_PCREL";
384 // A list of registers separated by comma. Used by load/store multiple.
385 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
386 def reglist : Operand<i32> {
387 let EncoderMethod = "getRegisterListOpValue";
388 let ParserMatchClass = RegListAsmOperand;
389 let PrintMethod = "printRegisterList";
390 let DecoderMethod = "DecodeRegListOperand";
393 def DPRRegListAsmOperand : AsmOperandClass { let Name = "DPRRegList"; }
394 def dpr_reglist : Operand<i32> {
395 let EncoderMethod = "getRegisterListOpValue";
396 let ParserMatchClass = DPRRegListAsmOperand;
397 let PrintMethod = "printRegisterList";
398 let DecoderMethod = "DecodeDPRRegListOperand";
401 def SPRRegListAsmOperand : AsmOperandClass { let Name = "SPRRegList"; }
402 def spr_reglist : Operand<i32> {
403 let EncoderMethod = "getRegisterListOpValue";
404 let ParserMatchClass = SPRRegListAsmOperand;
405 let PrintMethod = "printRegisterList";
406 let DecoderMethod = "DecodeSPRRegListOperand";
409 // An operand for the CONSTPOOL_ENTRY pseudo-instruction.
410 def cpinst_operand : Operand<i32> {
411 let PrintMethod = "printCPInstOperand";
415 def pclabel : Operand<i32> {
416 let PrintMethod = "printPCLabel";
419 // ADR instruction labels.
420 def adrlabel : Operand<i32> {
421 let EncoderMethod = "getAdrLabelOpValue";
424 def neon_vcvt_imm32 : Operand<i32> {
425 let EncoderMethod = "getNEONVcvtImm32OpValue";
426 let DecoderMethod = "DecodeVCVTImmOperand";
429 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
430 def rot_imm_XFORM: SDNodeXForm<imm, [{
431 switch (N->getZExtValue()){
433 case 0: return CurDAG->getTargetConstant(0, MVT::i32);
434 case 8: return CurDAG->getTargetConstant(1, MVT::i32);
435 case 16: return CurDAG->getTargetConstant(2, MVT::i32);
436 case 24: return CurDAG->getTargetConstant(3, MVT::i32);
439 def RotImmAsmOperand : AsmOperandClass {
441 let ParserMethod = "parseRotImm";
443 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
444 int32_t v = N->getZExtValue();
445 return v == 8 || v == 16 || v == 24; }],
447 let PrintMethod = "printRotImmOperand";
448 let ParserMatchClass = RotImmAsmOperand;
451 // shift_imm: An integer that encodes a shift amount and the type of shift
452 // (asr or lsl). The 6-bit immediate encodes as:
455 // {4-0} imm5 shift amount.
456 // asr #32 encoded as imm5 == 0.
457 def ShifterImmAsmOperand : AsmOperandClass {
458 let Name = "ShifterImm";
459 let ParserMethod = "parseShifterImm";
461 def shift_imm : Operand<i32> {
462 let PrintMethod = "printShiftImmOperand";
463 let ParserMatchClass = ShifterImmAsmOperand;
466 // shifter_operand operands: so_reg_reg, so_reg_imm, and so_imm.
467 def ShiftedRegAsmOperand : AsmOperandClass { let Name = "RegShiftedReg"; }
468 def so_reg_reg : Operand<i32>, // reg reg imm
469 ComplexPattern<i32, 3, "SelectRegShifterOperand",
470 [shl, srl, sra, rotr]> {
471 let EncoderMethod = "getSORegRegOpValue";
472 let PrintMethod = "printSORegRegOperand";
473 let DecoderMethod = "DecodeSORegRegOperand";
474 let ParserMatchClass = ShiftedRegAsmOperand;
475 let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
478 def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
479 def so_reg_imm : Operand<i32>, // reg imm
480 ComplexPattern<i32, 2, "SelectImmShifterOperand",
481 [shl, srl, sra, rotr]> {
482 let EncoderMethod = "getSORegImmOpValue";
483 let PrintMethod = "printSORegImmOperand";
484 let DecoderMethod = "DecodeSORegImmOperand";
485 let ParserMatchClass = ShiftedImmAsmOperand;
486 let MIOperandInfo = (ops GPR, i32imm);
489 // FIXME: Does this need to be distinct from so_reg?
490 def shift_so_reg_reg : Operand<i32>, // reg reg imm
491 ComplexPattern<i32, 3, "SelectShiftRegShifterOperand",
492 [shl,srl,sra,rotr]> {
493 let EncoderMethod = "getSORegRegOpValue";
494 let PrintMethod = "printSORegRegOperand";
495 let DecoderMethod = "DecodeSORegRegOperand";
496 let MIOperandInfo = (ops GPR, GPR, i32imm);
499 // FIXME: Does this need to be distinct from so_reg?
500 def shift_so_reg_imm : Operand<i32>, // reg reg imm
501 ComplexPattern<i32, 2, "SelectShiftImmShifterOperand",
502 [shl,srl,sra,rotr]> {
503 let EncoderMethod = "getSORegImmOpValue";
504 let PrintMethod = "printSORegImmOperand";
505 let DecoderMethod = "DecodeSORegImmOperand";
506 let MIOperandInfo = (ops GPR, i32imm);
510 // so_imm - Match a 32-bit shifter_operand immediate operand, which is an
511 // 8-bit immediate rotated by an arbitrary number of bits.
512 def SOImmAsmOperand: AsmOperandClass { let Name = "ARMSOImm"; }
513 def so_imm : Operand<i32>, ImmLeaf<i32, [{
514 return ARM_AM::getSOImmVal(Imm) != -1;
516 let EncoderMethod = "getSOImmOpValue";
517 let ParserMatchClass = SOImmAsmOperand;
518 let DecoderMethod = "DecodeSOImmOperand";
521 // Break so_imm's up into two pieces. This handles immediates with up to 16
522 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
523 // get the first/second pieces.
524 def so_imm2part : PatLeaf<(imm), [{
525 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
528 /// arm_i32imm - True for +V6T2, or true only if so_imm2part is true.
530 def arm_i32imm : PatLeaf<(imm), [{
531 if (Subtarget->hasV6T2Ops())
533 return ARM_AM::isSOImmTwoPartVal((unsigned)N->getZExtValue());
536 /// imm0_7 predicate - Immediate in the range [0,7].
537 def Imm0_7AsmOperand: AsmOperandClass { let Name = "Imm0_7"; }
538 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
539 return Imm >= 0 && Imm < 8;
541 let ParserMatchClass = Imm0_7AsmOperand;
544 /// imm0_15 predicate - Immediate in the range [0,15].
545 def Imm0_15AsmOperand: AsmOperandClass { let Name = "Imm0_15"; }
546 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
547 return Imm >= 0 && Imm < 16;
549 let ParserMatchClass = Imm0_15AsmOperand;
552 /// imm0_31 predicate - True if the 32-bit immediate is in the range [0,31].
553 def Imm0_31AsmOperand: AsmOperandClass { let Name = "Imm0_31"; }
554 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
555 return Imm >= 0 && Imm < 32;
557 let ParserMatchClass = Imm0_31AsmOperand;
560 /// imm0_255 predicate - Immediate in the range [0,255].
561 def Imm0_255AsmOperand : AsmOperandClass { let Name = "Imm0_255"; }
562 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
563 let ParserMatchClass = Imm0_255AsmOperand;
566 // imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
567 // a relocatable expression.
569 // FIXME: This really needs a Thumb version separate from the ARM version.
570 // While the range is the same, and can thus use the same match class,
571 // the encoding is different so it should have a different encoder method.
572 def Imm0_65535ExprAsmOperand: AsmOperandClass { let Name = "Imm0_65535Expr"; }
573 def imm0_65535_expr : Operand<i32> {
574 let EncoderMethod = "getHiLo16ImmOpValue";
575 let ParserMatchClass = Imm0_65535ExprAsmOperand;
578 /// imm24b - True if the 32-bit immediate is encodable in 24 bits.
579 def Imm24bitAsmOperand: AsmOperandClass { let Name = "Imm24bit"; }
580 def imm24b : Operand<i32>, ImmLeaf<i32, [{
581 return Imm >= 0 && Imm <= 0xffffff;
583 let ParserMatchClass = Imm24bitAsmOperand;
587 /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
589 def BitfieldAsmOperand : AsmOperandClass {
590 let Name = "Bitfield";
591 let ParserMethod = "parseBitfield";
593 def bf_inv_mask_imm : Operand<i32>,
595 return ARM::isBitFieldInvertedMask(N->getZExtValue());
597 let EncoderMethod = "getBitfieldInvertedMaskOpValue";
598 let PrintMethod = "printBitfieldInvMaskImmOperand";
599 let DecoderMethod = "DecodeBitfieldMaskOperand";
600 let ParserMatchClass = BitfieldAsmOperand;
603 /// lsb_pos_imm - position of the lsb bit, used by BFI4p and t2BFI4p
604 def lsb_pos_imm : Operand<i32>, ImmLeaf<i32, [{
605 return isInt<5>(Imm);
608 /// width_imm - number of bits to be copied, used by BFI4p and t2BFI4p
609 def width_imm : Operand<i32>, ImmLeaf<i32, [{
610 return Imm > 0 && Imm <= 32;
612 let EncoderMethod = "getMsbOpValue";
615 def imm1_32_XFORM: SDNodeXForm<imm, [{
616 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
618 def Imm1_32AsmOperand: AsmOperandClass { let Name = "Imm1_32"; }
619 def imm1_32 : Operand<i32>, PatLeaf<(imm), [{
620 uint64_t Imm = N->getZExtValue();
621 return Imm > 0 && Imm <= 32;
624 let PrintMethod = "printImmPlusOneOperand";
625 let ParserMatchClass = Imm1_32AsmOperand;
628 def imm1_16_XFORM: SDNodeXForm<imm, [{
629 return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, MVT::i32);
631 def Imm1_16AsmOperand: AsmOperandClass { let Name = "Imm1_16"; }
632 def imm1_16 : Operand<i32>, PatLeaf<(imm), [{ return Imm > 0 && Imm <= 16; }],
634 let PrintMethod = "printImmPlusOneOperand";
635 let ParserMatchClass = Imm1_16AsmOperand;
638 // Define ARM specific addressing modes.
639 // addrmode_imm12 := reg +/- imm12
641 def MemImm12OffsetAsmOperand : AsmOperandClass { let Name = "MemImm12Offset"; }
642 def addrmode_imm12 : Operand<i32>,
643 ComplexPattern<i32, 2, "SelectAddrModeImm12", []> {
644 // 12-bit immediate operand. Note that instructions using this encode
645 // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other
646 // immediate values are as normal.
648 let EncoderMethod = "getAddrModeImm12OpValue";
649 let PrintMethod = "printAddrModeImm12Operand";
650 let DecoderMethod = "DecodeAddrModeImm12Operand";
651 let ParserMatchClass = MemImm12OffsetAsmOperand;
652 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
654 // ldst_so_reg := reg +/- reg shop imm
656 def MemRegOffsetAsmOperand : AsmOperandClass { let Name = "MemRegOffset"; }
657 def ldst_so_reg : Operand<i32>,
658 ComplexPattern<i32, 3, "SelectLdStSOReg", []> {
659 let EncoderMethod = "getLdStSORegOpValue";
660 // FIXME: Simplify the printer
661 let PrintMethod = "printAddrMode2Operand";
662 let DecoderMethod = "DecodeSORegMemOperand";
663 let ParserMatchClass = MemRegOffsetAsmOperand;
664 let MIOperandInfo = (ops GPR:$base, GPRnopc:$offsreg, i32imm:$shift);
667 // postidx_imm8 := +/- [0,255]
670 // {8} 1 is imm8 is non-negative. 0 otherwise.
671 // {7-0} [0,255] imm8 value.
672 def PostIdxImm8AsmOperand : AsmOperandClass { let Name = "PostIdxImm8"; }
673 def postidx_imm8 : Operand<i32> {
674 let PrintMethod = "printPostIdxImm8Operand";
675 let ParserMatchClass = PostIdxImm8AsmOperand;
676 let MIOperandInfo = (ops i32imm);
679 // postidx_imm8s4 := +/- [0,1020]
682 // {8} 1 is imm8 is non-negative. 0 otherwise.
683 // {7-0} [0,255] imm8 value, scaled by 4.
684 def postidx_imm8s4 : Operand<i32> {
685 let PrintMethod = "printPostIdxImm8s4Operand";
686 let MIOperandInfo = (ops i32imm);
690 // postidx_reg := +/- reg
692 def PostIdxRegAsmOperand : AsmOperandClass {
693 let Name = "PostIdxReg";
694 let ParserMethod = "parsePostIdxReg";
696 def postidx_reg : Operand<i32> {
697 let EncoderMethod = "getPostIdxRegOpValue";
698 let DecoderMethod = "DecodePostIdxReg";
699 let PrintMethod = "printPostIdxRegOperand";
700 let ParserMatchClass = PostIdxRegAsmOperand;
701 let MIOperandInfo = (ops GPR, i32imm);
705 // addrmode2 := reg +/- imm12
706 // := reg +/- reg shop imm
708 // FIXME: addrmode2 should be refactored the rest of the way to always
709 // use explicit imm vs. reg versions above (addrmode_imm12 and ldst_so_reg).
710 def AddrMode2AsmOperand : AsmOperandClass { let Name = "AddrMode2"; }
711 def addrmode2 : Operand<i32>,
712 ComplexPattern<i32, 3, "SelectAddrMode2", []> {
713 let EncoderMethod = "getAddrMode2OpValue";
714 let PrintMethod = "printAddrMode2Operand";
715 let ParserMatchClass = AddrMode2AsmOperand;
716 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
719 def PostIdxRegShiftedAsmOperand : AsmOperandClass {
720 let Name = "PostIdxRegShifted";
721 let ParserMethod = "parsePostIdxReg";
723 def am2offset_reg : Operand<i32>,
724 ComplexPattern<i32, 2, "SelectAddrMode2OffsetReg",
725 [], [SDNPWantRoot]> {
726 let EncoderMethod = "getAddrMode2OffsetOpValue";
727 let PrintMethod = "printAddrMode2OffsetOperand";
728 // When using this for assembly, it's always as a post-index offset.
729 let ParserMatchClass = PostIdxRegShiftedAsmOperand;
730 let MIOperandInfo = (ops GPR, i32imm);
733 // FIXME: am2offset_imm should only need the immediate, not the GPR. Having
734 // the GPR is purely vestigal at this point.
735 def AM2OffsetImmAsmOperand : AsmOperandClass { let Name = "AM2OffsetImm"; }
736 def am2offset_imm : Operand<i32>,
737 ComplexPattern<i32, 2, "SelectAddrMode2OffsetImm",
738 [], [SDNPWantRoot]> {
739 let EncoderMethod = "getAddrMode2OffsetOpValue";
740 let PrintMethod = "printAddrMode2OffsetOperand";
741 let ParserMatchClass = AM2OffsetImmAsmOperand;
742 let MIOperandInfo = (ops GPR, i32imm);
746 // addrmode3 := reg +/- reg
747 // addrmode3 := reg +/- imm8
749 // FIXME: split into imm vs. reg versions.
750 def AddrMode3AsmOperand : AsmOperandClass { let Name = "AddrMode3"; }
751 def addrmode3 : Operand<i32>,
752 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
753 let EncoderMethod = "getAddrMode3OpValue";
754 let PrintMethod = "printAddrMode3Operand";
755 let ParserMatchClass = AddrMode3AsmOperand;
756 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
759 // FIXME: split into imm vs. reg versions.
760 // FIXME: parser method to handle +/- register.
761 def AM3OffsetAsmOperand : AsmOperandClass {
762 let Name = "AM3Offset";
763 let ParserMethod = "parseAM3Offset";
765 def am3offset : Operand<i32>,
766 ComplexPattern<i32, 2, "SelectAddrMode3Offset",
767 [], [SDNPWantRoot]> {
768 let EncoderMethod = "getAddrMode3OffsetOpValue";
769 let PrintMethod = "printAddrMode3OffsetOperand";
770 let ParserMatchClass = AM3OffsetAsmOperand;
771 let MIOperandInfo = (ops GPR, i32imm);
774 // ldstm_mode := {ia, ib, da, db}
776 def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> {
777 let EncoderMethod = "getLdStmModeOpValue";
778 let PrintMethod = "printLdStmModeOperand";
781 // addrmode5 := reg +/- imm8*4
783 def AddrMode5AsmOperand : AsmOperandClass { let Name = "AddrMode5"; }
784 def addrmode5 : Operand<i32>,
785 ComplexPattern<i32, 2, "SelectAddrMode5", []> {
786 let PrintMethod = "printAddrMode5Operand";
787 let EncoderMethod = "getAddrMode5OpValue";
788 let DecoderMethod = "DecodeAddrMode5Operand";
789 let ParserMatchClass = AddrMode5AsmOperand;
790 let MIOperandInfo = (ops GPR:$base, i32imm);
793 // addrmode6 := reg with optional alignment
795 def addrmode6 : Operand<i32>,
796 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
797 let PrintMethod = "printAddrMode6Operand";
798 let MIOperandInfo = (ops GPR:$addr, i32imm);
799 let EncoderMethod = "getAddrMode6AddressOpValue";
800 let DecoderMethod = "DecodeAddrMode6Operand";
803 def am6offset : Operand<i32>,
804 ComplexPattern<i32, 1, "SelectAddrMode6Offset",
805 [], [SDNPWantRoot]> {
806 let PrintMethod = "printAddrMode6OffsetOperand";
807 let MIOperandInfo = (ops GPR);
808 let EncoderMethod = "getAddrMode6OffsetOpValue";
809 let DecoderMethod = "DecodeGPRRegisterClass";
812 // Special version of addrmode6 to handle alignment encoding for VST1/VLD1
813 // (single element from one lane) for size 32.
814 def addrmode6oneL32 : Operand<i32>,
815 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
816 let PrintMethod = "printAddrMode6Operand";
817 let MIOperandInfo = (ops GPR:$addr, i32imm);
818 let EncoderMethod = "getAddrMode6OneLane32AddressOpValue";
821 // Special version of addrmode6 to handle alignment encoding for VLD-dup
822 // instructions, specifically VLD4-dup.
823 def addrmode6dup : Operand<i32>,
824 ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
825 let PrintMethod = "printAddrMode6Operand";
826 let MIOperandInfo = (ops GPR:$addr, i32imm);
827 let EncoderMethod = "getAddrMode6DupAddressOpValue";
830 // addrmodepc := pc + reg
832 def addrmodepc : Operand<i32>,
833 ComplexPattern<i32, 2, "SelectAddrModePC", []> {
834 let PrintMethod = "printAddrModePCOperand";
835 let MIOperandInfo = (ops GPR, i32imm);
838 // addr_offset_none := reg
840 def MemNoOffsetAsmOperand : AsmOperandClass { let Name = "MemNoOffset"; }
841 def addr_offset_none : Operand<i32>,
842 ComplexPattern<i32, 1, "SelectAddrOffsetNone", []> {
843 let PrintMethod = "printAddrMode7Operand";
844 let DecoderMethod = "DecodeAddrMode7Operand";
845 let ParserMatchClass = MemNoOffsetAsmOperand;
846 let MIOperandInfo = (ops GPR:$base);
849 def nohash_imm : Operand<i32> {
850 let PrintMethod = "printNoHashImmediate";
853 def CoprocNumAsmOperand : AsmOperandClass {
854 let Name = "CoprocNum";
855 let ParserMethod = "parseCoprocNumOperand";
857 def p_imm : Operand<i32> {
858 let PrintMethod = "printPImmediate";
859 let ParserMatchClass = CoprocNumAsmOperand;
860 let DecoderMethod = "DecodeCoprocessor";
863 def CoprocRegAsmOperand : AsmOperandClass {
864 let Name = "CoprocReg";
865 let ParserMethod = "parseCoprocRegOperand";
867 def c_imm : Operand<i32> {
868 let PrintMethod = "printCImmediate";
869 let ParserMatchClass = CoprocRegAsmOperand;
872 //===----------------------------------------------------------------------===//
874 include "ARMInstrFormats.td"
876 //===----------------------------------------------------------------------===//
877 // Multiclass helpers...
880 /// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
881 /// binop that produces a value.
882 multiclass AsI1_bin_irs<bits<4> opcod, string opc,
883 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
884 PatFrag opnode, string baseOpc, bit Commutable = 0> {
885 // The register-immediate version is re-materializable. This is useful
886 // in particular for taking the address of a local.
887 let isReMaterializable = 1 in {
888 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
889 iii, opc, "\t$Rd, $Rn, $imm",
890 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
895 let Inst{19-16} = Rn;
896 let Inst{15-12} = Rd;
897 let Inst{11-0} = imm;
900 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
901 iir, opc, "\t$Rd, $Rn, $Rm",
902 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
907 let isCommutable = Commutable;
908 let Inst{19-16} = Rn;
909 let Inst{15-12} = Rd;
910 let Inst{11-4} = 0b00000000;
914 def rsi : AsI1<opcod, (outs GPR:$Rd),
915 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
916 iis, opc, "\t$Rd, $Rn, $shift",
917 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
922 let Inst{19-16} = Rn;
923 let Inst{15-12} = Rd;
924 let Inst{11-5} = shift{11-5};
926 let Inst{3-0} = shift{3-0};
929 def rsr : AsI1<opcod, (outs GPR:$Rd),
930 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
931 iis, opc, "\t$Rd, $Rn, $shift",
932 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
937 let Inst{19-16} = Rn;
938 let Inst{15-12} = Rd;
939 let Inst{11-8} = shift{11-8};
941 let Inst{6-5} = shift{6-5};
943 let Inst{3-0} = shift{3-0};
946 // Assembly aliases for optional destination operand when it's the same
947 // as the source operand.
948 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
949 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
950 so_imm:$imm, pred:$p,
953 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
954 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
958 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
959 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
960 so_reg_imm:$shift, pred:$p,
963 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
964 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
965 so_reg_reg:$shift, pred:$p,
971 /// AsI1_rbin_irs - Same as AsI1_bin_irs except the order of operands are
972 /// reversed. The 'rr' form is only defined for the disassembler; for codegen
973 /// it is equivalent to the AsI1_bin_irs counterpart.
974 multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
975 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
976 PatFrag opnode, string baseOpc, bit Commutable = 0> {
977 // The register-immediate version is re-materializable. This is useful
978 // in particular for taking the address of a local.
979 let isReMaterializable = 1 in {
980 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
981 iii, opc, "\t$Rd, $Rn, $imm",
982 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
987 let Inst{19-16} = Rn;
988 let Inst{15-12} = Rd;
989 let Inst{11-0} = imm;
992 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
993 iir, opc, "\t$Rd, $Rn, $Rm",
994 [/* pattern left blank */]> {
998 let Inst{11-4} = 0b00000000;
1001 let Inst{15-12} = Rd;
1002 let Inst{19-16} = Rn;
1005 def rsi : AsI1<opcod, (outs GPR:$Rd),
1006 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1007 iis, opc, "\t$Rd, $Rn, $shift",
1008 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1013 let Inst{19-16} = Rn;
1014 let Inst{15-12} = Rd;
1015 let Inst{11-5} = shift{11-5};
1017 let Inst{3-0} = shift{3-0};
1020 def rsr : AsI1<opcod, (outs GPR:$Rd),
1021 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1022 iis, opc, "\t$Rd, $Rn, $shift",
1023 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1028 let Inst{19-16} = Rn;
1029 let Inst{15-12} = Rd;
1030 let Inst{11-8} = shift{11-8};
1032 let Inst{6-5} = shift{6-5};
1034 let Inst{3-0} = shift{3-0};
1037 // Assembly aliases for optional destination operand when it's the same
1038 // as the source operand.
1039 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1040 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1041 so_imm:$imm, pred:$p,
1044 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1045 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1049 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1050 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1051 so_reg_imm:$shift, pred:$p,
1054 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1055 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1056 so_reg_reg:$shift, pred:$p,
1062 /// AsI1_rbin_s_is - Same as AsI1_rbin_s_is except sets 's' bit.
1063 let isCodeGenOnly = 1, Defs = [CPSR] in {
1064 multiclass AsI1_rbin_s_is<bits<4> opcod, string opc,
1065 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1066 PatFrag opnode, bit Commutable = 0> {
1067 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1068 iii, opc, "\t$Rd, $Rn, $imm",
1069 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]> {
1074 let Inst{19-16} = Rn;
1075 let Inst{15-12} = Rd;
1076 let Inst{11-0} = imm;
1079 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1080 iir, opc, "\t$Rd, $Rn, $Rm",
1081 [/* pattern left blank */]> {
1085 let Inst{11-4} = 0b00000000;
1088 let Inst{15-12} = Rd;
1089 let Inst{19-16} = Rn;
1092 def rsi : AsI1<opcod, (outs GPR:$Rd),
1093 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1094 iis, opc, "\t$Rd, $Rn, $shift",
1095 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
1100 let Inst{19-16} = Rn;
1101 let Inst{15-12} = Rd;
1102 let Inst{11-5} = shift{11-5};
1104 let Inst{3-0} = shift{3-0};
1107 def rsr : AsI1<opcod, (outs GPR:$Rd),
1108 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1109 iis, opc, "\t$Rd, $Rn, $shift",
1110 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
1115 let Inst{19-16} = Rn;
1116 let Inst{15-12} = Rd;
1117 let Inst{11-8} = shift{11-8};
1119 let Inst{6-5} = shift{6-5};
1121 let Inst{3-0} = shift{3-0};
1126 /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
1127 /// instruction modifies the CPSR register.
1128 let isCodeGenOnly = 1, Defs = [CPSR] in {
1129 multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
1130 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1131 PatFrag opnode, bit Commutable = 0> {
1132 def ri : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
1133 iii, opc, "\t$Rd, $Rn, $imm",
1134 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]> {
1140 let Inst{19-16} = Rn;
1141 let Inst{15-12} = Rd;
1142 let Inst{11-0} = imm;
1144 def rr : AI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1145 iir, opc, "\t$Rd, $Rn, $Rm",
1146 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
1150 let isCommutable = Commutable;
1153 let Inst{19-16} = Rn;
1154 let Inst{15-12} = Rd;
1155 let Inst{11-4} = 0b00000000;
1158 def rsi : AI1<opcod, (outs GPR:$Rd),
1159 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1160 iis, opc, "\t$Rd, $Rn, $shift",
1161 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
1167 let Inst{19-16} = Rn;
1168 let Inst{15-12} = Rd;
1169 let Inst{11-5} = shift{11-5};
1171 let Inst{3-0} = shift{3-0};
1174 def rsr : AI1<opcod, (outs GPR:$Rd),
1175 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1176 iis, opc, "\t$Rd, $Rn, $shift",
1177 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
1183 let Inst{19-16} = Rn;
1184 let Inst{15-12} = Rd;
1185 let Inst{11-8} = shift{11-8};
1187 let Inst{6-5} = shift{6-5};
1189 let Inst{3-0} = shift{3-0};
1194 /// AI1_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test
1195 /// patterns. Similar to AsI1_bin_irs except the instruction does not produce
1196 /// a explicit result, only implicitly set CPSR.
1197 let isCompare = 1, Defs = [CPSR] in {
1198 multiclass AI1_cmp_irs<bits<4> opcod, string opc,
1199 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
1200 PatFrag opnode, bit Commutable = 0> {
1201 def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
1203 [(opnode GPR:$Rn, so_imm:$imm)]> {
1208 let Inst{19-16} = Rn;
1209 let Inst{15-12} = 0b0000;
1210 let Inst{11-0} = imm;
1212 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1214 [(opnode GPR:$Rn, GPR:$Rm)]> {
1217 let isCommutable = Commutable;
1220 let Inst{19-16} = Rn;
1221 let Inst{15-12} = 0b0000;
1222 let Inst{11-4} = 0b00000000;
1225 def rsi : AI1<opcod, (outs),
1226 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1227 opc, "\t$Rn, $shift",
1228 [(opnode GPR:$Rn, so_reg_imm:$shift)]> {
1233 let Inst{19-16} = Rn;
1234 let Inst{15-12} = 0b0000;
1235 let Inst{11-5} = shift{11-5};
1237 let Inst{3-0} = shift{3-0};
1239 def rsr : AI1<opcod, (outs),
1240 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1241 opc, "\t$Rn, $shift",
1242 [(opnode GPR:$Rn, so_reg_reg:$shift)]> {
1247 let Inst{19-16} = Rn;
1248 let Inst{15-12} = 0b0000;
1249 let Inst{11-8} = shift{11-8};
1251 let Inst{6-5} = shift{6-5};
1253 let Inst{3-0} = shift{3-0};
1259 /// AI_ext_rrot - A unary operation with two forms: one whose operand is a
1260 /// register and one whose operand is a register rotated by 8/16/24.
1261 /// FIXME: Remove the 'r' variant. Its rot_imm is zero.
1262 class AI_ext_rrot<bits<8> opcod, string opc, PatFrag opnode>
1263 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1264 IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
1265 [(set GPRnopc:$Rd, (opnode (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1266 Requires<[IsARM, HasV6]> {
1270 let Inst{19-16} = 0b1111;
1271 let Inst{15-12} = Rd;
1272 let Inst{11-10} = rot;
1276 class AI_ext_rrot_np<bits<8> opcod, string opc>
1277 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPRnopc:$Rm, rot_imm:$rot),
1278 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", []>,
1279 Requires<[IsARM, HasV6]> {
1281 let Inst{19-16} = 0b1111;
1282 let Inst{11-10} = rot;
1285 /// AI_exta_rrot - A binary operation with two forms: one whose operand is a
1286 /// register and one whose operand is a register rotated by 8/16/24.
1287 class AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode>
1288 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1289 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1290 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1291 (rotr GPRnopc:$Rm, rot_imm:$rot)))]>,
1292 Requires<[IsARM, HasV6]> {
1297 let Inst{19-16} = Rn;
1298 let Inst{15-12} = Rd;
1299 let Inst{11-10} = rot;
1300 let Inst{9-4} = 0b000111;
1304 class AI_exta_rrot_np<bits<8> opcod, string opc>
1305 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1306 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1307 Requires<[IsARM, HasV6]> {
1310 let Inst{19-16} = Rn;
1311 let Inst{11-10} = rot;
1314 /// AI1_adde_sube_irs - Define instructions and patterns for adde and sube.
1315 multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
1316 string baseOpc, bit Commutable = 0> {
1317 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1318 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1319 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1320 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1326 let Inst{15-12} = Rd;
1327 let Inst{19-16} = Rn;
1328 let Inst{11-0} = imm;
1330 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1331 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1332 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1337 let Inst{11-4} = 0b00000000;
1339 let isCommutable = Commutable;
1341 let Inst{15-12} = Rd;
1342 let Inst{19-16} = Rn;
1344 def rsi : AsI1<opcod, (outs GPR:$Rd),
1345 (ins GPR:$Rn, so_reg_imm:$shift),
1346 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1347 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1353 let Inst{19-16} = Rn;
1354 let Inst{15-12} = Rd;
1355 let Inst{11-5} = shift{11-5};
1357 let Inst{3-0} = shift{3-0};
1359 def rsr : AsI1<opcod, (outs GPR:$Rd),
1360 (ins GPR:$Rn, so_reg_reg:$shift),
1361 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1362 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift, CPSR))]>,
1368 let Inst{19-16} = Rn;
1369 let Inst{15-12} = Rd;
1370 let Inst{11-8} = shift{11-8};
1372 let Inst{6-5} = shift{6-5};
1374 let Inst{3-0} = shift{3-0};
1378 // Assembly aliases for optional destination operand when it's the same
1379 // as the source operand.
1380 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1381 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1382 so_imm:$imm, pred:$p,
1385 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1386 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1390 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1391 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1392 so_reg_imm:$shift, pred:$p,
1395 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1396 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1397 so_reg_reg:$shift, pred:$p,
1402 /// AI1_rsc_irs - Define instructions and patterns for rsc
1403 multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode,
1405 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1406 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
1407 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1408 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1414 let Inst{15-12} = Rd;
1415 let Inst{19-16} = Rn;
1416 let Inst{11-0} = imm;
1418 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1419 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1420 [/* pattern left blank */]> {
1424 let Inst{11-4} = 0b00000000;
1427 let Inst{15-12} = Rd;
1428 let Inst{19-16} = Rn;
1430 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1431 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1432 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1438 let Inst{19-16} = Rn;
1439 let Inst{15-12} = Rd;
1440 let Inst{11-5} = shift{11-5};
1442 let Inst{3-0} = shift{3-0};
1444 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
1445 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1446 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
1452 let Inst{19-16} = Rn;
1453 let Inst{15-12} = Rd;
1454 let Inst{11-8} = shift{11-8};
1456 let Inst{6-5} = shift{6-5};
1458 let Inst{3-0} = shift{3-0};
1462 // Assembly aliases for optional destination operand when it's the same
1463 // as the source operand.
1464 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"),
1465 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn,
1466 so_imm:$imm, pred:$p,
1469 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $Rm"),
1470 (!cast<Instruction>(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn,
1474 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1475 (!cast<Instruction>(!strconcat(baseOpc, "rsi")) GPR:$Rdn, GPR:$Rdn,
1476 so_reg_imm:$shift, pred:$p,
1479 def : InstAlias<!strconcat(opc, "${s}${p} $Rdn, $shift"),
1480 (!cast<Instruction>(!strconcat(baseOpc, "rsr")) GPR:$Rdn, GPR:$Rdn,
1481 so_reg_reg:$shift, pred:$p,
1486 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1487 multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
1488 InstrItinClass iir, PatFrag opnode> {
1489 // Note: We use the complex addrmode_imm12 rather than just an input
1490 // GPR and a constrained immediate so that we can use this to match
1491 // frame index references and avoid matching constant pool references.
1492 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1493 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1494 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1497 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1498 let Inst{19-16} = addr{16-13}; // Rn
1499 let Inst{15-12} = Rt;
1500 let Inst{11-0} = addr{11-0}; // imm12
1502 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1503 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1504 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1507 let shift{4} = 0; // Inst{4} = 0
1508 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1509 let Inst{19-16} = shift{16-13}; // Rn
1510 let Inst{15-12} = Rt;
1511 let Inst{11-0} = shift{11-0};
1516 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1517 multiclass AI_ldr1nopc<bit isByte, string opc, InstrItinClass iii,
1518 InstrItinClass iir, PatFrag opnode> {
1519 // Note: We use the complex addrmode_imm12 rather than just an input
1520 // GPR and a constrained immediate so that we can use this to match
1521 // frame index references and avoid matching constant pool references.
1522 def i12: AI2ldst<0b010, 1, isByte, (outs GPRnopc:$Rt), (ins addrmode_imm12:$addr),
1523 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1524 [(set GPRnopc:$Rt, (opnode addrmode_imm12:$addr))]> {
1527 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1528 let Inst{19-16} = addr{16-13}; // Rn
1529 let Inst{15-12} = Rt;
1530 let Inst{11-0} = addr{11-0}; // imm12
1532 def rs : AI2ldst<0b011, 1, isByte, (outs GPRnopc:$Rt), (ins ldst_so_reg:$shift),
1533 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1534 [(set GPRnopc:$Rt, (opnode ldst_so_reg:$shift))]> {
1537 let shift{4} = 0; // Inst{4} = 0
1538 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1539 let Inst{19-16} = shift{16-13}; // Rn
1540 let Inst{15-12} = Rt;
1541 let Inst{11-0} = shift{11-0};
1547 multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
1548 InstrItinClass iir, PatFrag opnode> {
1549 // Note: We use the complex addrmode_imm12 rather than just an input
1550 // GPR and a constrained immediate so that we can use this to match
1551 // frame index references and avoid matching constant pool references.
1552 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1553 (ins GPR:$Rt, addrmode_imm12:$addr),
1554 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1555 [(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
1558 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1559 let Inst{19-16} = addr{16-13}; // Rn
1560 let Inst{15-12} = Rt;
1561 let Inst{11-0} = addr{11-0}; // imm12
1563 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
1564 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1565 [(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
1568 let shift{4} = 0; // Inst{4} = 0
1569 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1570 let Inst{19-16} = shift{16-13}; // Rn
1571 let Inst{15-12} = Rt;
1572 let Inst{11-0} = shift{11-0};
1576 multiclass AI_str1nopc<bit isByte, string opc, InstrItinClass iii,
1577 InstrItinClass iir, PatFrag opnode> {
1578 // Note: We use the complex addrmode_imm12 rather than just an input
1579 // GPR and a constrained immediate so that we can use this to match
1580 // frame index references and avoid matching constant pool references.
1581 def i12 : AI2ldst<0b010, 0, isByte, (outs),
1582 (ins GPRnopc:$Rt, addrmode_imm12:$addr),
1583 AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
1584 [(opnode GPRnopc:$Rt, addrmode_imm12:$addr)]> {
1587 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1588 let Inst{19-16} = addr{16-13}; // Rn
1589 let Inst{15-12} = Rt;
1590 let Inst{11-0} = addr{11-0}; // imm12
1592 def rs : AI2ldst<0b011, 0, isByte, (outs), (ins GPRnopc:$Rt, ldst_so_reg:$shift),
1593 AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
1594 [(opnode GPRnopc:$Rt, ldst_so_reg:$shift)]> {
1597 let shift{4} = 0; // Inst{4} = 0
1598 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1599 let Inst{19-16} = shift{16-13}; // Rn
1600 let Inst{15-12} = Rt;
1601 let Inst{11-0} = shift{11-0};
1606 //===----------------------------------------------------------------------===//
1608 //===----------------------------------------------------------------------===//
1610 //===----------------------------------------------------------------------===//
1611 // Miscellaneous Instructions.
1614 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool in
1615 /// the function. The first operand is the ID# for this instruction, the second
1616 /// is the index into the MachineConstantPool that this is, the third is the
1617 /// size in bytes of this constant pool entry.
1618 let neverHasSideEffects = 1, isNotDuplicable = 1 in
1619 def CONSTPOOL_ENTRY :
1620 PseudoInst<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
1621 i32imm:$size), NoItinerary, []>;
1623 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
1624 // from removing one half of the matched pairs. That breaks PEI, which assumes
1625 // these will always be in pairs, and asserts if it finds otherwise. Better way?
1626 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1627 def ADJCALLSTACKUP :
1628 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2, pred:$p), NoItinerary,
1629 [(ARMcallseq_end timm:$amt1, timm:$amt2)]>;
1631 def ADJCALLSTACKDOWN :
1632 PseudoInst<(outs), (ins i32imm:$amt, pred:$p), NoItinerary,
1633 [(ARMcallseq_start timm:$amt)]>;
1636 // Atomic pseudo-insts which will be lowered to ldrexd/strexd loops.
1637 // (These psuedos use a hand-written selection code).
1638 let usesCustomInserter = 1, Uses = [CPSR] in {
1639 def ATOMOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1640 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1642 def ATOMXOR6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1643 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1645 def ATOMADD6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1646 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1648 def ATOMSUB6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1649 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1651 def ATOMNAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1652 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1654 def ATOMAND6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1655 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1657 def ATOMSWAP6432 : PseudoInst<(outs GPR:$dst1, GPR:$dst2),
1658 (ins GPR:$addr, GPR:$src1, GPR:$src2),
1662 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1663 Requires<[IsARM, HasV6T2]> {
1664 let Inst{27-16} = 0b001100100000;
1665 let Inst{15-8} = 0b11110000;
1666 let Inst{7-0} = 0b00000000;
1669 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1670 Requires<[IsARM, HasV6T2]> {
1671 let Inst{27-16} = 0b001100100000;
1672 let Inst{15-8} = 0b11110000;
1673 let Inst{7-0} = 0b00000001;
1676 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1677 Requires<[IsARM, HasV6T2]> {
1678 let Inst{27-16} = 0b001100100000;
1679 let Inst{15-8} = 0b11110000;
1680 let Inst{7-0} = 0b00000010;
1683 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1684 Requires<[IsARM, HasV6T2]> {
1685 let Inst{27-16} = 0b001100100000;
1686 let Inst{15-8} = 0b11110000;
1687 let Inst{7-0} = 0b00000011;
1690 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
1691 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
1696 let Inst{15-12} = Rd;
1697 let Inst{19-16} = Rn;
1698 let Inst{27-20} = 0b01101000;
1699 let Inst{7-4} = 0b1011;
1700 let Inst{11-8} = 0b1111;
1703 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1704 []>, Requires<[IsARM, HasV6T2]> {
1705 let Inst{27-16} = 0b001100100000;
1706 let Inst{15-8} = 0b11110000;
1707 let Inst{7-0} = 0b00000100;
1710 // The i32imm operand $val can be used by a debugger to store more information
1711 // about the breakpoint.
1712 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
1713 "bkpt", "\t$val", []>, Requires<[IsARM]> {
1715 let Inst{3-0} = val{3-0};
1716 let Inst{19-8} = val{15-4};
1717 let Inst{27-20} = 0b00010010;
1718 let Inst{7-4} = 0b0111;
1721 // Change Processor State
1722 // FIXME: We should use InstAlias to handle the optional operands.
1723 class CPS<dag iops, string asm_ops>
1724 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
1725 []>, Requires<[IsARM]> {
1731 let Inst{31-28} = 0b1111;
1732 let Inst{27-20} = 0b00010000;
1733 let Inst{19-18} = imod;
1734 let Inst{17} = M; // Enabled if mode is set;
1736 let Inst{8-6} = iflags;
1738 let Inst{4-0} = mode;
1741 let DecoderMethod = "DecodeCPSInstruction" in {
1743 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1744 "$imod\t$iflags, $mode">;
1745 let mode = 0, M = 0 in
1746 def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
1748 let imod = 0, iflags = 0, M = 1 in
1749 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1752 // Preload signals the memory system of possible future data/instruction access.
1753 multiclass APreLoad<bits<1> read, bits<1> data, string opc> {
1755 def i12 : AXI<(outs), (ins addrmode_imm12:$addr), MiscFrm, IIC_Preload,
1756 !strconcat(opc, "\t$addr"),
1757 [(ARMPreload addrmode_imm12:$addr, (i32 read), (i32 data))]> {
1760 let Inst{31-26} = 0b111101;
1761 let Inst{25} = 0; // 0 for immediate form
1762 let Inst{24} = data;
1763 let Inst{23} = addr{12}; // U (add = ('U' == 1))
1764 let Inst{22} = read;
1765 let Inst{21-20} = 0b01;
1766 let Inst{19-16} = addr{16-13}; // Rn
1767 let Inst{15-12} = 0b1111;
1768 let Inst{11-0} = addr{11-0}; // imm12
1771 def rs : AXI<(outs), (ins ldst_so_reg:$shift), MiscFrm, IIC_Preload,
1772 !strconcat(opc, "\t$shift"),
1773 [(ARMPreload ldst_so_reg:$shift, (i32 read), (i32 data))]> {
1775 let Inst{31-26} = 0b111101;
1776 let Inst{25} = 1; // 1 for register form
1777 let Inst{24} = data;
1778 let Inst{23} = shift{12}; // U (add = ('U' == 1))
1779 let Inst{22} = read;
1780 let Inst{21-20} = 0b01;
1781 let Inst{19-16} = shift{16-13}; // Rn
1782 let Inst{15-12} = 0b1111;
1783 let Inst{11-0} = shift{11-0};
1788 defm PLD : APreLoad<1, 1, "pld">, Requires<[IsARM]>;
1789 defm PLDW : APreLoad<0, 1, "pldw">, Requires<[IsARM,HasV7,HasMP]>;
1790 defm PLI : APreLoad<1, 0, "pli">, Requires<[IsARM,HasV7]>;
1792 def SETEND : AXI<(outs), (ins setend_op:$end), MiscFrm, NoItinerary,
1793 "setend\t$end", []>, Requires<[IsARM]> {
1795 let Inst{31-10} = 0b1111000100000001000000;
1800 def DBG : AI<(outs), (ins imm0_15:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt",
1801 []>, Requires<[IsARM, HasV7]> {
1803 let Inst{27-4} = 0b001100100000111100001111;
1804 let Inst{3-0} = opt;
1807 // A5.4 Permanently UNDEFINED instructions.
1808 let isBarrier = 1, isTerminator = 1 in
1809 def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
1812 let Inst = 0xe7ffdefe;
1815 // Address computation and loads and stores in PIC mode.
1816 let isNotDuplicable = 1 in {
1817 def PICADD : ARMPseudoInst<(outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
1819 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
1821 let AddedComplexity = 10 in {
1822 def PICLDR : ARMPseudoInst<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
1824 [(set GPR:$dst, (load addrmodepc:$addr))]>;
1826 def PICLDRH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1828 [(set GPR:$Rt, (zextloadi16 addrmodepc:$addr))]>;
1830 def PICLDRB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1832 [(set GPR:$Rt, (zextloadi8 addrmodepc:$addr))]>;
1834 def PICLDRSH : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1836 [(set GPR:$Rt, (sextloadi16 addrmodepc:$addr))]>;
1838 def PICLDRSB : ARMPseudoInst<(outs GPR:$Rt), (ins addrmodepc:$addr, pred:$p),
1840 [(set GPR:$Rt, (sextloadi8 addrmodepc:$addr))]>;
1842 let AddedComplexity = 10 in {
1843 def PICSTR : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1844 4, IIC_iStore_r, [(store GPR:$src, addrmodepc:$addr)]>;
1846 def PICSTRH : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1847 4, IIC_iStore_bh_r, [(truncstorei16 GPR:$src,
1848 addrmodepc:$addr)]>;
1850 def PICSTRB : ARMPseudoInst<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
1851 4, IIC_iStore_bh_r, [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
1853 } // isNotDuplicable = 1
1856 // LEApcrel - Load a pc-relative address into a register without offending the
1858 let neverHasSideEffects = 1, isReMaterializable = 1 in
1859 // The 'adr' mnemonic encodes differently if the label is before or after
1860 // the instruction. The {24-21} opcode bits are set by the fixup, as we don't
1861 // know until then which form of the instruction will be used.
1862 def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
1863 MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
1866 let Inst{27-25} = 0b001;
1868 let Inst{23-22} = label{13-12};
1871 let Inst{19-16} = 0b1111;
1872 let Inst{15-12} = Rd;
1873 let Inst{11-0} = label{11-0};
1875 def LEApcrel : ARMPseudoInst<(outs GPR:$Rd), (ins i32imm:$label, pred:$p),
1878 def LEApcrelJT : ARMPseudoInst<(outs GPR:$Rd),
1879 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1882 //===----------------------------------------------------------------------===//
1883 // Control Flow Instructions.
1886 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1888 def BX_RET : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1889 "bx", "\tlr", [(ARMretflag)]>,
1890 Requires<[IsARM, HasV4T]> {
1891 let Inst{27-0} = 0b0001001011111111111100011110;
1895 def MOVPCLR : AI<(outs), (ins), BrMiscFrm, IIC_Br,
1896 "mov", "\tpc, lr", [(ARMretflag)]>,
1897 Requires<[IsARM, NoV4T]> {
1898 let Inst{27-0} = 0b0001101000001111000000001110;
1902 // Indirect branches
1903 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1905 def BX : AXI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br, "bx\t$dst",
1906 [(brind GPR:$dst)]>,
1907 Requires<[IsARM, HasV4T]> {
1909 let Inst{31-4} = 0b1110000100101111111111110001;
1910 let Inst{3-0} = dst;
1913 def BX_pred : AI<(outs), (ins GPR:$dst), BrMiscFrm, IIC_Br,
1914 "bx", "\t$dst", [/* pattern left blank */]>,
1915 Requires<[IsARM, HasV4T]> {
1917 let Inst{27-4} = 0b000100101111111111110001;
1918 let Inst{3-0} = dst;
1922 // All calls clobber the non-callee saved registers. SP is marked as
1923 // a use to prevent stack-pointer assignments that appear immediately
1924 // before calls from potentially appearing dead.
1926 // On non-Darwin platforms R9 is callee-saved.
1927 // FIXME: Do we really need a non-predicated version? If so, it should
1928 // at least be a pseudo instruction expanding to the predicated version
1929 // at MC lowering time.
1930 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1932 def BL : ABXI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1933 IIC_Br, "bl\t$func",
1934 [(ARMcall tglobaladdr:$func)]>,
1935 Requires<[IsARM, IsNotDarwin]> {
1936 let Inst{31-28} = 0b1110;
1938 let Inst{23-0} = func;
1939 let DecoderMethod = "DecodeBranchImmInstruction";
1942 def BL_pred : ABI<0b1011, (outs), (ins bl_target:$func, variable_ops),
1943 IIC_Br, "bl", "\t$func",
1944 [(ARMcall_pred tglobaladdr:$func)]>,
1945 Requires<[IsARM, IsNotDarwin]> {
1947 let Inst{23-0} = func;
1948 let DecoderMethod = "DecodeBranchImmInstruction";
1952 def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1953 IIC_Br, "blx\t$func",
1954 [(ARMcall GPR:$func)]>,
1955 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1957 let Inst{31-4} = 0b1110000100101111111111110011;
1958 let Inst{3-0} = func;
1961 def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
1962 IIC_Br, "blx", "\t$func",
1963 [(ARMcall_pred GPR:$func)]>,
1964 Requires<[IsARM, HasV5T, IsNotDarwin]> {
1966 let Inst{27-4} = 0b000100101111111111110011;
1967 let Inst{3-0} = func;
1971 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
1972 def BX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1973 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1974 Requires<[IsARM, HasV4T, IsNotDarwin]>;
1977 def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
1978 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
1979 Requires<[IsARM, NoV4T, IsNotDarwin]>;
1983 // On Darwin R9 is call-clobbered.
1984 // R7 is marked as a use to prevent frame-pointer assignments from being
1985 // moved above / below calls.
1986 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
1987 Uses = [R7, SP] in {
1988 def BLr9 : ARMPseudoExpand<(outs), (ins bl_target:$func, variable_ops),
1990 [(ARMcall tglobaladdr:$func)], (BL bl_target:$func)>,
1991 Requires<[IsARM, IsDarwin]>;
1993 def BLr9_pred : ARMPseudoExpand<(outs),
1994 (ins bl_target:$func, pred:$p, variable_ops),
1996 [(ARMcall_pred tglobaladdr:$func)],
1997 (BL_pred bl_target:$func, pred:$p)>,
1998 Requires<[IsARM, IsDarwin]>;
2001 def BLXr9 : ARMPseudoExpand<(outs), (ins GPR:$func, variable_ops),
2003 [(ARMcall GPR:$func)],
2005 Requires<[IsARM, HasV5T, IsDarwin]>;
2007 def BLXr9_pred: ARMPseudoExpand<(outs), (ins GPR:$func, pred:$p,variable_ops),
2009 [(ARMcall_pred GPR:$func)],
2010 (BLX_pred GPR:$func, pred:$p)>,
2011 Requires<[IsARM, HasV5T, IsDarwin]>;
2014 // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
2015 def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
2016 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2017 Requires<[IsARM, HasV4T, IsDarwin]>;
2020 def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
2021 8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
2022 Requires<[IsARM, NoV4T, IsDarwin]>;
2025 let isBranch = 1, isTerminator = 1 in {
2026 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
2027 // a two-value operand where a dag node expects two operands. :(
2028 def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
2029 IIC_Br, "b", "\t$target",
2030 [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
2032 let Inst{23-0} = target;
2033 let DecoderMethod = "DecodeBranchImmInstruction";
2036 let isBarrier = 1 in {
2037 // B is "predicable" since it's just a Bcc with an 'always' condition.
2038 let isPredicable = 1 in
2039 // FIXME: We shouldn't need this pseudo at all. Just using Bcc directly
2040 // should be sufficient.
2041 // FIXME: Is B really a Barrier? That doesn't seem right.
2042 def B : ARMPseudoExpand<(outs), (ins br_target:$target), 4, IIC_Br,
2043 [(br bb:$target)], (Bcc br_target:$target, (ops 14, zero_reg))>;
2045 let isNotDuplicable = 1, isIndirectBranch = 1 in {
2046 def BR_JTr : ARMPseudoInst<(outs),
2047 (ins GPR:$target, i32imm:$jt, i32imm:$id),
2049 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
2050 // FIXME: This shouldn't use the generic "addrmode2," but rather be split
2051 // into i12 and rs suffixed versions.
2052 def BR_JTm : ARMPseudoInst<(outs),
2053 (ins addrmode2:$target, i32imm:$jt, i32imm:$id),
2055 [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
2057 def BR_JTadd : ARMPseudoInst<(outs),
2058 (ins GPR:$target, GPR:$idx, i32imm:$jt, i32imm:$id),
2060 [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
2062 } // isNotDuplicable = 1, isIndirectBranch = 1
2068 def BLXi : AXI<(outs), (ins blx_target:$target), BrMiscFrm, NoItinerary,
2069 "blx\t$target", []>,
2070 Requires<[IsARM, HasV5T]> {
2071 let Inst{31-25} = 0b1111101;
2073 let Inst{23-0} = target{24-1};
2074 let Inst{24} = target{0};
2077 // Branch and Exchange Jazelle
2078 def BXJ : ABI<0b0001, (outs), (ins GPR:$func), NoItinerary, "bxj", "\t$func",
2079 [/* pattern left blank */]> {
2081 let Inst{23-20} = 0b0010;
2082 let Inst{19-8} = 0xfff;
2083 let Inst{7-4} = 0b0010;
2084 let Inst{3-0} = func;
2089 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
2091 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2093 def TCRETURNdi : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2094 IIC_Br, []>, Requires<[IsDarwin]>;
2096 def TCRETURNri : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2097 IIC_Br, []>, Requires<[IsDarwin]>;
2099 def TAILJMPd : ARMPseudoExpand<(outs), (ins br_target:$dst, variable_ops),
2101 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2102 Requires<[IsARM, IsDarwin]>;
2104 def TAILJMPr : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2107 Requires<[IsARM, IsDarwin]>;
2111 // Non-Darwin versions (the difference is R9).
2112 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
2114 def TCRETURNdiND : PseudoInst<(outs), (ins i32imm:$dst, variable_ops),
2115 IIC_Br, []>, Requires<[IsNotDarwin]>;
2117 def TCRETURNriND : PseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
2118 IIC_Br, []>, Requires<[IsNotDarwin]>;
2120 def TAILJMPdND : ARMPseudoExpand<(outs), (ins brtarget:$dst, variable_ops),
2122 (Bcc br_target:$dst, (ops 14, zero_reg))>,
2123 Requires<[IsARM, IsNotDarwin]>;
2125 def TAILJMPrND : ARMPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
2128 Requires<[IsARM, IsNotDarwin]>;
2132 // Secure Monitor Call is a system instruction.
2133 def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
2136 let Inst{23-4} = 0b01100000000000000111;
2137 let Inst{3-0} = opt;
2140 // Supervisor Call (Software Interrupt)
2141 let isCall = 1, Uses = [SP] in {
2142 def SVC : ABI<0b1111, (outs), (ins imm24b:$svc), IIC_Br, "svc", "\t$svc", []> {
2144 let Inst{23-0} = svc;
2148 // Store Return State
2149 class SRSI<bit wb, string asm>
2150 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
2151 NoItinerary, asm, "", []> {
2153 let Inst{31-28} = 0b1111;
2154 let Inst{27-25} = 0b100;
2158 let Inst{19-16} = 0b1101; // SP
2159 let Inst{15-5} = 0b00000101000;
2160 let Inst{4-0} = mode;
2163 def SRSDA : SRSI<0, "srsda\tsp, $mode"> {
2164 let Inst{24-23} = 0;
2166 def SRSDA_UPD : SRSI<1, "srsda\tsp!, $mode"> {
2167 let Inst{24-23} = 0;
2169 def SRSDB : SRSI<0, "srsdb\tsp, $mode"> {
2170 let Inst{24-23} = 0b10;
2172 def SRSDB_UPD : SRSI<1, "srsdb\tsp!, $mode"> {
2173 let Inst{24-23} = 0b10;
2175 def SRSIA : SRSI<0, "srsia\tsp, $mode"> {
2176 let Inst{24-23} = 0b01;
2178 def SRSIA_UPD : SRSI<1, "srsia\tsp!, $mode"> {
2179 let Inst{24-23} = 0b01;
2181 def SRSIB : SRSI<0, "srsib\tsp, $mode"> {
2182 let Inst{24-23} = 0b11;
2184 def SRSIB_UPD : SRSI<1, "srsib\tsp!, $mode"> {
2185 let Inst{24-23} = 0b11;
2188 // Return From Exception
2189 class RFEI<bit wb, string asm>
2190 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2191 NoItinerary, asm, "", []> {
2193 let Inst{31-28} = 0b1111;
2194 let Inst{27-25} = 0b100;
2198 let Inst{19-16} = Rn;
2199 let Inst{15-0} = 0xa00;
2202 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2203 let Inst{24-23} = 0;
2205 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2206 let Inst{24-23} = 0;
2208 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2209 let Inst{24-23} = 0b10;
2211 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2212 let Inst{24-23} = 0b10;
2214 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2215 let Inst{24-23} = 0b01;
2217 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2218 let Inst{24-23} = 0b01;
2220 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2221 let Inst{24-23} = 0b11;
2223 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2224 let Inst{24-23} = 0b11;
2227 //===----------------------------------------------------------------------===//
2228 // Load / store Instructions.
2234 defm LDR : AI_ldr1<0, "ldr", IIC_iLoad_r, IIC_iLoad_si,
2235 UnOpFrag<(load node:$Src)>>;
2236 defm LDRB : AI_ldr1nopc<1, "ldrb", IIC_iLoad_bh_r, IIC_iLoad_bh_si,
2237 UnOpFrag<(zextloadi8 node:$Src)>>;
2238 defm STR : AI_str1<0, "str", IIC_iStore_r, IIC_iStore_si,
2239 BinOpFrag<(store node:$LHS, node:$RHS)>>;
2240 defm STRB : AI_str1nopc<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
2241 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
2243 // Special LDR for loads from non-pc-relative constpools.
2244 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
2245 isReMaterializable = 1, isCodeGenOnly = 1 in
2246 def LDRcp : AI2ldst<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2247 AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
2251 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2252 let Inst{19-16} = 0b1111;
2253 let Inst{15-12} = Rt;
2254 let Inst{11-0} = addr{11-0}; // imm12
2257 // Loads with zero extension
2258 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2259 IIC_iLoad_bh_r, "ldrh", "\t$Rt, $addr",
2260 [(set GPR:$Rt, (zextloadi16 addrmode3:$addr))]>;
2262 // Loads with sign extension
2263 def LDRSH : AI3ld<0b1111, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2264 IIC_iLoad_bh_r, "ldrsh", "\t$Rt, $addr",
2265 [(set GPR:$Rt, (sextloadi16 addrmode3:$addr))]>;
2267 def LDRSB : AI3ld<0b1101, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2268 IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
2269 [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
2271 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2273 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
2274 (ins addrmode3:$addr), LdMiscFrm,
2275 IIC_iLoad_d_r, "ldrd", "\t$Rd, $dst2, $addr",
2276 []>, Requires<[IsARM, HasV5TE]>;
2280 multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
2281 def _PRE_IMM : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2282 (ins addrmode_imm12:$addr), IndexModePre, LdFrm, itin,
2283 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2286 let Inst{23} = addr{12};
2287 let Inst{19-16} = addr{16-13};
2288 let Inst{11-0} = addr{11-0};
2289 let DecoderMethod = "DecodeLDRPreImm";
2290 let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
2293 def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2294 (ins ldst_so_reg:$addr), IndexModePre, LdFrm, itin,
2295 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2298 let Inst{23} = addr{12};
2299 let Inst{19-16} = addr{16-13};
2300 let Inst{11-0} = addr{11-0};
2302 let DecoderMethod = "DecodeLDRPreReg";
2303 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
2306 def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2307 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2308 IndexModePost, LdFrm, itin,
2309 opc, "\t$Rt, $addr, $offset",
2310 "$addr.base = $Rn_wb", []> {
2316 let Inst{23} = offset{12};
2317 let Inst{19-16} = addr;
2318 let Inst{11-0} = offset{11-0};
2320 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2323 def _POST_IMM : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2324 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2325 IndexModePost, LdFrm, itin,
2326 opc, "\t$Rt, $addr, $offset",
2327 "$addr.base = $Rn_wb", []> {
2333 let Inst{23} = offset{12};
2334 let Inst{19-16} = addr;
2335 let Inst{11-0} = offset{11-0};
2337 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2342 let mayLoad = 1, neverHasSideEffects = 1 in {
2343 defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
2344 defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>;
2347 multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
2348 def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
2349 (ins addrmode3:$addr), IndexModePre,
2351 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2353 let Inst{23} = addr{8}; // U bit
2354 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2355 let Inst{19-16} = addr{12-9}; // Rn
2356 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2357 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2358 let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
2359 let DecoderMethod = "DecodeAddrMode3Instruction";
2361 def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2362 (ins addr_offset_none:$addr, am3offset:$offset),
2363 IndexModePost, LdMiscFrm, itin,
2364 opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2368 let Inst{23} = offset{8}; // U bit
2369 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2370 let Inst{19-16} = addr;
2371 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2372 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2373 let DecoderMethod = "DecodeAddrMode3Instruction";
2377 let mayLoad = 1, neverHasSideEffects = 1 in {
2378 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2379 defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>;
2380 defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>;
2381 let hasExtraDefRegAllocReq = 1 in {
2382 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2383 (ins addrmode3:$addr), IndexModePre,
2384 LdMiscFrm, IIC_iLoad_d_ru,
2385 "ldrd", "\t$Rt, $Rt2, $addr!",
2386 "$addr.base = $Rn_wb", []> {
2388 let Inst{23} = addr{8}; // U bit
2389 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2390 let Inst{19-16} = addr{12-9}; // Rn
2391 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2392 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2393 let DecoderMethod = "DecodeAddrMode3Instruction";
2394 let AsmMatchConverter = "cvtLdrdPre";
2396 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
2397 (ins addr_offset_none:$addr, am3offset:$offset),
2398 IndexModePost, LdMiscFrm, IIC_iLoad_d_ru,
2399 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
2400 "$addr.base = $Rn_wb", []> {
2403 let Inst{23} = offset{8}; // U bit
2404 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2405 let Inst{19-16} = addr;
2406 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2407 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2408 let DecoderMethod = "DecodeAddrMode3Instruction";
2410 } // hasExtraDefRegAllocReq = 1
2411 } // mayLoad = 1, neverHasSideEffects = 1
2413 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT.
2414 let mayLoad = 1, neverHasSideEffects = 1 in {
2415 def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2416 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2417 IndexModePost, LdFrm, IIC_iLoad_ru,
2418 "ldrt", "\t$Rt, $addr, $offset",
2419 "$addr.base = $Rn_wb", []> {
2425 let Inst{23} = offset{12};
2426 let Inst{21} = 1; // overwrite
2427 let Inst{19-16} = addr;
2428 let Inst{11-5} = offset{11-5};
2430 let Inst{3-0} = offset{3-0};
2431 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2434 def LDRT_POST_IMM : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2435 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2436 IndexModePost, LdFrm, IIC_iLoad_ru,
2437 "ldrt", "\t$Rt, $addr, $offset",
2438 "$addr.base = $Rn_wb", []> {
2444 let Inst{23} = offset{12};
2445 let Inst{21} = 1; // overwrite
2446 let Inst{19-16} = addr;
2447 let Inst{11-0} = offset{11-0};
2448 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2451 def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2452 (ins addr_offset_none:$addr, am2offset_reg:$offset),
2453 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2454 "ldrbt", "\t$Rt, $addr, $offset",
2455 "$addr.base = $Rn_wb", []> {
2461 let Inst{23} = offset{12};
2462 let Inst{21} = 1; // overwrite
2463 let Inst{19-16} = addr;
2464 let Inst{11-5} = offset{11-5};
2466 let Inst{3-0} = offset{3-0};
2467 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2470 def LDRBT_POST_IMM : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
2471 (ins addr_offset_none:$addr, am2offset_imm:$offset),
2472 IndexModePost, LdFrm, IIC_iLoad_bh_ru,
2473 "ldrbt", "\t$Rt, $addr, $offset",
2474 "$addr.base = $Rn_wb", []> {
2480 let Inst{23} = offset{12};
2481 let Inst{21} = 1; // overwrite
2482 let Inst{19-16} = addr;
2483 let Inst{11-0} = offset{11-0};
2484 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2487 multiclass AI3ldrT<bits<4> op, string opc> {
2488 def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2489 (ins addr_offset_none:$addr, postidx_imm8:$offset),
2490 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2491 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2493 let Inst{23} = offset{8};
2495 let Inst{11-8} = offset{7-4};
2496 let Inst{3-0} = offset{3-0};
2497 let AsmMatchConverter = "cvtLdExtTWriteBackImm";
2499 def r : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
2500 (ins addr_offset_none:$addr, postidx_reg:$Rm),
2501 IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru, opc,
2502 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2504 let Inst{23} = Rm{4};
2507 let Inst{3-0} = Rm{3-0};
2508 let AsmMatchConverter = "cvtLdExtTWriteBackReg";
2512 defm LDRSBT : AI3ldrT<0b1101, "ldrsbt">;
2513 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2514 defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
2519 // Stores with truncate
2520 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2521 IIC_iStore_bh_r, "strh", "\t$Rt, $addr",
2522 [(truncstorei16 GPR:$Rt, addrmode3:$addr)]>;
2525 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2526 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$src2, addrmode3:$addr),
2527 StMiscFrm, IIC_iStore_d_r,
2528 "strd", "\t$Rt, $src2, $addr", []>,
2529 Requires<[IsARM, HasV5TE]> {
2534 multiclass AI2_stridx<bit isByte, string opc, InstrItinClass itin> {
2535 def _PRE_IMM : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2536 (ins GPR:$Rt, addrmode_imm12:$addr), IndexModePre,
2538 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2541 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2542 let Inst{19-16} = addr{16-13}; // Rn
2543 let Inst{11-0} = addr{11-0}; // imm12
2544 let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
2545 let DecoderMethod = "DecodeSTRPreImm";
2548 def _PRE_REG : AI2ldstidx<0, isByte, 1, (outs GPR:$Rn_wb),
2549 (ins GPR:$Rt, ldst_so_reg:$addr),
2550 IndexModePre, StFrm, itin,
2551 opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2554 let Inst{23} = addr{12}; // U (add = ('U' == 1))
2555 let Inst{19-16} = addr{16-13}; // Rn
2556 let Inst{11-0} = addr{11-0};
2557 let Inst{4} = 0; // Inst{4} = 0
2558 let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
2559 let DecoderMethod = "DecodeSTRPreReg";
2561 def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2562 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2563 IndexModePost, StFrm, itin,
2564 opc, "\t$Rt, $addr, $offset",
2565 "$addr.base = $Rn_wb", []> {
2571 let Inst{23} = offset{12};
2572 let Inst{19-16} = addr;
2573 let Inst{11-0} = offset{11-0};
2575 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2578 def _POST_IMM : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
2579 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2580 IndexModePost, StFrm, itin,
2581 opc, "\t$Rt, $addr, $offset",
2582 "$addr.base = $Rn_wb", []> {
2588 let Inst{23} = offset{12};
2589 let Inst{19-16} = addr;
2590 let Inst{11-0} = offset{11-0};
2592 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2596 let mayStore = 1, neverHasSideEffects = 1 in {
2597 defm STR : AI2_stridx<0, "str", IIC_iStore_ru>;
2598 defm STRB : AI2_stridx<1, "strb", IIC_iStore_bh_ru>;
2601 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2602 am2offset_reg:$offset),
2603 (STR_POST_REG GPR:$Rt, addr_offset_none:$addr,
2604 am2offset_reg:$offset)>;
2605 def : ARMPat<(post_store GPR:$Rt, addr_offset_none:$addr,
2606 am2offset_imm:$offset),
2607 (STR_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2608 am2offset_imm:$offset)>;
2609 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2610 am2offset_reg:$offset),
2611 (STRB_POST_REG GPR:$Rt, addr_offset_none:$addr,
2612 am2offset_reg:$offset)>;
2613 def : ARMPat<(post_truncsti8 GPR:$Rt, addr_offset_none:$addr,
2614 am2offset_imm:$offset),
2615 (STRB_POST_IMM GPR:$Rt, addr_offset_none:$addr,
2616 am2offset_imm:$offset)>;
2618 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't
2619 // put the patterns on the instruction definitions directly as ISel wants
2620 // the address base and offset to be separate operands, not a single
2621 // complex operand like we represent the instructions themselves. The
2622 // pseudos map between the two.
2623 let usesCustomInserter = 1,
2624 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
2625 def STRi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2626 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2629 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2630 def STRr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2631 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2634 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2635 def STRBi_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2636 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
2639 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
2640 def STRBr_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2641 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
2644 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
2645 def STRH_preidx: ARMPseudoInst<(outs GPR:$Rn_wb),
2646 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
2649 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
2654 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2655 (ins GPR:$Rt, addrmode3:$addr), IndexModePre,
2656 StMiscFrm, IIC_iStore_bh_ru,
2657 "strh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
2659 let Inst{23} = addr{8}; // U bit
2660 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2661 let Inst{19-16} = addr{12-9}; // Rn
2662 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2663 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2664 let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
2665 let DecoderMethod = "DecodeAddrMode3Instruction";
2668 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
2669 (ins GPR:$Rt, addr_offset_none:$addr, am3offset:$offset),
2670 IndexModePost, StMiscFrm, IIC_iStore_bh_ru,
2671 "strh", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb",
2672 [(set GPR:$Rn_wb, (post_truncsti16 GPR:$Rt,
2673 addr_offset_none:$addr,
2674 am3offset:$offset))]> {
2677 let Inst{23} = offset{8}; // U bit
2678 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2679 let Inst{19-16} = addr;
2680 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2681 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2682 let DecoderMethod = "DecodeAddrMode3Instruction";
2685 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2686 def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
2687 (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
2688 IndexModePre, StMiscFrm, IIC_iStore_d_ru,
2689 "strd", "\t$Rt, $Rt2, $addr!",
2690 "$addr.base = $Rn_wb", []> {
2692 let Inst{23} = addr{8}; // U bit
2693 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
2694 let Inst{19-16} = addr{12-9}; // Rn
2695 let Inst{11-8} = addr{7-4}; // imm7_4/zero
2696 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
2697 let DecoderMethod = "DecodeAddrMode3Instruction";
2698 let AsmMatchConverter = "cvtStrdPre";
2701 def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
2702 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr,
2704 IndexModePost, StMiscFrm, IIC_iStore_d_ru,
2705 "strd", "\t$Rt, $Rt2, $addr, $offset",
2706 "$addr.base = $Rn_wb", []> {
2709 let Inst{23} = offset{8}; // U bit
2710 let Inst{22} = offset{9}; // 1 == imm8, 0 == Rm
2711 let Inst{19-16} = addr;
2712 let Inst{11-8} = offset{7-4}; // imm7_4/zero
2713 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
2714 let DecoderMethod = "DecodeAddrMode3Instruction";
2716 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2718 // STRT, STRBT, and STRHT
2720 def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2721 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2722 IndexModePost, StFrm, IIC_iStore_bh_ru,
2723 "strbt", "\t$Rt, $addr, $offset",
2724 "$addr.base = $Rn_wb", []> {
2730 let Inst{23} = offset{12};
2731 let Inst{21} = 1; // overwrite
2732 let Inst{19-16} = addr;
2733 let Inst{11-5} = offset{11-5};
2735 let Inst{3-0} = offset{3-0};
2736 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2739 def STRBT_POST_IMM : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
2740 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2741 IndexModePost, StFrm, IIC_iStore_bh_ru,
2742 "strbt", "\t$Rt, $addr, $offset",
2743 "$addr.base = $Rn_wb", []> {
2749 let Inst{23} = offset{12};
2750 let Inst{21} = 1; // overwrite
2751 let Inst{19-16} = addr;
2752 let Inst{11-0} = offset{11-0};
2753 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2756 let mayStore = 1, neverHasSideEffects = 1 in {
2757 def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2758 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_reg:$offset),
2759 IndexModePost, StFrm, IIC_iStore_ru,
2760 "strt", "\t$Rt, $addr, $offset",
2761 "$addr.base = $Rn_wb", []> {
2767 let Inst{23} = offset{12};
2768 let Inst{21} = 1; // overwrite
2769 let Inst{19-16} = addr;
2770 let Inst{11-5} = offset{11-5};
2772 let Inst{3-0} = offset{3-0};
2773 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2776 def STRT_POST_IMM : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
2777 (ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
2778 IndexModePost, StFrm, IIC_iStore_ru,
2779 "strt", "\t$Rt, $addr, $offset",
2780 "$addr.base = $Rn_wb", []> {
2786 let Inst{23} = offset{12};
2787 let Inst{21} = 1; // overwrite
2788 let Inst{19-16} = addr;
2789 let Inst{11-0} = offset{11-0};
2790 let DecoderMethod = "DecodeAddrMode2IdxInstruction";
2795 multiclass AI3strT<bits<4> op, string opc> {
2796 def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2797 (ins GPR:$Rt, addr_offset_none:$addr, postidx_imm8:$offset),
2798 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2799 "\t$Rt, $addr, $offset", "$addr.base = $base_wb", []> {
2801 let Inst{23} = offset{8};
2803 let Inst{11-8} = offset{7-4};
2804 let Inst{3-0} = offset{3-0};
2805 let AsmMatchConverter = "cvtStExtTWriteBackImm";
2807 def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
2808 (ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
2809 IndexModePost, StMiscFrm, IIC_iStore_bh_ru, opc,
2810 "\t$Rt, $addr, $Rm", "$addr.base = $base_wb", []> {
2812 let Inst{23} = Rm{4};
2815 let Inst{3-0} = Rm{3-0};
2816 let AsmMatchConverter = "cvtStExtTWriteBackReg";
2821 defm STRHT : AI3strT<0b1011, "strht">;
2824 //===----------------------------------------------------------------------===//
2825 // Load / store multiple Instructions.
2828 multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
2829 InstrItinClass itin, InstrItinClass itin_upd> {
2830 // IA is the default, so no need for an explicit suffix on the
2831 // mnemonic here. Without it is the cannonical spelling.
2833 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2834 IndexModeNone, f, itin,
2835 !strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
2836 let Inst{24-23} = 0b01; // Increment After
2837 let Inst{21} = 0; // No writeback
2838 let Inst{20} = L_bit;
2841 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2842 IndexModeUpd, f, itin_upd,
2843 !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2844 let Inst{24-23} = 0b01; // Increment After
2845 let Inst{21} = 1; // Writeback
2846 let Inst{20} = L_bit;
2848 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2851 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2852 IndexModeNone, f, itin,
2853 !strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
2854 let Inst{24-23} = 0b00; // Decrement After
2855 let Inst{21} = 0; // No writeback
2856 let Inst{20} = L_bit;
2859 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2860 IndexModeUpd, f, itin_upd,
2861 !strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2862 let Inst{24-23} = 0b00; // Decrement After
2863 let Inst{21} = 1; // Writeback
2864 let Inst{20} = L_bit;
2866 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2869 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2870 IndexModeNone, f, itin,
2871 !strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
2872 let Inst{24-23} = 0b10; // Decrement Before
2873 let Inst{21} = 0; // No writeback
2874 let Inst{20} = L_bit;
2877 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2878 IndexModeUpd, f, itin_upd,
2879 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2880 let Inst{24-23} = 0b10; // Decrement Before
2881 let Inst{21} = 1; // Writeback
2882 let Inst{20} = L_bit;
2884 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2887 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2888 IndexModeNone, f, itin,
2889 !strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
2890 let Inst{24-23} = 0b11; // Increment Before
2891 let Inst{21} = 0; // No writeback
2892 let Inst{20} = L_bit;
2895 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
2896 IndexModeUpd, f, itin_upd,
2897 !strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
2898 let Inst{24-23} = 0b11; // Increment Before
2899 let Inst{21} = 1; // Writeback
2900 let Inst{20} = L_bit;
2902 let DecoderMethod = "DecodeMemMultipleWritebackInstruction";
2906 let neverHasSideEffects = 1 in {
2908 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2909 defm LDM : arm_ldst_mult<"ldm", 1, LdStMulFrm, IIC_iLoad_m, IIC_iLoad_mu>;
2911 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
2912 defm STM : arm_ldst_mult<"stm", 0, LdStMulFrm, IIC_iStore_m, IIC_iStore_mu>;
2914 } // neverHasSideEffects
2916 // FIXME: remove when we have a way to marking a MI with these properties.
2917 // FIXME: Should pc be an implicit operand like PICADD, etc?
2918 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
2919 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
2920 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
2921 reglist:$regs, variable_ops),
2922 4, IIC_iLoad_mBr, [],
2923 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
2924 RegConstraint<"$Rn = $wb">;
2926 //===----------------------------------------------------------------------===//
2927 // Move Instructions.
2930 let neverHasSideEffects = 1 in
2931 def MOVr : AsI1<0b1101, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMOVr,
2932 "mov", "\t$Rd, $Rm", []>, UnaryDP {
2936 let Inst{19-16} = 0b0000;
2937 let Inst{11-4} = 0b00000000;
2940 let Inst{15-12} = Rd;
2943 // A version for the smaller set of tail call registers.
2944 let neverHasSideEffects = 1 in
2945 def MOVr_TC : AsI1<0b1101, (outs tcGPR:$Rd), (ins tcGPR:$Rm), DPFrm,
2946 IIC_iMOVr, "mov", "\t$Rd, $Rm", []>, UnaryDP {
2950 let Inst{11-4} = 0b00000000;
2953 let Inst{15-12} = Rd;
2956 def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
2957 DPSoRegRegFrm, IIC_iMOVsr,
2958 "mov", "\t$Rd, $src",
2959 [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>, UnaryDP {
2962 let Inst{15-12} = Rd;
2963 let Inst{19-16} = 0b0000;
2964 let Inst{11-8} = src{11-8};
2966 let Inst{6-5} = src{6-5};
2968 let Inst{3-0} = src{3-0};
2972 def MOVsi : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_imm:$src),
2973 DPSoRegImmFrm, IIC_iMOVsr,
2974 "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_imm:$src)]>,
2978 let Inst{15-12} = Rd;
2979 let Inst{19-16} = 0b0000;
2980 let Inst{11-5} = src{11-5};
2982 let Inst{3-0} = src{3-0};
2986 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2987 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
2988 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP {
2992 let Inst{15-12} = Rd;
2993 let Inst{19-16} = 0b0000;
2994 let Inst{11-0} = imm;
2997 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
2998 def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
3000 "movw", "\t$Rd, $imm",
3001 [(set GPR:$Rd, imm0_65535:$imm)]>,
3002 Requires<[IsARM, HasV6T2]>, UnaryDP {
3005 let Inst{15-12} = Rd;
3006 let Inst{11-0} = imm{11-0};
3007 let Inst{19-16} = imm{15-12};
3012 def : InstAlias<"mov${p} $Rd, $imm",
3013 (MOVi16 GPR:$Rd, imm0_65535_expr:$imm, pred:$p)>,
3016 def MOVi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3017 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3019 let Constraints = "$src = $Rd" in {
3020 def MOVTi16 : AI1<0b1010, (outs GPRnopc:$Rd),
3021 (ins GPR:$src, imm0_65535_expr:$imm),
3023 "movt", "\t$Rd, $imm",
3025 (or (and GPR:$src, 0xffff),
3026 lo16AllZero:$imm))]>, UnaryDP,
3027 Requires<[IsARM, HasV6T2]> {
3030 let Inst{15-12} = Rd;
3031 let Inst{11-0} = imm{11-0};
3032 let Inst{19-16} = imm{15-12};
3037 def MOVTi16_ga_pcrel : PseudoInst<(outs GPR:$Rd),
3038 (ins GPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
3042 def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
3043 Requires<[IsARM, HasV6T2]>;
3045 let Uses = [CPSR] in
3046 def RRX: PseudoInst<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVsi,
3047 [(set GPR:$Rd, (ARMrrx GPR:$Rm))]>, UnaryDP,
3050 // These aren't really mov instructions, but we have to define them this way
3051 // due to flag operands.
3053 let Defs = [CPSR] in {
3054 def MOVsrl_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3055 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>, UnaryDP,
3057 def MOVsra_flag : PseudoInst<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVsi,
3058 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>, UnaryDP,
3062 //===----------------------------------------------------------------------===//
3063 // Extend Instructions.
3068 def SXTB : AI_ext_rrot<0b01101010,
3069 "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
3070 def SXTH : AI_ext_rrot<0b01101011,
3071 "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
3073 def SXTAB : AI_exta_rrot<0b01101010,
3074 "sxtab", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
3075 def SXTAH : AI_exta_rrot<0b01101011,
3076 "sxtah", BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
3078 def SXTB16 : AI_ext_rrot_np<0b01101000, "sxtb16">;
3080 def SXTAB16 : AI_exta_rrot_np<0b01101000, "sxtab16">;
3084 let AddedComplexity = 16 in {
3085 def UXTB : AI_ext_rrot<0b01101110,
3086 "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
3087 def UXTH : AI_ext_rrot<0b01101111,
3088 "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
3089 def UXTB16 : AI_ext_rrot<0b01101100,
3090 "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
3092 // FIXME: This pattern incorrectly assumes the shl operator is a rotate.
3093 // The transformation should probably be done as a combiner action
3094 // instead so we can include a check for masking back in the upper
3095 // eight bits of the source into the lower eight bits of the result.
3096 //def : ARMV6Pat<(and (shl GPR:$Src, (i32 8)), 0xFF00FF),
3097 // (UXTB16r_rot GPR:$Src, 3)>;
3098 def : ARMV6Pat<(and (srl GPR:$Src, (i32 8)), 0xFF00FF),
3099 (UXTB16 GPR:$Src, 1)>;
3101 def UXTAB : AI_exta_rrot<0b01101110, "uxtab",
3102 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
3103 def UXTAH : AI_exta_rrot<0b01101111, "uxtah",
3104 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
3107 // This isn't safe in general, the add is two 16-bit units, not a 32-bit add.
3108 def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
3111 def SBFX : I<(outs GPRnopc:$Rd),
3112 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3113 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3114 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3115 Requires<[IsARM, HasV6T2]> {
3120 let Inst{27-21} = 0b0111101;
3121 let Inst{6-4} = 0b101;
3122 let Inst{20-16} = width;
3123 let Inst{15-12} = Rd;
3124 let Inst{11-7} = lsb;
3128 def UBFX : I<(outs GPR:$Rd),
3129 (ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
3130 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3131 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3132 Requires<[IsARM, HasV6T2]> {
3137 let Inst{27-21} = 0b0111111;
3138 let Inst{6-4} = 0b101;
3139 let Inst{20-16} = width;
3140 let Inst{15-12} = Rd;
3141 let Inst{11-7} = lsb;
3145 //===----------------------------------------------------------------------===//
3146 // Arithmetic Instructions.
3149 defm ADD : AsI1_bin_irs<0b0100, "add",
3150 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3151 BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>;
3152 defm SUB : AsI1_bin_irs<0b0010, "sub",
3153 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3154 BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">;
3156 // ADD and SUB with 's' bit set.
3157 defm ADDS : AI1_bin_s_irs<0b0100, "adds",
3158 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3159 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
3160 defm SUBS : AI1_bin_s_irs<0b0010, "subs",
3161 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3162 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3164 defm ADC : AI1_adde_sube_irs<0b0101, "adc",
3165 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
3167 defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
3168 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3171 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3172 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3173 BinOpFrag<(sub node:$LHS, node:$RHS)>, "RSB">;
3174 defm RSBS : AsI1_rbin_s_is<0b0011, "rsb",
3175 IIC_iALUi, IIC_iALUr, IIC_iALUsr,
3176 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
3178 defm RSC : AI1_rsc_irs<0b0111, "rsc",
3179 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
3182 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
3183 // The assume-no-carry-in form uses the negation of the input since add/sub
3184 // assume opposite meanings of the carry flag (i.e., carry == !borrow).
3185 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory
3187 def : ARMPat<(add GPR:$src, so_imm_neg:$imm),
3188 (SUBri GPR:$src, so_imm_neg:$imm)>;
3189 def : ARMPat<(ARMaddc GPR:$src, so_imm_neg:$imm),
3190 (SUBSri GPR:$src, so_imm_neg:$imm)>;
3192 // The with-carry-in form matches bitwise not instead of the negation.
3193 // Effectively, the inverse interpretation of the carry flag already accounts
3194 // for part of the negation.
3195 def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
3196 (SBCri GPR:$src, so_imm_not:$imm)>;
3198 // Note: These are implemented in C++ code, because they have to generate
3199 // ADD/SUBrs instructions, which use a complex pattern that a xform function
3201 // (mul X, 2^n+1) -> (add (X << n), X)
3202 // (mul X, 2^n-1) -> (rsb X, (X << n))
3204 // ARM Arithmetic Instruction
3205 // GPR:$dst = GPR:$a op GPR:$b
3206 class AAI<bits<8> op27_20, bits<8> op11_4, string opc,
3207 list<dag> pattern = [],
3208 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3209 string asm = "\t$Rd, $Rn, $Rm">
3210 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern> {
3214 let Inst{27-20} = op27_20;
3215 let Inst{11-4} = op11_4;
3216 let Inst{19-16} = Rn;
3217 let Inst{15-12} = Rd;
3221 // Saturating add/subtract
3223 def QADD : AAI<0b00010000, 0b00000101, "qadd",
3224 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))],
3225 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3226 def QSUB : AAI<0b00010010, 0b00000101, "qsub",
3227 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))],
3228 (ins GPRnopc:$Rm, GPRnopc:$Rn), "\t$Rd, $Rm, $Rn">;
3229 def QDADD : AAI<0b00010100, 0b00000101, "qdadd", [],
3230 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3232 def QDSUB : AAI<0b00010110, 0b00000101, "qdsub", [],
3233 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3236 def QADD16 : AAI<0b01100010, 0b11110001, "qadd16">;
3237 def QADD8 : AAI<0b01100010, 0b11111001, "qadd8">;
3238 def QASX : AAI<0b01100010, 0b11110011, "qasx">;
3239 def QSAX : AAI<0b01100010, 0b11110101, "qsax">;
3240 def QSUB16 : AAI<0b01100010, 0b11110111, "qsub16">;
3241 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
3242 def UQADD16 : AAI<0b01100110, 0b11110001, "uqadd16">;
3243 def UQADD8 : AAI<0b01100110, 0b11111001, "uqadd8">;
3244 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
3245 def UQSAX : AAI<0b01100110, 0b11110101, "uqsax">;
3246 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
3247 def UQSUB8 : AAI<0b01100110, 0b11111111, "uqsub8">;
3249 // Signed/Unsigned add/subtract
3251 def SASX : AAI<0b01100001, 0b11110011, "sasx">;
3252 def SADD16 : AAI<0b01100001, 0b11110001, "sadd16">;
3253 def SADD8 : AAI<0b01100001, 0b11111001, "sadd8">;
3254 def SSAX : AAI<0b01100001, 0b11110101, "ssax">;
3255 def SSUB16 : AAI<0b01100001, 0b11110111, "ssub16">;
3256 def SSUB8 : AAI<0b01100001, 0b11111111, "ssub8">;
3257 def UASX : AAI<0b01100101, 0b11110011, "uasx">;
3258 def UADD16 : AAI<0b01100101, 0b11110001, "uadd16">;
3259 def UADD8 : AAI<0b01100101, 0b11111001, "uadd8">;
3260 def USAX : AAI<0b01100101, 0b11110101, "usax">;
3261 def USUB16 : AAI<0b01100101, 0b11110111, "usub16">;
3262 def USUB8 : AAI<0b01100101, 0b11111111, "usub8">;
3264 // Signed/Unsigned halving add/subtract
3266 def SHASX : AAI<0b01100011, 0b11110011, "shasx">;
3267 def SHADD16 : AAI<0b01100011, 0b11110001, "shadd16">;
3268 def SHADD8 : AAI<0b01100011, 0b11111001, "shadd8">;
3269 def SHSAX : AAI<0b01100011, 0b11110101, "shsax">;
3270 def SHSUB16 : AAI<0b01100011, 0b11110111, "shsub16">;
3271 def SHSUB8 : AAI<0b01100011, 0b11111111, "shsub8">;
3272 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
3273 def UHADD16 : AAI<0b01100111, 0b11110001, "uhadd16">;
3274 def UHADD8 : AAI<0b01100111, 0b11111001, "uhadd8">;
3275 def UHSAX : AAI<0b01100111, 0b11110101, "uhsax">;
3276 def UHSUB16 : AAI<0b01100111, 0b11110111, "uhsub16">;
3277 def UHSUB8 : AAI<0b01100111, 0b11111111, "uhsub8">;
3279 // Unsigned Sum of Absolute Differences [and Accumulate].
3281 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3282 MulFrm /* for convenience */, NoItinerary, "usad8",
3283 "\t$Rd, $Rn, $Rm", []>,
3284 Requires<[IsARM, HasV6]> {
3288 let Inst{27-20} = 0b01111000;
3289 let Inst{15-12} = 0b1111;
3290 let Inst{7-4} = 0b0001;
3291 let Inst{19-16} = Rd;
3292 let Inst{11-8} = Rm;
3295 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3296 MulFrm /* for convenience */, NoItinerary, "usada8",
3297 "\t$Rd, $Rn, $Rm, $Ra", []>,
3298 Requires<[IsARM, HasV6]> {
3303 let Inst{27-20} = 0b01111000;
3304 let Inst{7-4} = 0b0001;
3305 let Inst{19-16} = Rd;
3306 let Inst{15-12} = Ra;
3307 let Inst{11-8} = Rm;
3311 // Signed/Unsigned saturate
3313 def SSAT : AI<(outs GPRnopc:$Rd),
3314 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3315 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3320 let Inst{27-21} = 0b0110101;
3321 let Inst{5-4} = 0b01;
3322 let Inst{20-16} = sat_imm;
3323 let Inst{15-12} = Rd;
3324 let Inst{11-7} = sh{4-0};
3325 let Inst{6} = sh{5};
3329 def SSAT16 : AI<(outs GPRnopc:$Rd),
3330 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
3331 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []> {
3335 let Inst{27-20} = 0b01101010;
3336 let Inst{11-4} = 0b11110011;
3337 let Inst{15-12} = Rd;
3338 let Inst{19-16} = sat_imm;
3342 def USAT : AI<(outs GPRnopc:$Rd),
3343 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
3344 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> {
3349 let Inst{27-21} = 0b0110111;
3350 let Inst{5-4} = 0b01;
3351 let Inst{15-12} = Rd;
3352 let Inst{11-7} = sh{4-0};
3353 let Inst{6} = sh{5};
3354 let Inst{20-16} = sat_imm;
3358 def USAT16 : AI<(outs GPRnopc:$Rd),
3359 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
3360 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
3364 let Inst{27-20} = 0b01101110;
3365 let Inst{11-4} = 0b11110011;
3366 let Inst{15-12} = Rd;
3367 let Inst{19-16} = sat_imm;
3371 def : ARMV6Pat<(int_arm_ssat GPRnopc:$a, imm:$pos),
3372 (SSAT imm:$pos, GPRnopc:$a, 0)>;
3373 def : ARMV6Pat<(int_arm_usat GPRnopc:$a, imm:$pos),
3374 (USAT imm:$pos, GPRnopc:$a, 0)>;
3376 //===----------------------------------------------------------------------===//
3377 // Bitwise Instructions.
3380 defm AND : AsI1_bin_irs<0b0000, "and",
3381 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3382 BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>;
3383 defm ORR : AsI1_bin_irs<0b1100, "orr",
3384 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3385 BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>;
3386 defm EOR : AsI1_bin_irs<0b0001, "eor",
3387 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3388 BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>;
3389 defm BIC : AsI1_bin_irs<0b1110, "bic",
3390 IIC_iBITi, IIC_iBITr, IIC_iBITsr,
3391 BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">;
3393 // FIXME: bf_inv_mask_imm should be two operands, the lsb and the msb, just
3394 // like in the actual instruction encoding. The complexity of mapping the mask
3395 // to the lsb/msb pair should be handled by ISel, not encapsulated in the
3396 // instruction description.
3397 def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm),
3398 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3399 "bfc", "\t$Rd, $imm", "$src = $Rd",
3400 [(set GPR:$Rd, (and GPR:$src, bf_inv_mask_imm:$imm))]>,
3401 Requires<[IsARM, HasV6T2]> {
3404 let Inst{27-21} = 0b0111110;
3405 let Inst{6-0} = 0b0011111;
3406 let Inst{15-12} = Rd;
3407 let Inst{11-7} = imm{4-0}; // lsb
3408 let Inst{20-16} = imm{9-5}; // msb
3411 // A8.6.18 BFI - Bitfield insert (Encoding A1)
3412 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
3413 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3414 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
3415 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
3416 bf_inv_mask_imm:$imm))]>,
3417 Requires<[IsARM, HasV6T2]> {
3421 let Inst{27-21} = 0b0111110;
3422 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3423 let Inst{15-12} = Rd;
3424 let Inst{11-7} = imm{4-0}; // lsb
3425 let Inst{20-16} = imm{9-5}; // width
3429 // GNU as only supports this form of bfi (w/ 4 arguments)
3430 let isAsmParserOnly = 1 in
3431 def BFI4p : I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn,
3432 lsb_pos_imm:$lsb, width_imm:$width),
3433 AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
3434 "bfi", "\t$Rd, $Rn, $lsb, $width", "$src = $Rd",
3435 []>, Requires<[IsARM, HasV6T2]> {
3440 let Inst{27-21} = 0b0111110;
3441 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
3442 let Inst{15-12} = Rd;
3443 let Inst{11-7} = lsb;
3444 let Inst{20-16} = width; // Custom encoder => lsb+width-1
3448 def MVNr : AsI1<0b1111, (outs GPR:$Rd), (ins GPR:$Rm), DPFrm, IIC_iMVNr,
3449 "mvn", "\t$Rd, $Rm",
3450 [(set GPR:$Rd, (not GPR:$Rm))]>, UnaryDP {
3454 let Inst{19-16} = 0b0000;
3455 let Inst{11-4} = 0b00000000;
3456 let Inst{15-12} = Rd;
3459 def MVNsi : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_imm:$shift),
3460 DPSoRegImmFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3461 [(set GPR:$Rd, (not so_reg_imm:$shift))]>, UnaryDP {
3465 let Inst{19-16} = 0b0000;
3466 let Inst{15-12} = Rd;
3467 let Inst{11-5} = shift{11-5};
3469 let Inst{3-0} = shift{3-0};
3471 def MVNsr : AsI1<0b1111, (outs GPR:$Rd), (ins so_reg_reg:$shift),
3472 DPSoRegRegFrm, IIC_iMVNsr, "mvn", "\t$Rd, $shift",
3473 [(set GPR:$Rd, (not so_reg_reg:$shift))]>, UnaryDP {
3477 let Inst{19-16} = 0b0000;
3478 let Inst{15-12} = Rd;
3479 let Inst{11-8} = shift{11-8};
3481 let Inst{6-5} = shift{6-5};
3483 let Inst{3-0} = shift{3-0};
3485 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3486 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3487 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3488 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP {
3492 let Inst{19-16} = 0b0000;
3493 let Inst{15-12} = Rd;
3494 let Inst{11-0} = imm;
3497 def : ARMPat<(and GPR:$src, so_imm_not:$imm),
3498 (BICri GPR:$src, so_imm_not:$imm)>;
3500 //===----------------------------------------------------------------------===//
3501 // Multiply Instructions.
3503 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3504 string opc, string asm, list<dag> pattern>
3505 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3509 let Inst{19-16} = Rd;
3510 let Inst{11-8} = Rm;
3513 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3514 string opc, string asm, list<dag> pattern>
3515 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3520 let Inst{19-16} = RdHi;
3521 let Inst{15-12} = RdLo;
3522 let Inst{11-8} = Rm;
3526 // FIXME: The v5 pseudos are only necessary for the additional Constraint
3527 // property. Remove them when it's possible to add those properties
3528 // on an individual MachineInstr, not just an instuction description.
3529 let isCommutable = 1 in {
3530 def MUL : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3531 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
3532 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
3533 Requires<[IsARM, HasV6]> {
3534 let Inst{15-12} = 0b0000;
3537 let Constraints = "@earlyclobber $Rd" in
3538 def MULv5: ARMPseudoExpand<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
3539 pred:$p, cc_out:$s),
3541 [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))],
3542 (MUL GPR:$Rd, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3543 Requires<[IsARM, NoV6]>;
3546 def MLA : AsMul1I32<0b0000001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3547 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
3548 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3549 Requires<[IsARM, HasV6]> {
3551 let Inst{15-12} = Ra;
3554 let Constraints = "@earlyclobber $Rd" in
3555 def MLAv5: ARMPseudoExpand<(outs GPR:$Rd),
3556 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s),
3558 [(set GPR:$Rd, (add (mul GPR:$Rn, GPR:$Rm), GPR:$Ra))],
3559 (MLA GPR:$Rd, GPR:$Rn, GPR:$Rm, GPR:$Ra, pred:$p, cc_out:$s)>,
3560 Requires<[IsARM, NoV6]>;
3562 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3563 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
3564 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3565 Requires<[IsARM, HasV6T2]> {
3570 let Inst{19-16} = Rd;
3571 let Inst{15-12} = Ra;
3572 let Inst{11-8} = Rm;
3576 // Extra precision multiplies with low / high results
3577 let neverHasSideEffects = 1 in {
3578 let isCommutable = 1 in {
3579 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
3580 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3581 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3582 Requires<[IsARM, HasV6]>;
3584 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
3585 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
3586 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3587 Requires<[IsARM, HasV6]>;
3589 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3590 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3591 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3593 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3594 Requires<[IsARM, NoV6]>;
3596 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3597 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3599 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3600 Requires<[IsARM, NoV6]>;
3604 // Multiply + accumulate
3605 def SMLAL : AsMul1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3606 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3607 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3608 Requires<[IsARM, HasV6]>;
3609 def UMLAL : AsMul1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
3610 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3611 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3612 Requires<[IsARM, HasV6]>;
3614 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
3615 (ins GPR:$Rn, GPR:$Rm), IIC_iMAC64,
3616 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3617 Requires<[IsARM, HasV6]> {
3622 let Inst{19-16} = RdHi;
3623 let Inst{15-12} = RdLo;
3624 let Inst{11-8} = Rm;
3628 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
3629 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3630 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3632 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3633 Requires<[IsARM, NoV6]>;
3634 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3635 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
3637 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3638 Requires<[IsARM, NoV6]>;
3639 def UMAALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
3640 (ins GPR:$Rn, GPR:$Rm, pred:$p),
3642 (UMAAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p)>,
3643 Requires<[IsARM, NoV6]>;
3646 } // neverHasSideEffects
3648 // Most significant word multiply
3649 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3650 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
3651 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
3652 Requires<[IsARM, HasV6]> {
3653 let Inst{15-12} = 0b1111;
3656 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3657 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
3658 Requires<[IsARM, HasV6]> {
3659 let Inst{15-12} = 0b1111;
3662 def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
3663 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3664 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
3665 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
3666 Requires<[IsARM, HasV6]>;
3668 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3669 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3670 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
3671 Requires<[IsARM, HasV6]>;
3673 def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
3674 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3675 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra",
3676 [(set GPR:$Rd, (sub GPR:$Ra, (mulhs GPR:$Rn, GPR:$Rm)))]>,
3677 Requires<[IsARM, HasV6]>;
3679 def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
3680 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
3681 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
3682 Requires<[IsARM, HasV6]>;
3684 multiclass AI_smul<string opc, PatFrag opnode> {
3685 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3686 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
3687 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3688 (sext_inreg GPR:$Rm, i16)))]>,
3689 Requires<[IsARM, HasV5TE]>;
3691 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3692 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
3693 [(set GPR:$Rd, (opnode (sext_inreg GPR:$Rn, i16),
3694 (sra GPR:$Rm, (i32 16))))]>,
3695 Requires<[IsARM, HasV5TE]>;
3697 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3698 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
3699 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3700 (sext_inreg GPR:$Rm, i16)))]>,
3701 Requires<[IsARM, HasV5TE]>;
3703 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3704 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
3705 [(set GPR:$Rd, (opnode (sra GPR:$Rn, (i32 16)),
3706 (sra GPR:$Rm, (i32 16))))]>,
3707 Requires<[IsARM, HasV5TE]>;
3709 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3710 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
3711 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3712 (sext_inreg GPR:$Rm, i16)), (i32 16)))]>,
3713 Requires<[IsARM, HasV5TE]>;
3715 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3716 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
3717 [(set GPR:$Rd, (sra (opnode GPR:$Rn,
3718 (sra GPR:$Rm, (i32 16))), (i32 16)))]>,
3719 Requires<[IsARM, HasV5TE]>;
3723 multiclass AI_smla<string opc, PatFrag opnode> {
3724 let DecoderMethod = "DecodeSMLAInstruction" in {
3725 def BB : AMulxyIa<0b0001000, 0b00, (outs GPRnopc:$Rd),
3726 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3727 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
3728 [(set GPRnopc:$Rd, (add GPR:$Ra,
3729 (opnode (sext_inreg GPRnopc:$Rn, i16),
3730 (sext_inreg GPRnopc:$Rm, i16))))]>,
3731 Requires<[IsARM, HasV5TE]>;
3733 def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
3734 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3735 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
3737 (add GPR:$Ra, (opnode (sext_inreg GPRnopc:$Rn, i16),
3738 (sra GPRnopc:$Rm, (i32 16)))))]>,
3739 Requires<[IsARM, HasV5TE]>;
3741 def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
3742 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3743 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
3745 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3746 (sext_inreg GPRnopc:$Rm, i16))))]>,
3747 Requires<[IsARM, HasV5TE]>;
3749 def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
3750 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3751 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
3753 (add GPR:$Ra, (opnode (sra GPRnopc:$Rn, (i32 16)),
3754 (sra GPRnopc:$Rm, (i32 16)))))]>,
3755 Requires<[IsARM, HasV5TE]>;
3757 def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
3758 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3759 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
3761 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3762 (sext_inreg GPRnopc:$Rm, i16)), (i32 16))))]>,
3763 Requires<[IsARM, HasV5TE]>;
3765 def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
3766 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3767 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
3769 (add GPR:$Ra, (sra (opnode GPRnopc:$Rn,
3770 (sra GPRnopc:$Rm, (i32 16))), (i32 16))))]>,
3771 Requires<[IsARM, HasV5TE]>;
3775 defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3776 defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
3778 // Halfword multiply accumulate long: SMLAL<x><y>.
3779 def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3780 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3781 IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3782 Requires<[IsARM, HasV5TE]>;
3784 def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3785 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3786 IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3787 Requires<[IsARM, HasV5TE]>;
3789 def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3790 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3791 IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3792 Requires<[IsARM, HasV5TE]>;
3794 def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3795 (ins GPRnopc:$Rn, GPRnopc:$Rm),
3796 IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3797 Requires<[IsARM, HasV5TE]>;
3799 // Helper class for AI_smld.
3800 class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
3801 InstrItinClass itin, string opc, string asm>
3802 : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> {
3805 let Inst{27-23} = 0b01110;
3806 let Inst{22} = long;
3807 let Inst{21-20} = 0b00;
3808 let Inst{11-8} = Rm;
3815 class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops,
3816 InstrItinClass itin, string opc, string asm>
3817 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3819 let Inst{15-12} = 0b1111;
3820 let Inst{19-16} = Rd;
3822 class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops,
3823 InstrItinClass itin, string opc, string asm>
3824 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3827 let Inst{19-16} = Rd;
3828 let Inst{15-12} = Ra;
3830 class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops,
3831 InstrItinClass itin, string opc, string asm>
3832 : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> {
3835 let Inst{19-16} = RdHi;
3836 let Inst{15-12} = RdLo;
3839 multiclass AI_smld<bit sub, string opc> {
3841 def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
3842 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3843 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
3845 def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
3846 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
3847 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
3849 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3850 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3851 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
3853 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
3854 (ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
3855 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
3859 defm SMLA : AI_smld<0, "smla">;
3860 defm SMLS : AI_smld<1, "smls">;
3862 multiclass AI_sdml<bit sub, string opc> {
3864 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
3865 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
3866 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
3867 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
3870 defm SMUA : AI_sdml<0, "smua">;
3871 defm SMUS : AI_sdml<1, "smus">;
3873 //===----------------------------------------------------------------------===//
3874 // Misc. Arithmetic Instructions.
3877 def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
3878 IIC_iUNAr, "clz", "\t$Rd, $Rm",
3879 [(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
3881 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3882 IIC_iUNAr, "rbit", "\t$Rd, $Rm",
3883 [(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
3884 Requires<[IsARM, HasV6T2]>;
3886 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3887 IIC_iUNAr, "rev", "\t$Rd, $Rm",
3888 [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
3890 let AddedComplexity = 5 in
3891 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3892 IIC_iUNAr, "rev16", "\t$Rd, $Rm",
3893 [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
3894 Requires<[IsARM, HasV6]>;
3896 let AddedComplexity = 5 in
3897 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
3898 IIC_iUNAr, "revsh", "\t$Rd, $Rm",
3899 [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
3900 Requires<[IsARM, HasV6]>;
3902 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
3903 (and (srl GPR:$Rm, (i32 8)), 0xFF)),
3906 def PKHBT : APKHI<0b01101000, 0, (outs GPR:$Rd),
3907 (ins GPR:$Rn, GPR:$Rm, pkh_lsl_amt:$sh),
3908 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3909 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF),
3910 (and (shl GPR:$Rm, pkh_lsl_amt:$sh),
3912 Requires<[IsARM, HasV6]>;
3914 // Alternate cases for PKHBT where identities eliminate some nodes.
3915 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (and GPR:$Rm, 0xFFFF0000)),
3916 (PKHBT GPR:$Rn, GPR:$Rm, 0)>;
3917 def : ARMV6Pat<(or (and GPR:$Rn, 0xFFFF), (shl GPR:$Rm, imm16_31:$sh)),
3918 (PKHBT GPR:$Rn, GPR:$Rm, imm16_31:$sh)>;
3920 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
3921 // will match the pattern below.
3922 def PKHTB : APKHI<0b01101000, 1, (outs GPR:$Rd),
3923 (ins GPR:$Rn, GPR:$Rm, pkh_asr_amt:$sh),
3924 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3925 [(set GPR:$Rd, (or (and GPR:$Rn, 0xFFFF0000),
3926 (and (sra GPR:$Rm, pkh_asr_amt:$sh),
3928 Requires<[IsARM, HasV6]>;
3930 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
3931 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
3932 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
3933 (PKHTB GPR:$src1, GPR:$src2, imm16_31:$sh)>;
3934 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
3935 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
3936 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$sh)>;
3938 //===----------------------------------------------------------------------===//
3939 // Comparison Instructions...
3942 defm CMP : AI1_cmp_irs<0b1010, "cmp",
3943 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
3944 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
3946 // ARMcmpZ can re-use the above instruction definitions.
3947 def : ARMPat<(ARMcmpZ GPR:$src, so_imm:$imm),
3948 (CMPri GPR:$src, so_imm:$imm)>;
3949 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
3950 (CMPrr GPR:$src, GPR:$rhs)>;
3951 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
3952 (CMPrsi GPR:$src, so_reg_imm:$rhs)>;
3953 def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
3954 (CMPrsr GPR:$src, so_reg_reg:$rhs)>;
3956 // FIXME: We have to be careful when using the CMN instruction and comparison
3957 // with 0. One would expect these two pieces of code should give identical
3973 // However, the CMN gives the *opposite* result when r1 is 0. This is because
3974 // the carry flag is set in the CMP case but not in the CMN case. In short, the
3975 // CMP instruction doesn't perform a truncate of the (logical) NOT of 0 plus the
3976 // value of r0 and the carry bit (because the "carry bit" parameter to
3977 // AddWithCarry is defined as 1 in this case, the carry flag will always be set
3978 // when r0 >= 0). The CMN instruction doesn't perform a NOT of 0 so there is
3979 // never a "carry" when this AddWithCarry is performed (because the "carry bit"
3980 // parameter to AddWithCarry is defined as 0).
3982 // When x is 0 and unsigned:
3986 // ~x + 1 = 0x1 0000 0000
3987 // (-x = 0) != (0x1 0000 0000 = ~x + 1)
3989 // Therefore, we should disable CMN when comparing against zero, until we can
3990 // limit when the CMN instruction is used (when we know that the RHS is not 0 or
3991 // when it's a comparison which doesn't look at the 'carry' flag).
3993 // (See the ARM docs for the "AddWithCarry" pseudo-code.)
3995 // This is related to <rdar://problem/7569620>.
3997 //defm CMN : AI1_cmp_irs<0b1011, "cmn",
3998 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
4000 // Note that TST/TEQ don't set all the same flags that CMP does!
4001 defm TST : AI1_cmp_irs<0b1000, "tst",
4002 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4003 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 1>;
4004 defm TEQ : AI1_cmp_irs<0b1001, "teq",
4005 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsr,
4006 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 1>;
4008 defm CMNz : AI1_cmp_irs<0b1011, "cmn",
4009 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr,
4010 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>>;
4012 //def : ARMPat<(ARMcmp GPR:$src, so_imm_neg:$imm),
4013 // (CMNri GPR:$src, so_imm_neg:$imm)>;
4015 def : ARMPat<(ARMcmpZ GPR:$src, so_imm_neg:$imm),
4016 (CMNzri GPR:$src, so_imm_neg:$imm)>;
4018 // Pseudo i64 compares for some floating point compares.
4019 let usesCustomInserter = 1, isBranch = 1, isTerminator = 1,
4021 def BCCi64 : PseudoInst<(outs),
4022 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, brtarget:$dst),
4024 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, GPR:$rhs1, GPR:$rhs2, bb:$dst)]>;
4026 def BCCZi64 : PseudoInst<(outs),
4027 (ins i32imm:$cc, GPR:$lhs1, GPR:$lhs2, brtarget:$dst), IIC_Br,
4028 [(ARMBcci64 imm:$cc, GPR:$lhs1, GPR:$lhs2, 0, 0, bb:$dst)]>;
4029 } // usesCustomInserter
4032 // Conditional moves
4033 // FIXME: should be able to write a pattern for ARMcmov, but can't use
4034 // a two-value operand where a dag node expects two operands. :(
4035 let neverHasSideEffects = 1 in {
4036 def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm, pred:$p),
4038 [/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
4039 RegConstraint<"$false = $Rd">;
4040 def MOVCCsi : ARMPseudoInst<(outs GPR:$Rd),
4041 (ins GPR:$false, so_reg_imm:$shift, pred:$p),
4043 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_imm:$shift,
4044 imm:$cc, CCR:$ccr))*/]>,
4045 RegConstraint<"$false = $Rd">;
4046 def MOVCCsr : ARMPseudoInst<(outs GPR:$Rd),
4047 (ins GPR:$false, so_reg_reg:$shift, pred:$p),
4049 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_reg_reg:$shift,
4050 imm:$cc, CCR:$ccr))*/]>,
4051 RegConstraint<"$false = $Rd">;
4054 let isMoveImm = 1 in
4055 def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
4056 (ins GPR:$false, imm0_65535_expr:$imm, pred:$p),
4059 RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
4061 let isMoveImm = 1 in
4062 def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
4063 (ins GPR:$false, so_imm:$imm, pred:$p),
4065 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
4066 RegConstraint<"$false = $Rd">;
4068 // Two instruction predicate mov immediate.
4069 let isMoveImm = 1 in
4070 def MOVCCi32imm : ARMPseudoInst<(outs GPR:$Rd),
4071 (ins GPR:$false, i32imm:$src, pred:$p),
4072 8, IIC_iCMOVix2, []>, RegConstraint<"$false = $Rd">;
4074 let isMoveImm = 1 in
4075 def MVNCCi : ARMPseudoInst<(outs GPR:$Rd),
4076 (ins GPR:$false, so_imm:$imm, pred:$p),
4078 [/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm_not:$imm, imm:$cc, CCR:$ccr))*/]>,
4079 RegConstraint<"$false = $Rd">;
4080 } // neverHasSideEffects
4082 //===----------------------------------------------------------------------===//
4083 // Atomic operations intrinsics
4086 def MemBarrierOptOperand : AsmOperandClass {
4087 let Name = "MemBarrierOpt";
4088 let ParserMethod = "parseMemBarrierOptOperand";
4090 def memb_opt : Operand<i32> {
4091 let PrintMethod = "printMemBOption";
4092 let ParserMatchClass = MemBarrierOptOperand;
4093 let DecoderMethod = "DecodeMemBarrierOption";
4096 // memory barriers protect the atomic sequences
4097 let hasSideEffects = 1 in {
4098 def DMB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4099 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>,
4100 Requires<[IsARM, HasDB]> {
4102 let Inst{31-4} = 0xf57ff05;
4103 let Inst{3-0} = opt;
4107 def DSB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4108 "dsb", "\t$opt", []>,
4109 Requires<[IsARM, HasDB]> {
4111 let Inst{31-4} = 0xf57ff04;
4112 let Inst{3-0} = opt;
4115 // ISB has only full system option
4116 def ISB : AInoP<(outs), (ins memb_opt:$opt), MiscFrm, NoItinerary,
4117 "isb", "\t$opt", []>,
4118 Requires<[IsARM, HasDB]> {
4120 let Inst{31-4} = 0xf57ff06;
4121 let Inst{3-0} = opt;
4124 let usesCustomInserter = 1 in {
4125 let Uses = [CPSR] in {
4126 def ATOMIC_LOAD_ADD_I8 : PseudoInst<
4127 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4128 [(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
4129 def ATOMIC_LOAD_SUB_I8 : PseudoInst<
4130 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4131 [(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
4132 def ATOMIC_LOAD_AND_I8 : PseudoInst<
4133 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4134 [(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
4135 def ATOMIC_LOAD_OR_I8 : PseudoInst<
4136 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4137 [(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
4138 def ATOMIC_LOAD_XOR_I8 : PseudoInst<
4139 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4140 [(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
4141 def ATOMIC_LOAD_NAND_I8 : PseudoInst<
4142 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4143 [(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
4144 def ATOMIC_LOAD_MIN_I8 : PseudoInst<
4145 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4146 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4147 def ATOMIC_LOAD_MAX_I8 : PseudoInst<
4148 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4149 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4150 def ATOMIC_LOAD_UMIN_I8 : PseudoInst<
4151 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4152 [(set GPR:$dst, (atomic_load_min_8 GPR:$ptr, GPR:$val))]>;
4153 def ATOMIC_LOAD_UMAX_I8 : PseudoInst<
4154 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4155 [(set GPR:$dst, (atomic_load_max_8 GPR:$ptr, GPR:$val))]>;
4156 def ATOMIC_LOAD_ADD_I16 : PseudoInst<
4157 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4158 [(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
4159 def ATOMIC_LOAD_SUB_I16 : PseudoInst<
4160 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4161 [(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
4162 def ATOMIC_LOAD_AND_I16 : PseudoInst<
4163 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4164 [(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
4165 def ATOMIC_LOAD_OR_I16 : PseudoInst<
4166 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4167 [(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
4168 def ATOMIC_LOAD_XOR_I16 : PseudoInst<
4169 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4170 [(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
4171 def ATOMIC_LOAD_NAND_I16 : PseudoInst<
4172 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4173 [(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
4174 def ATOMIC_LOAD_MIN_I16 : PseudoInst<
4175 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4176 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4177 def ATOMIC_LOAD_MAX_I16 : PseudoInst<
4178 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4179 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4180 def ATOMIC_LOAD_UMIN_I16 : PseudoInst<
4181 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4182 [(set GPR:$dst, (atomic_load_min_16 GPR:$ptr, GPR:$val))]>;
4183 def ATOMIC_LOAD_UMAX_I16 : PseudoInst<
4184 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4185 [(set GPR:$dst, (atomic_load_max_16 GPR:$ptr, GPR:$val))]>;
4186 def ATOMIC_LOAD_ADD_I32 : PseudoInst<
4187 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4188 [(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
4189 def ATOMIC_LOAD_SUB_I32 : PseudoInst<
4190 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4191 [(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
4192 def ATOMIC_LOAD_AND_I32 : PseudoInst<
4193 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4194 [(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
4195 def ATOMIC_LOAD_OR_I32 : PseudoInst<
4196 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4197 [(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
4198 def ATOMIC_LOAD_XOR_I32 : PseudoInst<
4199 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4200 [(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
4201 def ATOMIC_LOAD_NAND_I32 : PseudoInst<
4202 (outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
4203 [(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
4204 def ATOMIC_LOAD_MIN_I32 : PseudoInst<
4205 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4206 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4207 def ATOMIC_LOAD_MAX_I32 : PseudoInst<
4208 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4209 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4210 def ATOMIC_LOAD_UMIN_I32 : PseudoInst<
4211 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4212 [(set GPR:$dst, (atomic_load_min_32 GPR:$ptr, GPR:$val))]>;
4213 def ATOMIC_LOAD_UMAX_I32 : PseudoInst<
4214 (outs GPR:$dst), (ins GPR:$ptr, GPR:$val), NoItinerary,
4215 [(set GPR:$dst, (atomic_load_max_32 GPR:$ptr, GPR:$val))]>;
4217 def ATOMIC_SWAP_I8 : PseudoInst<
4218 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4219 [(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
4220 def ATOMIC_SWAP_I16 : PseudoInst<
4221 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4222 [(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
4223 def ATOMIC_SWAP_I32 : PseudoInst<
4224 (outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
4225 [(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
4227 def ATOMIC_CMP_SWAP_I8 : PseudoInst<
4228 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4229 [(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
4230 def ATOMIC_CMP_SWAP_I16 : PseudoInst<
4231 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4232 [(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
4233 def ATOMIC_CMP_SWAP_I32 : PseudoInst<
4234 (outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
4235 [(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
4239 let mayLoad = 1 in {
4240 def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4242 "ldrexb", "\t$Rt, $addr", []>;
4243 def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4244 NoItinerary, "ldrexh", "\t$Rt, $addr", []>;
4245 def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr),
4246 NoItinerary, "ldrex", "\t$Rt, $addr", []>;
4247 let hasExtraDefRegAllocReq = 1 in
4248 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
4249 NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
4250 let DecoderMethod = "DecodeDoubleRegLoad";
4254 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
4255 def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4256 NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
4257 def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4258 NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
4259 def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
4260 NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
4263 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
4264 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
4265 (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
4266 NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
4267 let DecoderMethod = "DecodeDoubleRegStore";
4270 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
4271 Requires<[IsARM, HasV7]> {
4272 let Inst{31-0} = 0b11110101011111111111000000011111;
4275 // SWP/SWPB are deprecated in V6/V7.
4276 let mayLoad = 1, mayStore = 1 in {
4277 def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4279 def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
4283 //===----------------------------------------------------------------------===//
4284 // Coprocessor Instructions.
4287 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4288 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4289 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4290 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4291 imm:$CRm, imm:$opc2)]> {
4299 let Inst{3-0} = CRm;
4301 let Inst{7-5} = opc2;
4302 let Inst{11-8} = cop;
4303 let Inst{15-12} = CRd;
4304 let Inst{19-16} = CRn;
4305 let Inst{23-20} = opc1;
4308 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4309 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4310 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4311 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4312 imm:$CRm, imm:$opc2)]> {
4313 let Inst{31-28} = 0b1111;
4321 let Inst{3-0} = CRm;
4323 let Inst{7-5} = opc2;
4324 let Inst{11-8} = cop;
4325 let Inst{15-12} = CRd;
4326 let Inst{19-16} = CRn;
4327 let Inst{23-20} = opc1;
4330 class ACI<dag oops, dag iops, string opc, string asm,
4331 IndexMode im = IndexModeNone>
4332 : InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
4334 let Inst{27-25} = 0b110;
4337 multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
4338 let DecoderNamespace = "Common" in {
4339 def _OFFSET : ACI<(outs),
4340 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4341 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
4342 let Inst{31-28} = op31_28;
4343 let Inst{24} = 1; // P = 1
4344 let Inst{21} = 0; // W = 0
4345 let Inst{22} = 0; // D = 0
4346 let Inst{20} = load;
4347 let DecoderMethod = "DecodeCopMemInstruction";
4350 def _PRE : ACI<(outs),
4351 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4352 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
4353 let Inst{31-28} = op31_28;
4354 let Inst{24} = 1; // P = 1
4355 let Inst{21} = 1; // W = 1
4356 let Inst{22} = 0; // D = 0
4357 let Inst{20} = load;
4358 let DecoderMethod = "DecodeCopMemInstruction";
4361 def _POST : ACI<(outs),
4362 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4363 !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
4364 let Inst{31-28} = op31_28;
4365 let Inst{24} = 0; // P = 0
4366 let Inst{21} = 1; // W = 1
4367 let Inst{22} = 0; // D = 0
4368 let Inst{20} = load;
4369 let DecoderMethod = "DecodeCopMemInstruction";
4372 def _OPTION : ACI<(outs),
4373 !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
4375 !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
4376 let Inst{31-28} = op31_28;
4377 let Inst{24} = 0; // P = 0
4378 let Inst{23} = 1; // U = 1
4379 let Inst{21} = 0; // W = 0
4380 let Inst{22} = 0; // D = 0
4381 let Inst{20} = load;
4382 let DecoderMethod = "DecodeCopMemInstruction";
4385 def L_OFFSET : ACI<(outs),
4386 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4387 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
4388 let Inst{31-28} = op31_28;
4389 let Inst{24} = 1; // P = 1
4390 let Inst{21} = 0; // W = 0
4391 let Inst{22} = 1; // D = 1
4392 let Inst{20} = load;
4393 let DecoderMethod = "DecodeCopMemInstruction";
4396 def L_PRE : ACI<(outs),
4397 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
4398 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
4400 let Inst{31-28} = op31_28;
4401 let Inst{24} = 1; // P = 1
4402 let Inst{21} = 1; // W = 1
4403 let Inst{22} = 1; // D = 1
4404 let Inst{20} = load;
4405 let DecoderMethod = "DecodeCopMemInstruction";
4408 def L_POST : ACI<(outs),
4409 !con((ins nohash_imm:$cop, nohash_imm:$CRd, addr_offset_none:$addr,
4410 postidx_imm8s4:$offset), ops),
4411 !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr, $offset",
4413 let Inst{31-28} = op31_28;
4414 let Inst{24} = 0; // P = 0
4415 let Inst{21} = 1; // W = 1
4416 let Inst{22} = 1; // D = 1
4417 let Inst{20} = load;
4418 let DecoderMethod = "DecodeCopMemInstruction";
4421 def L_OPTION : ACI<(outs),
4422 !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
4424 !strconcat(!strconcat(opc, "l"), cond),
4425 "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
4426 let Inst{31-28} = op31_28;
4427 let Inst{24} = 0; // P = 0
4428 let Inst{23} = 1; // U = 1
4429 let Inst{21} = 0; // W = 0
4430 let Inst{22} = 1; // D = 1
4431 let Inst{20} = load;
4432 let DecoderMethod = "DecodeCopMemInstruction";
4437 defm LDC : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc", "${p}">;
4438 defm LDC2 : LdStCop<0b1111, 1, (ins), "ldc2", "">;
4439 defm STC : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc", "${p}">;
4440 defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
4442 //===----------------------------------------------------------------------===//
4443 // Move between coprocessor and ARM core register.
4446 class MovRCopro<string opc, bit direction, dag oops, dag iops,
4448 : ABI<0b1110, oops, iops, NoItinerary, opc,
4449 "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
4450 let Inst{20} = direction;
4460 let Inst{15-12} = Rt;
4461 let Inst{11-8} = cop;
4462 let Inst{23-21} = opc1;
4463 let Inst{7-5} = opc2;
4464 let Inst{3-0} = CRm;
4465 let Inst{19-16} = CRn;
4468 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
4470 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4471 c_imm:$CRm, imm0_7:$opc2),
4472 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4473 imm:$CRm, imm:$opc2)]>;
4474 def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
4476 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4479 def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
4480 (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4482 class MovRCopro2<string opc, bit direction, dag oops, dag iops,
4484 : ABXI<0b1110, oops, iops, NoItinerary,
4485 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
4486 let Inst{31-28} = 0b1111;
4487 let Inst{20} = direction;
4497 let Inst{15-12} = Rt;
4498 let Inst{11-8} = cop;
4499 let Inst{23-21} = opc1;
4500 let Inst{7-5} = opc2;
4501 let Inst{3-0} = CRm;
4502 let Inst{19-16} = CRn;
4505 def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
4507 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4508 c_imm:$CRm, imm0_7:$opc2),
4509 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4510 imm:$CRm, imm:$opc2)]>;
4511 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
4513 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4516 def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
4517 imm:$CRm, imm:$opc2),
4518 (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
4520 class MovRRCopro<string opc, bit direction, list<dag> pattern = []>
4521 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4522 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4523 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4524 let Inst{23-21} = 0b010;
4525 let Inst{20} = direction;
4533 let Inst{15-12} = Rt;
4534 let Inst{19-16} = Rt2;
4535 let Inst{11-8} = cop;
4536 let Inst{7-4} = opc1;
4537 let Inst{3-0} = CRm;
4540 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4541 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4543 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
4545 class MovRRCopro2<string opc, bit direction, list<dag> pattern = []>
4546 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4547 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
4548 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
4549 let Inst{31-28} = 0b1111;
4550 let Inst{23-21} = 0b010;
4551 let Inst{20} = direction;
4559 let Inst{15-12} = Rt;
4560 let Inst{19-16} = Rt2;
4561 let Inst{11-8} = cop;
4562 let Inst{7-4} = opc1;
4563 let Inst{3-0} = CRm;
4566 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4567 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4569 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
4571 //===----------------------------------------------------------------------===//
4572 // Move between special register and ARM core register
4575 // Move to ARM core register from Special Register
4576 def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4577 "mrs", "\t$Rd, apsr", []> {
4579 let Inst{23-16} = 0b00001111;
4580 let Inst{15-12} = Rd;
4581 let Inst{7-4} = 0b0000;
4584 def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
4586 def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
4587 "mrs", "\t$Rd, spsr", []> {
4589 let Inst{23-16} = 0b01001111;
4590 let Inst{15-12} = Rd;
4591 let Inst{7-4} = 0b0000;
4594 // Move from ARM core register to Special Register
4596 // No need to have both system and application versions, the encodings are the
4597 // same and the assembly parser has no way to distinguish between them. The mask
4598 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
4599 // the mask with the fields to be accessed in the special register.
4600 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
4601 "msr", "\t$mask, $Rn", []> {
4606 let Inst{22} = mask{4}; // R bit
4607 let Inst{21-20} = 0b10;
4608 let Inst{19-16} = mask{3-0};
4609 let Inst{15-12} = 0b1111;
4610 let Inst{11-4} = 0b00000000;
4614 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
4615 "msr", "\t$mask, $a", []> {
4620 let Inst{22} = mask{4}; // R bit
4621 let Inst{21-20} = 0b10;
4622 let Inst{19-16} = mask{3-0};
4623 let Inst{15-12} = 0b1111;
4627 //===----------------------------------------------------------------------===//
4631 // __aeabi_read_tp preserves the registers r1-r3.
4632 // This is a pseudo inst so that we can get the encoding right,
4633 // complete with fixup for the aeabi_read_tp function.
4635 Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
4636 def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
4637 [(set R0, ARMthread_pointer)]>;
4640 //===----------------------------------------------------------------------===//
4641 // SJLJ Exception handling intrinsics
4642 // eh_sjlj_setjmp() is an instruction sequence to store the return
4643 // address and save #0 in R0 for the non-longjmp case.
4644 // Since by its nature we may be coming from some other function to get
4645 // here, and we're using the stack frame for the containing function to
4646 // save/restore registers, we can't keep anything live in regs across
4647 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
4648 // when we get here from a longjmp(). We force everything out of registers
4649 // except for our own input by listing the relevant registers in Defs. By
4650 // doing so, we also cause the prologue/epilogue code to actively preserve
4651 // all of the callee-saved resgisters, which is exactly what we want.
4652 // A constant value is passed in $val, and we use the location as a scratch.
4654 // These are pseudo-instructions and are lowered to individual MC-insts, so
4655 // no encoding information is necessary.
4657 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR,
4658 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], hasSideEffects = 1, isBarrier = 1 in {
4659 def Int_eh_sjlj_setjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4661 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4662 Requires<[IsARM, HasVFP2]>;
4666 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ],
4667 hasSideEffects = 1, isBarrier = 1 in {
4668 def Int_eh_sjlj_setjmp_nofp : PseudoInst<(outs), (ins GPR:$src, GPR:$val),
4670 [(set R0, (ARMeh_sjlj_setjmp GPR:$src, GPR:$val))]>,
4671 Requires<[IsARM, NoVFP]>;
4674 // FIXME: Non-Darwin version(s)
4675 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
4676 Defs = [ R7, LR, SP ] in {
4677 def Int_eh_sjlj_longjmp : PseudoInst<(outs), (ins GPR:$src, GPR:$scratch),
4679 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
4680 Requires<[IsARM, IsDarwin]>;
4683 // eh.sjlj.dispatchsetup pseudo-instruction.
4684 // This pseudo is used for ARM, Thumb1 and Thumb2. Any differences are
4685 // handled when the pseudo is expanded (which happens before any passes
4686 // that need the instruction size).
4687 let isBarrier = 1, hasSideEffects = 1 in
4688 def Int_eh_sjlj_dispatchsetup :
4689 PseudoInst<(outs), (ins GPR:$src), NoItinerary,
4690 [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
4691 Requires<[IsDarwin]>;
4693 //===----------------------------------------------------------------------===//
4694 // Non-Instruction Patterns
4697 // ARMv4 indirect branch using (MOVr PC, dst)
4698 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in
4699 def MOVPCRX : ARMPseudoExpand<(outs), (ins GPR:$dst),
4700 4, IIC_Br, [(brind GPR:$dst)],
4701 (MOVr PC, GPR:$dst, (ops 14, zero_reg), zero_reg)>,
4702 Requires<[IsARM, NoV4T]>;
4704 // Large immediate handling.
4706 // 32-bit immediate using two piece so_imms or movw + movt.
4707 // This is a single pseudo instruction, the benefit is that it can be remat'd
4708 // as a single unit instead of having to handle reg inputs.
4709 // FIXME: Remove this when we can do generalized remat.
4710 let isReMaterializable = 1, isMoveImm = 1 in
4711 def MOVi32imm : PseudoInst<(outs GPR:$dst), (ins i32imm:$src), IIC_iMOVix2,
4712 [(set GPR:$dst, (arm_i32imm:$src))]>,
4715 // Pseudo instruction that combines movw + movt + add pc (if PIC).
4716 // It also makes it possible to rematerialize the instructions.
4717 // FIXME: Remove this when we can do generalized remat and when machine licm
4718 // can properly the instructions.
4719 let isReMaterializable = 1 in {
4720 def MOV_ga_pcrel : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4722 [(set GPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
4723 Requires<[IsARM, UseMovt]>;
4725 def MOV_ga_dyn : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4727 [(set GPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>,
4728 Requires<[IsARM, UseMovt]>;
4730 let AddedComplexity = 10 in
4731 def MOV_ga_pcrel_ldr : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr),
4733 [(set GPR:$dst, (load (ARMWrapperPIC tglobaladdr:$addr)))]>,
4734 Requires<[IsARM, UseMovt]>;
4735 } // isReMaterializable
4737 // ConstantPool, GlobalAddress, and JumpTable
4738 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (LEApcrel tglobaladdr :$dst)>,
4739 Requires<[IsARM, DontUseMovt]>;
4740 def : ARMPat<(ARMWrapper tconstpool :$dst), (LEApcrel tconstpool :$dst)>;
4741 def : ARMPat<(ARMWrapper tglobaladdr :$dst), (MOVi32imm tglobaladdr :$dst)>,
4742 Requires<[IsARM, UseMovt]>;
4743 def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
4744 (LEApcrelJT tjumptable:$dst, imm:$id)>;
4746 // TODO: add,sub,and, 3-instr forms?
4749 def : ARMPat<(ARMtcret tcGPR:$dst),
4750 (TCRETURNri tcGPR:$dst)>, Requires<[IsDarwin]>;
4752 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4753 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4755 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4756 (TCRETURNdi texternalsym:$dst)>, Requires<[IsDarwin]>;
4758 def : ARMPat<(ARMtcret tcGPR:$dst),
4759 (TCRETURNriND tcGPR:$dst)>, Requires<[IsNotDarwin]>;
4761 def : ARMPat<(ARMtcret (i32 tglobaladdr:$dst)),
4762 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4764 def : ARMPat<(ARMtcret (i32 texternalsym:$dst)),
4765 (TCRETURNdiND texternalsym:$dst)>, Requires<[IsNotDarwin]>;
4768 def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
4769 Requires<[IsARM, IsNotDarwin]>;
4770 def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
4771 Requires<[IsARM, IsDarwin]>;
4773 // zextload i1 -> zextload i8
4774 def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4775 def : ARMPat<(zextloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4777 // extload -> zextload
4778 def : ARMPat<(extloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4779 def : ARMPat<(extloadi1 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4780 def : ARMPat<(extloadi8 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
4781 def : ARMPat<(extloadi8 ldst_so_reg:$addr), (LDRBrs ldst_so_reg:$addr)>;
4783 def : ARMPat<(extloadi16 addrmode3:$addr), (LDRH addrmode3:$addr)>;
4785 def : ARMPat<(extloadi8 addrmodepc:$addr), (PICLDRB addrmodepc:$addr)>;
4786 def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
4789 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4790 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4791 (SMULBB GPR:$a, GPR:$b)>;
4792 def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
4793 (SMULBB GPR:$a, GPR:$b)>;
4794 def : ARMV5TEPat<(mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4795 (sra GPR:$b, (i32 16))),
4796 (SMULBT GPR:$a, GPR:$b)>;
4797 def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
4798 (SMULBT GPR:$a, GPR:$b)>;
4799 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)),
4800 (sra (shl GPR:$b, (i32 16)), (i32 16))),
4801 (SMULTB GPR:$a, GPR:$b)>;
4802 def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
4803 (SMULTB GPR:$a, GPR:$b)>;
4804 def : ARMV5TEPat<(sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4806 (SMULWB GPR:$a, GPR:$b)>;
4807 def : ARMV5TEPat<(sra (mul GPR:$a, sext_16_node:$b), (i32 16)),
4808 (SMULWB GPR:$a, GPR:$b)>;
4810 def : ARMV5TEPat<(add GPR:$acc,
4811 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4812 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4813 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4814 def : ARMV5TEPat<(add GPR:$acc,
4815 (mul sext_16_node:$a, sext_16_node:$b)),
4816 (SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
4817 def : ARMV5TEPat<(add GPR:$acc,
4818 (mul (sra (shl GPR:$a, (i32 16)), (i32 16)),
4819 (sra GPR:$b, (i32 16)))),
4820 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4821 def : ARMV5TEPat<(add GPR:$acc,
4822 (mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
4823 (SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
4824 def : ARMV5TEPat<(add GPR:$acc,
4825 (mul (sra GPR:$a, (i32 16)),
4826 (sra (shl GPR:$b, (i32 16)), (i32 16)))),
4827 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4828 def : ARMV5TEPat<(add GPR:$acc,
4829 (mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
4830 (SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
4831 def : ARMV5TEPat<(add GPR:$acc,
4832 (sra (mul GPR:$a, (sra (shl GPR:$b, (i32 16)), (i32 16))),
4834 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4835 def : ARMV5TEPat<(add GPR:$acc,
4836 (sra (mul GPR:$a, sext_16_node:$b), (i32 16))),
4837 (SMLAWB GPR:$a, GPR:$b, GPR:$acc)>;
4840 // Pre-v7 uses MCR for synchronization barriers.
4841 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
4842 Requires<[IsARM, HasV6]>;
4844 // SXT/UXT with no rotate
4845 let AddedComplexity = 16 in {
4846 def : ARMV6Pat<(and GPR:$Src, 0x000000FF), (UXTB GPR:$Src, 0)>;
4847 def : ARMV6Pat<(and GPR:$Src, 0x0000FFFF), (UXTH GPR:$Src, 0)>;
4848 def : ARMV6Pat<(and GPR:$Src, 0x00FF00FF), (UXTB16 GPR:$Src, 0)>;
4849 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
4850 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
4851 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
4852 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
4855 def : ARMV6Pat<(sext_inreg GPR:$Src, i8), (SXTB GPR:$Src, 0)>;
4856 def : ARMV6Pat<(sext_inreg GPR:$Src, i16), (SXTH GPR:$Src, 0)>;
4858 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
4859 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
4860 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
4861 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
4863 // Atomic load/store patterns
4864 def : ARMPat<(atomic_load_8 ldst_so_reg:$src),
4865 (LDRBrs ldst_so_reg:$src)>;
4866 def : ARMPat<(atomic_load_8 addrmode_imm12:$src),
4867 (LDRBi12 addrmode_imm12:$src)>;
4868 def : ARMPat<(atomic_load_16 addrmode3:$src),
4869 (LDRH addrmode3:$src)>;
4870 def : ARMPat<(atomic_load_32 ldst_so_reg:$src),
4871 (LDRrs ldst_so_reg:$src)>;
4872 def : ARMPat<(atomic_load_32 addrmode_imm12:$src),
4873 (LDRi12 addrmode_imm12:$src)>;
4874 def : ARMPat<(atomic_store_8 ldst_so_reg:$ptr, GPR:$val),
4875 (STRBrs GPR:$val, ldst_so_reg:$ptr)>;
4876 def : ARMPat<(atomic_store_8 addrmode_imm12:$ptr, GPR:$val),
4877 (STRBi12 GPR:$val, addrmode_imm12:$ptr)>;
4878 def : ARMPat<(atomic_store_16 addrmode3:$ptr, GPR:$val),
4879 (STRH GPR:$val, addrmode3:$ptr)>;
4880 def : ARMPat<(atomic_store_32 ldst_so_reg:$ptr, GPR:$val),
4881 (STRrs GPR:$val, ldst_so_reg:$ptr)>;
4882 def : ARMPat<(atomic_store_32 addrmode_imm12:$ptr, GPR:$val),
4883 (STRi12 GPR:$val, addrmode_imm12:$ptr)>;
4886 //===----------------------------------------------------------------------===//
4890 include "ARMInstrThumb.td"
4892 //===----------------------------------------------------------------------===//
4896 include "ARMInstrThumb2.td"
4898 //===----------------------------------------------------------------------===//
4899 // Floating Point Support
4902 include "ARMInstrVFP.td"
4904 //===----------------------------------------------------------------------===//
4905 // Advanced SIMD (NEON) Support
4908 include "ARMInstrNEON.td"
4910 //===----------------------------------------------------------------------===//
4911 // Assembler aliases
4915 def : InstAlias<"dmb", (DMB 0xf)>, Requires<[IsARM, HasDB]>;
4916 def : InstAlias<"dsb", (DSB 0xf)>, Requires<[IsARM, HasDB]>;
4917 def : InstAlias<"isb", (ISB 0xf)>, Requires<[IsARM, HasDB]>;
4919 // System instructions
4920 def : MnemonicAlias<"swi", "svc">;
4922 // Load / Store Multiple
4923 def : MnemonicAlias<"ldmfd", "ldm">;
4924 def : MnemonicAlias<"ldmia", "ldm">;
4925 def : MnemonicAlias<"stmfd", "stmdb">;
4926 def : MnemonicAlias<"stmia", "stm">;
4927 def : MnemonicAlias<"stmea", "stm">;
4929 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the
4930 // shift amount is zero (i.e., unspecified).
4931 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4932 (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>,
4933 Requires<[IsARM, HasV6]>;
4934 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4935 (PKHBT GPR:$Rd, GPR:$Rn, GPR:$Rm, 0, pred:$p)>,
4936 Requires<[IsARM, HasV6]>;
4938 // PUSH/POP aliases for STM/LDM
4939 def : ARMInstAlias<"push${p} $regs", (STMDB_UPD SP, pred:$p, reglist:$regs)>;
4940 def : ARMInstAlias<"pop${p} $regs", (LDMIA_UPD SP, pred:$p, reglist:$regs)>;
4942 // SSAT/USAT optional shift operand.
4943 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
4944 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4945 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
4946 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
4949 // Extend instruction optional rotate operand.
4950 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
4951 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4952 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
4953 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4954 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
4955 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4956 def : ARMInstAlias<"sxtb${p} $Rd, $Rm",
4957 (SXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4958 def : ARMInstAlias<"sxtb16${p} $Rd, $Rm",
4959 (SXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4960 def : ARMInstAlias<"sxth${p} $Rd, $Rm",
4961 (SXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4963 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
4964 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4965 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
4966 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4967 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
4968 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
4969 def : ARMInstAlias<"uxtb${p} $Rd, $Rm",
4970 (UXTB GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4971 def : ARMInstAlias<"uxtb16${p} $Rd, $Rm",
4972 (UXTB16 GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4973 def : ARMInstAlias<"uxth${p} $Rd, $Rm",
4974 (UXTH GPRnopc:$Rd, GPRnopc:$Rm, 0, pred:$p)>;
4978 def : MnemonicAlias<"rfefa", "rfeda">;
4979 def : MnemonicAlias<"rfeea", "rfedb">;
4980 def : MnemonicAlias<"rfefd", "rfeia">;
4981 def : MnemonicAlias<"rfeed", "rfeib">;
4982 def : MnemonicAlias<"rfe", "rfeia">;
4985 def : MnemonicAlias<"srsfa", "srsda">;
4986 def : MnemonicAlias<"srsea", "srsdb">;
4987 def : MnemonicAlias<"srsfd", "srsia">;
4988 def : MnemonicAlias<"srsed", "srsib">;
4989 def : MnemonicAlias<"srs", "srsia">;
4991 // LDRSBT/LDRHT/LDRSHT post-index offset if optional.
4992 // Note that the write-back output register is a dummy operand for MC (it's
4993 // only meaningful for codegen), so we just pass zero here.
4994 // FIXME: tblgen not cooperating with argument conversions.
4995 //def : InstAlias<"ldrsbt${p} $Rt, $addr",
4996 // (LDRSBTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0,pred:$p)>;
4997 //def : InstAlias<"ldrht${p} $Rt, $addr",
4998 // (LDRHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>;
4999 //def : InstAlias<"ldrsht${p} $Rt, $addr",
5000 // (LDRSHTi GPR:$Rt, GPR:$Rt, addr_offset_none:$addr, 0, pred:$p)>;