1 //===-- ARMInstrInfo.h - ARM Instruction Information ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMINSTRINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMINSTRINFO_H
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMRegisterInfo.h"
23 class ARMInstrInfo : public ARMBaseInstrInfo {
26 explicit ARMInstrInfo(const ARMSubtarget &STI);
28 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
29 void getNoopForMachoTarget(MCInst &NopInst) const override;
31 // Return the non-pre/post incrementing version of 'Opc'. Return 0
32 // if there is not such an opcode.
33 unsigned getUnindexedOpcode(unsigned Opc) const override;
35 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
36 /// such, whenever a client has an instance of instruction info, it should
37 /// always be able to get register info as well (through this method).
39 const ARMRegisterInfo &getRegisterInfo() const override { return RI; }
41 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
43 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
44 /// the list is modeled as <Reg:SubReg, SubIdx>.
45 /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
47 /// - vreg1:sub1, sub0
50 /// \returns true if it is possible to build such an input sequence
51 /// with the pair \p MI, \p DefIdx. False otherwise.
53 /// \pre MI.isRegSequenceLike().
54 bool getRegSequenceLikeInputs(
55 const MachineInstr &MI, unsigned DefIdx,
56 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
58 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
60 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
61 /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
62 /// - vreg1:sub1, sub0
64 /// \returns true if it is possible to build such an input sequence
65 /// with the pair \p MI, \p DefIdx. False otherwise.
67 /// \pre MI.isExtractSubregLike().
68 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
69 RegSubRegPairAndIdx &InputReg) const override;
71 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
73 /// \p [out] BaseReg and \p [out] InsertedReg contain
74 /// the equivalent inputs of INSERT_SUBREG.
75 /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
76 /// - BaseReg: vreg0:sub0
77 /// - InsertedReg: vreg1:sub1, sub3
79 /// \returns true if it is possible to build such an input sequence
80 /// with the pair \p MI, \p DefIdx. False otherwise.
82 /// \pre MI.isInsertSubregLike().
84 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
85 RegSubRegPair &BaseReg,
86 RegSubRegPairAndIdx &InsertedReg) const override;
89 void expandLoadStackGuard(MachineBasicBlock::iterator MI,
90 Reloc::Model RM) const override;