1 //===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARMINSTRUCTIONINFO_H
15 #define ARMINSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "ARMRegisterInfo.h"
23 /// ARMII - This namespace holds all of the target specific flags that
24 /// instruction info tracks.
28 //===------------------------------------------------------------------===//
31 //===------------------------------------------------------------------===//
32 // This three-bit field describes the addressing mode used. Zero is unused
33 // so that we can tell if we forgot to set a value.
45 AddrModeTs = 9, // i8 * 4 for pc and sp relative data
47 // Size* - Flags to keep track of the size of an instruction.
49 SizeMask = 7 << SizeShift,
50 SizeSpecial = 1, // 0 byte pseudo or special case.
55 // IndexMode - Unindex, pre-indexed, or post-indexed. Only valid for load
58 IndexModeMask = 3 << IndexModeShift,
64 OpcodeMask = 0xf << OpcodeShift,
68 FormMask = 31 << FormShift,
70 // Pseudo instructions
71 Pseudo = 1 << FormShift,
73 // Multiply instructions
74 MulFrm = 2 << FormShift,
75 MulSMLAW = 3 << FormShift,
76 MulSMULW = 4 << FormShift,
77 MulSMLA = 5 << FormShift,
78 MulSMUL = 6 << FormShift,
80 // Branch instructions
81 Branch = 7 << FormShift,
82 BranchMisc = 8 << FormShift,
84 // Data Processing instructions
85 UnaryFrm = 9 << FormShift,
86 BinaryFrm = 10 << FormShift,
89 LdFrm = 11 << FormShift,
90 StFrm = 12 << FormShift,
92 // Miscellaneous arithmetic instructions
93 ArithMisc = 13 << FormShift,
96 ThumbFrm = 14 << FormShift,
99 VPFFrm = 15 << FormShift,
101 // Field shifts - such shifts are used to set field while generating
102 // machine instructions.
113 class ARMInstrInfo : public TargetInstrInfoImpl {
114 const ARMRegisterInfo RI;
116 explicit ARMInstrInfo(const ARMSubtarget &STI);
118 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
119 /// such, whenever a client has an instance of instruction info, it should
120 /// always be able to get register info as well (through this method).
122 virtual const ARMRegisterInfo &getRegisterInfo() const { return RI; }
124 /// getPointerRegClass - Return the register class to use to hold pointers.
125 /// This is used for addressing modes.
126 virtual const TargetRegisterClass *getPointerRegClass() const;
128 /// Return true if the instruction is a register to register move and
129 /// leave the source and dest operands in the passed parameters.
131 virtual bool isMoveInstr(const MachineInstr &MI,
132 unsigned &SrcReg, unsigned &DstReg) const;
133 virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
134 virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
136 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
137 unsigned DestReg, const MachineInstr *Orig) const;
139 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
140 MachineBasicBlock::iterator &MBBI,
141 LiveVariables *LV) const;
144 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
145 MachineBasicBlock *&FBB,
146 SmallVectorImpl<MachineOperand> &Cond) const;
147 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
148 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
149 MachineBasicBlock *FBB,
150 const SmallVectorImpl<MachineOperand> &Cond) const;
151 virtual bool copyRegToReg(MachineBasicBlock &MBB,
152 MachineBasicBlock::iterator I,
153 unsigned DestReg, unsigned SrcReg,
154 const TargetRegisterClass *DestRC,
155 const TargetRegisterClass *SrcRC) const;
156 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
157 MachineBasicBlock::iterator MBBI,
158 unsigned SrcReg, bool isKill, int FrameIndex,
159 const TargetRegisterClass *RC) const;
161 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
162 SmallVectorImpl<MachineOperand> &Addr,
163 const TargetRegisterClass *RC,
164 SmallVectorImpl<MachineInstr*> &NewMIs) const;
166 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
167 MachineBasicBlock::iterator MBBI,
168 unsigned DestReg, int FrameIndex,
169 const TargetRegisterClass *RC) const;
171 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
172 SmallVectorImpl<MachineOperand> &Addr,
173 const TargetRegisterClass *RC,
174 SmallVectorImpl<MachineInstr*> &NewMIs) const;
175 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
176 MachineBasicBlock::iterator MI,
177 const std::vector<CalleeSavedInfo> &CSI) const;
178 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
179 MachineBasicBlock::iterator MI,
180 const std::vector<CalleeSavedInfo> &CSI) const;
182 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
184 SmallVectorImpl<unsigned> &Ops,
185 int FrameIndex) const;
187 virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
189 SmallVectorImpl<unsigned> &Ops,
190 MachineInstr* LoadMI) const {
194 virtual bool canFoldMemoryOperand(MachineInstr *MI,
195 SmallVectorImpl<unsigned> &Ops) const;
197 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
199 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
201 // Predication support.
202 virtual bool isPredicated(const MachineInstr *MI) const;
205 bool PredicateInstruction(MachineInstr *MI,
206 const SmallVectorImpl<MachineOperand> &Pred) const;
209 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
210 const SmallVectorImpl<MachineOperand> &Pred2) const;
212 virtual bool DefinesPredicate(MachineInstr *MI,
213 std::vector<MachineOperand> &Pred) const;
215 /// GetInstSize - Returns the size of the specified MachineInstr.
217 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;