1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/Support/CommandLine.h"
29 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
30 cl::desc("Enable ARM 2-addr to 3-addr conv"));
33 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
34 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
38 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
42 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI)
43 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
47 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
48 : ARMBaseInstrInfo(STI) {
51 /// Return true if the instruction is a register to register move and
52 /// leave the source and dest operands in the passed parameters.
54 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
55 unsigned &SrcReg, unsigned &DstReg,
56 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
57 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
59 unsigned oc = MI.getOpcode();
67 SrcReg = MI.getOperand(1).getReg();
68 DstReg = MI.getOperand(0).getReg();
71 assert(MI.getDesc().getNumOperands() >= 2 &&
72 MI.getOperand(0).isReg() &&
73 MI.getOperand(1).isReg() &&
74 "Invalid ARM MOV instruction");
75 SrcReg = MI.getOperand(1).getReg();
76 DstReg = MI.getOperand(0).getReg();
81 unsigned ARMInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
82 int &FrameIndex) const {
83 switch (MI->getOpcode()) {
86 if (MI->getOperand(1).isFI() &&
87 MI->getOperand(2).isReg() &&
88 MI->getOperand(3).isImm() &&
89 MI->getOperand(2).getReg() == 0 &&
90 MI->getOperand(3).getImm() == 0) {
91 FrameIndex = MI->getOperand(1).getIndex();
92 return MI->getOperand(0).getReg();
97 if (MI->getOperand(1).isFI() &&
98 MI->getOperand(2).isImm() &&
99 MI->getOperand(2).getImm() == 0) {
100 FrameIndex = MI->getOperand(1).getIndex();
101 return MI->getOperand(0).getReg();
108 unsigned ARMInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
109 int &FrameIndex) const {
110 switch (MI->getOpcode()) {
113 if (MI->getOperand(1).isFI() &&
114 MI->getOperand(2).isReg() &&
115 MI->getOperand(3).isImm() &&
116 MI->getOperand(2).getReg() == 0 &&
117 MI->getOperand(3).getImm() == 0) {
118 FrameIndex = MI->getOperand(1).getIndex();
119 return MI->getOperand(0).getReg();
124 if (MI->getOperand(1).isFI() &&
125 MI->getOperand(2).isImm() &&
126 MI->getOperand(2).getImm() == 0) {
127 FrameIndex = MI->getOperand(1).getIndex();
128 return MI->getOperand(0).getReg();
136 void ARMBaseInstrInfo::reMaterialize(MachineBasicBlock &MBB,
137 MachineBasicBlock::iterator I,
139 const MachineInstr *Orig) const {
140 DebugLoc dl = Orig->getDebugLoc();
141 if (Orig->getOpcode() == ARM::MOVi2pieces) {
142 RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(),
143 Orig->getOperand(2).getImm(),
144 Orig->getOperand(3).getReg(), this, false, dl);
148 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
149 MI->getOperand(0).setReg(DestReg);
153 static unsigned getUnindexedOpcode(unsigned Opc) {
166 case ARM::LDRSH_POST:
169 case ARM::LDRSB_POST:
185 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
186 MachineBasicBlock::iterator &MBBI,
187 LiveVariables *LV) const {
191 MachineInstr *MI = MBBI;
192 MachineFunction &MF = *MI->getParent()->getParent();
193 unsigned TSFlags = MI->getDesc().TSFlags;
195 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
196 default: return NULL;
197 case ARMII::IndexModePre:
200 case ARMII::IndexModePost:
204 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
206 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
210 MachineInstr *UpdateMI = NULL;
211 MachineInstr *MemMI = NULL;
212 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
213 const TargetInstrDesc &TID = MI->getDesc();
214 unsigned NumOps = TID.getNumOperands();
215 bool isLoad = !TID.mayStore();
216 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
217 const MachineOperand &Base = MI->getOperand(2);
218 const MachineOperand &Offset = MI->getOperand(NumOps-3);
219 unsigned WBReg = WB.getReg();
220 unsigned BaseReg = Base.getReg();
221 unsigned OffReg = Offset.getReg();
222 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
223 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
226 assert(false && "Unknown indexed op!");
228 case ARMII::AddrMode2: {
229 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
230 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
232 int SOImmVal = ARM_AM::getSOImmVal(Amt);
234 // Can't encode it in a so_imm operand. This transformation will
235 // add more than 1 instruction. Abandon!
237 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
238 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
239 .addReg(BaseReg).addImm(SOImmVal)
240 .addImm(Pred).addReg(0).addReg(0);
241 } else if (Amt != 0) {
242 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
243 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
244 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
245 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
246 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
247 .addImm(Pred).addReg(0).addReg(0);
249 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
250 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
251 .addReg(BaseReg).addReg(OffReg)
252 .addImm(Pred).addReg(0).addReg(0);
255 case ARMII::AddrMode3 : {
256 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
257 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
259 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
260 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
261 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
262 .addReg(BaseReg).addImm(Amt)
263 .addImm(Pred).addReg(0).addReg(0);
265 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
266 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
267 .addReg(BaseReg).addReg(OffReg)
268 .addImm(Pred).addReg(0).addReg(0);
273 std::vector<MachineInstr*> NewMIs;
276 MemMI = BuildMI(MF, MI->getDebugLoc(),
277 get(MemOpc), MI->getOperand(0).getReg())
278 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
280 MemMI = BuildMI(MF, MI->getDebugLoc(),
281 get(MemOpc)).addReg(MI->getOperand(1).getReg())
282 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
283 NewMIs.push_back(MemMI);
284 NewMIs.push_back(UpdateMI);
287 MemMI = BuildMI(MF, MI->getDebugLoc(),
288 get(MemOpc), MI->getOperand(0).getReg())
289 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
291 MemMI = BuildMI(MF, MI->getDebugLoc(),
292 get(MemOpc)).addReg(MI->getOperand(1).getReg())
293 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
295 UpdateMI->getOperand(0).setIsDead();
296 NewMIs.push_back(UpdateMI);
297 NewMIs.push_back(MemMI);
300 // Transfer LiveVariables states, kill / dead info.
302 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
303 MachineOperand &MO = MI->getOperand(i);
304 if (MO.isReg() && MO.getReg() &&
305 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
306 unsigned Reg = MO.getReg();
308 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
310 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
312 LV->addVirtualRegisterDead(Reg, NewMI);
314 if (MO.isUse() && MO.isKill()) {
315 for (unsigned j = 0; j < 2; ++j) {
316 // Look at the two new MI's in reverse order.
317 MachineInstr *NewMI = NewMIs[j];
318 if (!NewMI->readsRegister(Reg))
320 LV->addVirtualRegisterKilled(Reg, NewMI);
321 if (VI.removeKill(MI))
322 VI.Kills.push_back(NewMI);
330 MFI->insert(MBBI, NewMIs[1]);
331 MFI->insert(MBBI, NewMIs[0]);
337 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
338 MachineBasicBlock *&FBB,
339 SmallVectorImpl<MachineOperand> &Cond,
340 bool AllowModify) const {
341 // If the block has no terminators, it just falls into the block after it.
342 MachineBasicBlock::iterator I = MBB.end();
343 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
346 // Get the last instruction in the block.
347 MachineInstr *LastInst = I;
349 // If there is only one terminator instruction, process it.
350 unsigned LastOpc = LastInst->getOpcode();
351 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
352 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
353 TBB = LastInst->getOperand(0).getMBB();
356 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
357 // Block ends with fall-through condbranch.
358 TBB = LastInst->getOperand(0).getMBB();
359 Cond.push_back(LastInst->getOperand(1));
360 Cond.push_back(LastInst->getOperand(2));
363 return true; // Can't handle indirect branch.
366 // Get the instruction before it if it is a terminator.
367 MachineInstr *SecondLastInst = I;
369 // If there are three terminators, we don't know what sort of block this is.
370 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
373 // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
374 unsigned SecondLastOpc = SecondLastInst->getOpcode();
375 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
376 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
377 TBB = SecondLastInst->getOperand(0).getMBB();
378 Cond.push_back(SecondLastInst->getOperand(1));
379 Cond.push_back(SecondLastInst->getOperand(2));
380 FBB = LastInst->getOperand(0).getMBB();
384 // If the block ends with two unconditional branches, handle it. The second
385 // one is not executed, so remove it.
386 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
387 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
388 TBB = SecondLastInst->getOperand(0).getMBB();
391 I->eraseFromParent();
395 // ...likewise if it ends with a branch table followed by an unconditional
396 // branch. The branch folder can create these, and we must get rid of them for
397 // correctness of Thumb constant islands.
398 if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
399 SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr) &&
400 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
403 I->eraseFromParent();
407 // Otherwise, can't handle this.
412 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
413 MachineFunction &MF = *MBB.getParent();
414 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
415 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
416 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
418 MachineBasicBlock::iterator I = MBB.end();
419 if (I == MBB.begin()) return 0;
421 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
424 // Remove the branch.
425 I->eraseFromParent();
429 if (I == MBB.begin()) return 1;
431 if (I->getOpcode() != BccOpc)
434 // Remove the branch.
435 I->eraseFromParent();
440 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
441 MachineBasicBlock *FBB,
442 const SmallVectorImpl<MachineOperand> &Cond) const {
443 // FIXME this should probably have a DebugLoc argument
444 DebugLoc dl = DebugLoc::getUnknownLoc();
445 MachineFunction &MF = *MBB.getParent();
446 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
447 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
448 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
450 // Shouldn't be a fall through.
451 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
452 assert((Cond.size() == 2 || Cond.size() == 0) &&
453 "ARM branch conditions have two components!");
456 if (Cond.empty()) // Unconditional branch?
457 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
459 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
460 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
464 // Two-way conditional branch.
465 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
466 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
467 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
471 bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
472 MachineBasicBlock::iterator I,
473 unsigned DestReg, unsigned SrcReg,
474 const TargetRegisterClass *DestRC,
475 const TargetRegisterClass *SrcRC) const {
476 DebugLoc DL = DebugLoc::getUnknownLoc();
477 if (I != MBB.end()) DL = I->getDebugLoc();
479 if (DestRC != SrcRC) {
480 // Not yet supported!
484 if (DestRC == ARM::GPRRegisterClass)
485 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
487 else if (DestRC == ARM::SPRRegisterClass)
488 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
490 else if (DestRC == ARM::DPRRegisterClass)
491 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
493 else if (DestRC == ARM::QPRRegisterClass)
494 BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
502 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
503 unsigned SrcReg, bool isKill, int FI,
504 const TargetRegisterClass *RC) const {
505 DebugLoc DL = DebugLoc::getUnknownLoc();
506 if (I != MBB.end()) DL = I->getDebugLoc();
508 if (RC == ARM::GPRRegisterClass) {
509 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
510 .addReg(SrcReg, getKillRegState(isKill))
511 .addFrameIndex(FI).addReg(0).addImm(0));
512 } else if (RC == ARM::DPRRegisterClass) {
513 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
514 .addReg(SrcReg, getKillRegState(isKill))
515 .addFrameIndex(FI).addImm(0));
517 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
518 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
519 .addReg(SrcReg, getKillRegState(isKill))
520 .addFrameIndex(FI).addImm(0));
524 void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
526 SmallVectorImpl<MachineOperand> &Addr,
527 const TargetRegisterClass *RC,
528 SmallVectorImpl<MachineInstr*> &NewMIs) const{
529 DebugLoc DL = DebugLoc::getUnknownLoc();
531 if (RC == ARM::GPRRegisterClass) {
533 } else if (RC == ARM::DPRRegisterClass) {
536 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
540 MachineInstrBuilder MIB =
541 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
542 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
543 MIB.addOperand(Addr[i]);
545 NewMIs.push_back(MIB);
550 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
551 unsigned DestReg, int FI,
552 const TargetRegisterClass *RC) const {
553 DebugLoc DL = DebugLoc::getUnknownLoc();
554 if (I != MBB.end()) DL = I->getDebugLoc();
556 if (RC == ARM::GPRRegisterClass) {
557 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
558 .addFrameIndex(FI).addReg(0).addImm(0));
559 } else if (RC == ARM::DPRRegisterClass) {
560 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
561 .addFrameIndex(FI).addImm(0));
563 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
564 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
565 .addFrameIndex(FI).addImm(0));
570 loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
571 SmallVectorImpl<MachineOperand> &Addr,
572 const TargetRegisterClass *RC,
573 SmallVectorImpl<MachineInstr*> &NewMIs) const {
574 DebugLoc DL = DebugLoc::getUnknownLoc();
576 if (RC == ARM::GPRRegisterClass) {
578 } else if (RC == ARM::DPRRegisterClass) {
581 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
585 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
586 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
587 MIB.addOperand(Addr[i]);
589 NewMIs.push_back(MIB);
593 MachineInstr *ARMInstrInfo::
594 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
595 const SmallVectorImpl<unsigned> &Ops, int FI) const {
596 if (Ops.size() != 1) return NULL;
598 unsigned OpNum = Ops[0];
599 unsigned Opc = MI->getOpcode();
600 MachineInstr *NewMI = NULL;
604 if (MI->getOperand(4).getReg() == ARM::CPSR)
605 // If it is updating CPSR, then it cannot be folded.
607 unsigned Pred = MI->getOperand(2).getImm();
608 unsigned PredReg = MI->getOperand(3).getReg();
609 if (OpNum == 0) { // move -> store
610 unsigned SrcReg = MI->getOperand(1).getReg();
611 bool isKill = MI->getOperand(1).isKill();
612 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
613 .addReg(SrcReg, getKillRegState(isKill))
614 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
615 } else { // move -> load
616 unsigned DstReg = MI->getOperand(0).getReg();
617 bool isDead = MI->getOperand(0).isDead();
618 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
619 .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
620 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
625 unsigned Pred = MI->getOperand(2).getImm();
626 unsigned PredReg = MI->getOperand(3).getReg();
627 if (OpNum == 0) { // move -> store
628 unsigned SrcReg = MI->getOperand(1).getReg();
629 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
630 .addReg(SrcReg).addFrameIndex(FI)
631 .addImm(0).addImm(Pred).addReg(PredReg);
632 } else { // move -> load
633 unsigned DstReg = MI->getOperand(0).getReg();
634 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS), DstReg)
636 .addImm(0).addImm(Pred).addReg(PredReg);
641 unsigned Pred = MI->getOperand(2).getImm();
642 unsigned PredReg = MI->getOperand(3).getReg();
643 if (OpNum == 0) { // move -> store
644 unsigned SrcReg = MI->getOperand(1).getReg();
645 bool isKill = MI->getOperand(1).isKill();
646 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
647 .addReg(SrcReg, getKillRegState(isKill))
648 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
649 } else { // move -> load
650 unsigned DstReg = MI->getOperand(0).getReg();
651 bool isDead = MI->getOperand(0).isDead();
652 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
653 .addReg(DstReg, RegState::Define | getDeadRegState(isDead))
654 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
663 bool ARMBaseInstrInfo::
664 canFoldMemoryOperand(const MachineInstr *MI,
665 const SmallVectorImpl<unsigned> &Ops) const {
666 if (Ops.size() != 1) return false;
668 unsigned OpNum = Ops[0];
669 unsigned Opc = MI->getOpcode();
673 // If it is updating CPSR, then it cannot be folded.
674 return MI->getOperand(4).getReg() != ARM::CPSR;
676 case ARM::tMOVlor2hir:
677 case ARM::tMOVhir2lor:
678 case ARM::tMOVhir2hir: {
679 if (OpNum == 0) { // move -> store
680 unsigned SrcReg = MI->getOperand(1).getReg();
681 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
682 // tSpill cannot take a high register operand.
684 } else { // move -> load
685 unsigned DstReg = MI->getOperand(0).getReg();
686 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
687 // tRestore cannot target a high register operand.
698 return false; // FIXME
705 ARMBaseInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
706 if (MBB.empty()) return false;
708 switch (MBB.back().getOpcode()) {
709 case ARM::BX_RET: // Return.
712 case ARM::tBX_RET_vararg:
715 case ARM::tB: // Uncond branch.
717 case ARM::BR_JTr: // Jumptable branch.
718 case ARM::BR_JTm: // Jumptable branch through mem.
719 case ARM::BR_JTadd: // Jumptable branch add to pc.
721 default: return false;
725 bool ARMBaseInstrInfo::
726 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
727 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
728 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
732 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
733 int PIdx = MI->findFirstPredOperandIdx();
734 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
737 bool ARMBaseInstrInfo::
738 PredicateInstruction(MachineInstr *MI,
739 const SmallVectorImpl<MachineOperand> &Pred) const {
740 unsigned Opc = MI->getOpcode();
741 if (Opc == ARM::B || Opc == ARM::tB) {
742 MI->setDesc(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
743 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
744 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
748 int PIdx = MI->findFirstPredOperandIdx();
750 MachineOperand &PMO = MI->getOperand(PIdx);
751 PMO.setImm(Pred[0].getImm());
752 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
758 bool ARMBaseInstrInfo::
759 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
760 const SmallVectorImpl<MachineOperand> &Pred2) const {
761 if (Pred1.size() > 2 || Pred2.size() > 2)
764 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
765 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
775 return CC2 == ARMCC::HI;
777 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
779 return CC2 == ARMCC::GT;
781 return CC2 == ARMCC::LT;
785 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
786 std::vector<MachineOperand> &Pred) const {
787 const TargetInstrDesc &TID = MI->getDesc();
788 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
792 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
793 const MachineOperand &MO = MI->getOperand(i);
794 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
804 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
805 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
806 unsigned JTI) DISABLE_INLINE;
807 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
809 return JT[JTI].MBBs.size();
812 /// GetInstSize - Return the size of the specified MachineInstr.
814 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
815 const MachineBasicBlock &MBB = *MI->getParent();
816 const MachineFunction *MF = MBB.getParent();
817 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
819 // Basic size info comes from the TSFlags field.
820 const TargetInstrDesc &TID = MI->getDesc();
821 unsigned TSFlags = TID.TSFlags;
823 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
825 // If this machine instr is an inline asm, measure it.
826 if (MI->getOpcode() == ARM::INLINEASM)
827 return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
830 switch (MI->getOpcode()) {
832 assert(0 && "Unknown or unset size field for instr!");
834 case TargetInstrInfo::IMPLICIT_DEF:
835 case TargetInstrInfo::DECLARE:
836 case TargetInstrInfo::DBG_LABEL:
837 case TargetInstrInfo::EH_LABEL:
842 case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
843 case ARMII::Size4Bytes: return 4; // Arm instruction.
844 case ARMII::Size2Bytes: return 2; // Thumb instruction.
845 case ARMII::SizeSpecial: {
846 switch (MI->getOpcode()) {
847 case ARM::CONSTPOOL_ENTRY:
848 // If this machine instr is a constant pool entry, its size is recorded as
850 return MI->getOperand(2).getImm();
851 case ARM::Int_eh_sjlj_setjmp: return 12;
856 // These are jumptable branches, i.e. a branch followed by an inlined
857 // jumptable. The size is 4 + 4 * number of entries.
858 unsigned NumOps = TID.getNumOperands();
859 MachineOperand JTOP =
860 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
861 unsigned JTI = JTOP.getIndex();
862 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
863 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
864 assert(JTI < JT.size());
865 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
866 // 4 aligned. The assembler / linker may add 2 byte padding just before
867 // the JT entries. The size does not include this padding; the
868 // constant islands pass does separate bookkeeping for it.
869 // FIXME: If we know the size of the function is less than (1 << 16) *2
870 // bytes, we can use 16-bit entries instead. Then there won't be an
872 return getNumJTEntries(JT, JTI) * 4 +
873 (MI->getOpcode()==ARM::tBR_JTr ? 2 : 4);
876 // Otherwise, pseudo-instruction sizes are zero.
881 return 0; // Not reached