1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMTargetMachine.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/GlobalVariable.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCInst.h"
32 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
33 : ARMBaseInstrInfo(STI), RI(STI) {
36 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
37 void ARMInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
39 NopInst.setOpcode(ARM::HINT);
40 NopInst.addOperand(MCOperand::CreateImm(0));
41 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
42 NopInst.addOperand(MCOperand::CreateReg(0));
44 NopInst.setOpcode(ARM::MOVr);
45 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
46 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
47 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
48 NopInst.addOperand(MCOperand::CreateReg(0));
49 NopInst.addOperand(MCOperand::CreateReg(0));
53 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
56 case ARM::LDR_PRE_IMM:
57 case ARM::LDR_PRE_REG:
58 case ARM::LDR_POST_IMM:
59 case ARM::LDR_POST_REG:
64 case ARM::LDRB_PRE_IMM:
65 case ARM::LDRB_PRE_REG:
66 case ARM::LDRB_POST_IMM:
67 case ARM::LDRB_POST_REG:
75 case ARM::STR_PRE_IMM:
76 case ARM::STR_PRE_REG:
77 case ARM::STR_POST_IMM:
78 case ARM::STR_POST_REG:
83 case ARM::STRB_PRE_IMM:
84 case ARM::STRB_PRE_REG:
85 case ARM::STRB_POST_IMM:
86 case ARM::STRB_POST_REG:
93 void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI,
94 Reloc::Model RM) const {
95 MachineFunction &MF = *MI->getParent()->getParent();
96 const ARMSubtarget &Subtarget = MF.getTarget().getSubtarget<ARMSubtarget>();
98 if (!Subtarget.useMovt(MF)) {
99 if (RM == Reloc::PIC_)
100 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12, RM);
102 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12, RM);
106 if (RM != Reloc::PIC_) {
107 expandLoadStackGuardBase(MI, ARM::MOVi32imm, ARM::LDRi12, RM);
111 const GlobalValue *GV =
112 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
114 if (!Subtarget.GVIsIndirectSymbol(GV, RM)) {
115 expandLoadStackGuardBase(MI, ARM::MOV_ga_pcrel, ARM::LDRi12, RM);
119 MachineBasicBlock &MBB = *MI->getParent();
120 DebugLoc DL = MI->getDebugLoc();
121 unsigned Reg = MI->getOperand(0).getReg();
122 MachineInstrBuilder MIB;
124 MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg)
125 .addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
126 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
127 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
128 MachinePointerInfo::getGOT(), Flag, 4, 4);
129 MIB.addMemOperand(MMO);
130 MIB = BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg);
131 MIB.addReg(Reg, RegState::Kill).addImm(0);
132 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
137 /// ARMCGBR - Create Global Base Reg pass. This initializes the PIC
138 /// global base register for ARM ELF.
139 struct ARMCGBR : public MachineFunctionPass {
141 ARMCGBR() : MachineFunctionPass(ID) {}
143 bool runOnMachineFunction(MachineFunction &MF) override {
144 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
145 if (AFI->getGlobalBaseReg() == 0)
148 const ARMTargetMachine *TM =
149 static_cast<const ARMTargetMachine *>(&MF.getTarget());
150 if (TM->getRelocationModel() != Reloc::PIC_)
153 LLVMContext *Context = &MF.getFunction()->getContext();
154 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
155 unsigned PCAdj = TM->getSubtarget<ARMSubtarget>().isThumb() ? 4 : 8;
156 ARMConstantPoolValue *CPV = ARMConstantPoolSymbol::Create(
157 *Context, "_GLOBAL_OFFSET_TABLE_", ARMPCLabelIndex, PCAdj);
159 unsigned Align = TM->getDataLayout()->getPrefTypeAlignment(
160 Type::getInt32PtrTy(*Context));
161 unsigned Idx = MF.getConstantPool()->getConstantPoolIndex(CPV, Align);
163 MachineBasicBlock &FirstMBB = MF.front();
164 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
165 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
167 MF.getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
168 const ARMSubtarget &STI =
169 static_cast<const ARMSubtarget &>(MF.getSubtarget());
170 unsigned Opc = STI.isThumb2() ? ARM::t2LDRpci : ARM::LDRcp;
171 const TargetInstrInfo &TII = *STI.getInstrInfo();
172 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL,
173 TII.get(Opc), TempReg)
174 .addConstantPoolIndex(Idx);
175 if (Opc == ARM::LDRcp)
179 // Fix the GOT address by adding pc.
180 unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
181 Opc = STI.isThumb2() ? ARM::tPICADD : ARM::PICADD;
182 MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), GlobalBaseReg)
184 .addImm(ARMPCLabelIndex);
185 if (Opc == ARM::PICADD)
192 const char *getPassName() const override {
193 return "ARM PIC Global Base Reg Initialization";
196 void getAnalysisUsage(AnalysisUsage &AU) const override {
197 AU.setPreservesCFG();
198 MachineFunctionPass::getAnalysisUsage(AU);
203 char ARMCGBR::ID = 0;
205 llvm::createARMGlobalBaseRegPass() { return new ARMCGBR(); }