1 //===-- ARMInstrInfo.cpp - ARM Instruction Information --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMTargetMachine.h"
19 #include "MCTargetDesc/ARMAddressingModes.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/GlobalVariable.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCInst.h"
32 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
33 : ARMBaseInstrInfo(STI), RI(STI) {
36 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
37 void ARMInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
39 NopInst.setOpcode(ARM::HINT);
40 NopInst.addOperand(MCOperand::CreateImm(0));
41 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
42 NopInst.addOperand(MCOperand::CreateReg(0));
44 NopInst.setOpcode(ARM::MOVr);
45 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
46 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
47 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
48 NopInst.addOperand(MCOperand::CreateReg(0));
49 NopInst.addOperand(MCOperand::CreateReg(0));
53 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
56 case ARM::LDR_PRE_IMM:
57 case ARM::LDR_PRE_REG:
58 case ARM::LDR_POST_IMM:
59 case ARM::LDR_POST_REG:
64 case ARM::LDRB_PRE_IMM:
65 case ARM::LDRB_PRE_REG:
66 case ARM::LDRB_POST_IMM:
67 case ARM::LDRB_POST_REG:
75 case ARM::STR_PRE_IMM:
76 case ARM::STR_PRE_REG:
77 case ARM::STR_POST_IMM:
78 case ARM::STR_POST_REG:
83 case ARM::STRB_PRE_IMM:
84 case ARM::STRB_PRE_REG:
85 case ARM::STRB_POST_IMM:
86 case ARM::STRB_POST_REG:
93 void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI,
94 Reloc::Model RM) const {
95 if (RM == Reloc::PIC_)
96 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_pcrel, ARM::LDRi12, RM);
98 expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12, RM);
101 bool ARMInstrInfo::getRegSequenceLikeInputs(
102 const MachineInstr &MI, unsigned DefIdx,
103 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
104 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
105 assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
107 switch (MI.getOpcode()) {
109 // dX = VMOVDRR rY, rZ
111 // dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1
112 // Populate the InputRegs accordingly.
114 const MachineOperand *MOReg = &MI.getOperand(1);
116 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
118 MOReg = &MI.getOperand(2);
120 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
123 llvm_unreachable("Target dependent opcode missing");
126 bool ARMInstrInfo::getExtractSubregLikeInputs(
127 const MachineInstr &MI, unsigned DefIdx,
128 RegSubRegPairAndIdx &InputReg) const {
129 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
130 assert(MI.isExtractSubregLike() && "Invalid kind of instruction");
132 switch (MI.getOpcode()) {
134 // rX, rY = VMOVRRD dZ
136 // rX = EXTRACT_SUBREG dZ, ssub_0
137 // rY = EXTRACT_SUBREG dZ, ssub_1
138 const MachineOperand &MOReg = MI.getOperand(2);
139 InputReg.Reg = MOReg.getReg();
140 InputReg.SubReg = MOReg.getSubReg();
141 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
144 llvm_unreachable("Target dependent opcode missing");
147 bool ARMInstrInfo::getInsertSubregLikeInputs(
148 const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,
149 RegSubRegPairAndIdx &InsertedReg) const {
150 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
151 assert(MI.isInsertSubregLike() && "Invalid kind of instruction");
153 switch (MI.getOpcode()) {
155 // dX = VSETLNi32 dY, rZ, imm
156 const MachineOperand &MOBaseReg = MI.getOperand(1);
157 const MachineOperand &MOInsertedReg = MI.getOperand(2);
158 const MachineOperand &MOIndex = MI.getOperand(3);
159 BaseReg.Reg = MOBaseReg.getReg();
160 BaseReg.SubReg = MOBaseReg.getSubReg();
162 InsertedReg.Reg = MOInsertedReg.getReg();
163 InsertedReg.SubReg = MOInsertedReg.getSubReg();
164 InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1;
167 llvm_unreachable("Target dependent opcode missing");
171 /// ARMCGBR - Create Global Base Reg pass. This initializes the PIC
172 /// global base register for ARM ELF.
173 struct ARMCGBR : public MachineFunctionPass {
175 ARMCGBR() : MachineFunctionPass(ID) {}
177 bool runOnMachineFunction(MachineFunction &MF) override {
178 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
179 if (AFI->getGlobalBaseReg() == 0)
182 const ARMTargetMachine *TM =
183 static_cast<const ARMTargetMachine *>(&MF.getTarget());
184 if (TM->getRelocationModel() != Reloc::PIC_)
187 LLVMContext *Context = &MF.getFunction()->getContext();
188 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
189 unsigned PCAdj = TM->getSubtarget<ARMSubtarget>().isThumb() ? 4 : 8;
190 ARMConstantPoolValue *CPV = ARMConstantPoolSymbol::Create(
191 *Context, "_GLOBAL_OFFSET_TABLE_", ARMPCLabelIndex, PCAdj);
194 TM->getSubtargetImpl()->getDataLayout()->getPrefTypeAlignment(
195 Type::getInt32PtrTy(*Context));
196 unsigned Idx = MF.getConstantPool()->getConstantPoolIndex(CPV, Align);
198 MachineBasicBlock &FirstMBB = MF.front();
199 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
200 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
202 MF.getRegInfo().createVirtualRegister(&ARM::rGPRRegClass);
203 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ?
204 ARM::t2LDRpci : ARM::LDRcp;
205 const TargetInstrInfo &TII = *TM->getSubtargetImpl()->getInstrInfo();
206 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL,
207 TII.get(Opc), TempReg)
208 .addConstantPoolIndex(Idx);
209 if (Opc == ARM::LDRcp)
213 // Fix the GOT address by adding pc.
214 unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
215 Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? ARM::tPICADD
217 MIB = BuildMI(FirstMBB, MBBI, DL, TII.get(Opc), GlobalBaseReg)
219 .addImm(ARMPCLabelIndex);
220 if (Opc == ARM::PICADD)
227 const char *getPassName() const override {
228 return "ARM PIC Global Base Reg Initialization";
231 void getAnalysisUsage(AnalysisUsage &AU) const override {
232 AU.setPreservesCFG();
233 MachineFunctionPass::getAnalysisUsage(AU);
238 char ARMCGBR::ID = 0;
240 llvm::createARMGlobalBaseRegPass() { return new ARMCGBR(); }