1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/Support/CommandLine.h"
29 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
30 cl::desc("Enable ARM 2-addr to 3-addr conv"));
33 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
34 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
38 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
42 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget &STI)
43 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)) {
46 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
47 : ARMBaseInstrInfo(STI), RI(*this, STI) {
50 void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB,
51 MachineBasicBlock::iterator I,
53 const MachineInstr *Orig) const {
54 DebugLoc dl = Orig->getDebugLoc();
55 if (Orig->getOpcode() == ARM::MOVi2pieces) {
56 RI.emitLoadConstPool(MBB, I, this, dl,
58 Orig->getOperand(1).getImm(),
59 (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
60 Orig->getOperand(3).getReg());
64 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
65 MI->getOperand(0).setReg(DestReg);
69 static unsigned getUnindexedOpcode(unsigned Opc) {
101 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
102 MachineBasicBlock::iterator &MBBI,
103 LiveVariables *LV) const {
107 MachineInstr *MI = MBBI;
108 MachineFunction &MF = *MI->getParent()->getParent();
109 unsigned TSFlags = MI->getDesc().TSFlags;
111 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
112 default: return NULL;
113 case ARMII::IndexModePre:
116 case ARMII::IndexModePost:
120 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
122 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
126 MachineInstr *UpdateMI = NULL;
127 MachineInstr *MemMI = NULL;
128 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
129 const TargetInstrDesc &TID = MI->getDesc();
130 unsigned NumOps = TID.getNumOperands();
131 bool isLoad = !TID.mayStore();
132 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
133 const MachineOperand &Base = MI->getOperand(2);
134 const MachineOperand &Offset = MI->getOperand(NumOps-3);
135 unsigned WBReg = WB.getReg();
136 unsigned BaseReg = Base.getReg();
137 unsigned OffReg = Offset.getReg();
138 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
139 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
142 assert(false && "Unknown indexed op!");
144 case ARMII::AddrMode2: {
145 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
146 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
148 int SOImmVal = ARM_AM::getSOImmVal(Amt);
150 // Can't encode it in a so_imm operand. This transformation will
151 // add more than 1 instruction. Abandon!
153 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
154 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
155 .addReg(BaseReg).addImm(SOImmVal)
156 .addImm(Pred).addReg(0).addReg(0);
157 } else if (Amt != 0) {
158 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
159 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
160 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
161 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
162 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
163 .addImm(Pred).addReg(0).addReg(0);
165 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
166 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
167 .addReg(BaseReg).addReg(OffReg)
168 .addImm(Pred).addReg(0).addReg(0);
171 case ARMII::AddrMode3 : {
172 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
173 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
175 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
176 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
177 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
178 .addReg(BaseReg).addImm(Amt)
179 .addImm(Pred).addReg(0).addReg(0);
181 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
182 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
183 .addReg(BaseReg).addReg(OffReg)
184 .addImm(Pred).addReg(0).addReg(0);
189 std::vector<MachineInstr*> NewMIs;
192 MemMI = BuildMI(MF, MI->getDebugLoc(),
193 get(MemOpc), MI->getOperand(0).getReg())
194 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
196 MemMI = BuildMI(MF, MI->getDebugLoc(),
197 get(MemOpc)).addReg(MI->getOperand(1).getReg())
198 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
199 NewMIs.push_back(MemMI);
200 NewMIs.push_back(UpdateMI);
203 MemMI = BuildMI(MF, MI->getDebugLoc(),
204 get(MemOpc), MI->getOperand(0).getReg())
205 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
207 MemMI = BuildMI(MF, MI->getDebugLoc(),
208 get(MemOpc)).addReg(MI->getOperand(1).getReg())
209 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
211 UpdateMI->getOperand(0).setIsDead();
212 NewMIs.push_back(UpdateMI);
213 NewMIs.push_back(MemMI);
216 // Transfer LiveVariables states, kill / dead info.
218 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
219 MachineOperand &MO = MI->getOperand(i);
220 if (MO.isReg() && MO.getReg() &&
221 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
222 unsigned Reg = MO.getReg();
224 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
226 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
228 LV->addVirtualRegisterDead(Reg, NewMI);
230 if (MO.isUse() && MO.isKill()) {
231 for (unsigned j = 0; j < 2; ++j) {
232 // Look at the two new MI's in reverse order.
233 MachineInstr *NewMI = NewMIs[j];
234 if (!NewMI->readsRegister(Reg))
236 LV->addVirtualRegisterKilled(Reg, NewMI);
237 if (VI.removeKill(MI))
238 VI.Kills.push_back(NewMI);
246 MFI->insert(MBBI, NewMIs[1]);
247 MFI->insert(MBBI, NewMIs[0]);
253 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
254 MachineBasicBlock *&FBB,
255 SmallVectorImpl<MachineOperand> &Cond,
256 bool AllowModify) const {
257 // If the block has no terminators, it just falls into the block after it.
258 MachineBasicBlock::iterator I = MBB.end();
259 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
262 // Get the last instruction in the block.
263 MachineInstr *LastInst = I;
265 // If there is only one terminator instruction, process it.
266 unsigned LastOpc = LastInst->getOpcode();
267 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
268 if (LastOpc == ARM::B || LastOpc == ARM::tB || LastOpc == ARM::t2B) {
269 TBB = LastInst->getOperand(0).getMBB();
272 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc || LastOpc == ARM::t2Bcc) {
273 // Block ends with fall-through condbranch.
274 TBB = LastInst->getOperand(0).getMBB();
275 Cond.push_back(LastInst->getOperand(1));
276 Cond.push_back(LastInst->getOperand(2));
279 return true; // Can't handle indirect branch.
282 // Get the instruction before it if it is a terminator.
283 MachineInstr *SecondLastInst = I;
285 // If there are three terminators, we don't know what sort of block this is.
286 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
289 // If the block ends with ARM::B/ARM::tB/ARM::t2B and a
290 // ARM::Bcc/ARM::tBcc/ARM::t2Bcc, handle it.
291 unsigned SecondLastOpc = SecondLastInst->getOpcode();
292 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
293 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB) ||
294 (SecondLastOpc == ARM::t2Bcc && LastOpc == ARM::t2B)) {
295 TBB = SecondLastInst->getOperand(0).getMBB();
296 Cond.push_back(SecondLastInst->getOperand(1));
297 Cond.push_back(SecondLastInst->getOperand(2));
298 FBB = LastInst->getOperand(0).getMBB();
302 // If the block ends with two unconditional branches, handle it. The second
303 // one is not executed, so remove it.
304 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB ||
305 SecondLastOpc==ARM::t2B) &&
306 (LastOpc == ARM::B || LastOpc == ARM::tB || LastOpc == ARM::t2B)) {
307 TBB = SecondLastInst->getOperand(0).getMBB();
310 I->eraseFromParent();
314 // ...likewise if it ends with a branch table followed by an unconditional
315 // branch. The branch folder can create these, and we must get rid of them for
316 // correctness of Thumb constant islands.
317 if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
318 SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr ||
319 SecondLastOpc == ARM::t2BR_JTr || SecondLastOpc==ARM::t2BR_JTm ||
320 SecondLastOpc == ARM::t2BR_JTadd) &&
321 (LastOpc == ARM::B || LastOpc == ARM::tB || LastOpc == ARM::t2B)) {
324 I->eraseFromParent();
328 // Otherwise, can't handle this.
333 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
334 MachineFunction &MF = *MBB.getParent();
335 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
336 int BOpc = AFI->isThumbFunction() ?
337 (AFI->isThumb2Function() ? ARM::t2B : ARM::tB) : ARM::B;
338 int BccOpc = AFI->isThumbFunction() ?
339 (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
341 MachineBasicBlock::iterator I = MBB.end();
342 if (I == MBB.begin()) return 0;
344 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
347 // Remove the branch.
348 I->eraseFromParent();
352 if (I == MBB.begin()) return 1;
354 if (I->getOpcode() != BccOpc)
357 // Remove the branch.
358 I->eraseFromParent();
363 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
364 MachineBasicBlock *FBB,
365 const SmallVectorImpl<MachineOperand> &Cond) const {
366 // FIXME this should probably have a DebugLoc argument
367 DebugLoc dl = DebugLoc::getUnknownLoc();
368 MachineFunction &MF = *MBB.getParent();
369 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
370 int BOpc = AFI->isThumbFunction() ?
371 (AFI->isThumb2Function() ? ARM::t2B : ARM::tB) : ARM::B;
372 int BccOpc = AFI->isThumbFunction() ?
373 (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
375 // Shouldn't be a fall through.
376 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
377 assert((Cond.size() == 2 || Cond.size() == 0) &&
378 "ARM branch conditions have two components!");
381 if (Cond.empty()) // Unconditional branch?
382 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
384 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
385 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
389 // Two-way conditional branch.
390 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
391 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
392 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
397 ARMBaseInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
398 if (MBB.empty()) return false;
400 switch (MBB.back().getOpcode()) {
401 case ARM::BX_RET: // Return.
404 case ARM::tBX_RET_vararg:
408 case ARM::t2B: // Uncond branch.
411 case ARM::BR_JTr: // Jumptable branch.
413 case ARM::BR_JTm: // Jumptable branch through mem.
414 case ARM::t2BR_JTadd:
415 case ARM::BR_JTadd: // Jumptable branch add to pc.
417 default: return false;
421 bool ARMBaseInstrInfo::
422 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
423 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
424 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
428 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
429 int PIdx = MI->findFirstPredOperandIdx();
430 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
433 bool ARMBaseInstrInfo::
434 PredicateInstruction(MachineInstr *MI,
435 const SmallVectorImpl<MachineOperand> &Pred) const {
436 unsigned Opc = MI->getOpcode();
437 if (Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B) {
438 MI->setDesc(get((Opc == ARM::B) ? ARM::Bcc :
439 ((Opc == ARM::tB) ? ARM::tBcc : ARM::t2Bcc)));
440 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
441 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
445 int PIdx = MI->findFirstPredOperandIdx();
447 MachineOperand &PMO = MI->getOperand(PIdx);
448 PMO.setImm(Pred[0].getImm());
449 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
455 bool ARMBaseInstrInfo::
456 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
457 const SmallVectorImpl<MachineOperand> &Pred2) const {
458 if (Pred1.size() > 2 || Pred2.size() > 2)
461 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
462 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
472 return CC2 == ARMCC::HI;
474 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
476 return CC2 == ARMCC::GT;
478 return CC2 == ARMCC::LT;
482 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
483 std::vector<MachineOperand> &Pred) const {
484 const TargetInstrDesc &TID = MI->getDesc();
485 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
489 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
490 const MachineOperand &MO = MI->getOperand(i);
491 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
501 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
502 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
503 unsigned JTI) DISABLE_INLINE;
504 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
506 return JT[JTI].MBBs.size();
509 /// GetInstSize - Return the size of the specified MachineInstr.
511 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
512 const MachineBasicBlock &MBB = *MI->getParent();
513 const MachineFunction *MF = MBB.getParent();
514 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
516 // Basic size info comes from the TSFlags field.
517 const TargetInstrDesc &TID = MI->getDesc();
518 unsigned TSFlags = TID.TSFlags;
520 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
522 // If this machine instr is an inline asm, measure it.
523 if (MI->getOpcode() == ARM::INLINEASM)
524 return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
527 switch (MI->getOpcode()) {
529 assert(0 && "Unknown or unset size field for instr!");
531 case TargetInstrInfo::IMPLICIT_DEF:
532 case TargetInstrInfo::DECLARE:
533 case TargetInstrInfo::DBG_LABEL:
534 case TargetInstrInfo::EH_LABEL:
539 case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
540 case ARMII::Size4Bytes: return 4; // Arm instruction.
541 case ARMII::Size2Bytes: return 2; // Thumb instruction.
542 case ARMII::SizeSpecial: {
543 switch (MI->getOpcode()) {
544 case ARM::CONSTPOOL_ENTRY:
545 // If this machine instr is a constant pool entry, its size is recorded as
547 return MI->getOperand(2).getImm();
548 case ARM::Int_eh_sjlj_setjmp: return 12;
554 case ARM::t2BR_JTadd:
556 // These are jumptable branches, i.e. a branch followed by an inlined
557 // jumptable. The size is 4 + 4 * number of entries.
558 unsigned NumOps = TID.getNumOperands();
559 MachineOperand JTOP =
560 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
561 unsigned JTI = JTOP.getIndex();
562 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
563 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
564 assert(JTI < JT.size());
565 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
566 // 4 aligned. The assembler / linker may add 2 byte padding just before
567 // the JT entries. The size does not include this padding; the
568 // constant islands pass does separate bookkeeping for it.
569 // FIXME: If we know the size of the function is less than (1 << 16) *2
570 // bytes, we can use 16-bit entries instead. Then there won't be an
572 return getNumJTEntries(JT, JTI) * 4 +
573 ((MI->getOpcode()==ARM::tBR_JTr) ? 2 : 4);
576 // Otherwise, pseudo-instruction sizes are zero.
581 return 0; // Not reached
584 /// Return true if the instruction is a register to register move and
585 /// leave the source and dest operands in the passed parameters.
588 ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
589 unsigned &SrcReg, unsigned &DstReg,
590 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
591 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
593 unsigned oc = MI.getOpcode();
601 SrcReg = MI.getOperand(1).getReg();
602 DstReg = MI.getOperand(0).getReg();
605 assert(MI.getDesc().getNumOperands() >= 2 &&
606 MI.getOperand(0).isReg() &&
607 MI.getOperand(1).isReg() &&
608 "Invalid ARM MOV instruction");
609 SrcReg = MI.getOperand(1).getReg();
610 DstReg = MI.getOperand(0).getReg();
616 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
617 int &FrameIndex) const {
618 switch (MI->getOpcode()) {
621 if (MI->getOperand(1).isFI() &&
622 MI->getOperand(2).isReg() &&
623 MI->getOperand(3).isImm() &&
624 MI->getOperand(2).getReg() == 0 &&
625 MI->getOperand(3).getImm() == 0) {
626 FrameIndex = MI->getOperand(1).getIndex();
627 return MI->getOperand(0).getReg();
632 if (MI->getOperand(1).isFI() &&
633 MI->getOperand(2).isImm() &&
634 MI->getOperand(2).getImm() == 0) {
635 FrameIndex = MI->getOperand(1).getIndex();
636 return MI->getOperand(0).getReg();
644 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
645 int &FrameIndex) const {
646 switch (MI->getOpcode()) {
649 if (MI->getOperand(1).isFI() &&
650 MI->getOperand(2).isReg() &&
651 MI->getOperand(3).isImm() &&
652 MI->getOperand(2).getReg() == 0 &&
653 MI->getOperand(3).getImm() == 0) {
654 FrameIndex = MI->getOperand(1).getIndex();
655 return MI->getOperand(0).getReg();
660 if (MI->getOperand(1).isFI() &&
661 MI->getOperand(2).isImm() &&
662 MI->getOperand(2).getImm() == 0) {
663 FrameIndex = MI->getOperand(1).getIndex();
664 return MI->getOperand(0).getReg();
673 ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
674 MachineBasicBlock::iterator I,
675 unsigned DestReg, unsigned SrcReg,
676 const TargetRegisterClass *DestRC,
677 const TargetRegisterClass *SrcRC) const {
678 DebugLoc DL = DebugLoc::getUnknownLoc();
679 if (I != MBB.end()) DL = I->getDebugLoc();
681 if (DestRC != SrcRC) {
682 // Not yet supported!
686 if (DestRC == ARM::GPRRegisterClass)
687 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
689 else if (DestRC == ARM::SPRRegisterClass)
690 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
692 else if (DestRC == ARM::DPRRegisterClass)
693 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
695 else if (DestRC == ARM::QPRRegisterClass)
696 BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
703 void ARMBaseInstrInfo::
704 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
705 unsigned SrcReg, bool isKill, int FI,
706 const TargetRegisterClass *RC) const {
707 DebugLoc DL = DebugLoc::getUnknownLoc();
708 if (I != MBB.end()) DL = I->getDebugLoc();
710 if (RC == ARM::GPRRegisterClass) {
711 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
712 .addReg(SrcReg, getKillRegState(isKill))
713 .addFrameIndex(FI).addReg(0).addImm(0));
714 } else if (RC == ARM::DPRRegisterClass) {
715 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
716 .addReg(SrcReg, getKillRegState(isKill))
717 .addFrameIndex(FI).addImm(0));
719 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
720 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
721 .addReg(SrcReg, getKillRegState(isKill))
722 .addFrameIndex(FI).addImm(0));
727 ARMBaseInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
729 SmallVectorImpl<MachineOperand> &Addr,
730 const TargetRegisterClass *RC,
731 SmallVectorImpl<MachineInstr*> &NewMIs) const{
732 DebugLoc DL = DebugLoc::getUnknownLoc();
734 if (RC == ARM::GPRRegisterClass) {
736 } else if (RC == ARM::DPRRegisterClass) {
739 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
743 MachineInstrBuilder MIB =
744 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
745 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
746 MIB.addOperand(Addr[i]);
748 NewMIs.push_back(MIB);
752 void ARMBaseInstrInfo::
753 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
754 unsigned DestReg, int FI,
755 const TargetRegisterClass *RC) const {
756 DebugLoc DL = DebugLoc::getUnknownLoc();
757 if (I != MBB.end()) DL = I->getDebugLoc();
759 if (RC == ARM::GPRRegisterClass) {
760 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
761 .addFrameIndex(FI).addReg(0).addImm(0));
762 } else if (RC == ARM::DPRRegisterClass) {
763 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
764 .addFrameIndex(FI).addImm(0));
766 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
767 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
768 .addFrameIndex(FI).addImm(0));
772 void ARMBaseInstrInfo::
773 loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
774 SmallVectorImpl<MachineOperand> &Addr,
775 const TargetRegisterClass *RC,
776 SmallVectorImpl<MachineInstr*> &NewMIs) const {
777 DebugLoc DL = DebugLoc::getUnknownLoc();
779 if (RC == ARM::GPRRegisterClass) {
781 } else if (RC == ARM::DPRRegisterClass) {
784 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
788 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
789 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
790 MIB.addOperand(Addr[i]);
792 NewMIs.push_back(MIB);
796 MachineInstr *ARMBaseInstrInfo::
797 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
798 const SmallVectorImpl<unsigned> &Ops, int FI) const {
799 if (Ops.size() != 1) return NULL;
801 unsigned OpNum = Ops[0];
802 unsigned Opc = MI->getOpcode();
803 MachineInstr *NewMI = NULL;
807 if (MI->getOperand(4).getReg() == ARM::CPSR)
808 // If it is updating CPSR, then it cannot be folded.
810 unsigned Pred = MI->getOperand(2).getImm();
811 unsigned PredReg = MI->getOperand(3).getReg();
812 if (OpNum == 0) { // move -> store
813 unsigned SrcReg = MI->getOperand(1).getReg();
814 bool isKill = MI->getOperand(1).isKill();
815 bool isUndef = MI->getOperand(1).isUndef();
816 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
817 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
818 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
819 } else { // move -> load
820 unsigned DstReg = MI->getOperand(0).getReg();
821 bool isDead = MI->getOperand(0).isDead();
822 bool isUndef = MI->getOperand(0).isUndef();
823 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
826 getDeadRegState(isDead) |
827 getUndefRegState(isUndef))
828 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
833 unsigned Pred = MI->getOperand(2).getImm();
834 unsigned PredReg = MI->getOperand(3).getReg();
835 if (OpNum == 0) { // move -> store
836 unsigned SrcReg = MI->getOperand(1).getReg();
837 bool isKill = MI->getOperand(1).isKill();
838 bool isUndef = MI->getOperand(1).isUndef();
839 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
840 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
842 .addImm(0).addImm(Pred).addReg(PredReg);
843 } else { // move -> load
844 unsigned DstReg = MI->getOperand(0).getReg();
845 bool isDead = MI->getOperand(0).isDead();
846 bool isUndef = MI->getOperand(0).isUndef();
847 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
850 getDeadRegState(isDead) |
851 getUndefRegState(isUndef))
852 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
857 unsigned Pred = MI->getOperand(2).getImm();
858 unsigned PredReg = MI->getOperand(3).getReg();
859 if (OpNum == 0) { // move -> store
860 unsigned SrcReg = MI->getOperand(1).getReg();
861 bool isKill = MI->getOperand(1).isKill();
862 bool isUndef = MI->getOperand(1).isUndef();
863 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
864 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
865 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
866 } else { // move -> load
867 unsigned DstReg = MI->getOperand(0).getReg();
868 bool isDead = MI->getOperand(0).isDead();
869 bool isUndef = MI->getOperand(0).isUndef();
870 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
873 getDeadRegState(isDead) |
874 getUndefRegState(isUndef))
875 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
885 ARMBaseInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
887 const SmallVectorImpl<unsigned> &Ops,
888 MachineInstr* LoadMI) const {
893 ARMBaseInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
894 const SmallVectorImpl<unsigned> &Ops) const {
895 if (Ops.size() != 1) return false;
897 unsigned Opc = MI->getOpcode();
901 // If it is updating CPSR, then it cannot be folded.
902 return MI->getOperand(4).getReg() != ARM::CPSR;
909 return false; // FIXME