1 //===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMAddressingModes.h"
17 #include "ARMGenInstrInfo.inc"
18 #include "ARMMachineFunctionInfo.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineJumpTableInfo.h"
24 #include "llvm/Target/TargetAsmInfo.h"
25 #include "llvm/Support/CommandLine.h"
29 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
30 cl::desc("Enable ARM 2-addr to 3-addr conv"));
33 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
34 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
38 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
42 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
43 : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
48 /// Return true if the instruction is a register to register move and
49 /// leave the source and dest operands in the passed parameters.
51 bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
52 unsigned &SrcReg, unsigned &DstReg,
53 unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
54 SrcSubIdx = DstSubIdx = 0; // No sub-registers.
56 unsigned oc = MI.getOpcode();
62 SrcReg = MI.getOperand(1).getReg();
63 DstReg = MI.getOperand(0).getReg();
67 assert(MI.getDesc().getNumOperands() >= 2 &&
68 MI.getOperand(0).isReg() &&
69 MI.getOperand(1).isReg() &&
70 "Invalid ARM MOV instruction");
71 SrcReg = MI.getOperand(1).getReg();
72 DstReg = MI.getOperand(0).getReg();
77 unsigned ARMInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
78 int &FrameIndex) const {
79 switch (MI->getOpcode()) {
82 if (MI->getOperand(1).isFI() &&
83 MI->getOperand(2).isReg() &&
84 MI->getOperand(3).isImm() &&
85 MI->getOperand(2).getReg() == 0 &&
86 MI->getOperand(3).getImm() == 0) {
87 FrameIndex = MI->getOperand(1).getIndex();
88 return MI->getOperand(0).getReg();
93 if (MI->getOperand(1).isFI() &&
94 MI->getOperand(2).isImm() &&
95 MI->getOperand(2).getImm() == 0) {
96 FrameIndex = MI->getOperand(1).getIndex();
97 return MI->getOperand(0).getReg();
101 if (MI->getOperand(1).isFI() &&
102 MI->getOperand(2).isImm() &&
103 MI->getOperand(2).getImm() == 0) {
104 FrameIndex = MI->getOperand(1).getIndex();
105 return MI->getOperand(0).getReg();
112 unsigned ARMInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
113 int &FrameIndex) const {
114 switch (MI->getOpcode()) {
117 if (MI->getOperand(1).isFI() &&
118 MI->getOperand(2).isReg() &&
119 MI->getOperand(3).isImm() &&
120 MI->getOperand(2).getReg() == 0 &&
121 MI->getOperand(3).getImm() == 0) {
122 FrameIndex = MI->getOperand(1).getIndex();
123 return MI->getOperand(0).getReg();
128 if (MI->getOperand(1).isFI() &&
129 MI->getOperand(2).isImm() &&
130 MI->getOperand(2).getImm() == 0) {
131 FrameIndex = MI->getOperand(1).getIndex();
132 return MI->getOperand(0).getReg();
136 if (MI->getOperand(1).isFI() &&
137 MI->getOperand(2).isImm() &&
138 MI->getOperand(2).getImm() == 0) {
139 FrameIndex = MI->getOperand(1).getIndex();
140 return MI->getOperand(0).getReg();
147 void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB,
148 MachineBasicBlock::iterator I,
150 const MachineInstr *Orig) const {
151 DebugLoc dl = Orig->getDebugLoc();
152 if (Orig->getOpcode() == ARM::MOVi2pieces) {
153 RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(),
154 Orig->getOperand(2).getImm(),
155 Orig->getOperand(3).getReg(), this, false, dl);
159 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
160 MI->getOperand(0).setReg(DestReg);
164 static unsigned getUnindexedOpcode(unsigned Opc) {
177 case ARM::LDRSH_POST:
180 case ARM::LDRSB_POST:
196 ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
197 MachineBasicBlock::iterator &MBBI,
198 LiveVariables *LV) const {
202 MachineInstr *MI = MBBI;
203 MachineFunction &MF = *MI->getParent()->getParent();
204 unsigned TSFlags = MI->getDesc().TSFlags;
206 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
207 default: return NULL;
208 case ARMII::IndexModePre:
211 case ARMII::IndexModePost:
215 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
217 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
221 MachineInstr *UpdateMI = NULL;
222 MachineInstr *MemMI = NULL;
223 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
224 const TargetInstrDesc &TID = MI->getDesc();
225 unsigned NumOps = TID.getNumOperands();
226 bool isLoad = !TID.mayStore();
227 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
228 const MachineOperand &Base = MI->getOperand(2);
229 const MachineOperand &Offset = MI->getOperand(NumOps-3);
230 unsigned WBReg = WB.getReg();
231 unsigned BaseReg = Base.getReg();
232 unsigned OffReg = Offset.getReg();
233 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
234 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
237 assert(false && "Unknown indexed op!");
239 case ARMII::AddrMode2: {
240 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
241 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
243 int SOImmVal = ARM_AM::getSOImmVal(Amt);
245 // Can't encode it in a so_imm operand. This transformation will
246 // add more than 1 instruction. Abandon!
248 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
249 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
250 .addReg(BaseReg).addImm(SOImmVal)
251 .addImm(Pred).addReg(0).addReg(0);
252 } else if (Amt != 0) {
253 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
254 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
255 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
256 get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
257 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
258 .addImm(Pred).addReg(0).addReg(0);
260 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
261 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
262 .addReg(BaseReg).addReg(OffReg)
263 .addImm(Pred).addReg(0).addReg(0);
266 case ARMII::AddrMode3 : {
267 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
268 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
270 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
271 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
272 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
273 .addReg(BaseReg).addImm(Amt)
274 .addImm(Pred).addReg(0).addReg(0);
276 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
277 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
278 .addReg(BaseReg).addReg(OffReg)
279 .addImm(Pred).addReg(0).addReg(0);
284 std::vector<MachineInstr*> NewMIs;
287 MemMI = BuildMI(MF, MI->getDebugLoc(),
288 get(MemOpc), MI->getOperand(0).getReg())
289 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
291 MemMI = BuildMI(MF, MI->getDebugLoc(),
292 get(MemOpc)).addReg(MI->getOperand(1).getReg())
293 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
294 NewMIs.push_back(MemMI);
295 NewMIs.push_back(UpdateMI);
298 MemMI = BuildMI(MF, MI->getDebugLoc(),
299 get(MemOpc), MI->getOperand(0).getReg())
300 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
302 MemMI = BuildMI(MF, MI->getDebugLoc(),
303 get(MemOpc)).addReg(MI->getOperand(1).getReg())
304 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
306 UpdateMI->getOperand(0).setIsDead();
307 NewMIs.push_back(UpdateMI);
308 NewMIs.push_back(MemMI);
311 // Transfer LiveVariables states, kill / dead info.
313 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
314 MachineOperand &MO = MI->getOperand(i);
315 if (MO.isReg() && MO.getReg() &&
316 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
317 unsigned Reg = MO.getReg();
319 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
321 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
323 LV->addVirtualRegisterDead(Reg, NewMI);
325 if (MO.isUse() && MO.isKill()) {
326 for (unsigned j = 0; j < 2; ++j) {
327 // Look at the two new MI's in reverse order.
328 MachineInstr *NewMI = NewMIs[j];
329 if (!NewMI->readsRegister(Reg))
331 LV->addVirtualRegisterKilled(Reg, NewMI);
332 if (VI.removeKill(MI))
333 VI.Kills.push_back(NewMI);
341 MFI->insert(MBBI, NewMIs[1]);
342 MFI->insert(MBBI, NewMIs[0]);
347 bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
348 MachineBasicBlock *&FBB,
349 SmallVectorImpl<MachineOperand> &Cond,
350 bool AllowModify) const {
351 // If the block has no terminators, it just falls into the block after it.
352 MachineBasicBlock::iterator I = MBB.end();
353 if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
356 // Get the last instruction in the block.
357 MachineInstr *LastInst = I;
359 // If there is only one terminator instruction, process it.
360 unsigned LastOpc = LastInst->getOpcode();
361 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
362 if (LastOpc == ARM::B || LastOpc == ARM::tB) {
363 TBB = LastInst->getOperand(0).getMBB();
366 if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
367 // Block ends with fall-through condbranch.
368 TBB = LastInst->getOperand(0).getMBB();
369 Cond.push_back(LastInst->getOperand(1));
370 Cond.push_back(LastInst->getOperand(2));
373 return true; // Can't handle indirect branch.
376 // Get the instruction before it if it is a terminator.
377 MachineInstr *SecondLastInst = I;
379 // If there are three terminators, we don't know what sort of block this is.
380 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
383 // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
384 unsigned SecondLastOpc = SecondLastInst->getOpcode();
385 if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
386 (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
387 TBB = SecondLastInst->getOperand(0).getMBB();
388 Cond.push_back(SecondLastInst->getOperand(1));
389 Cond.push_back(SecondLastInst->getOperand(2));
390 FBB = LastInst->getOperand(0).getMBB();
394 // If the block ends with two unconditional branches, handle it. The second
395 // one is not executed, so remove it.
396 if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
397 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
398 TBB = SecondLastInst->getOperand(0).getMBB();
401 I->eraseFromParent();
405 // ...likewise if it ends with a branch table followed by an unconditional
406 // branch. The branch folder can create these, and we must get rid of them for
407 // correctness of Thumb constant islands.
408 if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
409 SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr) &&
410 (LastOpc == ARM::B || LastOpc == ARM::tB)) {
413 I->eraseFromParent();
417 // Otherwise, can't handle this.
422 unsigned ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
423 MachineFunction &MF = *MBB.getParent();
424 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
425 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
426 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
428 MachineBasicBlock::iterator I = MBB.end();
429 if (I == MBB.begin()) return 0;
431 if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
434 // Remove the branch.
435 I->eraseFromParent();
439 if (I == MBB.begin()) return 1;
441 if (I->getOpcode() != BccOpc)
444 // Remove the branch.
445 I->eraseFromParent();
450 ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
451 MachineBasicBlock *FBB,
452 const SmallVectorImpl<MachineOperand> &Cond) const {
453 // FIXME this should probably have a DebugLoc argument
454 DebugLoc dl = DebugLoc::getUnknownLoc();
455 MachineFunction &MF = *MBB.getParent();
456 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
457 int BOpc = AFI->isThumbFunction() ? ARM::tB : ARM::B;
458 int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
460 // Shouldn't be a fall through.
461 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
462 assert((Cond.size() == 2 || Cond.size() == 0) &&
463 "ARM branch conditions have two components!");
466 if (Cond.empty()) // Unconditional branch?
467 BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
469 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
470 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
474 // Two-way conditional branch.
475 BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
476 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
477 BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
481 bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
482 MachineBasicBlock::iterator I,
483 unsigned DestReg, unsigned SrcReg,
484 const TargetRegisterClass *DestRC,
485 const TargetRegisterClass *SrcRC) const {
486 if (DestRC != SrcRC) {
487 // Not yet supported!
491 DebugLoc DL = DebugLoc::getUnknownLoc();
492 if (I != MBB.end()) DL = I->getDebugLoc();
494 if (DestRC == ARM::GPRRegisterClass) {
495 MachineFunction &MF = *MBB.getParent();
496 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
497 if (AFI->isThumbFunction())
498 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
500 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
502 } else if (DestRC == ARM::SPRRegisterClass)
503 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
505 else if (DestRC == ARM::DPRRegisterClass)
506 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
515 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
516 unsigned SrcReg, bool isKill, int FI,
517 const TargetRegisterClass *RC) const {
518 DebugLoc DL = DebugLoc::getUnknownLoc();
519 if (I != MBB.end()) DL = I->getDebugLoc();
521 if (RC == ARM::GPRRegisterClass) {
522 MachineFunction &MF = *MBB.getParent();
523 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
524 if (AFI->isThumbFunction())
525 BuildMI(MBB, I, DL, get(ARM::tSpill))
526 .addReg(SrcReg, false, false, isKill)
527 .addFrameIndex(FI).addImm(0);
529 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
530 .addReg(SrcReg, false, false, isKill)
531 .addFrameIndex(FI).addReg(0).addImm(0));
532 } else if (RC == ARM::DPRRegisterClass) {
533 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
534 .addReg(SrcReg, false, false, isKill)
535 .addFrameIndex(FI).addImm(0));
537 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
538 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
539 .addReg(SrcReg, false, false, isKill)
540 .addFrameIndex(FI).addImm(0));
544 void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
546 SmallVectorImpl<MachineOperand> &Addr,
547 const TargetRegisterClass *RC,
548 SmallVectorImpl<MachineInstr*> &NewMIs) const{
549 DebugLoc DL = DebugLoc::getUnknownLoc();
551 if (RC == ARM::GPRRegisterClass) {
552 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
553 if (AFI->isThumbFunction()) {
554 Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
555 MachineInstrBuilder MIB =
556 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
557 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
558 MIB.addOperand(Addr[i]);
559 NewMIs.push_back(MIB);
563 } else if (RC == ARM::DPRRegisterClass) {
566 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
570 MachineInstrBuilder MIB =
571 BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
572 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
573 MIB.addOperand(Addr[i]);
575 NewMIs.push_back(MIB);
580 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
581 unsigned DestReg, int FI,
582 const TargetRegisterClass *RC) const {
583 DebugLoc DL = DebugLoc::getUnknownLoc();
584 if (I != MBB.end()) DL = I->getDebugLoc();
586 if (RC == ARM::GPRRegisterClass) {
587 MachineFunction &MF = *MBB.getParent();
588 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
589 if (AFI->isThumbFunction())
590 BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
591 .addFrameIndex(FI).addImm(0);
593 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
594 .addFrameIndex(FI).addReg(0).addImm(0));
595 } else if (RC == ARM::DPRRegisterClass) {
596 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
597 .addFrameIndex(FI).addImm(0));
599 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
600 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
601 .addFrameIndex(FI).addImm(0));
606 loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
607 SmallVectorImpl<MachineOperand> &Addr,
608 const TargetRegisterClass *RC,
609 SmallVectorImpl<MachineInstr*> &NewMIs) const {
610 DebugLoc DL = DebugLoc::getUnknownLoc();
612 if (RC == ARM::GPRRegisterClass) {
613 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
614 if (AFI->isThumbFunction()) {
615 Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
616 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
617 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
618 MIB.addOperand(Addr[i]);
619 NewMIs.push_back(MIB);
623 } else if (RC == ARM::DPRRegisterClass) {
626 assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
630 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
631 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
632 MIB.addOperand(Addr[i]);
634 NewMIs.push_back(MIB);
639 spillCalleeSavedRegisters(MachineBasicBlock &MBB,
640 MachineBasicBlock::iterator MI,
641 const std::vector<CalleeSavedInfo> &CSI) const {
642 MachineFunction &MF = *MBB.getParent();
643 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
644 if (!AFI->isThumbFunction() || CSI.empty())
647 DebugLoc DL = DebugLoc::getUnknownLoc();
648 if (MI != MBB.end()) DL = MI->getDebugLoc();
650 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
651 for (unsigned i = CSI.size(); i != 0; --i) {
652 unsigned Reg = CSI[i-1].getReg();
653 // Add the callee-saved register as live-in. It's killed at the spill.
655 MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
661 restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
662 MachineBasicBlock::iterator MI,
663 const std::vector<CalleeSavedInfo> &CSI) const {
664 MachineFunction &MF = *MBB.getParent();
665 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
666 if (!AFI->isThumbFunction() || CSI.empty())
669 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
670 MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
671 MBB.insert(MI, PopMI);
672 for (unsigned i = CSI.size(); i != 0; --i) {
673 unsigned Reg = CSI[i-1].getReg();
674 if (Reg == ARM::LR) {
675 // Special epilogue for vararg functions. See emitEpilogue
679 PopMI->setDesc(get(ARM::tPOP_RET));
682 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
687 MachineInstr *ARMInstrInfo::
688 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
689 const SmallVectorImpl<unsigned> &Ops, int FI) const {
690 if (Ops.size() != 1) return NULL;
692 unsigned OpNum = Ops[0];
693 unsigned Opc = MI->getOpcode();
694 MachineInstr *NewMI = NULL;
698 if (MI->getOperand(4).getReg() == ARM::CPSR)
699 // If it is updating CPSR, then it cannot be folded.
701 unsigned Pred = MI->getOperand(2).getImm();
702 unsigned PredReg = MI->getOperand(3).getReg();
703 if (OpNum == 0) { // move -> store
704 unsigned SrcReg = MI->getOperand(1).getReg();
705 bool isKill = MI->getOperand(1).isKill();
706 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
707 .addReg(SrcReg, false, false, isKill)
708 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
709 } else { // move -> load
710 unsigned DstReg = MI->getOperand(0).getReg();
711 bool isDead = MI->getOperand(0).isDead();
712 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
713 .addReg(DstReg, true, false, false, isDead)
714 .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
719 if (OpNum == 0) { // move -> store
720 unsigned SrcReg = MI->getOperand(1).getReg();
721 bool isKill = MI->getOperand(1).isKill();
722 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
723 // tSpill cannot take a high register operand.
725 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
726 .addReg(SrcReg, false, false, isKill)
727 .addFrameIndex(FI).addImm(0);
728 } else { // move -> load
729 unsigned DstReg = MI->getOperand(0).getReg();
730 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
731 // tRestore cannot target a high register operand.
733 bool isDead = MI->getOperand(0).isDead();
734 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
735 .addReg(DstReg, true, false, false, isDead)
736 .addFrameIndex(FI).addImm(0);
741 unsigned Pred = MI->getOperand(2).getImm();
742 unsigned PredReg = MI->getOperand(3).getReg();
743 if (OpNum == 0) { // move -> store
744 unsigned SrcReg = MI->getOperand(1).getReg();
745 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
746 .addReg(SrcReg).addFrameIndex(FI)
747 .addImm(0).addImm(Pred).addReg(PredReg);
748 } else { // move -> load
749 unsigned DstReg = MI->getOperand(0).getReg();
750 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS), DstReg)
752 .addImm(0).addImm(Pred).addReg(PredReg);
757 unsigned Pred = MI->getOperand(2).getImm();
758 unsigned PredReg = MI->getOperand(3).getReg();
759 if (OpNum == 0) { // move -> store
760 unsigned SrcReg = MI->getOperand(1).getReg();
761 bool isKill = MI->getOperand(1).isKill();
762 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
763 .addReg(SrcReg, false, false, isKill)
764 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
765 } else { // move -> load
766 unsigned DstReg = MI->getOperand(0).getReg();
767 bool isDead = MI->getOperand(0).isDead();
768 NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
769 .addReg(DstReg, true, false, false, isDead)
770 .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
780 canFoldMemoryOperand(const MachineInstr *MI,
781 const SmallVectorImpl<unsigned> &Ops) const {
782 if (Ops.size() != 1) return false;
784 unsigned OpNum = Ops[0];
785 unsigned Opc = MI->getOpcode();
789 // If it is updating CPSR, then it cannot be folded.
790 return MI->getOperand(4).getReg() != ARM::CPSR;
792 if (OpNum == 0) { // move -> store
793 unsigned SrcReg = MI->getOperand(1).getReg();
794 if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
795 // tSpill cannot take a high register operand.
797 } else { // move -> load
798 unsigned DstReg = MI->getOperand(0).getReg();
799 if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
800 // tRestore cannot target a high register operand.
813 bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
814 if (MBB.empty()) return false;
816 switch (MBB.back().getOpcode()) {
817 case ARM::BX_RET: // Return.
820 case ARM::tBX_RET_vararg:
823 case ARM::tB: // Uncond branch.
825 case ARM::BR_JTr: // Jumptable branch.
826 case ARM::BR_JTm: // Jumptable branch through mem.
827 case ARM::BR_JTadd: // Jumptable branch add to pc.
829 default: return false;
834 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
835 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
836 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
840 bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
841 int PIdx = MI->findFirstPredOperandIdx();
842 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
846 PredicateInstruction(MachineInstr *MI,
847 const SmallVectorImpl<MachineOperand> &Pred) const {
848 unsigned Opc = MI->getOpcode();
849 if (Opc == ARM::B || Opc == ARM::tB) {
850 MI->setDesc(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
851 MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
852 MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
856 int PIdx = MI->findFirstPredOperandIdx();
858 MachineOperand &PMO = MI->getOperand(PIdx);
859 PMO.setImm(Pred[0].getImm());
860 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
867 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
868 const SmallVectorImpl<MachineOperand> &Pred2) const {
869 if (Pred1.size() > 2 || Pred2.size() > 2)
872 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
873 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
883 return CC2 == ARMCC::HI;
885 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
887 return CC2 == ARMCC::GT;
889 return CC2 == ARMCC::LT;
893 bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
894 std::vector<MachineOperand> &Pred) const {
895 const TargetInstrDesc &TID = MI->getDesc();
896 if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
900 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
901 const MachineOperand &MO = MI->getOperand(i);
902 if (MO.isReg() && MO.getReg() == ARM::CPSR) {
912 /// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
913 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
914 unsigned JTI) DISABLE_INLINE;
915 static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
917 return JT[JTI].MBBs.size();
920 /// GetInstSize - Return the size of the specified MachineInstr.
922 unsigned ARMInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
923 const MachineBasicBlock &MBB = *MI->getParent();
924 const MachineFunction *MF = MBB.getParent();
925 const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
927 // Basic size info comes from the TSFlags field.
928 const TargetInstrDesc &TID = MI->getDesc();
929 unsigned TSFlags = TID.TSFlags;
931 switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
933 // If this machine instr is an inline asm, measure it.
934 if (MI->getOpcode() == ARM::INLINEASM)
935 return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
938 switch (MI->getOpcode()) {
940 assert(0 && "Unknown or unset size field for instr!");
942 case TargetInstrInfo::IMPLICIT_DEF:
943 case TargetInstrInfo::DECLARE:
944 case TargetInstrInfo::DBG_LABEL:
945 case TargetInstrInfo::EH_LABEL:
950 case ARMII::Size8Bytes: return 8; // Arm instruction x 2.
951 case ARMII::Size4Bytes: return 4; // Arm instruction.
952 case ARMII::Size2Bytes: return 2; // Thumb instruction.
953 case ARMII::SizeSpecial: {
954 switch (MI->getOpcode()) {
955 case ARM::CONSTPOOL_ENTRY:
956 // If this machine instr is a constant pool entry, its size is recorded as
958 return MI->getOperand(2).getImm();
963 // These are jumptable branches, i.e. a branch followed by an inlined
964 // jumptable. The size is 4 + 4 * number of entries.
965 unsigned NumOps = TID.getNumOperands();
966 MachineOperand JTOP =
967 MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
968 unsigned JTI = JTOP.getIndex();
969 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
970 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
971 assert(JTI < JT.size());
972 // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
973 // 4 aligned. The assembler / linker may add 2 byte padding just before
974 // the JT entries. The size does not include this padding; the
975 // constant islands pass does separate bookkeeping for it.
976 // FIXME: If we know the size of the function is less than (1 << 16) *2
977 // bytes, we can use 16-bit entries instead. Then there won't be an
979 return getNumJTEntries(JT, JTI) * 4 +
980 (MI->getOpcode()==ARM::tBR_JTr ? 2 : 4);
983 // Otherwise, pseudo-instruction sizes are zero.
988 return 0; // Not reached