1 //===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
74 // The instruction has an Rn register operand.
75 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
76 // it doesn't have a Rn operand.
77 class UnaryDP { bit isUnaryDataProc = 1; }
79 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
80 // a 16-bit Thumb instruction if certain conditions are met.
81 class Xform16Bit { bit canXformTo16Bit = 1; }
83 //===----------------------------------------------------------------------===//
84 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
87 // FIXME: Once the JIT is MC-ized, these can go away.
89 class AddrMode<bits<5> val> {
92 def AddrModeNone : AddrMode<0>;
93 def AddrMode1 : AddrMode<1>;
94 def AddrMode2 : AddrMode<2>;
95 def AddrMode3 : AddrMode<3>;
96 def AddrMode4 : AddrMode<4>;
97 def AddrMode5 : AddrMode<5>;
98 def AddrMode6 : AddrMode<6>;
99 def AddrModeT1_1 : AddrMode<7>;
100 def AddrModeT1_2 : AddrMode<8>;
101 def AddrModeT1_4 : AddrMode<9>;
102 def AddrModeT1_s : AddrMode<10>;
103 def AddrModeT2_i12 : AddrMode<11>;
104 def AddrModeT2_i8 : AddrMode<12>;
105 def AddrModeT2_so : AddrMode<13>;
106 def AddrModeT2_pc : AddrMode<14>;
107 def AddrModeT2_i8s4 : AddrMode<15>;
108 def AddrMode_i12 : AddrMode<16>;
111 class SizeFlagVal<bits<3> val> {
114 def SizeInvalid : SizeFlagVal<0>; // Unset.
115 def SizeSpecial : SizeFlagVal<1>; // Pseudo or special.
116 def Size8Bytes : SizeFlagVal<2>;
117 def Size4Bytes : SizeFlagVal<3>;
118 def Size2Bytes : SizeFlagVal<4>;
120 // Load / store index mode.
121 class IndexMode<bits<2> val> {
124 def IndexModeNone : IndexMode<0>;
125 def IndexModePre : IndexMode<1>;
126 def IndexModePost : IndexMode<2>;
127 def IndexModeUpd : IndexMode<3>;
129 // Instruction execution domain.
130 class Domain<bits<2> val> {
133 def GenericDomain : Domain<0>;
134 def VFPDomain : Domain<1>; // Instructions in VFP domain only
135 def NeonDomain : Domain<2>; // Instructions in Neon domain only
136 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
138 //===----------------------------------------------------------------------===//
139 // ARM special operands.
142 def CondCodeOperand : AsmOperandClass {
143 let Name = "CondCode";
144 let SuperClasses = [];
147 def CCOutOperand : AsmOperandClass {
149 let SuperClasses = [];
152 def MemBarrierOptOperand : AsmOperandClass {
153 let Name = "MemBarrierOpt";
154 let SuperClasses = [];
155 let ParserMethod = "tryParseMemBarrierOptOperand";
158 def ProcIFlagsOperand : AsmOperandClass {
159 let Name = "ProcIFlags";
160 let SuperClasses = [];
161 let ParserMethod = "tryParseProcIFlagsOperand";
164 // ARM imod and iflag operands, used only by the CPS instruction.
165 def imod_op : Operand<i32> {
166 let PrintMethod = "printCPSIMod";
169 def iflags_op : Operand<i32> {
170 let PrintMethod = "printCPSIFlag";
171 let ParserMatchClass = ProcIFlagsOperand;
174 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
175 // register whose default is 0 (no register).
176 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
177 (ops (i32 14), (i32 zero_reg))> {
178 let PrintMethod = "printPredicateOperand";
179 let ParserMatchClass = CondCodeOperand;
182 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
183 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
184 let EncoderMethod = "getCCOutOpValue";
185 let PrintMethod = "printSBitModifierOperand";
186 let ParserMatchClass = CCOutOperand;
189 // Same as cc_out except it defaults to setting CPSR.
190 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
191 let EncoderMethod = "getCCOutOpValue";
192 let PrintMethod = "printSBitModifierOperand";
193 let ParserMatchClass = CCOutOperand;
196 // ARM special operands for disassembly only.
198 def setend_op : Operand<i32> {
199 let PrintMethod = "printSetendOperand";
202 def cps_opt : Operand<i32> {
203 let PrintMethod = "printCPSOptionOperand";
206 def msr_mask : Operand<i32> {
207 let PrintMethod = "printMSRMaskOperand";
210 // A8.6.117, A8.6.118. Different instructions are generated for #0 and #-0.
211 // The neg_zero operand translates -0 to -1, -1 to -2, ..., etc.
212 def neg_zero : Operand<i32> {
213 let PrintMethod = "printNegZeroOperand";
216 //===----------------------------------------------------------------------===//
217 // ARM Instruction templates.
220 class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im,
221 Format f, Domain d, string cstr, InstrItinClass itin>
223 let Namespace = "ARM";
228 bits<2> IndexModeBits = IM.Value;
230 bits<6> Form = F.Value;
232 bit isUnaryDataProc = 0;
233 bit canXformTo16Bit = 0;
235 // If this is a pseudo instruction, mark it isCodeGenOnly.
236 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
238 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
239 let TSFlags{4-0} = AM.Value;
240 let TSFlags{7-5} = SZ.Value;
241 let TSFlags{9-8} = IndexModeBits;
242 let TSFlags{15-10} = Form;
243 let TSFlags{16} = isUnaryDataProc;
244 let TSFlags{17} = canXformTo16Bit;
245 let TSFlags{19-18} = D.Value;
247 let Constraints = cstr;
248 let Itinerary = itin;
255 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
256 Format f, Domain d, string cstr, InstrItinClass itin>
257 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding;
259 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
260 // on by adding flavors to specific instructions.
261 class InstThumb<AddrMode am, SizeFlagVal sz, IndexMode im,
262 Format f, Domain d, string cstr, InstrItinClass itin>
263 : InstTemplate<am, sz, im, f, d, cstr, itin>;
265 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
266 // FIXME: This really should derive from InstTemplate instead, as pseudos
267 // don't need encoding information. TableGen doesn't like that
268 // currently. Need to figure out why and fix it.
269 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, GenericDomain,
271 let OutOperandList = oops;
272 let InOperandList = iops;
273 let Pattern = pattern;
276 // PseudoInst that's ARM-mode only.
277 class ARMPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
279 : PseudoInst<oops, iops, itin, pattern> {
281 list<Predicate> Predicates = [IsARM];
284 // PseudoInst that's Thumb-mode only.
285 class tPseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
287 : PseudoInst<oops, iops, itin, pattern> {
289 list<Predicate> Predicates = [IsThumb];
292 // PseudoInst that's Thumb2-mode only.
293 class t2PseudoInst<dag oops, dag iops, SizeFlagVal sz, InstrItinClass itin,
295 : PseudoInst<oops, iops, itin, pattern> {
297 list<Predicate> Predicates = [IsThumb2];
299 // Almost all ARM instructions are predicable.
300 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
301 IndexMode im, Format f, InstrItinClass itin,
302 string opc, string asm, string cstr,
304 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
307 let OutOperandList = oops;
308 let InOperandList = !con(iops, (ins pred:$p));
309 let AsmString = !strconcat(opc, "${p}", asm);
310 let Pattern = pattern;
311 list<Predicate> Predicates = [IsARM];
314 // A few are not predicable
315 class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
316 IndexMode im, Format f, InstrItinClass itin,
317 string opc, string asm, string cstr,
319 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
320 let OutOperandList = oops;
321 let InOperandList = iops;
322 let AsmString = !strconcat(opc, asm);
323 let Pattern = pattern;
324 let isPredicable = 0;
325 list<Predicate> Predicates = [IsARM];
328 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
329 // operand since by default it's a zero register. It will become an implicit def
330 // once it's "flipped".
331 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
332 IndexMode im, Format f, InstrItinClass itin,
333 string opc, string asm, string cstr,
335 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
336 bits<4> p; // Predicate operand
337 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
341 let OutOperandList = oops;
342 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
343 let AsmString = !strconcat(opc, "${s}${p}", asm);
344 let Pattern = pattern;
345 list<Predicate> Predicates = [IsARM];
349 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
350 IndexMode im, Format f, InstrItinClass itin,
351 string asm, string cstr, list<dag> pattern>
352 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
353 let OutOperandList = oops;
354 let InOperandList = iops;
356 let Pattern = pattern;
357 list<Predicate> Predicates = [IsARM];
360 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
361 string opc, string asm, list<dag> pattern>
362 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
363 opc, asm, "", pattern>;
364 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
365 string opc, string asm, list<dag> pattern>
366 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
367 opc, asm, "", pattern>;
368 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
369 string asm, list<dag> pattern>
370 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
372 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
373 string opc, string asm, list<dag> pattern>
374 : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
375 opc, asm, "", pattern>;
377 // Ctrl flow instructions
378 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
379 string opc, string asm, list<dag> pattern>
380 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
381 opc, asm, "", pattern> {
382 let Inst{27-24} = opcod;
384 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
385 string asm, list<dag> pattern>
386 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, itin,
388 let Inst{27-24} = opcod;
391 // BR_JT instructions
392 class JTI<dag oops, dag iops, InstrItinClass itin,
393 string asm, list<dag> pattern>
394 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm, itin,
397 // Atomic load/store instructions
398 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
399 string opc, string asm, list<dag> pattern>
400 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
401 opc, asm, "", pattern> {
404 let Inst{27-23} = 0b00011;
405 let Inst{22-21} = opcod;
407 let Inst{19-16} = Rn;
408 let Inst{15-12} = Rt;
409 let Inst{11-0} = 0b111110011111;
411 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
412 string opc, string asm, list<dag> pattern>
413 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, LdStExFrm, itin,
414 opc, asm, "", pattern> {
418 let Inst{27-23} = 0b00011;
419 let Inst{22-21} = opcod;
421 let Inst{19-16} = Rn;
422 let Inst{15-12} = Rd;
423 let Inst{11-4} = 0b11111001;
426 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
427 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, [$Rn]", pattern> {
431 let Inst{27-23} = 0b00010;
433 let Inst{21-20} = 0b00;
434 let Inst{19-16} = Rn;
435 let Inst{15-12} = Rt;
436 let Inst{11-4} = 0b00001001;
440 // addrmode1 instructions
441 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
442 string opc, string asm, list<dag> pattern>
443 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
444 opc, asm, "", pattern> {
445 let Inst{24-21} = opcod;
446 let Inst{27-26} = 0b00;
448 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
449 string opc, string asm, list<dag> pattern>
450 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
451 opc, asm, "", pattern> {
452 let Inst{24-21} = opcod;
453 let Inst{27-26} = 0b00;
455 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
456 string asm, list<dag> pattern>
457 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, itin,
459 let Inst{24-21} = opcod;
460 let Inst{27-26} = 0b00;
465 // LDR/LDRB/STR/STRB/...
466 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
467 Format f, InstrItinClass itin, string opc, string asm,
469 : I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
471 let Inst{27-25} = op;
472 let Inst{24} = 1; // 24 == P
474 let Inst{22} = isByte;
475 let Inst{21} = 0; // 21 == W
478 // Indexed load/stores
479 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
480 IndexMode im, Format f, InstrItinClass itin, string opc,
481 string asm, string cstr, list<dag> pattern>
482 : I<oops, iops, AddrMode2, Size4Bytes, im, f, itin,
483 opc, asm, cstr, pattern> {
485 let Inst{27-26} = 0b01;
486 let Inst{24} = isPre; // P bit
487 let Inst{22} = isByte; // B bit
488 let Inst{21} = isPre; // W bit
489 let Inst{20} = isLd; // L bit
490 let Inst{15-12} = Rt;
492 class AI2stridx<bit isByte, bit isPre, dag oops, dag iops,
493 IndexMode im, Format f, InstrItinClass itin, string opc,
494 string asm, string cstr, list<dag> pattern>
495 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
497 // AM2 store w/ two operands: (GPR, am2offset)
498 // {13} 1 == Rm, 0 == imm12
503 let Inst{25} = offset{13};
504 let Inst{23} = offset{12};
505 let Inst{19-16} = Rn;
506 let Inst{11-0} = offset{11-0};
509 // addrmode3 instructions
510 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
511 InstrItinClass itin, string opc, string asm, list<dag> pattern>
512 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
513 opc, asm, "", pattern> {
516 let Inst{27-25} = 0b000;
517 let Inst{24} = 1; // P bit
518 let Inst{23} = addr{8}; // U bit
519 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
520 let Inst{21} = 0; // W bit
521 let Inst{20} = op20; // L bit
522 let Inst{19-16} = addr{12-9}; // Rn
523 let Inst{15-12} = Rt; // Rt
524 let Inst{11-8} = addr{7-4}; // imm7_4/zero
526 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
529 class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
530 IndexMode im, Format f, InstrItinClass itin, string opc,
531 string asm, string cstr, list<dag> pattern>
532 : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin,
533 opc, asm, cstr, pattern> {
535 let Inst{27-25} = 0b000;
536 let Inst{24} = isPre; // P bit
537 let Inst{21} = isPre; // W bit
538 let Inst{20} = op20; // L bit
539 let Inst{15-12} = Rt; // Rt
542 class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
543 IndexMode im, Format f, InstrItinClass itin, string opc,
544 string asm, string cstr, list<dag> pattern>
545 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
547 // AM3 store w/ two operands: (GPR, am3offset)
551 let Inst{27-25} = 0b000;
552 let Inst{23} = offset{8};
553 let Inst{22} = offset{9};
554 let Inst{19-16} = Rn;
555 let Inst{15-12} = Rt; // Rt
556 let Inst{11-8} = offset{7-4}; // imm7_4/zero
558 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
562 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
563 string opc, string asm, list<dag> pattern>
564 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, itin,
565 opc, asm, "", pattern> {
568 let Inst{27-25} = 0b000;
569 let Inst{24} = 1; // P bit
570 let Inst{23} = addr{8}; // U bit
571 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
572 let Inst{21} = 0; // W bit
573 let Inst{20} = 0; // L bit
574 let Inst{19-16} = addr{12-9}; // Rn
575 let Inst{15-12} = Rt; // Rt
576 let Inst{11-8} = addr{7-4}; // imm7_4/zero
578 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
581 // Pre-indexed stores
582 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
583 string opc, string asm, string cstr, list<dag> pattern>
584 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
585 opc, asm, cstr, pattern> {
587 let Inst{5} = 1; // H bit
588 let Inst{6} = 0; // S bit
590 let Inst{20} = 0; // L bit
591 let Inst{21} = 1; // W bit
592 let Inst{24} = 1; // P bit
593 let Inst{27-25} = 0b000;
595 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
596 string opc, string asm, string cstr, list<dag> pattern>
597 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, itin,
598 opc, asm, cstr, pattern> {
600 let Inst{5} = 1; // H bit
601 let Inst{6} = 1; // S bit
603 let Inst{20} = 0; // L bit
604 let Inst{21} = 1; // W bit
605 let Inst{24} = 1; // P bit
606 let Inst{27-25} = 0b000;
609 // Post-indexed stores
610 class AI3sthpo<dag oops, dag iops, Format f, InstrItinClass itin,
611 string opc, string asm, string cstr, list<dag> pattern>
612 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
613 opc, asm, cstr,pattern> {
615 let Inst{5} = 1; // H bit
616 let Inst{6} = 0; // S bit
618 let Inst{20} = 0; // L bit
619 let Inst{21} = 0; // W bit
620 let Inst{24} = 0; // P bit
621 let Inst{27-25} = 0b000;
623 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
624 string opc, string asm, string cstr, list<dag> pattern>
625 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
626 opc, asm, cstr, pattern> {
628 let Inst{5} = 1; // H bit
629 let Inst{6} = 1; // S bit
631 let Inst{20} = 0; // L bit
632 let Inst{21} = 0; // W bit
633 let Inst{24} = 0; // P bit
634 let Inst{27-25} = 0b000;
637 // addrmode4 instructions
638 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
639 string asm, string cstr, list<dag> pattern>
640 : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> {
645 let Inst{27-25} = 0b100;
646 let Inst{22} = 0; // S bit
647 let Inst{19-16} = Rn;
648 let Inst{15-0} = regs;
651 // Unsigned multiply, multiply-accumulate instructions.
652 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
653 string opc, string asm, list<dag> pattern>
654 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
655 opc, asm, "", pattern> {
656 let Inst{7-4} = 0b1001;
657 let Inst{20} = 0; // S bit
658 let Inst{27-21} = opcod;
660 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
661 string opc, string asm, list<dag> pattern>
662 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
663 opc, asm, "", pattern> {
664 let Inst{7-4} = 0b1001;
665 let Inst{27-21} = opcod;
668 // Most significant word multiply
669 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
670 InstrItinClass itin, string opc, string asm, list<dag> pattern>
671 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
672 opc, asm, "", pattern> {
676 let Inst{7-4} = opc7_4;
678 let Inst{27-21} = opcod;
679 let Inst{19-16} = Rd;
683 // MSW multiple w/ Ra operand
684 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
685 InstrItinClass itin, string opc, string asm, list<dag> pattern>
686 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
688 let Inst{15-12} = Ra;
691 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
692 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
693 InstrItinClass itin, string opc, string asm, list<dag> pattern>
694 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, itin,
695 opc, asm, "", pattern> {
701 let Inst{27-21} = opcod;
702 let Inst{6-5} = bit6_5;
706 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
707 InstrItinClass itin, string opc, string asm, list<dag> pattern>
708 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
710 let Inst{19-16} = Rd;
713 // AMulxyI with Ra operand
714 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
715 InstrItinClass itin, string opc, string asm, list<dag> pattern>
716 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
718 let Inst{15-12} = Ra;
721 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
722 InstrItinClass itin, string opc, string asm, list<dag> pattern>
723 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
726 let Inst{19-16} = RdHi;
727 let Inst{15-12} = RdLo;
730 // Extend instructions.
731 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
732 string opc, string asm, list<dag> pattern>
733 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, itin,
734 opc, asm, "", pattern> {
735 // All AExtI instructions have Rd and Rm register operands.
738 let Inst{15-12} = Rd;
740 let Inst{7-4} = 0b0111;
741 let Inst{9-8} = 0b00;
742 let Inst{27-20} = opcod;
745 // Misc Arithmetic instructions.
746 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
747 InstrItinClass itin, string opc, string asm, list<dag> pattern>
748 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
749 opc, asm, "", pattern> {
752 let Inst{27-20} = opcod;
753 let Inst{19-16} = 0b1111;
754 let Inst{15-12} = Rd;
755 let Inst{11-8} = 0b1111;
756 let Inst{7-4} = opc7_4;
761 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
762 string opc, string asm, list<dag> pattern>
763 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, itin,
764 opc, asm, "", pattern> {
769 let Inst{27-20} = opcod;
770 let Inst{19-16} = Rn;
771 let Inst{15-12} = Rd;
772 let Inst{11-7} = sh{7-3};
774 let Inst{5-4} = 0b01;
778 //===----------------------------------------------------------------------===//
780 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
781 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
782 list<Predicate> Predicates = [IsARM];
784 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
785 list<Predicate> Predicates = [IsARM, HasV5TE];
787 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
788 list<Predicate> Predicates = [IsARM, HasV6];
791 //===----------------------------------------------------------------------===//
792 // Thumb Instruction Format Definitions.
795 class ThumbI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
796 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
797 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
798 let OutOperandList = oops;
799 let InOperandList = iops;
801 let Pattern = pattern;
802 list<Predicate> Predicates = [IsThumb];
805 // TI - Thumb instruction.
806 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
807 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
809 // Two-address instructions
810 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
812 : ThumbI<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "$lhs = $dst",
815 // tBL, tBX 32-bit instructions
816 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
817 dag oops, dag iops, InstrItinClass itin, string asm,
819 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>,
821 let Inst{31-27} = opcod1;
822 let Inst{15-14} = opcod2;
823 let Inst{12} = opcod3;
826 // Move to/from coprocessor instructions
827 class T1Cop<dag oops, dag iops, string asm, list<dag> pattern>
828 : ThumbI<oops, iops, AddrModeNone, Size4Bytes, NoItinerary, asm, "", pattern>,
829 Encoding, Requires<[IsThumb, HasV6]> {
830 let Inst{31-28} = 0b1110;
833 // BR_JT instructions
834 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
836 : ThumbI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
839 class Thumb1I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
840 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
841 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
842 let OutOperandList = oops;
843 let InOperandList = iops;
845 let Pattern = pattern;
846 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
849 class T1I<dag oops, dag iops, InstrItinClass itin,
850 string asm, list<dag> pattern>
851 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin, asm, "", pattern>;
852 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
853 string asm, list<dag> pattern>
854 : Thumb1I<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
856 // Two-address instructions
857 class T1It<dag oops, dag iops, InstrItinClass itin,
858 string asm, string cstr, list<dag> pattern>
859 : Thumb1I<oops, iops, AddrModeNone, Size2Bytes, itin,
862 // Thumb1 instruction that can either be predicated or set CPSR.
863 class Thumb1sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
865 string opc, string asm, string cstr, list<dag> pattern>
866 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
867 let OutOperandList = !con(oops, (outs s_cc_out:$s));
868 let InOperandList = !con(iops, (ins pred:$p));
869 let AsmString = !strconcat(opc, "${s}${p}", asm);
870 let Pattern = pattern;
871 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
874 class T1sI<dag oops, dag iops, InstrItinClass itin,
875 string opc, string asm, list<dag> pattern>
876 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
878 // Two-address instructions
879 class T1sIt<dag oops, dag iops, InstrItinClass itin,
880 string opc, string asm, list<dag> pattern>
881 : Thumb1sI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
882 "$Rn = $Rdn", pattern>;
884 // Thumb1 instruction that can be predicated.
885 class Thumb1pI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
887 string opc, string asm, string cstr, list<dag> pattern>
888 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
889 let OutOperandList = oops;
890 let InOperandList = !con(iops, (ins pred:$p));
891 let AsmString = !strconcat(opc, "${p}", asm);
892 let Pattern = pattern;
893 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
896 class T1pI<dag oops, dag iops, InstrItinClass itin,
897 string opc, string asm, list<dag> pattern>
898 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm, "", pattern>;
900 // Two-address instructions
901 class T1pIt<dag oops, dag iops, InstrItinClass itin,
902 string opc, string asm, list<dag> pattern>
903 : Thumb1pI<oops, iops, AddrModeNone, Size2Bytes, itin, opc, asm,
904 "$Rn = $Rdn", pattern>;
906 class T1pIs<dag oops, dag iops,
907 InstrItinClass itin, string opc, string asm, list<dag> pattern>
908 : Thumb1pI<oops, iops, AddrModeT1_s, Size2Bytes, itin, opc, asm, "", pattern>;
910 class Encoding16 : Encoding {
911 let Inst{31-16} = 0x0000;
914 // A6.2 16-bit Thumb instruction encoding
915 class T1Encoding<bits<6> opcode> : Encoding16 {
916 let Inst{15-10} = opcode;
919 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
920 class T1General<bits<5> opcode> : Encoding16 {
921 let Inst{15-14} = 0b00;
922 let Inst{13-9} = opcode;
925 // A6.2.2 Data-processing encoding.
926 class T1DataProcessing<bits<4> opcode> : Encoding16 {
927 let Inst{15-10} = 0b010000;
928 let Inst{9-6} = opcode;
931 // A6.2.3 Special data instructions and branch and exchange encoding.
932 class T1Special<bits<4> opcode> : Encoding16 {
933 let Inst{15-10} = 0b010001;
934 let Inst{9-6} = opcode;
937 // A6.2.4 Load/store single data item encoding.
938 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
939 let Inst{15-12} = opA;
940 let Inst{11-9} = opB;
942 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
944 // Helper classes to encode Thumb1 loads and stores. For immediates, the
945 // following bits are used for "opA" (see A6.2.4):
947 // 0b0110 => Immediate, 4 bytes
948 // 0b1000 => Immediate, 2 bytes
949 // 0b0111 => Immediate, 1 byte
950 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
951 InstrItinClass itin, string opc, string asm,
953 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>,
954 T1LoadStore<0b0101, opcode> {
957 let Inst{8-6} = addr{5-3}; // Rm
958 let Inst{5-3} = addr{2-0}; // Rn
961 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
962 InstrItinClass itin, string opc, string asm,
964 : Thumb1pI<oops, iops, am, Size2Bytes, itin, opc, asm, "", pattern>,
965 T1LoadStore<opA, {opB,?,?}> {
968 let Inst{10-6} = addr{7-3}; // imm5
969 let Inst{5-3} = addr{2-0}; // Rn
973 // A6.2.5 Miscellaneous 16-bit instructions encoding.
974 class T1Misc<bits<7> opcode> : Encoding16 {
975 let Inst{15-12} = 0b1011;
976 let Inst{11-5} = opcode;
979 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
980 class Thumb2I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
982 string opc, string asm, string cstr, list<dag> pattern>
983 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
984 let OutOperandList = oops;
985 let InOperandList = !con(iops, (ins pred:$p));
986 let AsmString = !strconcat(opc, "${p}", asm);
987 let Pattern = pattern;
988 list<Predicate> Predicates = [IsThumb2];
991 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
992 // input operand since by default it's a zero register. It will become an
993 // implicit def once it's "flipped".
995 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
997 class Thumb2sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
999 string opc, string asm, string cstr, list<dag> pattern>
1000 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1001 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1004 let OutOperandList = oops;
1005 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1006 let AsmString = !strconcat(opc, "${s}${p}", asm);
1007 let Pattern = pattern;
1008 list<Predicate> Predicates = [IsThumb2];
1012 class Thumb2XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1013 InstrItinClass itin,
1014 string asm, string cstr, list<dag> pattern>
1015 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1016 let OutOperandList = oops;
1017 let InOperandList = iops;
1018 let AsmString = asm;
1019 let Pattern = pattern;
1020 list<Predicate> Predicates = [IsThumb2];
1023 class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1024 InstrItinClass itin,
1025 string asm, string cstr, list<dag> pattern>
1026 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1027 let OutOperandList = oops;
1028 let InOperandList = iops;
1029 let AsmString = asm;
1030 let Pattern = pattern;
1031 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1034 class T2I<dag oops, dag iops, InstrItinClass itin,
1035 string opc, string asm, list<dag> pattern>
1036 : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1037 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1038 string opc, string asm, list<dag> pattern>
1039 : Thumb2I<oops, iops, AddrModeT2_i12, Size4Bytes, itin, opc, asm, "",pattern>;
1040 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1041 string opc, string asm, list<dag> pattern>
1042 : Thumb2I<oops, iops, AddrModeT2_i8, Size4Bytes, itin, opc, asm, "", pattern>;
1043 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1044 string opc, string asm, list<dag> pattern>
1045 : Thumb2I<oops, iops, AddrModeT2_so, Size4Bytes, itin, opc, asm, "", pattern>;
1046 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1047 string opc, string asm, list<dag> pattern>
1048 : Thumb2I<oops, iops, AddrModeT2_pc, Size4Bytes, itin, opc, asm, "", pattern>;
1049 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1050 string opc, string asm, list<dag> pattern>
1051 : Thumb2I<oops, iops, AddrModeT2_i8s4, Size4Bytes, itin, opc, asm, "",
1056 let Inst{31-25} = 0b1110100;
1058 let Inst{23} = addr{8};
1061 let Inst{20} = isLoad;
1062 let Inst{19-16} = addr{12-9};
1063 let Inst{15-12} = Rt{3-0};
1064 let Inst{11-8} = Rt2{3-0};
1065 let Inst{7-0} = addr{7-0};
1068 class T2sI<dag oops, dag iops, InstrItinClass itin,
1069 string opc, string asm, list<dag> pattern>
1070 : Thumb2sI<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;
1072 class T2XI<dag oops, dag iops, InstrItinClass itin,
1073 string asm, list<dag> pattern>
1074 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, "", pattern>;
1075 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1076 string asm, list<dag> pattern>
1077 : Thumb2XI<oops, iops, AddrModeNone, SizeSpecial, itin, asm, "", pattern>;
1079 // Move to/from coprocessor instructions
1080 class T2Cop<dag oops, dag iops, string asm, list<dag> pattern>
1081 : T2XI<oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2, HasV6]> {
1082 let Inst{31-28} = 0b1111;
1085 // Two-address instructions
1086 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1087 string asm, string cstr, list<dag> pattern>
1088 : Thumb2XI<oops, iops, AddrModeNone, Size4Bytes, itin, asm, cstr, pattern>;
1090 // T2Iidxldst - Thumb2 indexed load / store instructions.
1091 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1093 AddrMode am, IndexMode im, InstrItinClass itin,
1094 string opc, string asm, string cstr, list<dag> pattern>
1095 : InstARM<am, Size4Bytes, im, ThumbFrm, GenericDomain, cstr, itin> {
1096 let OutOperandList = oops;
1097 let InOperandList = !con(iops, (ins pred:$p));
1098 let AsmString = !strconcat(opc, "${p}", asm);
1099 let Pattern = pattern;
1100 list<Predicate> Predicates = [IsThumb2];
1101 let Inst{31-27} = 0b11111;
1102 let Inst{26-25} = 0b00;
1103 let Inst{24} = signed;
1105 let Inst{22-21} = opcod;
1106 let Inst{20} = load;
1108 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1109 let Inst{10} = pre; // The P bit.
1110 let Inst{8} = 1; // The W bit.
1113 let Inst{7-0} = addr{7-0};
1114 let Inst{9} = addr{8}; // Sign bit
1118 let Inst{15-12} = Rt{3-0};
1119 let Inst{19-16} = Rn{3-0};
1122 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1123 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1124 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1127 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1128 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1129 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1132 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1133 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1134 list<Predicate> Predicates = [IsThumb2];
1137 //===----------------------------------------------------------------------===//
1139 //===----------------------------------------------------------------------===//
1140 // ARM VFP Instruction templates.
1143 // Almost all VFP instructions are predicable.
1144 class VFPI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1145 IndexMode im, Format f, InstrItinClass itin,
1146 string opc, string asm, string cstr, list<dag> pattern>
1147 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1149 let Inst{31-28} = p;
1150 let OutOperandList = oops;
1151 let InOperandList = !con(iops, (ins pred:$p));
1152 let AsmString = !strconcat(opc, "${p}", asm);
1153 let Pattern = pattern;
1154 let PostEncoderMethod = "VFPThumb2PostEncoder";
1155 list<Predicate> Predicates = [HasVFP2];
1159 class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
1160 IndexMode im, Format f, InstrItinClass itin,
1161 string asm, string cstr, list<dag> pattern>
1162 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1164 let Inst{31-28} = p;
1165 let OutOperandList = oops;
1166 let InOperandList = iops;
1167 let AsmString = asm;
1168 let Pattern = pattern;
1169 let PostEncoderMethod = "VFPThumb2PostEncoder";
1170 list<Predicate> Predicates = [HasVFP2];
1173 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1174 string opc, string asm, list<dag> pattern>
1175 : VFPI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
1176 opc, asm, "", pattern> {
1177 let PostEncoderMethod = "VFPThumb2PostEncoder";
1180 // ARM VFP addrmode5 loads and stores
1181 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1182 InstrItinClass itin,
1183 string opc, string asm, list<dag> pattern>
1184 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1185 VFPLdStFrm, itin, opc, asm, "", pattern> {
1186 // Instruction operands.
1190 // Encode instruction operands.
1191 let Inst{23} = addr{8}; // U (add = (U == '1'))
1192 let Inst{22} = Dd{4};
1193 let Inst{19-16} = addr{12-9}; // Rn
1194 let Inst{15-12} = Dd{3-0};
1195 let Inst{7-0} = addr{7-0}; // imm8
1197 // TODO: Mark the instructions with the appropriate subtarget info.
1198 let Inst{27-24} = opcod1;
1199 let Inst{21-20} = opcod2;
1200 let Inst{11-9} = 0b101;
1201 let Inst{8} = 1; // Double precision
1203 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1204 let D = VFPNeonDomain;
1207 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1208 InstrItinClass itin,
1209 string opc, string asm, list<dag> pattern>
1210 : VFPI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
1211 VFPLdStFrm, itin, opc, asm, "", pattern> {
1212 // Instruction operands.
1216 // Encode instruction operands.
1217 let Inst{23} = addr{8}; // U (add = (U == '1'))
1218 let Inst{22} = Sd{0};
1219 let Inst{19-16} = addr{12-9}; // Rn
1220 let Inst{15-12} = Sd{4-1};
1221 let Inst{7-0} = addr{7-0}; // imm8
1223 // TODO: Mark the instructions with the appropriate subtarget info.
1224 let Inst{27-24} = opcod1;
1225 let Inst{21-20} = opcod2;
1226 let Inst{11-9} = 0b101;
1227 let Inst{8} = 0; // Single precision
1230 // VFP Load / store multiple pseudo instructions.
1231 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1233 : InstARM<AddrMode4, Size4Bytes, IndexModeNone, Pseudo, VFPNeonDomain,
1235 let OutOperandList = oops;
1236 let InOperandList = !con(iops, (ins pred:$p));
1237 let Pattern = pattern;
1238 list<Predicate> Predicates = [HasVFP2];
1241 // Load / store multiple
1242 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1243 string asm, string cstr, list<dag> pattern>
1244 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1245 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1246 // Instruction operands.
1250 // Encode instruction operands.
1251 let Inst{19-16} = Rn;
1252 let Inst{22} = regs{12};
1253 let Inst{15-12} = regs{11-8};
1254 let Inst{7-0} = regs{7-0};
1256 // TODO: Mark the instructions with the appropriate subtarget info.
1257 let Inst{27-25} = 0b110;
1258 let Inst{11-9} = 0b101;
1259 let Inst{8} = 1; // Double precision
1261 // 64-bit loads & stores operate on both NEON and VFP pipelines.
1262 let D = VFPNeonDomain;
1265 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1266 string asm, string cstr, list<dag> pattern>
1267 : VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
1268 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1269 // Instruction operands.
1273 // Encode instruction operands.
1274 let Inst{19-16} = Rn;
1275 let Inst{22} = regs{8};
1276 let Inst{15-12} = regs{12-9};
1277 let Inst{7-0} = regs{7-0};
1279 // TODO: Mark the instructions with the appropriate subtarget info.
1280 let Inst{27-25} = 0b110;
1281 let Inst{11-9} = 0b101;
1282 let Inst{8} = 0; // Single precision
1285 // Double precision, unary
1286 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1287 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1288 string asm, list<dag> pattern>
1289 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1290 // Instruction operands.
1294 // Encode instruction operands.
1295 let Inst{3-0} = Dm{3-0};
1296 let Inst{5} = Dm{4};
1297 let Inst{15-12} = Dd{3-0};
1298 let Inst{22} = Dd{4};
1300 let Inst{27-23} = opcod1;
1301 let Inst{21-20} = opcod2;
1302 let Inst{19-16} = opcod3;
1303 let Inst{11-9} = 0b101;
1304 let Inst{8} = 1; // Double precision
1305 let Inst{7-6} = opcod4;
1306 let Inst{4} = opcod5;
1309 // Double precision, binary
1310 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1311 dag iops, InstrItinClass itin, string opc, string asm,
1313 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1314 // Instruction operands.
1319 // Encode instruction operands.
1320 let Inst{3-0} = Dm{3-0};
1321 let Inst{5} = Dm{4};
1322 let Inst{19-16} = Dn{3-0};
1323 let Inst{7} = Dn{4};
1324 let Inst{15-12} = Dd{3-0};
1325 let Inst{22} = Dd{4};
1327 let Inst{27-23} = opcod1;
1328 let Inst{21-20} = opcod2;
1329 let Inst{11-9} = 0b101;
1330 let Inst{8} = 1; // Double precision
1335 // Single precision, unary
1336 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1337 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1338 string asm, list<dag> pattern>
1339 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1340 // Instruction operands.
1344 // Encode instruction operands.
1345 let Inst{3-0} = Sm{4-1};
1346 let Inst{5} = Sm{0};
1347 let Inst{15-12} = Sd{4-1};
1348 let Inst{22} = Sd{0};
1350 let Inst{27-23} = opcod1;
1351 let Inst{21-20} = opcod2;
1352 let Inst{19-16} = opcod3;
1353 let Inst{11-9} = 0b101;
1354 let Inst{8} = 0; // Single precision
1355 let Inst{7-6} = opcod4;
1356 let Inst{4} = opcod5;
1359 // Single precision unary, if no NEON. Same as ASuI except not available if
1361 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1362 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1363 string asm, list<dag> pattern>
1364 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1366 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1369 // Single precision, binary
1370 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1371 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1372 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1373 // Instruction operands.
1378 // Encode instruction operands.
1379 let Inst{3-0} = Sm{4-1};
1380 let Inst{5} = Sm{0};
1381 let Inst{19-16} = Sn{4-1};
1382 let Inst{7} = Sn{0};
1383 let Inst{15-12} = Sd{4-1};
1384 let Inst{22} = Sd{0};
1386 let Inst{27-23} = opcod1;
1387 let Inst{21-20} = opcod2;
1388 let Inst{11-9} = 0b101;
1389 let Inst{8} = 0; // Single precision
1394 // Single precision binary, if no NEON. Same as ASbI except not available if
1396 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1397 dag iops, InstrItinClass itin, string opc, string asm,
1399 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1400 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1402 // Instruction operands.
1407 // Encode instruction operands.
1408 let Inst{3-0} = Sm{4-1};
1409 let Inst{5} = Sm{0};
1410 let Inst{19-16} = Sn{4-1};
1411 let Inst{7} = Sn{0};
1412 let Inst{15-12} = Sd{4-1};
1413 let Inst{22} = Sd{0};
1416 // VFP conversion instructions
1417 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1418 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1420 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1421 let Inst{27-23} = opcod1;
1422 let Inst{21-20} = opcod2;
1423 let Inst{19-16} = opcod3;
1424 let Inst{11-8} = opcod4;
1429 // VFP conversion between floating-point and fixed-point
1430 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1431 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1433 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1434 // size (fixed-point number): sx == 0 ? 16 : 32
1435 let Inst{7} = op5; // sx
1438 // VFP conversion instructions, if no NEON
1439 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1440 dag oops, dag iops, InstrItinClass itin,
1441 string opc, string asm, list<dag> pattern>
1442 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1444 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1447 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1448 InstrItinClass itin,
1449 string opc, string asm, list<dag> pattern>
1450 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1451 let Inst{27-20} = opcod1;
1452 let Inst{11-8} = opcod2;
1456 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1457 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1458 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1460 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1461 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1462 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1464 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1465 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1466 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1468 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1469 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1470 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1472 //===----------------------------------------------------------------------===//
1474 //===----------------------------------------------------------------------===//
1475 // ARM NEON Instruction templates.
1478 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1479 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1481 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1482 let OutOperandList = oops;
1483 let InOperandList = !con(iops, (ins pred:$p));
1484 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1485 let Pattern = pattern;
1486 list<Predicate> Predicates = [HasNEON];
1489 // Same as NeonI except it does not have a "data type" specifier.
1490 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1491 InstrItinClass itin, string opc, string asm, string cstr,
1493 : InstARM<am, Size4Bytes, im, f, NeonDomain, cstr, itin> {
1494 let OutOperandList = oops;
1495 let InOperandList = !con(iops, (ins pred:$p));
1496 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1497 let Pattern = pattern;
1498 list<Predicate> Predicates = [HasNEON];
1501 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1502 dag oops, dag iops, InstrItinClass itin,
1503 string opc, string dt, string asm, string cstr, list<dag> pattern>
1504 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1506 let Inst{31-24} = 0b11110100;
1507 let Inst{23} = op23;
1508 let Inst{21-20} = op21_20;
1509 let Inst{11-8} = op11_8;
1510 let Inst{7-4} = op7_4;
1512 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1518 let Inst{22} = Vd{4};
1519 let Inst{15-12} = Vd{3-0};
1520 let Inst{19-16} = Rn{3-0};
1521 let Inst{3-0} = Rm{3-0};
1524 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1525 dag oops, dag iops, InstrItinClass itin,
1526 string opc, string dt, string asm, string cstr, list<dag> pattern>
1527 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1528 dt, asm, cstr, pattern> {
1532 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1533 : InstARM<AddrMode6, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1535 let OutOperandList = oops;
1536 let InOperandList = !con(iops, (ins pred:$p));
1537 list<Predicate> Predicates = [HasNEON];
1540 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1542 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, Pseudo, NeonDomain, cstr,
1544 let OutOperandList = oops;
1545 let InOperandList = !con(iops, (ins pred:$p));
1546 let Pattern = pattern;
1547 list<Predicate> Predicates = [HasNEON];
1550 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1551 string opc, string dt, string asm, string cstr, list<dag> pattern>
1552 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1554 let Inst{31-25} = 0b1111001;
1555 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1558 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1559 string opc, string asm, string cstr, list<dag> pattern>
1560 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1562 let Inst{31-25} = 0b1111001;
1563 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1566 // NEON "one register and a modified immediate" format.
1567 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1569 dag oops, dag iops, InstrItinClass itin,
1570 string opc, string dt, string asm, string cstr,
1572 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1573 let Inst{23} = op23;
1574 let Inst{21-19} = op21_19;
1575 let Inst{11-8} = op11_8;
1581 // Instruction operands.
1585 let Inst{15-12} = Vd{3-0};
1586 let Inst{22} = Vd{4};
1587 let Inst{24} = SIMM{7};
1588 let Inst{18-16} = SIMM{6-4};
1589 let Inst{3-0} = SIMM{3-0};
1592 // NEON 2 vector register format.
1593 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1594 bits<5> op11_7, bit op6, bit op4,
1595 dag oops, dag iops, InstrItinClass itin,
1596 string opc, string dt, string asm, string cstr, list<dag> pattern>
1597 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1598 let Inst{24-23} = op24_23;
1599 let Inst{21-20} = op21_20;
1600 let Inst{19-18} = op19_18;
1601 let Inst{17-16} = op17_16;
1602 let Inst{11-7} = op11_7;
1606 // Instruction operands.
1610 let Inst{15-12} = Vd{3-0};
1611 let Inst{22} = Vd{4};
1612 let Inst{3-0} = Vm{3-0};
1613 let Inst{5} = Vm{4};
1616 // Same as N2V except it doesn't have a datatype suffix.
1617 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1618 bits<5> op11_7, bit op6, bit op4,
1619 dag oops, dag iops, InstrItinClass itin,
1620 string opc, string asm, string cstr, list<dag> pattern>
1621 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1622 let Inst{24-23} = op24_23;
1623 let Inst{21-20} = op21_20;
1624 let Inst{19-18} = op19_18;
1625 let Inst{17-16} = op17_16;
1626 let Inst{11-7} = op11_7;
1630 // Instruction operands.
1634 let Inst{15-12} = Vd{3-0};
1635 let Inst{22} = Vd{4};
1636 let Inst{3-0} = Vm{3-0};
1637 let Inst{5} = Vm{4};
1640 // NEON 2 vector register with immediate.
1641 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1642 dag oops, dag iops, Format f, InstrItinClass itin,
1643 string opc, string dt, string asm, string cstr, list<dag> pattern>
1644 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1645 let Inst{24} = op24;
1646 let Inst{23} = op23;
1647 let Inst{11-8} = op11_8;
1652 // Instruction operands.
1657 let Inst{15-12} = Vd{3-0};
1658 let Inst{22} = Vd{4};
1659 let Inst{3-0} = Vm{3-0};
1660 let Inst{5} = Vm{4};
1661 let Inst{21-16} = SIMM{5-0};
1664 // NEON 3 vector register format.
1665 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1666 dag oops, dag iops, Format f, InstrItinClass itin,
1667 string opc, string dt, string asm, string cstr, list<dag> pattern>
1668 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1669 let Inst{24} = op24;
1670 let Inst{23} = op23;
1671 let Inst{21-20} = op21_20;
1672 let Inst{11-8} = op11_8;
1676 // Instruction operands.
1681 let Inst{15-12} = Vd{3-0};
1682 let Inst{22} = Vd{4};
1683 let Inst{19-16} = Vn{3-0};
1684 let Inst{7} = Vn{4};
1685 let Inst{3-0} = Vm{3-0};
1686 let Inst{5} = Vm{4};
1689 // Same as N3V except it doesn't have a data type suffix.
1690 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1692 dag oops, dag iops, Format f, InstrItinClass itin,
1693 string opc, string asm, string cstr, list<dag> pattern>
1694 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1695 let Inst{24} = op24;
1696 let Inst{23} = op23;
1697 let Inst{21-20} = op21_20;
1698 let Inst{11-8} = op11_8;
1702 // Instruction operands.
1707 let Inst{15-12} = Vd{3-0};
1708 let Inst{22} = Vd{4};
1709 let Inst{19-16} = Vn{3-0};
1710 let Inst{7} = Vn{4};
1711 let Inst{3-0} = Vm{3-0};
1712 let Inst{5} = Vm{4};
1715 // NEON VMOVs between scalar and core registers.
1716 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1717 dag oops, dag iops, Format f, InstrItinClass itin,
1718 string opc, string dt, string asm, list<dag> pattern>
1719 : InstARM<AddrModeNone, Size4Bytes, IndexModeNone, f, NeonDomain,
1721 let Inst{27-20} = opcod1;
1722 let Inst{11-8} = opcod2;
1723 let Inst{6-5} = opcod3;
1726 let OutOperandList = oops;
1727 let InOperandList = !con(iops, (ins pred:$p));
1728 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1729 let Pattern = pattern;
1730 list<Predicate> Predicates = [HasNEON];
1732 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1739 let Inst{31-28} = p{3-0};
1741 let Inst{19-16} = V{3-0};
1742 let Inst{15-12} = R{3-0};
1744 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1745 dag oops, dag iops, InstrItinClass itin,
1746 string opc, string dt, string asm, list<dag> pattern>
1747 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1748 opc, dt, asm, pattern>;
1749 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1750 dag oops, dag iops, InstrItinClass itin,
1751 string opc, string dt, string asm, list<dag> pattern>
1752 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1753 opc, dt, asm, pattern>;
1754 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1755 dag oops, dag iops, InstrItinClass itin,
1756 string opc, string dt, string asm, list<dag> pattern>
1757 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1758 opc, dt, asm, pattern>;
1760 // Vector Duplicate Lane (from scalar to all elements)
1761 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1762 InstrItinClass itin, string opc, string dt, string asm,
1764 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1765 let Inst{24-23} = 0b11;
1766 let Inst{21-20} = 0b11;
1767 let Inst{19-16} = op19_16;
1768 let Inst{11-7} = 0b11000;
1776 let Inst{22} = Vd{4};
1777 let Inst{15-12} = Vd{3-0};
1778 let Inst{5} = Vm{4};
1779 let Inst{3-0} = Vm{3-0};
1782 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1783 // for single-precision FP.
1784 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1785 list<Predicate> Predicates = [HasNEON,UseNEONForFP];