1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<1>;
23 def MulFrm : Format<2>;
24 def BrFrm : Format<3>;
25 def BrMiscFrm : Format<4>;
27 def DPFrm : Format<5>;
28 def DPSoRegFrm : Format<6>;
30 def LdFrm : Format<7>;
31 def StFrm : Format<8>;
32 def LdMiscFrm : Format<9>;
33 def StMiscFrm : Format<10>;
34 def LdMulFrm : Format<11>;
35 def StMulFrm : Format<12>;
37 def ArithMiscFrm : Format<13>;
38 def ExtFrm : Format<14>;
40 def VFPUnaryFrm : Format<15>;
41 def VFPBinaryFrm : Format<16>;
42 def VFPConv1Frm : Format<17>;
43 def VFPConv2Frm : Format<18>;
44 def VFPLdStFrm : Format<19>;
45 def VFPLdStMulFrm : Format<20>;
46 def VFPMiscFrm : Format<21>;
48 def ThumbFrm : Format<22>;
50 // Misc flag for data processing instructions that indicates whether
51 // the instruction has a Rn register operand.
52 class UnaryDP { bit isUnaryDataProc = 1; }
54 //===----------------------------------------------------------------------===//
56 // ARM Instruction templates.
59 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
60 Format f, string cstr>
64 let Namespace = "ARM";
68 bits<4> AddrModeBits = AM.Value;
71 bits<3> SizeFlag = SZ.Value;
74 bits<2> IndexModeBits = IM.Value;
77 bits<5> Form = F.Value;
80 // Attributes specific to ARM instructions...
82 bit isUnaryDataProc = 0;
84 let Constraints = cstr;
87 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
88 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
89 let OutOperandList = oops;
90 let InOperandList = iops;
92 let Pattern = pattern;
95 // Almost all ARM instructions are predicable.
96 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
97 IndexMode im, Format f, string opc, string asm, string cstr,
99 : InstARM<am, sz, im, f, cstr> {
100 let OutOperandList = oops;
101 let InOperandList = !con(iops, (ops pred:$p));
102 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
103 let Pattern = pattern;
104 list<Predicate> Predicates = [IsARM];
107 // Same as I except it can optionally modify CPSR. Note it's modeled as
108 // an input operand since by default it's a zero register. It will
109 // become an implicit def once it's "flipped".
110 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
111 IndexMode im, Format f, string opc, string asm, string cstr,
113 : InstARM<am, sz, im, f, cstr> {
114 let OutOperandList = oops;
115 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
116 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
117 let Pattern = pattern;
118 list<Predicate> Predicates = [IsARM];
122 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
123 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
124 : InstARM<am, sz, im, f, cstr> {
125 let OutOperandList = oops;
126 let InOperandList = iops;
128 let Pattern = pattern;
129 list<Predicate> Predicates = [IsARM];
132 class AI<dag oops, dag iops, Format f, string opc,
133 string asm, list<dag> pattern>
134 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
136 class AsI<dag oops, dag iops, Format f, string opc,
137 string asm, list<dag> pattern>
138 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
140 class AXI<dag oops, dag iops, Format f, string asm,
142 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
145 // Ctrl flow instructions
146 class ABI<bits<4> opcod, dag oops, dag iops, string opc,
147 string asm, list<dag> pattern>
148 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, opc,
150 let Inst{27-24} = opcod;
152 class ABXI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
153 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, asm,
155 let Inst{27-24} = opcod;
157 class ABXIx2<dag oops, dag iops, string asm, list<dag> pattern>
158 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, asm,
161 // BR_JT instructions
162 class JTI<dag oops, dag iops, string asm, list<dag> pattern>
163 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm,
166 // addrmode1 instructions
167 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
168 string asm, list<dag> pattern>
169 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
171 let Inst{24-21} = opcod;
172 let Inst{27-26} = {0,0};
174 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
175 string asm, list<dag> pattern>
176 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
178 let Inst{24-21} = opcod;
179 let Inst{27-26} = {0,0};
181 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
183 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
185 let Inst{24-21} = opcod;
186 let Inst{27-26} = {0,0};
188 class AI1x2<dag oops, dag iops, Format f, string opc,
189 string asm, list<dag> pattern>
190 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
194 // addrmode2 loads and stores
195 class AI2<dag oops, dag iops, Format f, string opc,
196 string asm, list<dag> pattern>
197 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
199 let Inst{27-26} = {0,1};
203 class AI2ldw<dag oops, dag iops, Format f, string opc,
204 string asm, list<dag> pattern>
205 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
207 let Inst{20} = 1; // L bit
208 let Inst{21} = 0; // W bit
209 let Inst{22} = 0; // B bit
210 let Inst{24} = 1; // P bit
211 let Inst{27-26} = {0,1};
213 class AXI2ldw<dag oops, dag iops, Format f, string asm,
215 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
217 let Inst{20} = 1; // L bit
218 let Inst{21} = 0; // W bit
219 let Inst{22} = 0; // B bit
220 let Inst{24} = 1; // P bit
221 let Inst{27-26} = {0,1};
223 class AI2ldb<dag oops, dag iops, Format f, string opc,
224 string asm, list<dag> pattern>
225 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
227 let Inst{20} = 1; // L bit
228 let Inst{21} = 0; // W bit
229 let Inst{22} = 1; // B bit
230 let Inst{24} = 1; // P bit
231 let Inst{27-26} = {0,1};
233 class AXI2ldb<dag oops, dag iops, Format f, string asm,
235 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
237 let Inst{20} = 1; // L bit
238 let Inst{21} = 0; // W bit
239 let Inst{22} = 1; // B bit
240 let Inst{24} = 1; // P bit
241 let Inst{27-26} = {0,1};
245 class AI2stw<dag oops, dag iops, Format f, string opc,
246 string asm, list<dag> pattern>
247 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
249 let Inst{20} = 0; // L bit
250 let Inst{21} = 0; // W bit
251 let Inst{22} = 0; // B bit
252 let Inst{24} = 1; // P bit
253 let Inst{27-26} = {0,1};
255 class AXI2stw<dag oops, dag iops, Format f, string asm,
257 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
259 let Inst{20} = 0; // L bit
260 let Inst{21} = 0; // W bit
261 let Inst{22} = 0; // B bit
262 let Inst{24} = 1; // P bit
263 let Inst{27-26} = {0,1};
265 class AI2stb<dag oops, dag iops, Format f, string opc,
266 string asm, list<dag> pattern>
267 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
269 let Inst{20} = 0; // L bit
270 let Inst{21} = 0; // W bit
271 let Inst{22} = 1; // B bit
272 let Inst{24} = 1; // P bit
273 let Inst{27-26} = {0,1};
275 class AXI2stb<dag oops, dag iops, Format f, string asm,
277 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
279 let Inst{20} = 0; // L bit
280 let Inst{21} = 0; // W bit
281 let Inst{22} = 1; // B bit
282 let Inst{24} = 1; // P bit
283 let Inst{27-26} = {0,1};
287 class AI2ldwpr<dag oops, dag iops, Format f, string opc,
288 string asm, string cstr, list<dag> pattern>
289 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
290 asm, cstr, pattern> {
291 let Inst{20} = 1; // L bit
292 let Inst{21} = 1; // W bit
293 let Inst{22} = 0; // B bit
294 let Inst{24} = 1; // P bit
295 let Inst{27-26} = {0,1};
297 class AI2ldbpr<dag oops, dag iops, Format f, string opc,
298 string asm, string cstr, list<dag> pattern>
299 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
300 asm, cstr, pattern> {
301 let Inst{20} = 1; // L bit
302 let Inst{21} = 1; // W bit
303 let Inst{22} = 1; // B bit
304 let Inst{24} = 1; // P bit
305 let Inst{27-26} = {0,1};
308 // Pre-indexed stores
309 class AI2stwpr<dag oops, dag iops, Format f, string opc,
310 string asm, string cstr, list<dag> pattern>
311 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
312 asm, cstr, pattern> {
313 let Inst{20} = 0; // L bit
314 let Inst{21} = 1; // W bit
315 let Inst{22} = 0; // B bit
316 let Inst{24} = 1; // P bit
317 let Inst{27-26} = {0,1};
319 class AI2stbpr<dag oops, dag iops, Format f, string opc,
320 string asm, string cstr, list<dag> pattern>
321 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
322 asm, cstr, pattern> {
323 let Inst{20} = 0; // L bit
324 let Inst{21} = 1; // W bit
325 let Inst{22} = 1; // B bit
326 let Inst{24} = 1; // P bit
327 let Inst{27-26} = {0,1};
330 // Post-indexed loads
331 class AI2ldwpo<dag oops, dag iops, Format f, string opc,
332 string asm, string cstr, list<dag> pattern>
333 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
335 let Inst{20} = 1; // L bit
336 let Inst{21} = 0; // W bit
337 let Inst{22} = 0; // B bit
338 let Inst{24} = 0; // P bit
339 let Inst{27-26} = {0,1};
341 class AI2ldbpo<dag oops, dag iops, Format f, string opc,
342 string asm, string cstr, list<dag> pattern>
343 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
345 let Inst{20} = 1; // L bit
346 let Inst{21} = 0; // W bit
347 let Inst{22} = 1; // B bit
348 let Inst{24} = 0; // P bit
349 let Inst{27-26} = {0,1};
352 // Post-indexed stores
353 class AI2stwpo<dag oops, dag iops, Format f, string opc,
354 string asm, string cstr, list<dag> pattern>
355 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
357 let Inst{20} = 0; // L bit
358 let Inst{21} = 0; // W bit
359 let Inst{22} = 0; // B bit
360 let Inst{24} = 0; // P bit
361 let Inst{27-26} = {0,1};
363 class AI2stbpo<dag oops, dag iops, Format f, string opc,
364 string asm, string cstr, list<dag> pattern>
365 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
367 let Inst{20} = 0; // L bit
368 let Inst{21} = 0; // W bit
369 let Inst{22} = 1; // B bit
370 let Inst{24} = 0; // P bit
371 let Inst{27-26} = {0,1};
374 // addrmode3 instructions
375 class AI3<dag oops, dag iops, Format f, string opc,
376 string asm, list<dag> pattern>
377 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
379 class AXI3<dag oops, dag iops, Format f, string asm,
381 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
385 class AI3ldh<dag oops, dag iops, Format f, string opc,
386 string asm, list<dag> pattern>
387 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
390 let Inst{5} = 1; // H bit
391 let Inst{6} = 0; // S bit
393 let Inst{20} = 1; // L bit
394 let Inst{21} = 0; // W bit
395 let Inst{24} = 1; // P bit
397 class AXI3ldh<dag oops, dag iops, Format f, string asm,
399 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
402 let Inst{5} = 1; // H bit
403 let Inst{6} = 0; // S bit
405 let Inst{20} = 1; // L bit
406 let Inst{21} = 0; // W bit
407 let Inst{24} = 1; // P bit
409 class AI3ldsh<dag oops, dag iops, Format f, string opc,
410 string asm, list<dag> pattern>
411 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
414 let Inst{5} = 1; // H bit
415 let Inst{6} = 1; // S bit
417 let Inst{20} = 1; // L bit
418 let Inst{21} = 0; // W bit
419 let Inst{24} = 1; // P bit
421 class AXI3ldsh<dag oops, dag iops, Format f, string asm,
423 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
426 let Inst{5} = 1; // H bit
427 let Inst{6} = 1; // S bit
429 let Inst{20} = 1; // L bit
430 let Inst{21} = 0; // W bit
431 let Inst{24} = 1; // P bit
433 class AI3ldsb<dag oops, dag iops, Format f, string opc,
434 string asm, list<dag> pattern>
435 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
438 let Inst{5} = 0; // H bit
439 let Inst{6} = 1; // S bit
441 let Inst{20} = 1; // L bit
442 let Inst{21} = 0; // W bit
443 let Inst{24} = 1; // P bit
445 class AXI3ldsb<dag oops, dag iops, Format f, string asm,
447 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
450 let Inst{5} = 0; // H bit
451 let Inst{6} = 1; // S bit
453 let Inst{20} = 1; // L bit
454 let Inst{21} = 0; // W bit
455 let Inst{24} = 1; // P bit
457 class AI3ldd<dag oops, dag iops, Format f, string opc,
458 string asm, list<dag> pattern>
459 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
462 let Inst{5} = 0; // H bit
463 let Inst{6} = 1; // S bit
465 let Inst{20} = 0; // L bit
466 let Inst{21} = 0; // W bit
467 let Inst{24} = 1; // P bit
471 class AI3sth<dag oops, dag iops, Format f, string opc,
472 string asm, list<dag> pattern>
473 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
476 let Inst{5} = 1; // H bit
477 let Inst{6} = 0; // S bit
479 let Inst{20} = 0; // L bit
480 let Inst{21} = 0; // W bit
481 let Inst{24} = 1; // P bit
483 class AXI3sth<dag oops, dag iops, Format f, string asm,
485 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
488 let Inst{5} = 1; // H bit
489 let Inst{6} = 0; // S bit
491 let Inst{20} = 0; // L bit
492 let Inst{21} = 0; // W bit
493 let Inst{24} = 1; // P bit
495 class AI3std<dag oops, dag iops, Format f, string opc,
496 string asm, list<dag> pattern>
497 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
500 let Inst{5} = 1; // H bit
501 let Inst{6} = 1; // S bit
503 let Inst{20} = 0; // L bit
504 let Inst{21} = 0; // W bit
505 let Inst{24} = 1; // P bit
509 class AI3ldhpr<dag oops, dag iops, Format f, string opc,
510 string asm, string cstr, list<dag> pattern>
511 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
512 asm, cstr, pattern> {
514 let Inst{5} = 1; // H bit
515 let Inst{6} = 0; // S bit
517 let Inst{20} = 1; // L bit
518 let Inst{21} = 1; // W bit
519 let Inst{24} = 1; // P bit
521 class AI3ldshpr<dag oops, dag iops, Format f, string opc,
522 string asm, string cstr, list<dag> pattern>
523 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
524 asm, cstr, pattern> {
526 let Inst{5} = 1; // H bit
527 let Inst{6} = 1; // S bit
529 let Inst{20} = 1; // L bit
530 let Inst{21} = 1; // W bit
531 let Inst{24} = 1; // P bit
533 class AI3ldsbpr<dag oops, dag iops, Format f, string opc,
534 string asm, string cstr, list<dag> pattern>
535 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
536 asm, cstr, pattern> {
538 let Inst{5} = 0; // H bit
539 let Inst{6} = 1; // S bit
541 let Inst{20} = 1; // L bit
542 let Inst{21} = 1; // W bit
543 let Inst{24} = 1; // P bit
546 // Pre-indexed stores
547 class AI3sthpr<dag oops, dag iops, Format f, string opc,
548 string asm, string cstr, list<dag> pattern>
549 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
550 asm, cstr, pattern> {
552 let Inst{5} = 1; // H bit
553 let Inst{6} = 0; // S bit
555 let Inst{20} = 0; // L bit
556 let Inst{21} = 1; // W bit
557 let Inst{24} = 1; // P bit
560 // Post-indexed loads
561 class AI3ldhpo<dag oops, dag iops, Format f, string opc,
562 string asm, string cstr, list<dag> pattern>
563 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
566 let Inst{5} = 1; // H bit
567 let Inst{6} = 0; // S bit
569 let Inst{20} = 1; // L bit
570 let Inst{21} = 1; // W bit
571 let Inst{24} = 0; // P bit
573 class AI3ldshpo<dag oops, dag iops, Format f, string opc,
574 string asm, string cstr, list<dag> pattern>
575 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
578 let Inst{5} = 1; // H bit
579 let Inst{6} = 1; // S bit
581 let Inst{20} = 1; // L bit
582 let Inst{21} = 1; // W bit
583 let Inst{24} = 0; // P bit
585 class AI3ldsbpo<dag oops, dag iops, Format f, string opc,
586 string asm, string cstr, list<dag> pattern>
587 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
590 let Inst{5} = 0; // H bit
591 let Inst{6} = 1; // S bit
593 let Inst{20} = 1; // L bit
594 let Inst{21} = 1; // W bit
595 let Inst{24} = 0; // P bit
598 // Post-indexed stores
599 class AI3sthpo<dag oops, dag iops, Format f, string opc,
600 string asm, string cstr, list<dag> pattern>
601 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
604 let Inst{5} = 1; // H bit
605 let Inst{6} = 0; // S bit
607 let Inst{20} = 0; // L bit
608 let Inst{21} = 1; // W bit
609 let Inst{24} = 0; // P bit
613 // addrmode4 instructions
614 class AXI4ld<dag oops, dag iops, Format f, string asm, list<dag> pattern>
615 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
617 let Inst{20} = 1; // L bit
618 let Inst{22} = 0; // S bit
619 let Inst{27-25} = 0b100;
621 class AXI4st<dag oops, dag iops, Format f, string asm, list<dag> pattern>
622 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
624 let Inst{20} = 0; // L bit
625 let Inst{22} = 0; // S bit
626 let Inst{27-25} = 0b100;
629 // Unsigned multiply, multiply-accumulate instructions.
630 class AMul1I<bits<7> opcod, dag oops, dag iops, string opc,
631 string asm, list<dag> pattern>
632 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
634 let Inst{7-4} = 0b1001;
635 let Inst{20} = 0; // S bit
636 let Inst{27-21} = opcod;
638 class AsMul1I<bits<7> opcod, dag oops, dag iops, string opc,
639 string asm, list<dag> pattern>
640 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
642 let Inst{7-4} = 0b1001;
643 let Inst{27-21} = opcod;
646 // Most significant word multiply
647 class AMul2I<bits<7> opcod, dag oops, dag iops, string opc,
648 string asm, list<dag> pattern>
649 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
651 let Inst{7-4} = 0b1001;
653 let Inst{27-21} = opcod;
656 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
657 class AMulxyI<bits<7> opcod, dag oops, dag iops, string opc,
658 string asm, list<dag> pattern>
659 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
664 let Inst{27-21} = opcod;
667 // Extend instructions.
668 class AExtI<bits<8> opcod, dag oops, dag iops, string opc,
669 string asm, list<dag> pattern>
670 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, opc,
672 let Inst{7-4} = 0b0111;
673 let Inst{27-20} = opcod;
676 // Misc Arithmetic instructions.
677 class AMiscA1I<bits<8> opcod, dag oops, dag iops, string opc,
678 string asm, list<dag> pattern>
679 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, opc,
681 let Inst{27-20} = opcod;
684 //===----------------------------------------------------------------------===//
686 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
687 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
688 list<Predicate> Predicates = [IsARM];
690 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
691 list<Predicate> Predicates = [IsARM, HasV5TE];
693 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
694 list<Predicate> Predicates = [IsARM, HasV6];
697 //===----------------------------------------------------------------------===//
699 // Thumb Instruction Format Definitions.
703 // TI - Thumb instruction.
705 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
706 string asm, string cstr, list<dag> pattern>
707 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
708 let OutOperandList = outs;
709 let InOperandList = ins;
711 let Pattern = pattern;
712 list<Predicate> Predicates = [IsThumb];
715 class TI<dag outs, dag ins, string asm, list<dag> pattern>
716 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
717 class TI1<dag outs, dag ins, string asm, list<dag> pattern>
718 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
719 class TI2<dag outs, dag ins, string asm, list<dag> pattern>
720 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
721 class TI4<dag outs, dag ins, string asm, list<dag> pattern>
722 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
723 class TIs<dag outs, dag ins, string asm, list<dag> pattern>
724 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
726 // Two-address instructions
727 class TIt<dag outs, dag ins, string asm, list<dag> pattern>
728 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
730 // BL, BLX(1) are translated by assembler into two instructions
731 class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
732 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
734 // BR_JT instructions
735 class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
736 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
739 //===----------------------------------------------------------------------===//
741 //===----------------------------------------------------------------------===//
742 // ARM VFP Instruction templates.
745 // ARM VFP addrmode5 loads and stores
746 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
747 string opc, string asm, list<dag> pattern>
748 : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
749 VFPLdStFrm, opc, asm, "", pattern> {
750 // TODO: Mark the instructions with the appropriate subtarget info.
751 let Inst{27-24} = opcod1;
752 let Inst{21-20} = opcod2;
753 let Inst{11-8} = 0b1011;
756 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
757 string opc, string asm, list<dag> pattern>
758 : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
759 VFPLdStFrm, opc, asm, "", pattern> {
760 // TODO: Mark the instructions with the appropriate subtarget info.
761 let Inst{27-24} = opcod1;
762 let Inst{21-20} = opcod2;
763 let Inst{11-8} = 0b1010;
766 // Load / store multiple
767 class AXSI5<dag oops, dag iops, string asm, list<dag> pattern>
768 : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
769 VFPLdStMulFrm, asm, "", pattern> {
770 // TODO: Mark the instructions with the appropriate subtarget info.
771 let Inst{27-25} = 0b110;
772 let Inst{11-8} = 0b1011;
775 class AXDI5<dag oops, dag iops, string asm, list<dag> pattern>
776 : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
777 VFPLdStMulFrm, asm, "", pattern> {
778 // TODO: Mark the instructions with the appropriate subtarget info.
779 let Inst{27-25} = 0b110;
780 let Inst{11-8} = 0b1010;
784 // Double precision, unary
785 class ADuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
786 string opc, string asm, list<dag> pattern>
787 : AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> {
788 let Inst{27-20} = opcod1;
789 let Inst{19-16} = opcod2;
790 let Inst{11-8} = 0b1011;
791 let Inst{7-4} = opcod3;
794 // Double precision, binary
795 class ADbI<bits<8> opcod, dag oops, dag iops, string opc,
796 string asm, list<dag> pattern>
797 : AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> {
798 let Inst{27-20} = opcod;
799 let Inst{11-8} = 0b1011;
802 // Single precision, unary
803 class ASuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
804 string opc, string asm, list<dag> pattern>
805 : AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> {
806 // Bits 22 (D bit) and 5 (M bit) will be changed during instruction encoding.
807 let Inst{27-20} = opcod1;
808 let Inst{19-16} = opcod2;
809 let Inst{11-8} = 0b1010;
810 let Inst{7-4} = opcod3;
813 // Single precision, binary
814 class ASbI<bits<8> opcod, dag oops, dag iops, string opc,
815 string asm, list<dag> pattern>
816 : AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> {
817 // Bit 22 (D bit) can be changed during instruction encoding.
818 let Inst{27-20} = opcod;
819 let Inst{11-8} = 0b1010;
822 class AVConv1I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
823 string asm, list<dag> pattern>
824 : AI<oops, iops, VFPConv1Frm, opc, asm, pattern> {
825 let Inst{27-20} = opcod1;
826 let Inst{11-8} = opcod2;
830 class AVConv2I<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3,
831 dag oops, dag iops, string opc, string asm, list<dag> pattern>
832 : AI<oops, iops, VFPConv1Frm, opc, asm, pattern> {
833 let Inst{27-20} = opcod1;
834 let Inst{19-16} = opcod2;
835 let Inst{11-8} = opcod3;
839 //===----------------------------------------------------------------------===//
842 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
843 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
844 list<Predicate> Predicates = [IsThumb];
847 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
848 list<Predicate> Predicates = [IsThumb, HasV5T];