1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<1>;
23 def MulFrm : Format<2>;
24 def MulSMLAW : Format<3>;
25 def MulSMULW : Format<4>;
26 def MulSMLA : Format<5>;
27 def MulSMUL : Format<6>;
28 def Branch : Format<7>;
29 def BranchMisc : Format<8>;
31 def DPRdIm : Format<9>;
32 def DPRdReg : Format<10>;
33 def DPRdSoReg : Format<11>;
34 def DPRdMisc : Format<12>;
35 def DPRnIm : Format<13>;
36 def DPRnReg : Format<14>;
37 def DPRnSoReg : Format<15>;
38 def DPRIm : Format<16>;
39 def DPRReg : Format<17>;
40 def DPRSoReg : Format<18>;
41 def DPRImS : Format<19>;
42 def DPRRegS : Format<20>;
43 def DPRSoRegS : Format<21>;
45 def LdFrm : Format<22>;
46 def StFrm : Format<23>;
48 def ArithMisc : Format<24>;
49 def ThumbFrm : Format<25>;
50 def VFPFrm : Format<26>;
53 //===----------------------------------------------------------------------===//
55 // ARM Instruction templates.
58 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
59 Format f, string cstr>
63 let Namespace = "ARM";
65 bits<4> Opcode = opcod;
67 bits<4> AddrModeBits = AM.Value;
70 bits<3> SizeFlag = SZ.Value;
73 bits<2> IndexModeBits = IM.Value;
76 bits<5> Form = F.Value;
78 let Constraints = cstr;
81 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
82 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
83 let OutOperandList = oops;
84 let InOperandList = iops;
86 let Pattern = pattern;
89 // Almost all ARM instructions are predicable.
90 class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
91 IndexMode im, Format f, string opc, string asm, string cstr,
93 : InstARM<opcod, am, sz, im, f, cstr> {
94 let OutOperandList = oops;
95 let InOperandList = !con(iops, (ops pred:$p));
96 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
97 let Pattern = pattern;
98 list<Predicate> Predicates = [IsARM];
101 // Same as I except it can optionally modify CPSR. Note it's modeled as
102 // an input operand since by default it's a zero register. It will
103 // become an implicit def once it's "flipped".
104 class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
105 IndexMode im, Format f, string opc, string asm, string cstr,
107 : InstARM<opcod, am, sz, im, f, cstr> {
108 let OutOperandList = oops;
109 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
110 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
111 let Pattern = pattern;
112 list<Predicate> Predicates = [IsARM];
115 class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
116 string asm, list<dag> pattern>
117 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
119 class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
120 string asm, list<dag> pattern>
121 : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
124 // addrmode1 instructions
125 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
126 string asm, list<dag> pattern>
127 : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
129 let Inst{21-24} = opcod;
132 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
133 string asm, list<dag> pattern>
134 : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
137 let Inst{21-24} = opcod;
140 class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
141 string asm, list<dag> pattern>
142 : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
146 // addrmode2 loads and stores
147 class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
148 string asm, list<dag> pattern>
149 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
155 class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
156 string asm, list<dag> pattern>
157 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
158 let Inst{20} = 1; // L bit
159 let Inst{21} = 0; // W bit
160 let Inst{22} = 0; // B bit
161 let Inst{24} = 1; // P bit
163 class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
164 string asm, list<dag> pattern>
165 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
166 let Inst{20} = 1; // L bit
167 let Inst{21} = 0; // W bit
168 let Inst{22} = 1; // B bit
169 let Inst{24} = 1; // P bit
173 class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
174 string asm, list<dag> pattern>
175 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
176 let Inst{20} = 0; // L bit
177 let Inst{21} = 0; // W bit
178 let Inst{22} = 0; // B bit
179 let Inst{24} = 1; // P bit
181 class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
182 string asm, list<dag> pattern>
183 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
184 let Inst{20} = 0; // L bit
185 let Inst{21} = 0; // W bit
186 let Inst{22} = 1; // B bit
187 let Inst{24} = 1; // P bit
191 class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
192 string asm, string cstr, list<dag> pattern>
193 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
194 asm, cstr, pattern> {
195 let Inst{20} = 1; // L bit
196 let Inst{21} = 1; // W bit
197 let Inst{22} = 0; // B bit
198 let Inst{24} = 1; // P bit
200 class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
201 string asm, string cstr, list<dag> pattern>
202 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
203 asm, cstr, pattern> {
204 let Inst{20} = 1; // L bit
205 let Inst{21} = 1; // W bit
206 let Inst{22} = 1; // B bit
207 let Inst{24} = 1; // P bit
210 // Pre-indexed stores
211 class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
212 string asm, string cstr, list<dag> pattern>
213 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
214 asm, cstr, pattern> {
215 let Inst{20} = 0; // L bit
216 let Inst{21} = 1; // W bit
217 let Inst{22} = 0; // B bit
218 let Inst{24} = 1; // P bit
220 class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
221 string asm, string cstr, list<dag> pattern>
222 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
223 asm, cstr, pattern> {
224 let Inst{20} = 0; // L bit
225 let Inst{21} = 1; // W bit
226 let Inst{22} = 1; // B bit
227 let Inst{24} = 1; // P bit
230 // Post-indexed loads
231 class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
232 string asm, string cstr, list<dag> pattern>
233 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
235 let Inst{20} = 1; // L bit
236 let Inst{21} = 0; // W bit
237 let Inst{22} = 0; // B bit
238 let Inst{24} = 0; // P bit
240 class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
241 string asm, string cstr, list<dag> pattern>
242 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
244 let Inst{20} = 1; // L bit
245 let Inst{21} = 0; // W bit
246 let Inst{22} = 1; // B bit
247 let Inst{24} = 0; // P bit
250 // Post-indexed stores
251 class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
252 string asm, string cstr, list<dag> pattern>
253 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
255 let Inst{20} = 0; // L bit
256 let Inst{21} = 0; // W bit
257 let Inst{22} = 0; // B bit
258 let Inst{24} = 0; // P bit
260 class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
261 string asm, string cstr, list<dag> pattern>
262 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
264 let Inst{20} = 0; // L bit
265 let Inst{21} = 0; // W bit
266 let Inst{22} = 1; // B bit
267 let Inst{24} = 0; // P bit
270 // addrmode3 instructions
271 class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
272 string asm, list<dag> pattern>
273 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
277 class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
278 string asm, list<dag> pattern>
279 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
282 let Inst{5} = 1; // H bit
283 let Inst{6} = 0; // S bit
285 let Inst{20} = 1; // L bit
286 let Inst{21} = 0; // W bit
287 let Inst{24} = 1; // P bit
289 class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
290 string asm, list<dag> pattern>
291 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
294 let Inst{5} = 1; // H bit
295 let Inst{6} = 1; // S bit
297 let Inst{20} = 1; // L bit
298 let Inst{21} = 0; // W bit
299 let Inst{24} = 1; // P bit
301 class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
302 string asm, list<dag> pattern>
303 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
306 let Inst{5} = 0; // H bit
307 let Inst{6} = 1; // S bit
309 let Inst{20} = 1; // L bit
310 let Inst{21} = 0; // W bit
311 let Inst{24} = 1; // P bit
313 class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc,
314 string asm, list<dag> pattern>
315 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
318 let Inst{5} = 0; // H bit
319 let Inst{6} = 1; // S bit
321 let Inst{20} = 0; // L bit
322 let Inst{21} = 0; // W bit
323 let Inst{24} = 1; // P bit
327 class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc,
328 string asm, list<dag> pattern>
329 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
332 let Inst{5} = 1; // H bit
333 let Inst{6} = 0; // S bit
335 let Inst{20} = 0; // L bit
336 let Inst{21} = 0; // W bit
337 let Inst{24} = 1; // P bit
339 class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc,
340 string asm, list<dag> pattern>
341 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
344 let Inst{5} = 1; // H bit
345 let Inst{6} = 1; // S bit
347 let Inst{20} = 0; // L bit
348 let Inst{21} = 0; // W bit
349 let Inst{24} = 1; // P bit
353 class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
354 string asm, string cstr, list<dag> pattern>
355 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
356 asm, cstr, pattern> {
358 let Inst{5} = 1; // H bit
359 let Inst{6} = 0; // S bit
361 let Inst{20} = 1; // L bit
362 let Inst{21} = 1; // W bit
363 let Inst{24} = 1; // P bit
365 class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
366 string asm, string cstr, list<dag> pattern>
367 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
368 asm, cstr, pattern> {
370 let Inst{5} = 1; // H bit
371 let Inst{6} = 1; // S bit
373 let Inst{20} = 1; // L bit
374 let Inst{21} = 1; // W bit
375 let Inst{24} = 1; // P bit
377 class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
378 string asm, string cstr, list<dag> pattern>
379 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
380 asm, cstr, pattern> {
382 let Inst{5} = 0; // H bit
383 let Inst{6} = 1; // S bit
385 let Inst{20} = 1; // L bit
386 let Inst{21} = 1; // W bit
387 let Inst{24} = 1; // P bit
390 // Pre-indexed stores
391 class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
392 string asm, string cstr, list<dag> pattern>
393 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
394 asm, cstr, pattern> {
396 let Inst{5} = 1; // H bit
397 let Inst{6} = 0; // S bit
399 let Inst{20} = 0; // L bit
400 let Inst{21} = 1; // W bit
401 let Inst{24} = 1; // P bit
404 // Post-indexed loads
405 class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
406 string asm, string cstr, list<dag> pattern>
407 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
410 let Inst{5} = 1; // H bit
411 let Inst{6} = 0; // S bit
413 let Inst{20} = 1; // L bit
414 let Inst{21} = 1; // W bit
415 let Inst{24} = 0; // P bit
417 class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
418 string asm, string cstr, list<dag> pattern>
419 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
422 let Inst{5} = 1; // H bit
423 let Inst{6} = 1; // S bit
425 let Inst{20} = 1; // L bit
426 let Inst{21} = 1; // W bit
427 let Inst{24} = 0; // P bit
429 class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
430 string asm, string cstr, list<dag> pattern>
431 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
434 let Inst{5} = 0; // H bit
435 let Inst{6} = 1; // S bit
437 let Inst{20} = 1; // L bit
438 let Inst{21} = 1; // W bit
439 let Inst{24} = 0; // P bit
442 // Post-indexed stores
443 class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
444 string asm, string cstr, list<dag> pattern>
445 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
448 let Inst{5} = 1; // H bit
449 let Inst{6} = 0; // S bit
451 let Inst{20} = 0; // L bit
452 let Inst{21} = 1; // W bit
453 let Inst{24} = 0; // P bit
457 // addrmode4 instructions
458 class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
459 string asm, list<dag> pattern>
460 : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
466 class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
467 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
468 : InstARM<opcod, am, sz, im, f, cstr> {
469 let OutOperandList = oops;
470 let InOperandList = iops;
472 let Pattern = pattern;
473 list<Predicate> Predicates = [IsARM];
476 class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
478 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
480 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
482 : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
484 class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
486 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
488 class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
490 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
492 class AXI4<bits<4> opcod, dag oops, dag iops, Format f, string asm,
494 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
497 class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
499 : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
502 // BR_JT instructions
503 class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
504 : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
506 class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
507 : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
509 class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
510 : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
514 //===----------------------------------------------------------------------===//
516 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
517 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
518 list<Predicate> Predicates = [IsARM];
520 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
521 list<Predicate> Predicates = [IsARM, HasV5TE];
523 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
524 list<Predicate> Predicates = [IsARM, HasV6];
527 //===----------------------------------------------------------------------===//
529 // Thumb Instruction Format Definitions.
533 // TI - Thumb instruction.
535 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
536 string asm, string cstr, list<dag> pattern>
537 // FIXME: Set all opcodes to 0 for now.
538 : InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
539 let OutOperandList = outs;
540 let InOperandList = ins;
542 let Pattern = pattern;
543 list<Predicate> Predicates = [IsThumb];
546 class TI<dag outs, dag ins, string asm, list<dag> pattern>
547 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
548 class TI1<dag outs, dag ins, string asm, list<dag> pattern>
549 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
550 class TI2<dag outs, dag ins, string asm, list<dag> pattern>
551 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
552 class TI4<dag outs, dag ins, string asm, list<dag> pattern>
553 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
554 class TIs<dag outs, dag ins, string asm, list<dag> pattern>
555 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
557 // Two-address instructions
558 class TIt<dag outs, dag ins, string asm, list<dag> pattern>
559 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
561 // BL, BLX(1) are translated by assembler into two instructions
562 class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
563 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
565 // BR_JT instructions
566 class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
567 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
570 //===----------------------------------------------------------------------===//
573 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
574 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
575 list<Predicate> Predicates = [IsThumb];
578 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
579 list<Predicate> Predicates = [IsThumb, HasV5T];