1 //===- ARMInstrFormats.td - ARM Instruction Formats ----------*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<6> val> {
22 def Pseudo : Format<0>;
23 def MulFrm : Format<1>;
24 def BrFrm : Format<2>;
25 def BrMiscFrm : Format<3>;
27 def DPFrm : Format<4>;
28 def DPSoRegRegFrm : Format<5>;
30 def LdFrm : Format<6>;
31 def StFrm : Format<7>;
32 def LdMiscFrm : Format<8>;
33 def StMiscFrm : Format<9>;
34 def LdStMulFrm : Format<10>;
36 def LdStExFrm : Format<11>;
38 def ArithMiscFrm : Format<12>;
39 def SatFrm : Format<13>;
40 def ExtFrm : Format<14>;
42 def VFPUnaryFrm : Format<15>;
43 def VFPBinaryFrm : Format<16>;
44 def VFPConv1Frm : Format<17>;
45 def VFPConv2Frm : Format<18>;
46 def VFPConv3Frm : Format<19>;
47 def VFPConv4Frm : Format<20>;
48 def VFPConv5Frm : Format<21>;
49 def VFPLdStFrm : Format<22>;
50 def VFPLdStMulFrm : Format<23>;
51 def VFPMiscFrm : Format<24>;
53 def ThumbFrm : Format<25>;
54 def MiscFrm : Format<26>;
56 def NGetLnFrm : Format<27>;
57 def NSetLnFrm : Format<28>;
58 def NDupFrm : Format<29>;
59 def NLdStFrm : Format<30>;
60 def N1RegModImmFrm: Format<31>;
61 def N2RegFrm : Format<32>;
62 def NVCVTFrm : Format<33>;
63 def NVDupLnFrm : Format<34>;
64 def N2RegVShLFrm : Format<35>;
65 def N2RegVShRFrm : Format<36>;
66 def N3RegFrm : Format<37>;
67 def N3RegVShFrm : Format<38>;
68 def NVExtFrm : Format<39>;
69 def NVMulSLFrm : Format<40>;
70 def NVTBLFrm : Format<41>;
71 def DPSoRegImmFrm : Format<42>;
75 // The instruction has an Rn register operand.
76 // UnaryDP - Indicates this is a unary data processing instruction, i.e.
77 // it doesn't have a Rn operand.
78 class UnaryDP { bit isUnaryDataProc = 1; }
80 // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
81 // a 16-bit Thumb instruction if certain conditions are met.
82 class Xform16Bit { bit canXformTo16Bit = 1; }
84 //===----------------------------------------------------------------------===//
85 // ARM Instruction flags. These need to match ARMBaseInstrInfo.h.
88 // FIXME: Once the JIT is MC-ized, these can go away.
90 class AddrMode<bits<5> val> {
93 def AddrModeNone : AddrMode<0>;
94 def AddrMode1 : AddrMode<1>;
95 def AddrMode2 : AddrMode<2>;
96 def AddrMode3 : AddrMode<3>;
97 def AddrMode4 : AddrMode<4>;
98 def AddrMode5 : AddrMode<5>;
99 def AddrMode6 : AddrMode<6>;
100 def AddrModeT1_1 : AddrMode<7>;
101 def AddrModeT1_2 : AddrMode<8>;
102 def AddrModeT1_4 : AddrMode<9>;
103 def AddrModeT1_s : AddrMode<10>;
104 def AddrModeT2_i12 : AddrMode<11>;
105 def AddrModeT2_i8 : AddrMode<12>;
106 def AddrModeT2_so : AddrMode<13>;
107 def AddrModeT2_pc : AddrMode<14>;
108 def AddrModeT2_i8s4 : AddrMode<15>;
109 def AddrMode_i12 : AddrMode<16>;
111 // Load / store index mode.
112 class IndexMode<bits<2> val> {
115 def IndexModeNone : IndexMode<0>;
116 def IndexModePre : IndexMode<1>;
117 def IndexModePost : IndexMode<2>;
118 def IndexModeUpd : IndexMode<3>;
120 // Instruction execution domain.
121 class Domain<bits<3> val> {
124 def GenericDomain : Domain<0>;
125 def VFPDomain : Domain<1>; // Instructions in VFP domain only
126 def NeonDomain : Domain<2>; // Instructions in Neon domain only
127 def VFPNeonDomain : Domain<3>; // Instructions in both VFP & Neon domains
128 def VFPNeonA8Domain : Domain<5>; // Instructions in VFP & Neon under A8
130 //===----------------------------------------------------------------------===//
131 // ARM special operands.
134 // ARM imod and iflag operands, used only by the CPS instruction.
135 def imod_op : Operand<i32> {
136 let PrintMethod = "printCPSIMod";
139 def ProcIFlagsOperand : AsmOperandClass {
140 let Name = "ProcIFlags";
141 let ParserMethod = "parseProcIFlagsOperand";
143 def iflags_op : Operand<i32> {
144 let PrintMethod = "printCPSIFlag";
145 let ParserMatchClass = ProcIFlagsOperand;
148 // ARM Predicate operand. Default to 14 = always (AL). Second part is CC
149 // register whose default is 0 (no register).
150 def CondCodeOperand : AsmOperandClass { let Name = "CondCode"; }
151 def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
152 (ops (i32 14), (i32 zero_reg))> {
153 let PrintMethod = "printPredicateOperand";
154 let ParserMatchClass = CondCodeOperand;
157 // Conditional code result for instructions whose 's' bit is set, e.g. subs.
158 def CCOutOperand : AsmOperandClass { let Name = "CCOut"; }
159 def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
160 let EncoderMethod = "getCCOutOpValue";
161 let PrintMethod = "printSBitModifierOperand";
162 let ParserMatchClass = CCOutOperand;
165 // Same as cc_out except it defaults to setting CPSR.
166 def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> {
167 let EncoderMethod = "getCCOutOpValue";
168 let PrintMethod = "printSBitModifierOperand";
169 let ParserMatchClass = CCOutOperand;
172 // ARM special operands for disassembly only.
174 def SetEndAsmOperand : AsmOperandClass {
175 let Name = "SetEndImm";
176 let ParserMethod = "parseSetEndImm";
178 def setend_op : Operand<i32> {
179 let PrintMethod = "printSetendOperand";
180 let ParserMatchClass = SetEndAsmOperand;
183 def MSRMaskOperand : AsmOperandClass {
184 let Name = "MSRMask";
185 let ParserMethod = "parseMSRMaskOperand";
187 def msr_mask : Operand<i32> {
188 let PrintMethod = "printMSRMaskOperand";
189 let ParserMatchClass = MSRMaskOperand;
192 // Shift Right Immediate - A shift right immediate is encoded differently from
193 // other shift immediates. The imm6 field is encoded like so:
196 // 8 imm6<5:3> = '001', 8 - <imm> is encoded in imm6<2:0>
197 // 16 imm6<5:4> = '01', 16 - <imm> is encoded in imm6<3:0>
198 // 32 imm6<5> = '1', 32 - <imm> is encoded in imm6<4:0>
199 // 64 64 - <imm> is encoded in imm6<5:0>
200 def shr_imm8 : Operand<i32> {
201 let EncoderMethod = "getShiftRight8Imm";
203 def shr_imm16 : Operand<i32> {
204 let EncoderMethod = "getShiftRight16Imm";
206 def shr_imm32 : Operand<i32> {
207 let EncoderMethod = "getShiftRight32Imm";
209 def shr_imm64 : Operand<i32> {
210 let EncoderMethod = "getShiftRight64Imm";
213 //===----------------------------------------------------------------------===//
214 // ARM Instruction templates.
217 class InstTemplate<AddrMode am, int sz, IndexMode im,
218 Format f, Domain d, string cstr, InstrItinClass itin>
220 let Namespace = "ARM";
225 bits<2> IndexModeBits = IM.Value;
227 bits<6> Form = F.Value;
229 bit isUnaryDataProc = 0;
230 bit canXformTo16Bit = 0;
232 // If this is a pseudo instruction, mark it isCodeGenOnly.
233 let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
235 // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h.
236 let TSFlags{4-0} = AM.Value;
237 let TSFlags{6-5} = IndexModeBits;
238 let TSFlags{12-7} = Form;
239 let TSFlags{13} = isUnaryDataProc;
240 let TSFlags{14} = canXformTo16Bit;
241 let TSFlags{17-15} = D.Value;
243 let Constraints = cstr;
244 let Itinerary = itin;
251 class InstARM<AddrMode am, int sz, IndexMode im,
252 Format f, Domain d, string cstr, InstrItinClass itin>
253 : InstTemplate<am, sz, im, f, d, cstr, itin>, Encoding {
254 let DecoderNamespace = "ARM";
257 // This Encoding-less class is used by Thumb1 to specify the encoding bits later
258 // on by adding flavors to specific instructions.
259 class InstThumb<AddrMode am, int sz, IndexMode im,
260 Format f, Domain d, string cstr, InstrItinClass itin>
261 : InstTemplate<am, sz, im, f, d, cstr, itin> {
262 let DecoderNamespace = "Thumb";
265 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
266 : InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo,
267 GenericDomain, "", itin> {
268 let OutOperandList = oops;
269 let InOperandList = iops;
270 let Pattern = pattern;
271 let isCodeGenOnly = 1;
275 // PseudoInst that's ARM-mode only.
276 class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
278 : PseudoInst<oops, iops, itin, pattern> {
280 list<Predicate> Predicates = [IsARM];
283 // PseudoInst that's Thumb-mode only.
284 class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
286 : PseudoInst<oops, iops, itin, pattern> {
288 list<Predicate> Predicates = [IsThumb];
291 // PseudoInst that's Thumb2-mode only.
292 class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
294 : PseudoInst<oops, iops, itin, pattern> {
296 list<Predicate> Predicates = [IsThumb2];
299 class ARMPseudoExpand<dag oops, dag iops, int sz,
300 InstrItinClass itin, list<dag> pattern,
302 : ARMPseudoInst<oops, iops, sz, itin, pattern>,
303 PseudoInstExpansion<Result>;
305 class tPseudoExpand<dag oops, dag iops, int sz,
306 InstrItinClass itin, list<dag> pattern,
308 : tPseudoInst<oops, iops, sz, itin, pattern>,
309 PseudoInstExpansion<Result>;
311 class t2PseudoExpand<dag oops, dag iops, int sz,
312 InstrItinClass itin, list<dag> pattern,
314 : t2PseudoInst<oops, iops, sz, itin, pattern>,
315 PseudoInstExpansion<Result>;
317 // Almost all ARM instructions are predicable.
318 class I<dag oops, dag iops, AddrMode am, int sz,
319 IndexMode im, Format f, InstrItinClass itin,
320 string opc, string asm, string cstr,
322 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
325 let OutOperandList = oops;
326 let InOperandList = !con(iops, (ins pred:$p));
327 let AsmString = !strconcat(opc, "${p}", asm);
328 let Pattern = pattern;
329 list<Predicate> Predicates = [IsARM];
332 // A few are not predicable
333 class InoP<dag oops, dag iops, AddrMode am, int sz,
334 IndexMode im, Format f, InstrItinClass itin,
335 string opc, string asm, string cstr,
337 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
338 let OutOperandList = oops;
339 let InOperandList = iops;
340 let AsmString = !strconcat(opc, asm);
341 let Pattern = pattern;
342 let isPredicable = 0;
343 list<Predicate> Predicates = [IsARM];
346 // Same as I except it can optionally modify CPSR. Note it's modeled as an input
347 // operand since by default it's a zero register. It will become an implicit def
348 // once it's "flipped".
349 class sI<dag oops, dag iops, AddrMode am, int sz,
350 IndexMode im, Format f, InstrItinClass itin,
351 string opc, string asm, string cstr,
353 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
354 bits<4> p; // Predicate operand
355 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
359 let OutOperandList = oops;
360 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
361 let AsmString = !strconcat(opc, "${s}${p}", asm);
362 let Pattern = pattern;
363 list<Predicate> Predicates = [IsARM];
367 class XI<dag oops, dag iops, AddrMode am, int sz,
368 IndexMode im, Format f, InstrItinClass itin,
369 string asm, string cstr, list<dag> pattern>
370 : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
371 let OutOperandList = oops;
372 let InOperandList = iops;
374 let Pattern = pattern;
375 list<Predicate> Predicates = [IsARM];
378 class AI<dag oops, dag iops, Format f, InstrItinClass itin,
379 string opc, string asm, list<dag> pattern>
380 : I<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
381 opc, asm, "", pattern>;
382 class AsI<dag oops, dag iops, Format f, InstrItinClass itin,
383 string opc, string asm, list<dag> pattern>
384 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
385 opc, asm, "", pattern>;
386 class AXI<dag oops, dag iops, Format f, InstrItinClass itin,
387 string asm, list<dag> pattern>
388 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
390 class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
391 string opc, string asm, list<dag> pattern>
392 : InoP<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
393 opc, asm, "", pattern>;
395 // Ctrl flow instructions
396 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
397 string opc, string asm, list<dag> pattern>
398 : I<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
399 opc, asm, "", pattern> {
400 let Inst{27-24} = opcod;
402 class ABXI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,
403 string asm, list<dag> pattern>
404 : XI<oops, iops, AddrModeNone, 4, IndexModeNone, BrFrm, itin,
406 let Inst{27-24} = opcod;
409 // BR_JT instructions
410 class JTI<dag oops, dag iops, InstrItinClass itin,
411 string asm, list<dag> pattern>
412 : XI<oops, iops, AddrModeNone, 0, IndexModeNone, BrMiscFrm, itin,
415 // Atomic load/store instructions
416 class AIldrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
417 string opc, string asm, list<dag> pattern>
418 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
419 opc, asm, "", pattern> {
422 let Inst{27-23} = 0b00011;
423 let Inst{22-21} = opcod;
425 let Inst{19-16} = addr;
426 let Inst{15-12} = Rt;
427 let Inst{11-0} = 0b111110011111;
429 class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
430 string opc, string asm, list<dag> pattern>
431 : I<oops, iops, AddrModeNone, 4, IndexModeNone, LdStExFrm, itin,
432 opc, asm, "", pattern> {
436 let Inst{27-23} = 0b00011;
437 let Inst{22-21} = opcod;
439 let Inst{19-16} = addr;
440 let Inst{15-12} = Rd;
441 let Inst{11-4} = 0b11111001;
444 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
445 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
449 let Inst{27-23} = 0b00010;
451 let Inst{21-20} = 0b00;
452 let Inst{19-16} = addr;
453 let Inst{15-12} = Rt;
454 let Inst{11-4} = 0b00001001;
458 // addrmode1 instructions
459 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
460 string opc, string asm, list<dag> pattern>
461 : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
462 opc, asm, "", pattern> {
463 let Inst{24-21} = opcod;
464 let Inst{27-26} = 0b00;
466 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
467 string opc, string asm, list<dag> pattern>
468 : sI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
469 opc, asm, "", pattern> {
470 let Inst{24-21} = opcod;
471 let Inst{27-26} = 0b00;
473 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
474 string asm, list<dag> pattern>
475 : XI<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
477 let Inst{24-21} = opcod;
478 let Inst{27-26} = 0b00;
483 // LDR/LDRB/STR/STRB/...
484 class AI2ldst<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
485 Format f, InstrItinClass itin, string opc, string asm,
487 : I<oops, iops, am, 4, IndexModeNone, f, itin, opc, asm,
489 let Inst{27-25} = op;
490 let Inst{24} = 1; // 24 == P
492 let Inst{22} = isByte;
493 let Inst{21} = 0; // 21 == W
496 // Indexed load/stores
497 class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
498 IndexMode im, Format f, InstrItinClass itin, string opc,
499 string asm, string cstr, list<dag> pattern>
500 : I<oops, iops, AddrMode2, 4, im, f, itin,
501 opc, asm, cstr, pattern> {
503 let Inst{27-26} = 0b01;
504 let Inst{24} = isPre; // P bit
505 let Inst{22} = isByte; // B bit
506 let Inst{21} = isPre; // W bit
507 let Inst{20} = isLd; // L bit
508 let Inst{15-12} = Rt;
510 class AI2stridx_reg<bit isByte, bit isPre, dag oops, dag iops,
511 IndexMode im, Format f, InstrItinClass itin, string opc,
512 string asm, string cstr, list<dag> pattern>
513 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
515 // AM2 store w/ two operands: (GPR, am2offset)
521 let Inst{23} = offset{12};
522 let Inst{19-16} = Rn;
523 let Inst{11-5} = offset{11-5};
525 let Inst{3-0} = offset{3-0};
528 class AI2stridx_imm<bit isByte, bit isPre, dag oops, dag iops,
529 IndexMode im, Format f, InstrItinClass itin, string opc,
530 string asm, string cstr, list<dag> pattern>
531 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
533 // AM2 store w/ two operands: (GPR, am2offset)
539 let Inst{23} = offset{12};
540 let Inst{19-16} = Rn;
541 let Inst{11-0} = offset{11-0};
545 // FIXME: Merge with the above class when addrmode2 gets used for STR, STRB
546 // but for now use this class for STRT and STRBT.
547 class AI2stridxT<bit isByte, bit isPre, dag oops, dag iops,
548 IndexMode im, Format f, InstrItinClass itin, string opc,
549 string asm, string cstr, list<dag> pattern>
550 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
552 // AM2 store w/ two operands: (GPR, am2offset)
554 // {13} 1 == Rm, 0 == imm12
558 let Inst{25} = addr{13};
559 let Inst{23} = addr{12};
560 let Inst{19-16} = addr{17-14};
561 let Inst{11-0} = addr{11-0};
564 // addrmode3 instructions
565 class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f,
566 InstrItinClass itin, string opc, string asm, list<dag> pattern>
567 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
568 opc, asm, "", pattern> {
571 let Inst{27-25} = 0b000;
572 let Inst{24} = 1; // P bit
573 let Inst{23} = addr{8}; // U bit
574 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
575 let Inst{21} = 0; // W bit
576 let Inst{20} = op20; // L bit
577 let Inst{19-16} = addr{12-9}; // Rn
578 let Inst{15-12} = Rt; // Rt
579 let Inst{11-8} = addr{7-4}; // imm7_4/zero
581 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
584 class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
585 IndexMode im, Format f, InstrItinClass itin, string opc,
586 string asm, string cstr, list<dag> pattern>
587 : I<oops, iops, AddrMode3, 4, im, f, itin,
588 opc, asm, cstr, pattern> {
590 let Inst{27-25} = 0b000;
591 let Inst{24} = isPre; // P bit
592 let Inst{21} = isPre; // W bit
593 let Inst{20} = op20; // L bit
594 let Inst{15-12} = Rt; // Rt
598 // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
599 // but for now use this class for LDRSBT, LDRHT, LDSHT.
600 class AI3ldstidxT<bits<4> op, bit isLoad, dag oops, dag iops,
601 IndexMode im, Format f, InstrItinClass itin, string opc,
602 string asm, string cstr, list<dag> pattern>
603 : I<oops, iops, AddrMode3, 4, im, f, itin, opc, asm, cstr, pattern> {
604 // {13} 1 == imm8, 0 == Rm
611 let Inst{27-25} = 0b000;
612 let Inst{24} = 0; // P bit
614 let Inst{20} = isLoad; // L bit
615 let Inst{19-16} = addr; // Rn
616 let Inst{15-12} = Rt; // Rt
620 class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
621 IndexMode im, Format f, InstrItinClass itin, string opc,
622 string asm, string cstr, list<dag> pattern>
623 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
625 // AM3 store w/ two operands: (GPR, am3offset)
629 let Inst{27-25} = 0b000;
630 let Inst{23} = offset{8};
631 let Inst{22} = offset{9};
632 let Inst{19-16} = Rn;
633 let Inst{15-12} = Rt; // Rt
634 let Inst{11-8} = offset{7-4}; // imm7_4/zero
636 let Inst{3-0} = offset{3-0}; // imm3_0/Rm
640 class AI3str<bits<4> op, dag oops, dag iops, Format f, InstrItinClass itin,
641 string opc, string asm, list<dag> pattern>
642 : I<oops, iops, AddrMode3, 4, IndexModeNone, f, itin,
643 opc, asm, "", pattern> {
646 let Inst{27-25} = 0b000;
647 let Inst{24} = 1; // P bit
648 let Inst{23} = addr{8}; // U bit
649 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
650 let Inst{21} = 0; // W bit
651 let Inst{20} = 0; // L bit
652 let Inst{19-16} = addr{12-9}; // Rn
653 let Inst{15-12} = Rt; // Rt
654 let Inst{11-8} = addr{7-4}; // imm7_4/zero
656 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
659 // Pre-indexed stores
660 class AI3sthpr<dag oops, dag iops, Format f, InstrItinClass itin,
661 string opc, string asm, string cstr, list<dag> pattern>
662 : I<oops, iops, AddrMode3, 4, IndexModePre, f, itin,
663 opc, asm, cstr, pattern> {
665 let Inst{5} = 1; // H bit
666 let Inst{6} = 0; // S bit
668 let Inst{20} = 0; // L bit
669 let Inst{21} = 1; // W bit
670 let Inst{24} = 1; // P bit
671 let Inst{27-25} = 0b000;
673 class AI3stdpr<dag oops, dag iops, Format f, InstrItinClass itin,
674 string opc, string asm, string cstr, list<dag> pattern>
675 : I<oops, iops, AddrMode3, 4, IndexModePre, f, itin,
676 opc, asm, cstr, pattern> {
678 let Inst{5} = 1; // H bit
679 let Inst{6} = 1; // S bit
681 let Inst{20} = 0; // L bit
682 let Inst{21} = 1; // W bit
683 let Inst{24} = 1; // P bit
684 let Inst{27-25} = 0b000;
687 // Post-indexed stores
688 class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
689 string opc, string asm, string cstr, list<dag> pattern>
690 : I<oops, iops, AddrMode3, 4, IndexModePost, f, itin,
691 opc, asm, cstr, pattern> {
693 let Inst{5} = 1; // H bit
694 let Inst{6} = 1; // S bit
696 let Inst{20} = 0; // L bit
697 let Inst{21} = 0; // W bit
698 let Inst{24} = 0; // P bit
699 let Inst{27-25} = 0b000;
702 // addrmode4 instructions
703 class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
704 string asm, string cstr, list<dag> pattern>
705 : XI<oops, iops, AddrMode4, 4, im, f, itin, asm, cstr, pattern> {
710 let Inst{27-25} = 0b100;
711 let Inst{22} = 0; // S bit
712 let Inst{19-16} = Rn;
713 let Inst{15-0} = regs;
716 // Unsigned multiply, multiply-accumulate instructions.
717 class AMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
718 string opc, string asm, list<dag> pattern>
719 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
720 opc, asm, "", pattern> {
721 let Inst{7-4} = 0b1001;
722 let Inst{20} = 0; // S bit
723 let Inst{27-21} = opcod;
725 class AsMul1I<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
726 string opc, string asm, list<dag> pattern>
727 : sI<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
728 opc, asm, "", pattern> {
729 let Inst{7-4} = 0b1001;
730 let Inst{27-21} = opcod;
733 // Most significant word multiply
734 class AMul2I<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
735 InstrItinClass itin, string opc, string asm, list<dag> pattern>
736 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
737 opc, asm, "", pattern> {
741 let Inst{7-4} = opc7_4;
743 let Inst{27-21} = opcod;
744 let Inst{19-16} = Rd;
748 // MSW multiple w/ Ra operand
749 class AMul2Ia<bits<7> opcod, bits<4> opc7_4, dag oops, dag iops,
750 InstrItinClass itin, string opc, string asm, list<dag> pattern>
751 : AMul2I<opcod, opc7_4, oops, iops, itin, opc, asm, pattern> {
753 let Inst{15-12} = Ra;
756 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
757 class AMulxyIbase<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
758 InstrItinClass itin, string opc, string asm, list<dag> pattern>
759 : I<oops, iops, AddrModeNone, 4, IndexModeNone, MulFrm, itin,
760 opc, asm, "", pattern> {
766 let Inst{27-21} = opcod;
767 let Inst{6-5} = bit6_5;
771 class AMulxyI<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
772 InstrItinClass itin, string opc, string asm, list<dag> pattern>
773 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
775 let Inst{19-16} = Rd;
778 // AMulxyI with Ra operand
779 class AMulxyIa<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
780 InstrItinClass itin, string opc, string asm, list<dag> pattern>
781 : AMulxyI<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
783 let Inst{15-12} = Ra;
786 class AMulxyI64<bits<7> opcod, bits<2> bit6_5, dag oops, dag iops,
787 InstrItinClass itin, string opc, string asm, list<dag> pattern>
788 : AMulxyIbase<opcod, bit6_5, oops, iops, itin, opc, asm, pattern> {
791 let Inst{19-16} = RdHi;
792 let Inst{15-12} = RdLo;
795 // Extend instructions.
796 class AExtI<bits<8> opcod, dag oops, dag iops, InstrItinClass itin,
797 string opc, string asm, list<dag> pattern>
798 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ExtFrm, itin,
799 opc, asm, "", pattern> {
800 // All AExtI instructions have Rd and Rm register operands.
803 let Inst{15-12} = Rd;
805 let Inst{7-4} = 0b0111;
806 let Inst{9-8} = 0b00;
807 let Inst{27-20} = opcod;
810 // Misc Arithmetic instructions.
811 class AMiscA1I<bits<8> opcod, bits<4> opc7_4, dag oops, dag iops,
812 InstrItinClass itin, string opc, string asm, list<dag> pattern>
813 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
814 opc, asm, "", pattern> {
817 let Inst{27-20} = opcod;
818 let Inst{19-16} = 0b1111;
819 let Inst{15-12} = Rd;
820 let Inst{11-8} = 0b1111;
821 let Inst{7-4} = opc7_4;
826 def PKHLSLAsmOperand : AsmOperandClass {
827 let Name = "PKHLSLImm";
828 let ParserMethod = "parsePKHLSLImm";
830 def pkh_lsl_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 32; }]>{
831 let PrintMethod = "printPKHLSLShiftImm";
832 let ParserMatchClass = PKHLSLAsmOperand;
834 def PKHASRAsmOperand : AsmOperandClass {
835 let Name = "PKHASRImm";
836 let ParserMethod = "parsePKHASRImm";
838 def pkh_asr_amt: Operand<i32>, ImmLeaf<i32, [{ return Imm > 0 && Imm <= 32; }]>{
839 let PrintMethod = "printPKHASRShiftImm";
840 let ParserMatchClass = PKHASRAsmOperand;
843 class APKHI<bits<8> opcod, bit tb, dag oops, dag iops, InstrItinClass itin,
844 string opc, string asm, list<dag> pattern>
845 : I<oops, iops, AddrModeNone, 4, IndexModeNone, ArithMiscFrm, itin,
846 opc, asm, "", pattern> {
851 let Inst{27-20} = opcod;
852 let Inst{19-16} = Rn;
853 let Inst{15-12} = Rd;
856 let Inst{5-4} = 0b01;
860 //===----------------------------------------------------------------------===//
862 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
863 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
864 list<Predicate> Predicates = [IsARM];
866 class ARMV5TPat<dag pattern, dag result> : Pat<pattern, result> {
867 list<Predicate> Predicates = [IsARM, HasV5T];
869 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
870 list<Predicate> Predicates = [IsARM, HasV5TE];
872 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
873 list<Predicate> Predicates = [IsARM, HasV6];
876 //===----------------------------------------------------------------------===//
877 // Thumb Instruction Format Definitions.
880 class ThumbI<dag oops, dag iops, AddrMode am, int sz,
881 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
882 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
883 let OutOperandList = oops;
884 let InOperandList = iops;
886 let Pattern = pattern;
887 list<Predicate> Predicates = [IsThumb];
890 // TI - Thumb instruction.
891 class TI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
892 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
894 // Two-address instructions
895 class TIt<dag oops, dag iops, InstrItinClass itin, string asm,
897 : ThumbI<oops, iops, AddrModeNone, 2, itin, asm, "$lhs = $dst",
900 // tBL, tBX 32-bit instructions
901 class TIx2<bits<5> opcod1, bits<2> opcod2, bit opcod3,
902 dag oops, dag iops, InstrItinClass itin, string asm,
904 : ThumbI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>,
906 let Inst{31-27} = opcod1;
907 let Inst{15-14} = opcod2;
908 let Inst{12} = opcod3;
911 // BR_JT instructions
912 class TJTI<dag oops, dag iops, InstrItinClass itin, string asm,
914 : ThumbI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
917 class Thumb1I<dag oops, dag iops, AddrMode am, int sz,
918 InstrItinClass itin, string asm, string cstr, list<dag> pattern>
919 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
920 let OutOperandList = oops;
921 let InOperandList = iops;
923 let Pattern = pattern;
924 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
927 class T1I<dag oops, dag iops, InstrItinClass itin,
928 string asm, list<dag> pattern>
929 : Thumb1I<oops, iops, AddrModeNone, 2, itin, asm, "", pattern>;
930 class T1Ix2<dag oops, dag iops, InstrItinClass itin,
931 string asm, list<dag> pattern>
932 : Thumb1I<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
934 // Two-address instructions
935 class T1It<dag oops, dag iops, InstrItinClass itin,
936 string asm, string cstr, list<dag> pattern>
937 : Thumb1I<oops, iops, AddrModeNone, 2, itin,
940 // Thumb1 instruction that can either be predicated or set CPSR.
941 class Thumb1sI<dag oops, dag iops, AddrMode am, int sz,
943 string opc, string asm, string cstr, list<dag> pattern>
944 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
945 let OutOperandList = !con(oops, (outs s_cc_out:$s));
946 let InOperandList = !con(iops, (ins pred:$p));
947 let AsmString = !strconcat(opc, "${s}${p}", asm);
948 let Pattern = pattern;
949 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
952 class T1sI<dag oops, dag iops, InstrItinClass itin,
953 string opc, string asm, list<dag> pattern>
954 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
956 // Two-address instructions
957 class T1sIt<dag oops, dag iops, InstrItinClass itin,
958 string opc, string asm, list<dag> pattern>
959 : Thumb1sI<oops, iops, AddrModeNone, 2, itin, opc, asm,
960 "$Rn = $Rdn", pattern>;
962 // Thumb1 instruction that can be predicated.
963 class Thumb1pI<dag oops, dag iops, AddrMode am, int sz,
965 string opc, string asm, string cstr, list<dag> pattern>
966 : InstThumb<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
967 let OutOperandList = oops;
968 let InOperandList = !con(iops, (ins pred:$p));
969 let AsmString = !strconcat(opc, "${p}", asm);
970 let Pattern = pattern;
971 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
974 class T1pI<dag oops, dag iops, InstrItinClass itin,
975 string opc, string asm, list<dag> pattern>
976 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm, "", pattern>;
978 // Two-address instructions
979 class T1pIt<dag oops, dag iops, InstrItinClass itin,
980 string opc, string asm, list<dag> pattern>
981 : Thumb1pI<oops, iops, AddrModeNone, 2, itin, opc, asm,
982 "$Rn = $Rdn", pattern>;
984 class T1pIs<dag oops, dag iops,
985 InstrItinClass itin, string opc, string asm, list<dag> pattern>
986 : Thumb1pI<oops, iops, AddrModeT1_s, 2, itin, opc, asm, "", pattern>;
988 class Encoding16 : Encoding {
989 let Inst{31-16} = 0x0000;
992 // A6.2 16-bit Thumb instruction encoding
993 class T1Encoding<bits<6> opcode> : Encoding16 {
994 let Inst{15-10} = opcode;
997 // A6.2.1 Shift (immediate), add, subtract, move, and compare encoding.
998 class T1General<bits<5> opcode> : Encoding16 {
999 let Inst{15-14} = 0b00;
1000 let Inst{13-9} = opcode;
1003 // A6.2.2 Data-processing encoding.
1004 class T1DataProcessing<bits<4> opcode> : Encoding16 {
1005 let Inst{15-10} = 0b010000;
1006 let Inst{9-6} = opcode;
1009 // A6.2.3 Special data instructions and branch and exchange encoding.
1010 class T1Special<bits<4> opcode> : Encoding16 {
1011 let Inst{15-10} = 0b010001;
1012 let Inst{9-6} = opcode;
1015 // A6.2.4 Load/store single data item encoding.
1016 class T1LoadStore<bits<4> opA, bits<3> opB> : Encoding16 {
1017 let Inst{15-12} = opA;
1018 let Inst{11-9} = opB;
1020 class T1LdStSP<bits<3> opB> : T1LoadStore<0b1001, opB>; // SP relative
1022 class T1BranchCond<bits<4> opcode> : Encoding16 {
1023 let Inst{15-12} = opcode;
1026 // Helper classes to encode Thumb1 loads and stores. For immediates, the
1027 // following bits are used for "opA" (see A6.2.4):
1029 // 0b0110 => Immediate, 4 bytes
1030 // 0b1000 => Immediate, 2 bytes
1031 // 0b0111 => Immediate, 1 byte
1032 class T1pILdStEncode<bits<3> opcode, dag oops, dag iops, AddrMode am,
1033 InstrItinClass itin, string opc, string asm,
1035 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1036 T1LoadStore<0b0101, opcode> {
1039 let Inst{8-6} = addr{5-3}; // Rm
1040 let Inst{5-3} = addr{2-0}; // Rn
1043 class T1pILdStEncodeImm<bits<4> opA, bit opB, dag oops, dag iops, AddrMode am,
1044 InstrItinClass itin, string opc, string asm,
1046 : Thumb1pI<oops, iops, am, 2, itin, opc, asm, "", pattern>,
1047 T1LoadStore<opA, {opB,?,?}> {
1050 let Inst{10-6} = addr{7-3}; // imm5
1051 let Inst{5-3} = addr{2-0}; // Rn
1055 // A6.2.5 Miscellaneous 16-bit instructions encoding.
1056 class T1Misc<bits<7> opcode> : Encoding16 {
1057 let Inst{15-12} = 0b1011;
1058 let Inst{11-5} = opcode;
1061 // Thumb2I - Thumb2 instruction. Almost all Thumb2 instructions are predicable.
1062 class Thumb2I<dag oops, dag iops, AddrMode am, int sz,
1063 InstrItinClass itin,
1064 string opc, string asm, string cstr, list<dag> pattern>
1065 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1066 let OutOperandList = oops;
1067 let InOperandList = !con(iops, (ins pred:$p));
1068 let AsmString = !strconcat(opc, "${p}", asm);
1069 let Pattern = pattern;
1070 list<Predicate> Predicates = [IsThumb2];
1071 let DecoderNamespace = "Thumb2";
1074 // Same as Thumb2I except it can optionally modify CPSR. Note it's modeled as an
1075 // input operand since by default it's a zero register. It will become an
1076 // implicit def once it's "flipped".
1078 // FIXME: This uses unified syntax so {s} comes before {p}. We should make it
1080 class Thumb2sI<dag oops, dag iops, AddrMode am, int sz,
1081 InstrItinClass itin,
1082 string opc, string asm, string cstr, list<dag> pattern>
1083 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1084 bits<1> s; // condition-code set flag ('1' if the insn should set the flags)
1087 let OutOperandList = oops;
1088 let InOperandList = !con(iops, (ins pred:$p, cc_out:$s));
1089 let AsmString = !strconcat(opc, "${s}${p}", asm);
1090 let Pattern = pattern;
1091 list<Predicate> Predicates = [IsThumb2];
1092 let DecoderNamespace = "Thumb2";
1096 class Thumb2XI<dag oops, dag iops, AddrMode am, int sz,
1097 InstrItinClass itin,
1098 string asm, string cstr, list<dag> pattern>
1099 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1100 let OutOperandList = oops;
1101 let InOperandList = iops;
1102 let AsmString = asm;
1103 let Pattern = pattern;
1104 list<Predicate> Predicates = [IsThumb2];
1105 let DecoderNamespace = "Thumb2";
1108 class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
1109 InstrItinClass itin,
1110 string asm, string cstr, list<dag> pattern>
1111 : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
1112 let OutOperandList = oops;
1113 let InOperandList = iops;
1114 let AsmString = asm;
1115 let Pattern = pattern;
1116 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1117 let DecoderNamespace = "Thumb";
1120 class T2I<dag oops, dag iops, InstrItinClass itin,
1121 string opc, string asm, list<dag> pattern>
1122 : Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1123 class T2Ii12<dag oops, dag iops, InstrItinClass itin,
1124 string opc, string asm, list<dag> pattern>
1125 : Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;
1126 class T2Ii8<dag oops, dag iops, InstrItinClass itin,
1127 string opc, string asm, list<dag> pattern>
1128 : Thumb2I<oops, iops, AddrModeT2_i8, 4, itin, opc, asm, "", pattern>;
1129 class T2Iso<dag oops, dag iops, InstrItinClass itin,
1130 string opc, string asm, list<dag> pattern>
1131 : Thumb2I<oops, iops, AddrModeT2_so, 4, itin, opc, asm, "", pattern>;
1132 class T2Ipc<dag oops, dag iops, InstrItinClass itin,
1133 string opc, string asm, list<dag> pattern>
1134 : Thumb2I<oops, iops, AddrModeT2_pc, 4, itin, opc, asm, "", pattern>;
1135 class T2Ii8s4<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1136 string opc, string asm, list<dag> pattern>
1137 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, "",
1142 let Inst{31-25} = 0b1110100;
1144 let Inst{23} = addr{8};
1147 let Inst{20} = isLoad;
1148 let Inst{19-16} = addr{12-9};
1149 let Inst{15-12} = Rt{3-0};
1150 let Inst{11-8} = Rt2{3-0};
1151 let Inst{7-0} = addr{7-0};
1154 class T2Ii8s4Tied<bit P, bit W, bit isLoad, dag oops, dag iops, InstrItinClass itin,
1155 string opc, string asm, list<dag> pattern>
1156 : Thumb2I<oops, iops, AddrModeT2_i8s4, 4, itin, opc, asm, "$base = $wb",
1162 let Inst{31-25} = 0b1110100;
1164 let Inst{23} = imm{8};
1167 let Inst{20} = isLoad;
1168 let Inst{19-16} = base{3-0};
1169 let Inst{15-12} = Rt{3-0};
1170 let Inst{11-8} = Rt2{3-0};
1171 let Inst{7-0} = imm{7-0};
1175 class T2sI<dag oops, dag iops, InstrItinClass itin,
1176 string opc, string asm, list<dag> pattern>
1177 : Thumb2sI<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
1179 class T2XI<dag oops, dag iops, InstrItinClass itin,
1180 string asm, list<dag> pattern>
1181 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, "", pattern>;
1182 class T2JTI<dag oops, dag iops, InstrItinClass itin,
1183 string asm, list<dag> pattern>
1184 : Thumb2XI<oops, iops, AddrModeNone, 0, itin, asm, "", pattern>;
1186 // Move to/from coprocessor instructions
1187 class T2Cop<bits<4> opc, dag oops, dag iops, string asm, list<dag> pattern>
1188 : T2XI <oops, iops, NoItinerary, asm, pattern>, Requires<[IsThumb2]> {
1189 let Inst{31-28} = opc;
1192 // Two-address instructions
1193 class T2XIt<dag oops, dag iops, InstrItinClass itin,
1194 string asm, string cstr, list<dag> pattern>
1195 : Thumb2XI<oops, iops, AddrModeNone, 4, itin, asm, cstr, pattern>;
1197 // T2Iidxldst - Thumb2 indexed load / store instructions.
1198 class T2Iidxldst<bit signed, bits<2> opcod, bit load, bit pre,
1200 AddrMode am, IndexMode im, InstrItinClass itin,
1201 string opc, string asm, string cstr, list<dag> pattern>
1202 : InstARM<am, 4, im, ThumbFrm, GenericDomain, cstr, itin> {
1203 let OutOperandList = oops;
1204 let InOperandList = !con(iops, (ins pred:$p));
1205 let AsmString = !strconcat(opc, "${p}", asm);
1206 let Pattern = pattern;
1207 list<Predicate> Predicates = [IsThumb2];
1208 let DecoderNamespace = "Thumb2";
1209 let Inst{31-27} = 0b11111;
1210 let Inst{26-25} = 0b00;
1211 let Inst{24} = signed;
1213 let Inst{22-21} = opcod;
1214 let Inst{20} = load;
1216 // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed
1217 let Inst{10} = pre; // The P bit.
1218 let Inst{8} = 1; // The W bit.
1221 let Inst{7-0} = addr{7-0};
1222 let Inst{9} = addr{8}; // Sign bit
1226 let Inst{15-12} = Rt{3-0};
1227 let Inst{19-16} = Rn{3-0};
1230 // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode.
1231 class Tv5Pat<dag pattern, dag result> : Pat<pattern, result> {
1232 list<Predicate> Predicates = [IsThumb, IsThumb1Only, HasV5T];
1235 // T1Pat - Same as Pat<>, but requires that the compiler be in Thumb1 mode.
1236 class T1Pat<dag pattern, dag result> : Pat<pattern, result> {
1237 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
1240 // T2v6Pat - Same as Pat<>, but requires V6T2 Thumb2 mode.
1241 class T2v6Pat<dag pattern, dag result> : Pat<pattern, result> {
1242 list<Predicate> Predicates = [IsThumb2, HasV6T2];
1245 // T2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
1246 class T2Pat<dag pattern, dag result> : Pat<pattern, result> {
1247 list<Predicate> Predicates = [IsThumb2];
1250 //===----------------------------------------------------------------------===//
1252 //===----------------------------------------------------------------------===//
1253 // ARM VFP Instruction templates.
1256 // Almost all VFP instructions are predicable.
1257 class VFPI<dag oops, dag iops, AddrMode am, int sz,
1258 IndexMode im, Format f, InstrItinClass itin,
1259 string opc, string asm, string cstr, list<dag> pattern>
1260 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1262 let Inst{31-28} = p;
1263 let OutOperandList = oops;
1264 let InOperandList = !con(iops, (ins pred:$p));
1265 let AsmString = !strconcat(opc, "${p}", asm);
1266 let Pattern = pattern;
1267 let PostEncoderMethod = "VFPThumb2PostEncoder";
1268 list<Predicate> Predicates = [HasVFP2];
1272 class VFPXI<dag oops, dag iops, AddrMode am, int sz,
1273 IndexMode im, Format f, InstrItinClass itin,
1274 string asm, string cstr, list<dag> pattern>
1275 : InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
1277 let Inst{31-28} = p;
1278 let OutOperandList = oops;
1279 let InOperandList = iops;
1280 let AsmString = asm;
1281 let Pattern = pattern;
1282 let PostEncoderMethod = "VFPThumb2PostEncoder";
1283 list<Predicate> Predicates = [HasVFP2];
1286 class VFPAI<dag oops, dag iops, Format f, InstrItinClass itin,
1287 string opc, string asm, list<dag> pattern>
1288 : VFPI<oops, iops, AddrModeNone, 4, IndexModeNone, f, itin,
1289 opc, asm, "", pattern> {
1290 let PostEncoderMethod = "VFPThumb2PostEncoder";
1293 // ARM VFP addrmode5 loads and stores
1294 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1295 InstrItinClass itin,
1296 string opc, string asm, list<dag> pattern>
1297 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1298 VFPLdStFrm, itin, opc, asm, "", pattern> {
1299 // Instruction operands.
1303 // Encode instruction operands.
1304 let Inst{23} = addr{8}; // U (add = (U == '1'))
1305 let Inst{22} = Dd{4};
1306 let Inst{19-16} = addr{12-9}; // Rn
1307 let Inst{15-12} = Dd{3-0};
1308 let Inst{7-0} = addr{7-0}; // imm8
1310 // TODO: Mark the instructions with the appropriate subtarget info.
1311 let Inst{27-24} = opcod1;
1312 let Inst{21-20} = opcod2;
1313 let Inst{11-9} = 0b101;
1314 let Inst{8} = 1; // Double precision
1316 // Loads & stores operate on both NEON and VFP pipelines.
1317 let D = VFPNeonDomain;
1320 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
1321 InstrItinClass itin,
1322 string opc, string asm, list<dag> pattern>
1323 : VFPI<oops, iops, AddrMode5, 4, IndexModeNone,
1324 VFPLdStFrm, itin, opc, asm, "", pattern> {
1325 // Instruction operands.
1329 // Encode instruction operands.
1330 let Inst{23} = addr{8}; // U (add = (U == '1'))
1331 let Inst{22} = Sd{0};
1332 let Inst{19-16} = addr{12-9}; // Rn
1333 let Inst{15-12} = Sd{4-1};
1334 let Inst{7-0} = addr{7-0}; // imm8
1336 // TODO: Mark the instructions with the appropriate subtarget info.
1337 let Inst{27-24} = opcod1;
1338 let Inst{21-20} = opcod2;
1339 let Inst{11-9} = 0b101;
1340 let Inst{8} = 0; // Single precision
1342 // Loads & stores operate on both NEON and VFP pipelines.
1343 let D = VFPNeonDomain;
1346 // VFP Load / store multiple pseudo instructions.
1347 class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
1349 : InstARM<AddrMode4, 4, IndexModeNone, Pseudo, VFPNeonDomain,
1351 let OutOperandList = oops;
1352 let InOperandList = !con(iops, (ins pred:$p));
1353 let Pattern = pattern;
1354 list<Predicate> Predicates = [HasVFP2];
1357 // Load / store multiple
1358 class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1359 string asm, string cstr, list<dag> pattern>
1360 : VFPXI<oops, iops, AddrMode4, 4, im,
1361 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1362 // Instruction operands.
1366 // Encode instruction operands.
1367 let Inst{19-16} = Rn;
1368 let Inst{22} = regs{12};
1369 let Inst{15-12} = regs{11-8};
1370 let Inst{7-0} = regs{7-0};
1372 // TODO: Mark the instructions with the appropriate subtarget info.
1373 let Inst{27-25} = 0b110;
1374 let Inst{11-9} = 0b101;
1375 let Inst{8} = 1; // Double precision
1378 class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
1379 string asm, string cstr, list<dag> pattern>
1380 : VFPXI<oops, iops, AddrMode4, 4, im,
1381 VFPLdStMulFrm, itin, asm, cstr, pattern> {
1382 // Instruction operands.
1386 // Encode instruction operands.
1387 let Inst{19-16} = Rn;
1388 let Inst{22} = regs{8};
1389 let Inst{15-12} = regs{12-9};
1390 let Inst{7-0} = regs{7-0};
1392 // TODO: Mark the instructions with the appropriate subtarget info.
1393 let Inst{27-25} = 0b110;
1394 let Inst{11-9} = 0b101;
1395 let Inst{8} = 0; // Single precision
1398 // Double precision, unary
1399 class ADuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1400 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1401 string asm, list<dag> pattern>
1402 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1403 // Instruction operands.
1407 // Encode instruction operands.
1408 let Inst{3-0} = Dm{3-0};
1409 let Inst{5} = Dm{4};
1410 let Inst{15-12} = Dd{3-0};
1411 let Inst{22} = Dd{4};
1413 let Inst{27-23} = opcod1;
1414 let Inst{21-20} = opcod2;
1415 let Inst{19-16} = opcod3;
1416 let Inst{11-9} = 0b101;
1417 let Inst{8} = 1; // Double precision
1418 let Inst{7-6} = opcod4;
1419 let Inst{4} = opcod5;
1422 // Double precision, binary
1423 class ADbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1424 dag iops, InstrItinClass itin, string opc, string asm,
1426 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1427 // Instruction operands.
1432 // Encode instruction operands.
1433 let Inst{3-0} = Dm{3-0};
1434 let Inst{5} = Dm{4};
1435 let Inst{19-16} = Dn{3-0};
1436 let Inst{7} = Dn{4};
1437 let Inst{15-12} = Dd{3-0};
1438 let Inst{22} = Dd{4};
1440 let Inst{27-23} = opcod1;
1441 let Inst{21-20} = opcod2;
1442 let Inst{11-9} = 0b101;
1443 let Inst{8} = 1; // Double precision
1448 // Single precision, unary
1449 class ASuI<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1450 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1451 string asm, list<dag> pattern>
1452 : VFPAI<oops, iops, VFPUnaryFrm, itin, opc, asm, pattern> {
1453 // Instruction operands.
1457 // Encode instruction operands.
1458 let Inst{3-0} = Sm{4-1};
1459 let Inst{5} = Sm{0};
1460 let Inst{15-12} = Sd{4-1};
1461 let Inst{22} = Sd{0};
1463 let Inst{27-23} = opcod1;
1464 let Inst{21-20} = opcod2;
1465 let Inst{19-16} = opcod3;
1466 let Inst{11-9} = 0b101;
1467 let Inst{8} = 0; // Single precision
1468 let Inst{7-6} = opcod4;
1469 let Inst{4} = opcod5;
1472 // Single precision unary, if no NEON. Same as ASuI except not available if
1474 class ASuIn<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<2> opcod4,
1475 bit opcod5, dag oops, dag iops, InstrItinClass itin, string opc,
1476 string asm, list<dag> pattern>
1477 : ASuI<opcod1, opcod2, opcod3, opcod4, opcod5, oops, iops, itin, opc, asm,
1479 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1482 // Single precision, binary
1483 class ASbI<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops, dag iops,
1484 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1485 : VFPAI<oops, iops, VFPBinaryFrm, itin, opc, asm, pattern> {
1486 // Instruction operands.
1491 // Encode instruction operands.
1492 let Inst{3-0} = Sm{4-1};
1493 let Inst{5} = Sm{0};
1494 let Inst{19-16} = Sn{4-1};
1495 let Inst{7} = Sn{0};
1496 let Inst{15-12} = Sd{4-1};
1497 let Inst{22} = Sd{0};
1499 let Inst{27-23} = opcod1;
1500 let Inst{21-20} = opcod2;
1501 let Inst{11-9} = 0b101;
1502 let Inst{8} = 0; // Single precision
1507 // Single precision binary, if no NEON. Same as ASbI except not available if
1509 class ASbIn<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
1510 dag iops, InstrItinClass itin, string opc, string asm,
1512 : ASbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
1513 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1515 // Instruction operands.
1520 // Encode instruction operands.
1521 let Inst{3-0} = Sm{4-1};
1522 let Inst{5} = Sm{0};
1523 let Inst{19-16} = Sn{4-1};
1524 let Inst{7} = Sn{0};
1525 let Inst{15-12} = Sd{4-1};
1526 let Inst{22} = Sd{0};
1529 // VFP conversion instructions
1530 class AVConv1I<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1531 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1533 : VFPAI<oops, iops, VFPConv1Frm, itin, opc, asm, pattern> {
1534 let Inst{27-23} = opcod1;
1535 let Inst{21-20} = opcod2;
1536 let Inst{19-16} = opcod3;
1537 let Inst{11-8} = opcod4;
1542 // VFP conversion between floating-point and fixed-point
1543 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
1544 dag oops, dag iops, InstrItinClass itin, string opc, string asm,
1546 : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
1547 // size (fixed-point number): sx == 0 ? 16 : 32
1548 let Inst{7} = op5; // sx
1551 // VFP conversion instructions, if no NEON
1552 class AVConv1In<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3, bits<4> opcod4,
1553 dag oops, dag iops, InstrItinClass itin,
1554 string opc, string asm, list<dag> pattern>
1555 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1557 list<Predicate> Predicates = [HasVFP2,DontUseNEONForFP];
1560 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
1561 InstrItinClass itin,
1562 string opc, string asm, list<dag> pattern>
1563 : VFPAI<oops, iops, f, itin, opc, asm, pattern> {
1564 let Inst{27-20} = opcod1;
1565 let Inst{11-8} = opcod2;
1569 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1570 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1571 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, itin, opc, asm, pattern>;
1573 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1574 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1575 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, itin, opc, asm, pattern>;
1577 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1578 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1579 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, itin, opc, asm, pattern>;
1581 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
1582 InstrItinClass itin, string opc, string asm, list<dag> pattern>
1583 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, itin, opc, asm, pattern>;
1585 //===----------------------------------------------------------------------===//
1587 //===----------------------------------------------------------------------===//
1588 // ARM NEON Instruction templates.
1591 class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1592 InstrItinClass itin, string opc, string dt, string asm, string cstr,
1594 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1595 let OutOperandList = oops;
1596 let InOperandList = !con(iops, (ins pred:$p));
1597 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1598 let Pattern = pattern;
1599 list<Predicate> Predicates = [HasNEON];
1602 // Same as NeonI except it does not have a "data type" specifier.
1603 class NeonXI<dag oops, dag iops, AddrMode am, IndexMode im, Format f,
1604 InstrItinClass itin, string opc, string asm, string cstr,
1606 : InstARM<am, 4, im, f, NeonDomain, cstr, itin> {
1607 let OutOperandList = oops;
1608 let InOperandList = !con(iops, (ins pred:$p));
1609 let AsmString = !strconcat(opc, "${p}", "\t", asm);
1610 let Pattern = pattern;
1611 list<Predicate> Predicates = [HasNEON];
1614 class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1615 dag oops, dag iops, InstrItinClass itin,
1616 string opc, string dt, string asm, string cstr, list<dag> pattern>
1617 : NeonI<oops, iops, AddrMode6, IndexModeNone, NLdStFrm, itin, opc, dt, asm,
1619 let Inst{31-24} = 0b11110100;
1620 let Inst{23} = op23;
1621 let Inst{21-20} = op21_20;
1622 let Inst{11-8} = op11_8;
1623 let Inst{7-4} = op7_4;
1625 let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder";
1631 let Inst{22} = Vd{4};
1632 let Inst{15-12} = Vd{3-0};
1633 let Inst{19-16} = Rn{3-0};
1634 let Inst{3-0} = Rm{3-0};
1637 class NLdStLn<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
1638 dag oops, dag iops, InstrItinClass itin,
1639 string opc, string dt, string asm, string cstr, list<dag> pattern>
1640 : NLdSt<op23, op21_20, op11_8, op7_4, oops, iops, itin, opc,
1641 dt, asm, cstr, pattern> {
1645 class PseudoNLdSt<dag oops, dag iops, InstrItinClass itin, string cstr>
1646 : InstARM<AddrMode6, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1648 let OutOperandList = oops;
1649 let InOperandList = !con(iops, (ins pred:$p));
1650 list<Predicate> Predicates = [HasNEON];
1653 class PseudoNeonI<dag oops, dag iops, InstrItinClass itin, string cstr,
1655 : InstARM<AddrModeNone, 4, IndexModeNone, Pseudo, NeonDomain, cstr,
1657 let OutOperandList = oops;
1658 let InOperandList = !con(iops, (ins pred:$p));
1659 let Pattern = pattern;
1660 list<Predicate> Predicates = [HasNEON];
1663 class NDataI<dag oops, dag iops, Format f, InstrItinClass itin,
1664 string opc, string dt, string asm, string cstr, list<dag> pattern>
1665 : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr,
1667 let Inst{31-25} = 0b1111001;
1668 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1671 class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin,
1672 string opc, string asm, string cstr, list<dag> pattern>
1673 : NeonXI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, asm,
1675 let Inst{31-25} = 0b1111001;
1676 let PostEncoderMethod = "NEONThumb2DataIPostEncoder";
1679 // NEON "one register and a modified immediate" format.
1680 class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
1682 dag oops, dag iops, InstrItinClass itin,
1683 string opc, string dt, string asm, string cstr,
1685 : NDataI<oops, iops, N1RegModImmFrm, itin, opc, dt, asm, cstr, pattern> {
1686 let Inst{23} = op23;
1687 let Inst{21-19} = op21_19;
1688 let Inst{11-8} = op11_8;
1694 // Instruction operands.
1698 let Inst{15-12} = Vd{3-0};
1699 let Inst{22} = Vd{4};
1700 let Inst{24} = SIMM{7};
1701 let Inst{18-16} = SIMM{6-4};
1702 let Inst{3-0} = SIMM{3-0};
1705 // NEON 2 vector register format.
1706 class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1707 bits<5> op11_7, bit op6, bit op4,
1708 dag oops, dag iops, InstrItinClass itin,
1709 string opc, string dt, string asm, string cstr, list<dag> pattern>
1710 : NDataI<oops, iops, N2RegFrm, itin, opc, dt, asm, cstr, pattern> {
1711 let Inst{24-23} = op24_23;
1712 let Inst{21-20} = op21_20;
1713 let Inst{19-18} = op19_18;
1714 let Inst{17-16} = op17_16;
1715 let Inst{11-7} = op11_7;
1719 // Instruction operands.
1723 let Inst{15-12} = Vd{3-0};
1724 let Inst{22} = Vd{4};
1725 let Inst{3-0} = Vm{3-0};
1726 let Inst{5} = Vm{4};
1729 // Same as N2V except it doesn't have a datatype suffix.
1730 class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
1731 bits<5> op11_7, bit op6, bit op4,
1732 dag oops, dag iops, InstrItinClass itin,
1733 string opc, string asm, string cstr, list<dag> pattern>
1734 : NDataXI<oops, iops, N2RegFrm, itin, opc, asm, cstr, pattern> {
1735 let Inst{24-23} = op24_23;
1736 let Inst{21-20} = op21_20;
1737 let Inst{19-18} = op19_18;
1738 let Inst{17-16} = op17_16;
1739 let Inst{11-7} = op11_7;
1743 // Instruction operands.
1747 let Inst{15-12} = Vd{3-0};
1748 let Inst{22} = Vd{4};
1749 let Inst{3-0} = Vm{3-0};
1750 let Inst{5} = Vm{4};
1753 // NEON 2 vector register with immediate.
1754 class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
1755 dag oops, dag iops, Format f, InstrItinClass itin,
1756 string opc, string dt, string asm, string cstr, list<dag> pattern>
1757 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1758 let Inst{24} = op24;
1759 let Inst{23} = op23;
1760 let Inst{11-8} = op11_8;
1765 // Instruction operands.
1770 let Inst{15-12} = Vd{3-0};
1771 let Inst{22} = Vd{4};
1772 let Inst{3-0} = Vm{3-0};
1773 let Inst{5} = Vm{4};
1774 let Inst{21-16} = SIMM{5-0};
1777 // NEON 3 vector register format.
1779 class N3VCommon<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1780 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1781 string opc, string dt, string asm, string cstr,
1783 : NDataI<oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1784 let Inst{24} = op24;
1785 let Inst{23} = op23;
1786 let Inst{21-20} = op21_20;
1787 let Inst{11-8} = op11_8;
1792 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
1793 dag oops, dag iops, Format f, InstrItinClass itin,
1794 string opc, string dt, string asm, string cstr, list<dag> pattern>
1795 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1796 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1798 // Instruction operands.
1803 let Inst{15-12} = Vd{3-0};
1804 let Inst{22} = Vd{4};
1805 let Inst{19-16} = Vn{3-0};
1806 let Inst{7} = Vn{4};
1807 let Inst{3-0} = Vm{3-0};
1808 let Inst{5} = Vm{4};
1811 class N3VLane32<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1812 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1813 string opc, string dt, string asm, string cstr,
1815 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1816 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1818 // Instruction operands.
1824 let Inst{15-12} = Vd{3-0};
1825 let Inst{22} = Vd{4};
1826 let Inst{19-16} = Vn{3-0};
1827 let Inst{7} = Vn{4};
1828 let Inst{3-0} = Vm{3-0};
1832 class N3VLane16<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1833 bit op4, dag oops, dag iops, Format f, InstrItinClass itin,
1834 string opc, string dt, string asm, string cstr,
1836 : N3VCommon<op24, op23, op21_20, op11_8, op6, op4,
1837 oops, iops, f, itin, opc, dt, asm, cstr, pattern> {
1839 // Instruction operands.
1845 let Inst{15-12} = Vd{3-0};
1846 let Inst{22} = Vd{4};
1847 let Inst{19-16} = Vn{3-0};
1848 let Inst{7} = Vn{4};
1849 let Inst{2-0} = Vm{2-0};
1850 let Inst{5} = lane{1};
1851 let Inst{3} = lane{0};
1854 // Same as N3V except it doesn't have a data type suffix.
1855 class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
1857 dag oops, dag iops, Format f, InstrItinClass itin,
1858 string opc, string asm, string cstr, list<dag> pattern>
1859 : NDataXI<oops, iops, f, itin, opc, asm, cstr, pattern> {
1860 let Inst{24} = op24;
1861 let Inst{23} = op23;
1862 let Inst{21-20} = op21_20;
1863 let Inst{11-8} = op11_8;
1867 // Instruction operands.
1872 let Inst{15-12} = Vd{3-0};
1873 let Inst{22} = Vd{4};
1874 let Inst{19-16} = Vn{3-0};
1875 let Inst{7} = Vn{4};
1876 let Inst{3-0} = Vm{3-0};
1877 let Inst{5} = Vm{4};
1880 // NEON VMOVs between scalar and core registers.
1881 class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1882 dag oops, dag iops, Format f, InstrItinClass itin,
1883 string opc, string dt, string asm, list<dag> pattern>
1884 : InstARM<AddrModeNone, 4, IndexModeNone, f, NeonDomain,
1886 let Inst{27-20} = opcod1;
1887 let Inst{11-8} = opcod2;
1888 let Inst{6-5} = opcod3;
1890 // A8.6.303, A8.6.328, A8.6.329
1891 let Inst{3-0} = 0b0000;
1893 let OutOperandList = oops;
1894 let InOperandList = !con(iops, (ins pred:$p));
1895 let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);
1896 let Pattern = pattern;
1897 list<Predicate> Predicates = [HasNEON];
1899 let PostEncoderMethod = "NEONThumb2DupPostEncoder";
1906 let Inst{31-28} = p{3-0};
1908 let Inst{19-16} = V{3-0};
1909 let Inst{15-12} = R{3-0};
1911 class NVGetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1912 dag oops, dag iops, InstrItinClass itin,
1913 string opc, string dt, string asm, list<dag> pattern>
1914 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NGetLnFrm, itin,
1915 opc, dt, asm, pattern>;
1916 class NVSetLane<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1917 dag oops, dag iops, InstrItinClass itin,
1918 string opc, string dt, string asm, list<dag> pattern>
1919 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NSetLnFrm, itin,
1920 opc, dt, asm, pattern>;
1921 class NVDup<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3,
1922 dag oops, dag iops, InstrItinClass itin,
1923 string opc, string dt, string asm, list<dag> pattern>
1924 : NVLaneOp<opcod1, opcod2, opcod3, oops, iops, NDupFrm, itin,
1925 opc, dt, asm, pattern>;
1927 // Vector Duplicate Lane (from scalar to all elements)
1928 class NVDupLane<bits<4> op19_16, bit op6, dag oops, dag iops,
1929 InstrItinClass itin, string opc, string dt, string asm,
1931 : NDataI<oops, iops, NVDupLnFrm, itin, opc, dt, asm, "", pattern> {
1932 let Inst{24-23} = 0b11;
1933 let Inst{21-20} = 0b11;
1934 let Inst{19-16} = op19_16;
1935 let Inst{11-7} = 0b11000;
1943 let Inst{22} = Vd{4};
1944 let Inst{15-12} = Vd{3-0};
1945 let Inst{5} = Vm{4};
1946 let Inst{3-0} = Vm{3-0};
1949 // NEONFPPat - Same as Pat<>, but requires that the compiler be using NEON
1950 // for single-precision FP.
1951 class NEONFPPat<dag pattern, dag result> : Pat<pattern, result> {
1952 list<Predicate> Predicates = [HasNEON,UseNEONForFP];