1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<1>;
23 def MulFrm : Format<2>;
24 def BrFrm : Format<3>;
25 def BrMiscFrm : Format<4>;
27 def DPFrm : Format<5>;
28 def DPSoRegFrm : Format<6>;
30 def LdFrm : Format<7>;
31 def StFrm : Format<8>;
32 def LdMiscFrm : Format<9>;
33 def StMiscFrm : Format<10>;
34 def LdMulFrm : Format<11>;
35 def StMulFrm : Format<12>;
37 def ArithMiscFrm : Format<13>;
38 def ExtFrm : Format<14>;
40 def VFPUnaryFrm : Format<15>;
41 def VFPBinaryFrm : Format<16>;
42 def VFPConv1Frm : Format<17>;
43 def VFPConv2Frm : Format<18>;
44 def VFPConv3Frm : Format<19>;
45 def VFPConv4Frm : Format<20>;
46 def VFPConv5Frm : Format<21>;
47 def VFPLdStFrm : Format<22>;
48 def VFPLdStMulFrm : Format<23>;
49 def VFPMiscFrm : Format<24>;
51 def ThumbFrm : Format<25>;
53 // Misc flag for data processing instructions that indicates whether
54 // the instruction has a Rn register operand.
55 class UnaryDP { bit isUnaryDataProc = 1; }
57 //===----------------------------------------------------------------------===//
59 // ARM Instruction templates.
62 class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
63 Format f, string cstr>
67 let Namespace = "ARM";
71 bits<4> AddrModeBits = AM.Value;
74 bits<3> SizeFlag = SZ.Value;
77 bits<2> IndexModeBits = IM.Value;
80 bits<5> Form = F.Value;
83 // Attributes specific to ARM instructions...
85 bit isUnaryDataProc = 0;
87 let Constraints = cstr;
90 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
91 : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
92 let OutOperandList = oops;
93 let InOperandList = iops;
95 let Pattern = pattern;
98 // Almost all ARM instructions are predicable.
99 class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
100 IndexMode im, Format f, string opc, string asm, string cstr,
102 : InstARM<am, sz, im, f, cstr> {
103 let OutOperandList = oops;
104 let InOperandList = !con(iops, (ops pred:$p));
105 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
106 let Pattern = pattern;
107 list<Predicate> Predicates = [IsARM];
110 // Same as I except it can optionally modify CPSR. Note it's modeled as
111 // an input operand since by default it's a zero register. It will
112 // become an implicit def once it's "flipped".
113 class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
114 IndexMode im, Format f, string opc, string asm, string cstr,
116 : InstARM<am, sz, im, f, cstr> {
117 let OutOperandList = oops;
118 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
119 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
120 let Pattern = pattern;
121 list<Predicate> Predicates = [IsARM];
125 class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
126 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
127 : InstARM<am, sz, im, f, cstr> {
128 let OutOperandList = oops;
129 let InOperandList = iops;
131 let Pattern = pattern;
132 list<Predicate> Predicates = [IsARM];
135 class AI<dag oops, dag iops, Format f, string opc,
136 string asm, list<dag> pattern>
137 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
139 class AsI<dag oops, dag iops, Format f, string opc,
140 string asm, list<dag> pattern>
141 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
143 class AXI<dag oops, dag iops, Format f, string asm,
145 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
148 // Ctrl flow instructions
149 class ABI<bits<4> opcod, dag oops, dag iops, string opc,
150 string asm, list<dag> pattern>
151 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, opc,
153 let Inst{27-24} = opcod;
155 class ABXI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
156 : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, BrFrm, asm,
158 let Inst{27-24} = opcod;
160 class ABXIx2<dag oops, dag iops, string asm, list<dag> pattern>
161 : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, BrMiscFrm, asm,
164 // BR_JT instructions
165 class JTI<dag oops, dag iops, string asm, list<dag> pattern>
166 : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm,
169 // addrmode1 instructions
170 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
171 string asm, list<dag> pattern>
172 : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
174 let Inst{24-21} = opcod;
175 let Inst{27-26} = {0,0};
177 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
178 string asm, list<dag> pattern>
179 : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
181 let Inst{24-21} = opcod;
182 let Inst{27-26} = {0,0};
184 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
186 : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
188 let Inst{24-21} = opcod;
189 let Inst{27-26} = {0,0};
191 class AI1x2<dag oops, dag iops, Format f, string opc,
192 string asm, list<dag> pattern>
193 : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
197 // addrmode2 loads and stores
198 class AI2<dag oops, dag iops, Format f, string opc,
199 string asm, list<dag> pattern>
200 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
202 let Inst{27-26} = {0,1};
206 class AI2ldw<dag oops, dag iops, Format f, string opc,
207 string asm, list<dag> pattern>
208 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
210 let Inst{20} = 1; // L bit
211 let Inst{21} = 0; // W bit
212 let Inst{22} = 0; // B bit
213 let Inst{24} = 1; // P bit
214 let Inst{27-26} = {0,1};
216 class AXI2ldw<dag oops, dag iops, Format f, string asm,
218 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
220 let Inst{20} = 1; // L bit
221 let Inst{21} = 0; // W bit
222 let Inst{22} = 0; // B bit
223 let Inst{24} = 1; // P bit
224 let Inst{27-26} = {0,1};
226 class AI2ldb<dag oops, dag iops, Format f, string opc,
227 string asm, list<dag> pattern>
228 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
230 let Inst{20} = 1; // L bit
231 let Inst{21} = 0; // W bit
232 let Inst{22} = 1; // B bit
233 let Inst{24} = 1; // P bit
234 let Inst{27-26} = {0,1};
236 class AXI2ldb<dag oops, dag iops, Format f, string asm,
238 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
240 let Inst{20} = 1; // L bit
241 let Inst{21} = 0; // W bit
242 let Inst{22} = 1; // B bit
243 let Inst{24} = 1; // P bit
244 let Inst{27-26} = {0,1};
248 class AI2stw<dag oops, dag iops, Format f, string opc,
249 string asm, list<dag> pattern>
250 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
252 let Inst{20} = 0; // L bit
253 let Inst{21} = 0; // W bit
254 let Inst{22} = 0; // B bit
255 let Inst{24} = 1; // P bit
256 let Inst{27-26} = {0,1};
258 class AXI2stw<dag oops, dag iops, Format f, string asm,
260 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
262 let Inst{20} = 0; // L bit
263 let Inst{21} = 0; // W bit
264 let Inst{22} = 0; // B bit
265 let Inst{24} = 1; // P bit
266 let Inst{27-26} = {0,1};
268 class AI2stb<dag oops, dag iops, Format f, string opc,
269 string asm, list<dag> pattern>
270 : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
272 let Inst{20} = 0; // L bit
273 let Inst{21} = 0; // W bit
274 let Inst{22} = 1; // B bit
275 let Inst{24} = 1; // P bit
276 let Inst{27-26} = {0,1};
278 class AXI2stb<dag oops, dag iops, Format f, string asm,
280 : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
282 let Inst{20} = 0; // L bit
283 let Inst{21} = 0; // W bit
284 let Inst{22} = 1; // B bit
285 let Inst{24} = 1; // P bit
286 let Inst{27-26} = {0,1};
290 class AI2ldwpr<dag oops, dag iops, Format f, string opc,
291 string asm, string cstr, list<dag> pattern>
292 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
293 asm, cstr, pattern> {
294 let Inst{20} = 1; // L bit
295 let Inst{21} = 1; // W bit
296 let Inst{22} = 0; // B bit
297 let Inst{24} = 1; // P bit
298 let Inst{27-26} = {0,1};
300 class AI2ldbpr<dag oops, dag iops, Format f, string opc,
301 string asm, string cstr, list<dag> pattern>
302 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
303 asm, cstr, pattern> {
304 let Inst{20} = 1; // L bit
305 let Inst{21} = 1; // W bit
306 let Inst{22} = 1; // B bit
307 let Inst{24} = 1; // P bit
308 let Inst{27-26} = {0,1};
311 // Pre-indexed stores
312 class AI2stwpr<dag oops, dag iops, Format f, string opc,
313 string asm, string cstr, list<dag> pattern>
314 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
315 asm, cstr, pattern> {
316 let Inst{20} = 0; // L bit
317 let Inst{21} = 1; // W bit
318 let Inst{22} = 0; // B bit
319 let Inst{24} = 1; // P bit
320 let Inst{27-26} = {0,1};
322 class AI2stbpr<dag oops, dag iops, Format f, string opc,
323 string asm, string cstr, list<dag> pattern>
324 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
325 asm, cstr, pattern> {
326 let Inst{20} = 0; // L bit
327 let Inst{21} = 1; // W bit
328 let Inst{22} = 1; // B bit
329 let Inst{24} = 1; // P bit
330 let Inst{27-26} = {0,1};
333 // Post-indexed loads
334 class AI2ldwpo<dag oops, dag iops, Format f, string opc,
335 string asm, string cstr, list<dag> pattern>
336 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
338 let Inst{20} = 1; // L bit
339 let Inst{21} = 0; // W bit
340 let Inst{22} = 0; // B bit
341 let Inst{24} = 0; // P bit
342 let Inst{27-26} = {0,1};
344 class AI2ldbpo<dag oops, dag iops, Format f, string opc,
345 string asm, string cstr, list<dag> pattern>
346 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
348 let Inst{20} = 1; // L bit
349 let Inst{21} = 0; // W bit
350 let Inst{22} = 1; // B bit
351 let Inst{24} = 0; // P bit
352 let Inst{27-26} = {0,1};
355 // Post-indexed stores
356 class AI2stwpo<dag oops, dag iops, Format f, string opc,
357 string asm, string cstr, list<dag> pattern>
358 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
360 let Inst{20} = 0; // L bit
361 let Inst{21} = 0; // W bit
362 let Inst{22} = 0; // B bit
363 let Inst{24} = 0; // P bit
364 let Inst{27-26} = {0,1};
366 class AI2stbpo<dag oops, dag iops, Format f, string opc,
367 string asm, string cstr, list<dag> pattern>
368 : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
370 let Inst{20} = 0; // L bit
371 let Inst{21} = 0; // W bit
372 let Inst{22} = 1; // B bit
373 let Inst{24} = 0; // P bit
374 let Inst{27-26} = {0,1};
377 // addrmode3 instructions
378 class AI3<dag oops, dag iops, Format f, string opc,
379 string asm, list<dag> pattern>
380 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
382 class AXI3<dag oops, dag iops, Format f, string asm,
384 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
388 class AI3ldh<dag oops, dag iops, Format f, string opc,
389 string asm, list<dag> pattern>
390 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
393 let Inst{5} = 1; // H bit
394 let Inst{6} = 0; // S bit
396 let Inst{20} = 1; // L bit
397 let Inst{21} = 0; // W bit
398 let Inst{24} = 1; // P bit
400 class AXI3ldh<dag oops, dag iops, Format f, string asm,
402 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
405 let Inst{5} = 1; // H bit
406 let Inst{6} = 0; // S bit
408 let Inst{20} = 1; // L bit
409 let Inst{21} = 0; // W bit
410 let Inst{24} = 1; // P bit
412 class AI3ldsh<dag oops, dag iops, Format f, string opc,
413 string asm, list<dag> pattern>
414 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
417 let Inst{5} = 1; // H bit
418 let Inst{6} = 1; // S bit
420 let Inst{20} = 1; // L bit
421 let Inst{21} = 0; // W bit
422 let Inst{24} = 1; // P bit
424 class AXI3ldsh<dag oops, dag iops, Format f, string asm,
426 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
429 let Inst{5} = 1; // H bit
430 let Inst{6} = 1; // S bit
432 let Inst{20} = 1; // L bit
433 let Inst{21} = 0; // W bit
434 let Inst{24} = 1; // P bit
436 class AI3ldsb<dag oops, dag iops, Format f, string opc,
437 string asm, list<dag> pattern>
438 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
441 let Inst{5} = 0; // H bit
442 let Inst{6} = 1; // S bit
444 let Inst{20} = 1; // L bit
445 let Inst{21} = 0; // W bit
446 let Inst{24} = 1; // P bit
448 class AXI3ldsb<dag oops, dag iops, Format f, string asm,
450 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
453 let Inst{5} = 0; // H bit
454 let Inst{6} = 1; // S bit
456 let Inst{20} = 1; // L bit
457 let Inst{21} = 0; // W bit
458 let Inst{24} = 1; // P bit
460 class AI3ldd<dag oops, dag iops, Format f, string opc,
461 string asm, list<dag> pattern>
462 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
465 let Inst{5} = 0; // H bit
466 let Inst{6} = 1; // S bit
468 let Inst{20} = 0; // L bit
469 let Inst{21} = 0; // W bit
470 let Inst{24} = 1; // P bit
474 class AI3sth<dag oops, dag iops, Format f, string opc,
475 string asm, list<dag> pattern>
476 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
479 let Inst{5} = 1; // H bit
480 let Inst{6} = 0; // S bit
482 let Inst{20} = 0; // L bit
483 let Inst{21} = 0; // W bit
484 let Inst{24} = 1; // P bit
486 class AXI3sth<dag oops, dag iops, Format f, string asm,
488 : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
491 let Inst{5} = 1; // H bit
492 let Inst{6} = 0; // S bit
494 let Inst{20} = 0; // L bit
495 let Inst{21} = 0; // W bit
496 let Inst{24} = 1; // P bit
498 class AI3std<dag oops, dag iops, Format f, string opc,
499 string asm, list<dag> pattern>
500 : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
503 let Inst{5} = 1; // H bit
504 let Inst{6} = 1; // S bit
506 let Inst{20} = 0; // L bit
507 let Inst{21} = 0; // W bit
508 let Inst{24} = 1; // P bit
512 class AI3ldhpr<dag oops, dag iops, Format f, string opc,
513 string asm, string cstr, list<dag> pattern>
514 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
515 asm, cstr, pattern> {
517 let Inst{5} = 1; // H bit
518 let Inst{6} = 0; // S bit
520 let Inst{20} = 1; // L bit
521 let Inst{21} = 1; // W bit
522 let Inst{24} = 1; // P bit
524 class AI3ldshpr<dag oops, dag iops, Format f, string opc,
525 string asm, string cstr, list<dag> pattern>
526 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
527 asm, cstr, pattern> {
529 let Inst{5} = 1; // H bit
530 let Inst{6} = 1; // S bit
532 let Inst{20} = 1; // L bit
533 let Inst{21} = 1; // W bit
534 let Inst{24} = 1; // P bit
536 class AI3ldsbpr<dag oops, dag iops, Format f, string opc,
537 string asm, string cstr, list<dag> pattern>
538 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
539 asm, cstr, pattern> {
541 let Inst{5} = 0; // H bit
542 let Inst{6} = 1; // S bit
544 let Inst{20} = 1; // L bit
545 let Inst{21} = 1; // W bit
546 let Inst{24} = 1; // P bit
549 // Pre-indexed stores
550 class AI3sthpr<dag oops, dag iops, Format f, string opc,
551 string asm, string cstr, list<dag> pattern>
552 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
553 asm, cstr, pattern> {
555 let Inst{5} = 1; // H bit
556 let Inst{6} = 0; // S bit
558 let Inst{20} = 0; // L bit
559 let Inst{21} = 1; // W bit
560 let Inst{24} = 1; // P bit
563 // Post-indexed loads
564 class AI3ldhpo<dag oops, dag iops, Format f, string opc,
565 string asm, string cstr, list<dag> pattern>
566 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
569 let Inst{5} = 1; // H bit
570 let Inst{6} = 0; // S bit
572 let Inst{20} = 1; // L bit
573 let Inst{21} = 1; // W bit
574 let Inst{24} = 0; // P bit
576 class AI3ldshpo<dag oops, dag iops, Format f, string opc,
577 string asm, string cstr, list<dag> pattern>
578 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
581 let Inst{5} = 1; // H bit
582 let Inst{6} = 1; // S bit
584 let Inst{20} = 1; // L bit
585 let Inst{21} = 1; // W bit
586 let Inst{24} = 0; // P bit
588 class AI3ldsbpo<dag oops, dag iops, Format f, string opc,
589 string asm, string cstr, list<dag> pattern>
590 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
593 let Inst{5} = 0; // H bit
594 let Inst{6} = 1; // S bit
596 let Inst{20} = 1; // L bit
597 let Inst{21} = 1; // W bit
598 let Inst{24} = 0; // P bit
601 // Post-indexed stores
602 class AI3sthpo<dag oops, dag iops, Format f, string opc,
603 string asm, string cstr, list<dag> pattern>
604 : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
607 let Inst{5} = 1; // H bit
608 let Inst{6} = 0; // S bit
610 let Inst{20} = 0; // L bit
611 let Inst{21} = 1; // W bit
612 let Inst{24} = 0; // P bit
616 // addrmode4 instructions
617 class AXI4ld<dag oops, dag iops, Format f, string asm, list<dag> pattern>
618 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
620 let Inst{20} = 1; // L bit
621 let Inst{22} = 0; // S bit
622 let Inst{27-25} = 0b100;
624 class AXI4st<dag oops, dag iops, Format f, string asm, list<dag> pattern>
625 : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
627 let Inst{20} = 0; // L bit
628 let Inst{22} = 0; // S bit
629 let Inst{27-25} = 0b100;
632 // Unsigned multiply, multiply-accumulate instructions.
633 class AMul1I<bits<7> opcod, dag oops, dag iops, string opc,
634 string asm, list<dag> pattern>
635 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
637 let Inst{7-4} = 0b1001;
638 let Inst{20} = 0; // S bit
639 let Inst{27-21} = opcod;
641 class AsMul1I<bits<7> opcod, dag oops, dag iops, string opc,
642 string asm, list<dag> pattern>
643 : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
645 let Inst{7-4} = 0b1001;
646 let Inst{27-21} = opcod;
649 // Most significant word multiply
650 class AMul2I<bits<7> opcod, dag oops, dag iops, string opc,
651 string asm, list<dag> pattern>
652 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
654 let Inst{7-4} = 0b1001;
656 let Inst{27-21} = opcod;
659 // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
660 class AMulxyI<bits<7> opcod, dag oops, dag iops, string opc,
661 string asm, list<dag> pattern>
662 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
667 let Inst{27-21} = opcod;
670 // Extend instructions.
671 class AExtI<bits<8> opcod, dag oops, dag iops, string opc,
672 string asm, list<dag> pattern>
673 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ExtFrm, opc,
675 let Inst{7-4} = 0b0111;
676 let Inst{27-20} = opcod;
679 // Misc Arithmetic instructions.
680 class AMiscA1I<bits<8> opcod, dag oops, dag iops, string opc,
681 string asm, list<dag> pattern>
682 : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, ArithMiscFrm, opc,
684 let Inst{27-20} = opcod;
687 //===----------------------------------------------------------------------===//
689 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
690 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
691 list<Predicate> Predicates = [IsARM];
693 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
694 list<Predicate> Predicates = [IsARM, HasV5TE];
696 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
697 list<Predicate> Predicates = [IsARM, HasV6];
700 //===----------------------------------------------------------------------===//
702 // Thumb Instruction Format Definitions.
706 // TI - Thumb instruction.
708 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
709 string asm, string cstr, list<dag> pattern>
710 : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
711 let OutOperandList = outs;
712 let InOperandList = ins;
714 let Pattern = pattern;
715 list<Predicate> Predicates = [IsThumb];
718 class TI<dag outs, dag ins, string asm, list<dag> pattern>
719 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
720 class TI1<dag outs, dag ins, string asm, list<dag> pattern>
721 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
722 class TI2<dag outs, dag ins, string asm, list<dag> pattern>
723 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
724 class TI4<dag outs, dag ins, string asm, list<dag> pattern>
725 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
726 class TIs<dag outs, dag ins, string asm, list<dag> pattern>
727 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
729 // Two-address instructions
730 class TIt<dag outs, dag ins, string asm, list<dag> pattern>
731 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
733 // BL, BLX(1) are translated by assembler into two instructions
734 class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
735 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
737 // BR_JT instructions
738 class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
739 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
742 //===----------------------------------------------------------------------===//
744 //===----------------------------------------------------------------------===//
745 // ARM VFP Instruction templates.
748 // ARM VFP addrmode5 loads and stores
749 class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
750 string opc, string asm, list<dag> pattern>
751 : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
752 VFPLdStFrm, opc, asm, "", pattern> {
753 // TODO: Mark the instructions with the appropriate subtarget info.
754 let Inst{27-24} = opcod1;
755 let Inst{21-20} = opcod2;
756 let Inst{11-8} = 0b1011;
759 class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
760 string opc, string asm, list<dag> pattern>
761 : I<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
762 VFPLdStFrm, opc, asm, "", pattern> {
763 // TODO: Mark the instructions with the appropriate subtarget info.
764 let Inst{27-24} = opcod1;
765 let Inst{21-20} = opcod2;
766 let Inst{11-8} = 0b1010;
769 // Load / store multiple
770 class AXSI5<dag oops, dag iops, string asm, list<dag> pattern>
771 : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
772 VFPLdStMulFrm, asm, "", pattern> {
773 // TODO: Mark the instructions with the appropriate subtarget info.
774 let Inst{27-25} = 0b110;
775 let Inst{11-8} = 0b1011;
778 class AXDI5<dag oops, dag iops, string asm, list<dag> pattern>
779 : XI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
780 VFPLdStMulFrm, asm, "", pattern> {
781 // TODO: Mark the instructions with the appropriate subtarget info.
782 let Inst{27-25} = 0b110;
783 let Inst{11-8} = 0b1010;
787 // Double precision, unary
788 class ADuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
789 string opc, string asm, list<dag> pattern>
790 : AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> {
791 let Inst{27-20} = opcod1;
792 let Inst{19-16} = opcod2;
793 let Inst{11-8} = 0b1011;
794 let Inst{7-4} = opcod3;
797 // Double precision, binary
798 class ADbI<bits<8> opcod, dag oops, dag iops, string opc,
799 string asm, list<dag> pattern>
800 : AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> {
801 let Inst{27-20} = opcod;
802 let Inst{11-8} = 0b1011;
805 // Single precision, unary
806 class ASuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
807 string opc, string asm, list<dag> pattern>
808 : AI<oops, iops, VFPUnaryFrm, opc, asm, pattern> {
809 // Bits 22 (D bit) and 5 (M bit) will be changed during instruction encoding.
810 let Inst{27-20} = opcod1;
811 let Inst{19-16} = opcod2;
812 let Inst{11-8} = 0b1010;
813 let Inst{7-4} = opcod3;
816 // Single precision, binary
817 class ASbI<bits<8> opcod, dag oops, dag iops, string opc,
818 string asm, list<dag> pattern>
819 : AI<oops, iops, VFPBinaryFrm, opc, asm, pattern> {
820 // Bit 22 (D bit) can be changed during instruction encoding.
821 let Inst{27-20} = opcod;
822 let Inst{11-8} = 0b1010;
825 // VFP conversion instructions
826 class AVConv1I<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3,
827 dag oops, dag iops, string opc, string asm, list<dag> pattern>
828 : AI<oops, iops, VFPConv1Frm, opc, asm, pattern> {
829 let Inst{27-20} = opcod1;
830 let Inst{19-16} = opcod2;
831 let Inst{11-8} = opcod3;
835 class AVConvXI<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, Format f,
836 string opc, string asm, list<dag> pattern>
837 : AI<oops, iops, f, opc, asm, pattern> {
838 let Inst{27-20} = opcod1;
839 let Inst{11-8} = opcod2;
843 class AVConv2I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
844 string asm, list<dag> pattern>
845 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv2Frm, opc, asm, pattern>;
847 class AVConv3I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
848 string asm, list<dag> pattern>
849 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv3Frm, opc, asm, pattern>;
851 class AVConv4I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
852 string asm, list<dag> pattern>
853 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv4Frm, opc, asm, pattern>;
855 class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops, string opc,
856 string asm, list<dag> pattern>
857 : AVConvXI<opcod1, opcod2, oops, iops, VFPConv5Frm, opc, asm, pattern>;
859 //===----------------------------------------------------------------------===//
862 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
863 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
864 list<Predicate> Predicates = [IsThumb];
867 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
868 list<Predicate> Predicates = [IsThumb, HasV5T];