1 //===- ARMInstrFormats.td - ARM Instruction Formats --*- tablegen -*---------=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 // ARM Instruction Format Definitions.
15 // Format specifies the encoding used by the instruction. This is part of the
16 // ad-hoc solution used to emit machine instruction encodings by our machine
18 class Format<bits<5> val> {
22 def Pseudo : Format<1>;
23 def MulFrm : Format<2>;
24 def MulSMLAW : Format<3>;
25 def MulSMULW : Format<4>;
26 def MulSMLA : Format<5>;
27 def MulSMUL : Format<6>;
28 def Branch : Format<7>;
29 def BranchMisc : Format<8>;
31 def DPRdIm : Format<9>;
32 def DPRdReg : Format<10>;
33 def DPRdSoReg : Format<11>;
34 def DPRdMisc : Format<12>;
35 def DPRnIm : Format<13>;
36 def DPRnReg : Format<14>;
37 def DPRnSoReg : Format<15>;
38 def DPRIm : Format<16>;
39 def DPRReg : Format<17>;
40 def DPRSoReg : Format<18>;
41 def DPRImS : Format<19>;
42 def DPRRegS : Format<20>;
43 def DPRSoRegS : Format<21>;
45 def LdFrm : Format<22>;
46 def StFrm : Format<23>;
48 def ArithMisc : Format<24>;
49 def ThumbFrm : Format<25>;
50 def VFPFrm : Format<26>;
53 //===----------------------------------------------------------------------===//
55 // ARM Instruction templates.
58 class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
59 Format f, string cstr>
63 let Namespace = "ARM";
65 bits<4> Opcode = opcod;
67 bits<4> AddrModeBits = AM.Value;
70 bits<3> SizeFlag = SZ.Value;
73 bits<2> IndexModeBits = IM.Value;
76 bits<5> Form = F.Value;
78 let Constraints = cstr;
81 class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
82 : InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
83 let OutOperandList = oops;
84 let InOperandList = iops;
86 let Pattern = pattern;
89 // Almost all ARM instructions are predicable.
90 class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
91 IndexMode im, Format f, string opc, string asm, string cstr,
93 : InstARM<opcod, am, sz, im, f, cstr> {
94 let OutOperandList = oops;
95 let InOperandList = !con(iops, (ops pred:$p));
96 let AsmString = !strconcat(opc, !strconcat("${p}", asm));
97 let Pattern = pattern;
98 list<Predicate> Predicates = [IsARM];
101 // Same as I except it can optionally modify CPSR. Note it's modeled as
102 // an input operand since by default it's a zero register. It will
103 // become an implicit def once it's "flipped".
104 class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
105 IndexMode im, Format f, string opc, string asm, string cstr,
107 : InstARM<opcod, am, sz, im, f, cstr> {
108 let OutOperandList = oops;
109 let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
110 let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
111 let Pattern = pattern;
112 list<Predicate> Predicates = [IsARM];
116 class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
117 IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
118 : InstARM<opcod, am, sz, im, f, cstr> {
119 let OutOperandList = oops;
120 let InOperandList = iops;
122 let Pattern = pattern;
123 list<Predicate> Predicates = [IsARM];
126 class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
127 string asm, list<dag> pattern>
128 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
130 class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
131 string asm, list<dag> pattern>
132 : sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
134 class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
136 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
139 // Ctrl flow instructions
140 class ABLpredI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
141 string asm, list<dag> pattern>
142 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
144 let Inst{24} = 1; // L bit
145 let Inst{25-27} = {1,0,1};
147 class ABLI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
149 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
151 let Inst{24} = 1; // L bit
152 let Inst{25-27} = {1,0,1};
155 class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
157 : XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
159 class ABI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
161 : XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
163 let Inst{24} = 0; // L bit
164 let Inst{25-27} = {1,0,1};
166 class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
167 string asm, list<dag> pattern>
168 : I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
170 let Inst{24} = 0; // L bit
171 let Inst{25-27} = {1,0,1};
174 // BR_JT instructions
176 class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
177 : XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
179 let Inst{20} = 0; // S Bit
180 let Inst{21-24} = {1,0,1,1};
181 let Inst{26-27} = {0,0};
184 class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
185 : XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
187 let Inst{20} = 0; // S bit
188 let Inst{21-24} = {0,0,1,0};
189 let Inst{26-27} = {0,0};
192 class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
193 : XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
195 let Inst{20} = 1; // L bit
196 let Inst{21} = 0; // W bit
197 let Inst{22} = 0; // B bit
198 let Inst{24} = 1; // P bit
199 let Inst{26-27} = {0,0};
203 // addrmode1 instructions
204 class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
205 string asm, list<dag> pattern>
206 : I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
208 let Inst{21-24} = opcod;
209 let Inst{26-27} = {0,0};
211 class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
212 string asm, list<dag> pattern>
213 : sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
215 let Inst{21-24} = opcod;
216 let Inst{26-27} = {0,0};
218 class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
220 : XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
222 let Inst{21-24} = opcod;
223 let Inst{26-27} = {0,0};
225 class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
226 string asm, list<dag> pattern>
227 : I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
231 // addrmode2 loads and stores
232 class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc,
233 string asm, list<dag> pattern>
234 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
236 let Inst{26-27} = {1,0};
238 class AXI2<bits<4> opcod, dag oops, dag iops, Format f, string asm,
240 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
244 class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
245 string asm, list<dag> pattern>
246 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
247 let Inst{20} = 1; // L bit
248 let Inst{21} = 0; // W bit
249 let Inst{22} = 0; // B bit
250 let Inst{24} = 1; // P bit
252 class AXI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
254 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
256 let Inst{20} = 1; // L bit
257 let Inst{21} = 0; // W bit
258 let Inst{22} = 0; // B bit
259 let Inst{24} = 1; // P bit
261 class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
262 string asm, list<dag> pattern>
263 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
264 let Inst{20} = 1; // L bit
265 let Inst{21} = 0; // W bit
266 let Inst{22} = 1; // B bit
267 let Inst{24} = 1; // P bit
269 class AXI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
271 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
273 let Inst{20} = 1; // L bit
274 let Inst{21} = 0; // W bit
275 let Inst{22} = 1; // B bit
276 let Inst{24} = 1; // P bit
280 class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
281 string asm, list<dag> pattern>
282 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
283 let Inst{20} = 0; // L bit
284 let Inst{21} = 0; // W bit
285 let Inst{22} = 0; // B bit
286 let Inst{24} = 1; // P bit
288 class AXI2stw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
290 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
292 let Inst{20} = 0; // L bit
293 let Inst{21} = 0; // W bit
294 let Inst{22} = 0; // B bit
295 let Inst{24} = 1; // P bit
297 class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
298 string asm, list<dag> pattern>
299 : AI2<opcod, oops, iops, f, opc, asm, pattern> {
300 let Inst{20} = 0; // L bit
301 let Inst{21} = 0; // W bit
302 let Inst{22} = 1; // B bit
303 let Inst{24} = 1; // P bit
305 class AXI2stb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
307 : XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, asm,
309 let Inst{20} = 0; // L bit
310 let Inst{21} = 0; // W bit
311 let Inst{22} = 1; // B bit
312 let Inst{24} = 1; // P bit
316 class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
317 string asm, string cstr, list<dag> pattern>
318 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
319 asm, cstr, pattern> {
320 let Inst{20} = 1; // L bit
321 let Inst{21} = 1; // W bit
322 let Inst{22} = 0; // B bit
323 let Inst{24} = 1; // P bit
325 class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
326 string asm, string cstr, list<dag> pattern>
327 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
328 asm, cstr, pattern> {
329 let Inst{20} = 1; // L bit
330 let Inst{21} = 1; // W bit
331 let Inst{22} = 1; // B bit
332 let Inst{24} = 1; // P bit
335 // Pre-indexed stores
336 class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
337 string asm, string cstr, list<dag> pattern>
338 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
339 asm, cstr, pattern> {
340 let Inst{20} = 0; // L bit
341 let Inst{21} = 1; // W bit
342 let Inst{22} = 0; // B bit
343 let Inst{24} = 1; // P bit
345 class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
346 string asm, string cstr, list<dag> pattern>
347 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
348 asm, cstr, pattern> {
349 let Inst{20} = 0; // L bit
350 let Inst{21} = 1; // W bit
351 let Inst{22} = 1; // B bit
352 let Inst{24} = 1; // P bit
355 // Post-indexed loads
356 class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
357 string asm, string cstr, list<dag> pattern>
358 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
360 let Inst{20} = 1; // L bit
361 let Inst{21} = 0; // W bit
362 let Inst{22} = 0; // B bit
363 let Inst{24} = 0; // P bit
365 class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
366 string asm, string cstr, list<dag> pattern>
367 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
369 let Inst{20} = 1; // L bit
370 let Inst{21} = 0; // W bit
371 let Inst{22} = 1; // B bit
372 let Inst{24} = 0; // P bit
375 // Post-indexed stores
376 class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
377 string asm, string cstr, list<dag> pattern>
378 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
380 let Inst{20} = 0; // L bit
381 let Inst{21} = 0; // W bit
382 let Inst{22} = 0; // B bit
383 let Inst{24} = 0; // P bit
385 class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
386 string asm, string cstr, list<dag> pattern>
387 : I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
389 let Inst{20} = 0; // L bit
390 let Inst{21} = 0; // W bit
391 let Inst{22} = 1; // B bit
392 let Inst{24} = 0; // P bit
395 // addrmode3 instructions
396 class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc,
397 string asm, list<dag> pattern>
398 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
400 class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm,
402 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
406 class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
407 string asm, list<dag> pattern>
408 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
411 let Inst{5} = 1; // H bit
412 let Inst{6} = 0; // S bit
414 let Inst{20} = 1; // L bit
415 let Inst{21} = 0; // W bit
416 let Inst{24} = 1; // P bit
418 class AXI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
420 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
423 let Inst{5} = 1; // H bit
424 let Inst{6} = 0; // S bit
426 let Inst{20} = 1; // L bit
427 let Inst{21} = 0; // W bit
428 let Inst{24} = 1; // P bit
430 class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
431 string asm, list<dag> pattern>
432 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
435 let Inst{5} = 1; // H bit
436 let Inst{6} = 1; // S bit
438 let Inst{20} = 1; // L bit
439 let Inst{21} = 0; // W bit
440 let Inst{24} = 1; // P bit
442 class AXI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
444 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
447 let Inst{5} = 1; // H bit
448 let Inst{6} = 1; // S bit
450 let Inst{20} = 1; // L bit
451 let Inst{21} = 0; // W bit
452 let Inst{24} = 1; // P bit
454 class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
455 string asm, list<dag> pattern>
456 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
459 let Inst{5} = 0; // H bit
460 let Inst{6} = 1; // S bit
462 let Inst{20} = 1; // L bit
463 let Inst{21} = 0; // W bit
464 let Inst{24} = 1; // P bit
466 class AXI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
468 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
471 let Inst{5} = 0; // H bit
472 let Inst{6} = 1; // S bit
474 let Inst{20} = 1; // L bit
475 let Inst{21} = 0; // W bit
476 let Inst{24} = 1; // P bit
478 class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc,
479 string asm, list<dag> pattern>
480 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
483 let Inst{5} = 0; // H bit
484 let Inst{6} = 1; // S bit
486 let Inst{20} = 0; // L bit
487 let Inst{21} = 0; // W bit
488 let Inst{24} = 1; // P bit
492 class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc,
493 string asm, list<dag> pattern>
494 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
497 let Inst{5} = 1; // H bit
498 let Inst{6} = 0; // S bit
500 let Inst{20} = 0; // L bit
501 let Inst{21} = 0; // W bit
502 let Inst{24} = 1; // P bit
504 class AXI3sth<bits<4> opcod, dag oops, dag iops, Format f, string asm,
506 : XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
509 let Inst{5} = 1; // H bit
510 let Inst{6} = 0; // S bit
512 let Inst{20} = 0; // L bit
513 let Inst{21} = 0; // W bit
514 let Inst{24} = 1; // P bit
516 class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc,
517 string asm, list<dag> pattern>
518 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
521 let Inst{5} = 1; // H bit
522 let Inst{6} = 1; // S bit
524 let Inst{20} = 0; // L bit
525 let Inst{21} = 0; // W bit
526 let Inst{24} = 1; // P bit
530 class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
531 string asm, string cstr, list<dag> pattern>
532 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
533 asm, cstr, pattern> {
535 let Inst{5} = 1; // H bit
536 let Inst{6} = 0; // S bit
538 let Inst{20} = 1; // L bit
539 let Inst{21} = 1; // W bit
540 let Inst{24} = 1; // P bit
542 class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
543 string asm, string cstr, list<dag> pattern>
544 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
545 asm, cstr, pattern> {
547 let Inst{5} = 1; // H bit
548 let Inst{6} = 1; // S bit
550 let Inst{20} = 1; // L bit
551 let Inst{21} = 1; // W bit
552 let Inst{24} = 1; // P bit
554 class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
555 string asm, string cstr, list<dag> pattern>
556 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
557 asm, cstr, pattern> {
559 let Inst{5} = 0; // H bit
560 let Inst{6} = 1; // S bit
562 let Inst{20} = 1; // L bit
563 let Inst{21} = 1; // W bit
564 let Inst{24} = 1; // P bit
567 // Pre-indexed stores
568 class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
569 string asm, string cstr, list<dag> pattern>
570 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
571 asm, cstr, pattern> {
573 let Inst{5} = 1; // H bit
574 let Inst{6} = 0; // S bit
576 let Inst{20} = 0; // L bit
577 let Inst{21} = 1; // W bit
578 let Inst{24} = 1; // P bit
581 // Post-indexed loads
582 class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
583 string asm, string cstr, list<dag> pattern>
584 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
587 let Inst{5} = 1; // H bit
588 let Inst{6} = 0; // S bit
590 let Inst{20} = 1; // L bit
591 let Inst{21} = 1; // W bit
592 let Inst{24} = 0; // P bit
594 class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
595 string asm, string cstr, list<dag> pattern>
596 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
599 let Inst{5} = 1; // H bit
600 let Inst{6} = 1; // S bit
602 let Inst{20} = 1; // L bit
603 let Inst{21} = 1; // W bit
604 let Inst{24} = 0; // P bit
606 class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
607 string asm, string cstr, list<dag> pattern>
608 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
611 let Inst{5} = 0; // H bit
612 let Inst{6} = 1; // S bit
614 let Inst{20} = 1; // L bit
615 let Inst{21} = 1; // W bit
616 let Inst{24} = 0; // P bit
619 // Post-indexed stores
620 class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
621 string asm, string cstr, list<dag> pattern>
622 : I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
625 let Inst{5} = 1; // H bit
626 let Inst{6} = 0; // S bit
628 let Inst{20} = 0; // L bit
629 let Inst{21} = 1; // W bit
630 let Inst{24} = 0; // P bit
634 // addrmode4 instructions
635 class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc,
636 string asm, list<dag> pattern>
637 : I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
639 let Inst{25-27} = {0,0,1};
641 class AXI4ld<bits<4> opcod, dag oops, dag iops, Format f, string asm,
643 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
645 let Inst{20} = 1; // L bit
646 let Inst{22} = 0; // S bit
647 let Inst{25-27} = {0,0,1};
649 class AXI4ldpc<bits<4> opcod, dag oops, dag iops, Format f, string asm,
651 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
653 let Inst{20} = 1; // L bit
654 let Inst{22} = 1; // S bit
655 let Inst{25-27} = {0,0,1};
657 class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm,
659 : XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
661 let Inst{20} = 0; // L bit
662 let Inst{22} = 0; // S bit
663 let Inst{25-27} = {0,0,1};
667 //===----------------------------------------------------------------------===//
669 // ARMPat - Same as Pat<>, but requires that the compiler be in ARM mode.
670 class ARMPat<dag pattern, dag result> : Pat<pattern, result> {
671 list<Predicate> Predicates = [IsARM];
673 class ARMV5TEPat<dag pattern, dag result> : Pat<pattern, result> {
674 list<Predicate> Predicates = [IsARM, HasV5TE];
676 class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
677 list<Predicate> Predicates = [IsARM, HasV6];
680 //===----------------------------------------------------------------------===//
682 // Thumb Instruction Format Definitions.
686 // TI - Thumb instruction.
688 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
689 string asm, string cstr, list<dag> pattern>
690 // FIXME: Set all opcodes to 0 for now.
691 : InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
692 let OutOperandList = outs;
693 let InOperandList = ins;
695 let Pattern = pattern;
696 list<Predicate> Predicates = [IsThumb];
699 class TI<dag outs, dag ins, string asm, list<dag> pattern>
700 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
701 class TI1<dag outs, dag ins, string asm, list<dag> pattern>
702 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
703 class TI2<dag outs, dag ins, string asm, list<dag> pattern>
704 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
705 class TI4<dag outs, dag ins, string asm, list<dag> pattern>
706 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
707 class TIs<dag outs, dag ins, string asm, list<dag> pattern>
708 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
710 // Two-address instructions
711 class TIt<dag outs, dag ins, string asm, list<dag> pattern>
712 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
714 // BL, BLX(1) are translated by assembler into two instructions
715 class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
716 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
718 // BR_JT instructions
719 class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
720 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
723 //===----------------------------------------------------------------------===//
726 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
727 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
728 list<Predicate> Predicates = [IsThumb];
731 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
732 list<Predicate> Predicates = [IsThumb, HasV5T];