1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
25 class ARMConstantPoolValue;
28 // ARM Specific DAG Nodes
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
34 // TargetExternalSymbol, and TargetGlobalAddress.
35 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
37 CALL, // Function call.
38 CALL_PRED, // Function call that's predicable.
39 CALL_NOLINK, // Function call with branch not branch-and-link.
40 tCALL, // Thumb function call.
41 BRCOND, // Conditional branch.
42 BR_JT, // Jumptable branch.
43 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
44 RET_FLAG, // Return with a flag operand.
46 PIC_ADD, // Add with a PC operand and a PIC label.
48 CMP, // ARM compare instructions.
49 CMPZ, // ARM compare that sets only Z flag.
50 CMPFP, // ARM VFP compare instruction, sets FPSCR.
51 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
52 FMSTAT, // ARM fmstat instruction.
53 CMOV, // ARM conditional move instructions.
54 CNEG, // ARM conditional negate instructions.
56 RBIT, // ARM bitreverse instruction
58 FTOSI, // FP to sint within a FP register.
59 FTOUI, // FP to uint within a FP register.
60 SITOF, // sint to FP within a FP register.
61 UITOF, // uint to FP within a FP register.
63 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
64 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
65 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
67 VMOVRRD, // double to two gprs.
68 VMOVDRR, // Two gprs to double.
70 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
71 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
73 TC_RETURN, // Tail call return pseudo.
77 DYN_ALLOC, // Dynamic allocation on the stack.
79 MEMBARRIER, // Memory barrier
80 SYNCBARRIER, // Memory sync barrier
82 VCEQ, // Vector compare equal.
83 VCGE, // Vector compare greater than or equal.
84 VCGEU, // Vector compare unsigned greater than or equal.
85 VCGT, // Vector compare greater than.
86 VCGTU, // Vector compare unsigned greater than.
87 VTST, // Vector test bits.
89 // Vector shift by immediate:
91 VSHRs, // ...right (signed)
92 VSHRu, // ...right (unsigned)
93 VSHLLs, // ...left long (signed)
94 VSHLLu, // ...left long (unsigned)
95 VSHLLi, // ...left long (with maximum shift count)
96 VSHRN, // ...right narrow
98 // Vector rounding shift by immediate:
99 VRSHRs, // ...right (signed)
100 VRSHRu, // ...right (unsigned)
101 VRSHRN, // ...right narrow
103 // Vector saturating shift by immediate:
104 VQSHLs, // ...left (signed)
105 VQSHLu, // ...left (unsigned)
106 VQSHLsu, // ...left (signed to unsigned)
107 VQSHRNs, // ...right narrow (signed)
108 VQSHRNu, // ...right narrow (unsigned)
109 VQSHRNsu, // ...right narrow (signed to unsigned)
111 // Vector saturating rounding shift by immediate:
112 VQRSHRNs, // ...right narrow (signed)
113 VQRSHRNu, // ...right narrow (unsigned)
114 VQRSHRNsu, // ...right narrow (signed to unsigned)
116 // Vector shift and insert:
120 // Vector get lane (VMOV scalar to ARM core register)
121 // (These are used for 8- and 16-bit element types only.)
122 VGETLANEu, // zero-extend vector extract element
123 VGETLANEs, // sign-extend vector extract element
131 VREV64, // reverse elements within 64-bit doublewords
132 VREV32, // reverse elements within 32-bit words
133 VREV16, // reverse elements within 16-bit halfwords
134 VZIP, // zip (interleave)
135 VUZP, // unzip (deinterleave)
138 // Floating-point max and min:
144 /// Define some predicates that are used for node matching.
146 /// getVMOVImm - If this is a build_vector of constants which can be
147 /// formed by using a VMOV instruction of the specified element size,
148 /// return the constant being splatted. The ByteSize field indicates the
149 /// number of bytes of each element [1248].
150 SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
152 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
153 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
154 /// instruction, returns its 8-bit integer representation. Otherwise,
156 int getVFPf32Imm(const APFloat &FPImm);
157 int getVFPf64Imm(const APFloat &FPImm);
160 //===--------------------------------------------------------------------===//
161 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
163 class ARMTargetLowering : public TargetLowering {
165 explicit ARMTargetLowering(TargetMachine &TM);
167 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
169 /// ReplaceNodeResults - Replace the results of node with an illegal result
170 /// type with new values built out of custom code.
172 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
173 SelectionDAG &DAG) const;
175 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
177 virtual const char *getTargetNodeName(unsigned Opcode) const;
179 virtual MachineBasicBlock *
180 EmitInstrWithCustomInserter(MachineInstr *MI,
181 MachineBasicBlock *MBB) const;
183 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
184 /// unaligned memory accesses. of the specified type.
185 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
186 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
188 /// isLegalAddressingMode - Return true if the addressing mode represented
189 /// by AM is legal for this target, for a load/store of the specified type.
190 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
191 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
193 /// isLegalICmpImmediate - Return true if the specified immediate is legal
194 /// icmp immediate, that is the target has icmp instructions which can
195 /// compare a register against the immediate without having to materialize
196 /// the immediate into a register.
197 virtual bool isLegalICmpImmediate(int64_t Imm) const;
199 /// getPreIndexedAddressParts - returns true by value, base pointer and
200 /// offset pointer and addressing mode by reference if the node's address
201 /// can be legally represented as pre-indexed load / store address.
202 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
204 ISD::MemIndexedMode &AM,
205 SelectionDAG &DAG) const;
207 /// getPostIndexedAddressParts - returns true by value, base pointer and
208 /// offset pointer and addressing mode by reference if this node can be
209 /// combined with a load / store to form a post-indexed load / store.
210 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
211 SDValue &Base, SDValue &Offset,
212 ISD::MemIndexedMode &AM,
213 SelectionDAG &DAG) const;
215 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
219 const SelectionDAG &DAG,
220 unsigned Depth) const;
223 ConstraintType getConstraintType(const std::string &Constraint) const;
224 std::pair<unsigned, const TargetRegisterClass*>
225 getRegForInlineAsmConstraint(const std::string &Constraint,
227 std::vector<unsigned>
228 getRegClassForInlineAsmConstraint(const std::string &Constraint,
231 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
232 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
233 /// true it means one of the asm constraint of the inline asm instruction
234 /// being processed is 'm'.
235 virtual void LowerAsmOperandForConstraint(SDValue Op,
236 char ConstraintLetter,
238 std::vector<SDValue> &Ops,
239 SelectionDAG &DAG) const;
241 const ARMSubtarget* getSubtarget() const {
245 /// getRegClassFor - Return the register class that should be used for the
246 /// specified value type.
247 virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
249 /// getFunctionAlignment - Return the Log2 alignment of this function.
250 virtual unsigned getFunctionAlignment(const Function *F) const;
252 Sched::Preference getSchedulingPreference(SDNode *N) const;
254 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
255 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
257 /// isFPImmLegal - Returns true if the target can instruction select the
258 /// specified FP immediate natively. If false, the legalizer will
259 /// materialize the FP immediate as a load from a constant pool.
260 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
263 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
264 /// make the right decision when generating code for different targets.
265 const ARMSubtarget *Subtarget;
267 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
269 unsigned ARMPCLabelIndex;
271 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
272 void addDRTypeForNEON(EVT VT);
273 void addQRTypeForNEON(EVT VT);
275 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
276 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
277 SDValue Chain, SDValue &Arg,
278 RegsToPassVector &RegsToPass,
279 CCValAssign &VA, CCValAssign &NextVA,
281 SmallVector<SDValue, 8> &MemOpChains,
282 ISD::ArgFlagsTy Flags) const;
283 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
284 SDValue &Root, SelectionDAG &DAG,
287 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
288 bool isVarArg) const;
289 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
290 DebugLoc dl, SelectionDAG &DAG,
291 const CCValAssign &VA,
292 ISD::ArgFlagsTy Flags) const;
293 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
294 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
295 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
296 const ARMSubtarget *Subtarget) const;
297 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
298 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
299 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
300 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
301 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
302 SelectionDAG &DAG) const;
303 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
304 SelectionDAG &DAG) const;
305 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
306 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
307 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
308 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
309 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
310 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
311 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
312 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
313 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
315 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
316 CallingConv::ID CallConv, bool isVarArg,
317 const SmallVectorImpl<ISD::InputArg> &Ins,
318 DebugLoc dl, SelectionDAG &DAG,
319 SmallVectorImpl<SDValue> &InVals) const;
322 LowerFormalArguments(SDValue Chain,
323 CallingConv::ID CallConv, bool isVarArg,
324 const SmallVectorImpl<ISD::InputArg> &Ins,
325 DebugLoc dl, SelectionDAG &DAG,
326 SmallVectorImpl<SDValue> &InVals) const;
329 LowerCall(SDValue Chain, SDValue Callee,
330 CallingConv::ID CallConv, bool isVarArg,
332 const SmallVectorImpl<ISD::OutputArg> &Outs,
333 const SmallVectorImpl<ISD::InputArg> &Ins,
334 DebugLoc dl, SelectionDAG &DAG,
335 SmallVectorImpl<SDValue> &InVals) const;
337 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
338 /// for tail call optimization. Targets which want to do tail call
339 /// optimization should implement this function.
340 bool IsEligibleForTailCallOptimization(SDValue Callee,
341 CallingConv::ID CalleeCC,
343 bool isCalleeStructRet,
344 bool isCallerStructRet,
345 const SmallVectorImpl<ISD::OutputArg> &Outs,
346 const SmallVectorImpl<ISD::InputArg> &Ins,
347 SelectionDAG& DAG) const;
349 LowerReturn(SDValue Chain,
350 CallingConv::ID CallConv, bool isVarArg,
351 const SmallVectorImpl<ISD::OutputArg> &Outs,
352 DebugLoc dl, SelectionDAG &DAG) const;
354 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
355 SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl) const;
357 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
358 MachineBasicBlock *BB,
359 unsigned Size) const;
360 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
361 MachineBasicBlock *BB,
363 unsigned BinOpcode) const;
368 #endif // ARMISELLOWERING_H