1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
25 class ARMConstantPoolValue;
28 // ARM Specific DAG Nodes
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
34 // TargetExternalSymbol, and TargetGlobalAddress.
35 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
37 CALL, // Function call.
38 CALL_PRED, // Function call that's predicable.
39 CALL_NOLINK, // Function call with branch not branch-and-link.
40 tCALL, // Thumb function call.
41 BRCOND, // Conditional branch.
42 BR_JT, // Jumptable branch.
43 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
44 RET_FLAG, // Return with a flag operand.
46 PIC_ADD, // Add with a PC operand and a PIC label.
48 CMP, // ARM compare instructions.
49 CMPZ, // ARM compare that sets only Z flag.
50 CMPFP, // ARM VFP compare instruction, sets FPSCR.
51 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
52 FMSTAT, // ARM fmstat instruction.
53 CMOV, // ARM conditional move instructions.
54 CNEG, // ARM conditional negate instructions.
56 RBIT, // ARM bitreverse instruction
58 FTOSI, // FP to sint within a FP register.
59 FTOUI, // FP to uint within a FP register.
60 SITOF, // sint to FP within a FP register.
61 UITOF, // uint to FP within a FP register.
62 F16_TO_F32, // Half FP to single FP within a FP register.
63 F32_TO_F16, // Single FP to half FP within a FP register.
65 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
66 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
67 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
69 VMOVRRD, // double to two gprs.
70 VMOVDRR, // Two gprs to double.
72 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
73 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
77 DYN_ALLOC, // Dynamic allocation on the stack.
79 MEMBARRIER, // Memory barrier
80 SYNCBARRIER, // Memory sync barrier
82 VCEQ, // Vector compare equal.
83 VCGE, // Vector compare greater than or equal.
84 VCGEU, // Vector compare unsigned greater than or equal.
85 VCGT, // Vector compare greater than.
86 VCGTU, // Vector compare unsigned greater than.
87 VTST, // Vector test bits.
89 // Vector shift by immediate:
91 VSHRs, // ...right (signed)
92 VSHRu, // ...right (unsigned)
93 VSHLLs, // ...left long (signed)
94 VSHLLu, // ...left long (unsigned)
95 VSHLLi, // ...left long (with maximum shift count)
96 VSHRN, // ...right narrow
98 // Vector rounding shift by immediate:
99 VRSHRs, // ...right (signed)
100 VRSHRu, // ...right (unsigned)
101 VRSHRN, // ...right narrow
103 // Vector saturating shift by immediate:
104 VQSHLs, // ...left (signed)
105 VQSHLu, // ...left (unsigned)
106 VQSHLsu, // ...left (signed to unsigned)
107 VQSHRNs, // ...right narrow (signed)
108 VQSHRNu, // ...right narrow (unsigned)
109 VQSHRNsu, // ...right narrow (signed to unsigned)
111 // Vector saturating rounding shift by immediate:
112 VQRSHRNs, // ...right narrow (signed)
113 VQRSHRNu, // ...right narrow (unsigned)
114 VQRSHRNsu, // ...right narrow (signed to unsigned)
116 // Vector shift and insert:
120 // Vector get lane (VMOV scalar to ARM core register)
121 // (These are used for 8- and 16-bit element types only.)
122 VGETLANEu, // zero-extend vector extract element
123 VGETLANEs, // sign-extend vector extract element
131 VREV64, // reverse elements within 64-bit doublewords
132 VREV32, // reverse elements within 32-bit words
133 VREV16, // reverse elements within 16-bit halfwords
134 VZIP, // zip (interleave)
135 VUZP, // unzip (deinterleave)
138 // Floating-point max and min:
144 /// Define some predicates that are used for node matching.
146 /// getVMOVImm - If this is a build_vector of constants which can be
147 /// formed by using a VMOV instruction of the specified element size,
148 /// return the constant being splatted. The ByteSize field indicates the
149 /// number of bytes of each element [1248].
150 SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
152 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
153 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
154 /// instruction, returns its 8-bit integer representation. Otherwise,
156 int getVFPf32Imm(const APFloat &FPImm);
157 int getVFPf64Imm(const APFloat &FPImm);
160 //===--------------------------------------------------------------------===//
161 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
163 class ARMTargetLowering : public TargetLowering {
164 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
166 explicit ARMTargetLowering(TargetMachine &TM);
168 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
170 /// ReplaceNodeResults - Replace the results of node with an illegal result
171 /// type with new values built out of custom code.
173 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
176 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
178 virtual const char *getTargetNodeName(unsigned Opcode) const;
180 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
181 MachineBasicBlock *MBB,
182 DenseMap<MachineBasicBlock*, MachineBasicBlock*>*) const;
184 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
185 /// unaligned memory accesses. of the specified type.
186 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
187 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
189 /// isLegalAddressingMode - Return true if the addressing mode represented
190 /// by AM is legal for this target, for a load/store of the specified type.
191 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
192 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
194 /// isLegalICmpImmediate - Return true if the specified immediate is legal
195 /// icmp immediate, that is the target has icmp instructions which can compare
196 /// a register against the immediate without having to materialize the
197 /// immediate into a register.
198 virtual bool isLegalICmpImmediate(int64_t Imm) const;
200 /// getPreIndexedAddressParts - returns true by value, base pointer and
201 /// offset pointer and addressing mode by reference if the node's address
202 /// can be legally represented as pre-indexed load / store address.
203 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
205 ISD::MemIndexedMode &AM,
206 SelectionDAG &DAG) const;
208 /// getPostIndexedAddressParts - returns true by value, base pointer and
209 /// offset pointer and addressing mode by reference if this node can be
210 /// combined with a load / store to form a post-indexed load / store.
211 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
212 SDValue &Base, SDValue &Offset,
213 ISD::MemIndexedMode &AM,
214 SelectionDAG &DAG) const;
216 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
220 const SelectionDAG &DAG,
221 unsigned Depth) const;
224 ConstraintType getConstraintType(const std::string &Constraint) const;
225 std::pair<unsigned, const TargetRegisterClass*>
226 getRegForInlineAsmConstraint(const std::string &Constraint,
228 std::vector<unsigned>
229 getRegClassForInlineAsmConstraint(const std::string &Constraint,
232 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
233 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
234 /// true it means one of the asm constraint of the inline asm instruction
235 /// being processed is 'm'.
236 virtual void LowerAsmOperandForConstraint(SDValue Op,
237 char ConstraintLetter,
239 std::vector<SDValue> &Ops,
240 SelectionDAG &DAG) const;
242 virtual const ARMSubtarget* getSubtarget() {
246 /// getFunctionAlignment - Return the Log2 alignment of this function.
247 virtual unsigned getFunctionAlignment(const Function *F) const;
249 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
250 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
252 /// isFPImmLegal - Returns true if the target can instruction select the
253 /// specified FP immediate natively. If false, the legalizer will
254 /// materialize the FP immediate as a load from a constant pool.
255 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
258 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
259 /// make the right decision when generating code for different targets.
260 const ARMSubtarget *Subtarget;
262 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
264 unsigned ARMPCLabelIndex;
266 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
267 void addDRTypeForNEON(EVT VT);
268 void addQRTypeForNEON(EVT VT);
270 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
271 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
272 SDValue Chain, SDValue &Arg,
273 RegsToPassVector &RegsToPass,
274 CCValAssign &VA, CCValAssign &NextVA,
276 SmallVector<SDValue, 8> &MemOpChains,
277 ISD::ArgFlagsTy Flags);
278 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
279 SDValue &Root, SelectionDAG &DAG, DebugLoc dl);
281 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const;
282 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
283 DebugLoc dl, SelectionDAG &DAG,
284 const CCValAssign &VA,
285 ISD::ArgFlagsTy Flags);
286 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG);
287 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
288 const ARMSubtarget *Subtarget);
289 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);
290 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG);
291 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG);
292 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
293 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
295 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
297 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG);
298 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
299 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
300 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
301 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
302 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG);
303 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG);
304 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG);
306 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
308 SDValue Dst, SDValue Src,
309 SDValue Size, unsigned Align,
311 const Value *DstSV, uint64_t DstSVOff,
312 const Value *SrcSV, uint64_t SrcSVOff);
313 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
314 CallingConv::ID CallConv, bool isVarArg,
315 const SmallVectorImpl<ISD::InputArg> &Ins,
316 DebugLoc dl, SelectionDAG &DAG,
317 SmallVectorImpl<SDValue> &InVals);
320 LowerFormalArguments(SDValue Chain,
321 CallingConv::ID CallConv, bool isVarArg,
322 const SmallVectorImpl<ISD::InputArg> &Ins,
323 DebugLoc dl, SelectionDAG &DAG,
324 SmallVectorImpl<SDValue> &InVals);
327 LowerCall(SDValue Chain, SDValue Callee,
328 CallingConv::ID CallConv, bool isVarArg,
330 const SmallVectorImpl<ISD::OutputArg> &Outs,
331 const SmallVectorImpl<ISD::InputArg> &Ins,
332 DebugLoc dl, SelectionDAG &DAG,
333 SmallVectorImpl<SDValue> &InVals);
336 LowerReturn(SDValue Chain,
337 CallingConv::ID CallConv, bool isVarArg,
338 const SmallVectorImpl<ISD::OutputArg> &Outs,
339 DebugLoc dl, SelectionDAG &DAG);
341 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
342 SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl);
344 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
345 MachineBasicBlock *BB,
346 unsigned Size) const;
347 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
348 MachineBasicBlock *BB,
350 unsigned BinOpcode) const;
355 #endif // ARMISELLOWERING_H