1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
18 #include "MCTargetDesc/ARMBaseInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
25 class ARMConstantPoolValue;
29 // ARM Specific DAG Nodes
30 enum NodeType : unsigned {
31 // Start the numbering where the builtin ops and target ops leave off.
32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
35 // TargetExternalSymbol, and TargetGlobalAddress.
36 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
38 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
40 // Add pseudo op to model memcpy for struct byval.
43 CALL, // Function call.
44 CALL_PRED, // Function call that's predicable.
45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
50 RET_FLAG, // Return with a flag operand.
51 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
53 PIC_ADD, // Add with a PC operand and a PIC label.
55 CMP, // ARM compare instructions.
56 CMN, // ARM CMN instructions.
57 CMPZ, // ARM compare that sets only Z flag.
58 CMPFP, // ARM VFP compare instruction, sets FPSCR.
59 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
60 FMSTAT, // ARM fmstat instruction.
62 CMOV, // ARM conditional move instructions.
66 RBIT, // ARM bitreverse instruction
68 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
69 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
70 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
72 ADDC, // Add with carry
73 ADDE, // Add using carry
74 SUBC, // Sub with carry
75 SUBE, // Sub using carry
77 VMOVRRD, // double to two gprs.
78 VMOVDRR, // Two gprs to double.
80 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
81 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
82 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
84 TC_RETURN, // Tail call return pseudo.
88 DYN_ALLOC, // Dynamic allocation on the stack.
90 MEMBARRIER_MCR, // Memory barrier (MCR)
94 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
95 WIN__DBZCHK, // Windows' divide by zero check
97 VCEQ, // Vector compare equal.
98 VCEQZ, // Vector compare equal to zero.
99 VCGE, // Vector compare greater than or equal.
100 VCGEZ, // Vector compare greater than or equal to zero.
101 VCLEZ, // Vector compare less than or equal to zero.
102 VCGEU, // Vector compare unsigned greater than or equal.
103 VCGT, // Vector compare greater than.
104 VCGTZ, // Vector compare greater than zero.
105 VCLTZ, // Vector compare less than zero.
106 VCGTU, // Vector compare unsigned greater than.
107 VTST, // Vector test bits.
109 // Vector shift by immediate:
111 VSHRs, // ...right (signed)
112 VSHRu, // ...right (unsigned)
114 // Vector rounding shift by immediate:
115 VRSHRs, // ...right (signed)
116 VRSHRu, // ...right (unsigned)
117 VRSHRN, // ...right narrow
119 // Vector saturating shift by immediate:
120 VQSHLs, // ...left (signed)
121 VQSHLu, // ...left (unsigned)
122 VQSHLsu, // ...left (signed to unsigned)
123 VQSHRNs, // ...right narrow (signed)
124 VQSHRNu, // ...right narrow (unsigned)
125 VQSHRNsu, // ...right narrow (signed to unsigned)
127 // Vector saturating rounding shift by immediate:
128 VQRSHRNs, // ...right narrow (signed)
129 VQRSHRNu, // ...right narrow (unsigned)
130 VQRSHRNsu, // ...right narrow (signed to unsigned)
132 // Vector shift and insert:
136 // Vector get lane (VMOV scalar to ARM core register)
137 // (These are used for 8- and 16-bit element types only.)
138 VGETLANEu, // zero-extend vector extract element
139 VGETLANEs, // sign-extend vector extract element
141 // Vector move immediate and move negated immediate:
145 // Vector move f32 immediate:
154 VREV64, // reverse elements within 64-bit doublewords
155 VREV32, // reverse elements within 32-bit words
156 VREV16, // reverse elements within 16-bit halfwords
157 VZIP, // zip (interleave)
158 VUZP, // unzip (deinterleave)
160 VTBL1, // 1-register shuffle with mask
161 VTBL2, // 2-register shuffle with mask
163 // Vector multiply long:
165 VMULLu, // ...unsigned
167 UMLAL, // 64bit Unsigned Accumulate Multiply
168 SMLAL, // 64bit Signed Accumulate Multiply
170 // Operands of the standard BUILD_VECTOR node are not legalized, which
171 // is fine if BUILD_VECTORs are always lowered to shuffles or other
172 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
173 // operands need to be legalized. Define an ARM-specific version of
174 // BUILD_VECTOR for this purpose.
180 // Vector OR with immediate
182 // Vector AND with NOT of immediate
185 // Vector bitwise select
188 // Pseudo-instruction representing a memory copy using ldm/stm
192 // Vector load N-element structure to all lanes:
193 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
197 // NEON loads with post-increment base updates:
209 // NEON stores with post-increment base updates:
220 /// Define some predicates that are used for node matching.
222 bool isBitFieldInvertedMask(unsigned v);
225 //===--------------------------------------------------------------------===//
226 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
228 class ARMTargetLowering : public TargetLowering {
230 explicit ARMTargetLowering(const TargetMachine &TM,
231 const ARMSubtarget &STI);
233 unsigned getJumpTableEncoding() const override;
234 bool useSoftFloat() const override;
236 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
238 /// ReplaceNodeResults - Replace the results of node with an illegal result
239 /// type with new values built out of custom code.
241 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
242 SelectionDAG &DAG) const override;
244 const char *getTargetNodeName(unsigned Opcode) const override;
246 bool isSelectSupported(SelectSupportKind Kind) const override {
247 // ARM does not support scalar condition selects on vectors.
248 return (Kind != ScalarCondVectorVal);
251 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
252 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
253 EVT VT) const override;
256 EmitInstrWithCustomInserter(MachineInstr *MI,
257 MachineBasicBlock *MBB) const override;
259 void AdjustInstrPostInstrSelection(MachineInstr *MI,
260 SDNode *Node) const override;
262 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
263 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
264 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
266 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
268 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
269 /// unaligned memory accesses of the specified type. Returns whether it
270 /// is "fast" by reference in the second argument.
271 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
273 bool *Fast) const override;
275 EVT getOptimalMemOpType(uint64_t Size,
276 unsigned DstAlign, unsigned SrcAlign,
277 bool IsMemset, bool ZeroMemset,
279 MachineFunction &MF) const override;
281 using TargetLowering::isZExtFree;
282 bool isZExtFree(SDValue Val, EVT VT2) const override;
284 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
286 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
289 /// isLegalAddressingMode - Return true if the addressing mode represented
290 /// by AM is legal for this target, for a load/store of the specified type.
291 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
292 Type *Ty, unsigned AS) const override;
293 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
295 /// isLegalICmpImmediate - Return true if the specified immediate is legal
296 /// icmp immediate, that is the target has icmp instructions which can
297 /// compare a register against the immediate without having to materialize
298 /// the immediate into a register.
299 bool isLegalICmpImmediate(int64_t Imm) const override;
301 /// isLegalAddImmediate - Return true if the specified immediate is legal
302 /// add immediate, that is the target has add instructions which can
303 /// add a register and the immediate without having to materialize
304 /// the immediate into a register.
305 bool isLegalAddImmediate(int64_t Imm) const override;
307 /// getPreIndexedAddressParts - returns true by value, base pointer and
308 /// offset pointer and addressing mode by reference if the node's address
309 /// can be legally represented as pre-indexed load / store address.
310 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
311 ISD::MemIndexedMode &AM,
312 SelectionDAG &DAG) const override;
314 /// getPostIndexedAddressParts - returns true by value, base pointer and
315 /// offset pointer and addressing mode by reference if this node can be
316 /// combined with a load / store to form a post-indexed load / store.
317 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
318 SDValue &Offset, ISD::MemIndexedMode &AM,
319 SelectionDAG &DAG) const override;
321 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
323 const SelectionDAG &DAG,
324 unsigned Depth) const override;
327 bool ExpandInlineAsm(CallInst *CI) const override;
329 ConstraintType getConstraintType(StringRef Constraint) const override;
331 /// Examine constraint string and operand type and determine a weight value.
332 /// The operand object must already have been set up with the operand type.
333 ConstraintWeight getSingleConstraintMatchWeight(
334 AsmOperandInfo &info, const char *constraint) const override;
336 std::pair<unsigned, const TargetRegisterClass *>
337 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
338 StringRef Constraint, MVT VT) const override;
340 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
341 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
342 /// true it means one of the asm constraint of the inline asm instruction
343 /// being processed is 'm'.
344 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
345 std::vector<SDValue> &Ops,
346 SelectionDAG &DAG) const override;
349 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
350 if (ConstraintCode == "Q")
351 return InlineAsm::Constraint_Q;
352 else if (ConstraintCode == "o")
353 return InlineAsm::Constraint_o;
354 else if (ConstraintCode.size() == 2) {
355 if (ConstraintCode[0] == 'U') {
356 switch(ConstraintCode[1]) {
360 return InlineAsm::Constraint_Um;
362 return InlineAsm::Constraint_Un;
364 return InlineAsm::Constraint_Uq;
366 return InlineAsm::Constraint_Us;
368 return InlineAsm::Constraint_Ut;
370 return InlineAsm::Constraint_Uv;
372 return InlineAsm::Constraint_Uy;
376 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
379 const ARMSubtarget* getSubtarget() const {
383 /// getRegClassFor - Return the register class that should be used for the
384 /// specified value type.
385 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
387 /// Returns true if a cast between SrcAS and DestAS is a noop.
388 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
389 // Addrspacecasts are always noops.
393 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
394 unsigned &PrefAlign) const override;
396 /// createFastISel - This method returns a target specific FastISel object,
397 /// or null if the target does not support "fast" ISel.
398 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
399 const TargetLibraryInfo *libInfo) const override;
401 Sched::Preference getSchedulingPreference(SDNode *N) const override;
404 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
405 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
407 /// isFPImmLegal - Returns true if the target can instruction select the
408 /// specified FP immediate natively. If false, the legalizer will
409 /// materialize the FP immediate as a load from a constant pool.
410 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
412 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
414 unsigned Intrinsic) const override;
416 /// \brief Returns true if it is beneficial to convert a load of a constant
417 /// to just the constant itself.
418 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
419 Type *Ty) const override;
421 /// \brief Returns true if an argument of type Ty needs to be passed in a
422 /// contiguous block of registers in calling convention CallConv.
423 bool functionArgumentNeedsConsecutiveRegisters(
424 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
426 /// If a physical register, this returns the register that receives the
427 /// exception address on entry to an EH pad.
429 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
431 /// If a physical register, this returns the register that receives the
432 /// exception typeid on entry to a landing pad.
434 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
436 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
437 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
438 AtomicOrdering Ord) const override;
439 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
440 Value *Addr, AtomicOrdering Ord) const override;
442 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
444 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
445 bool IsStore, bool IsLoad) const override;
446 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
447 bool IsStore, bool IsLoad) const override;
449 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
451 bool lowerInterleavedLoad(LoadInst *LI,
452 ArrayRef<ShuffleVectorInst *> Shuffles,
453 ArrayRef<unsigned> Indices,
454 unsigned Factor) const override;
455 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
456 unsigned Factor) const override;
458 TargetLoweringBase::AtomicExpansionKind
459 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
460 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
461 TargetLoweringBase::AtomicExpansionKind
462 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
463 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
465 bool useLoadStackGuardNode() const override;
467 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
468 unsigned &Cost) const override;
470 bool isCheapToSpeculateCttz() const override;
471 bool isCheapToSpeculateCtlz() const override;
474 std::pair<const TargetRegisterClass *, uint8_t>
475 findRepresentativeClass(const TargetRegisterInfo *TRI,
476 MVT VT) const override;
479 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
480 /// make the right decision when generating code for different targets.
481 const ARMSubtarget *Subtarget;
483 const TargetRegisterInfo *RegInfo;
485 const InstrItineraryData *Itins;
487 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
489 unsigned ARMPCLabelIndex;
491 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
492 void addDRTypeForNEON(MVT VT);
493 void addQRTypeForNEON(MVT VT);
494 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
496 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
497 void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
498 SDValue Chain, SDValue &Arg,
499 RegsToPassVector &RegsToPass,
500 CCValAssign &VA, CCValAssign &NextVA,
502 SmallVectorImpl<SDValue> &MemOpChains,
503 ISD::ArgFlagsTy Flags) const;
504 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
505 SDValue &Root, SelectionDAG &DAG,
508 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
509 bool isVarArg) const;
510 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
511 bool isVarArg) const;
512 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
513 SDLoc dl, SelectionDAG &DAG,
514 const CCValAssign &VA,
515 ISD::ArgFlagsTy Flags) const;
516 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
517 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
518 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
519 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
520 const ARMSubtarget *Subtarget) const;
521 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
522 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
523 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
524 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
525 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
526 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
527 SelectionDAG &DAG) const;
528 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
530 TLSModel::Model model) const;
531 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
532 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
533 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
534 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
535 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
536 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
537 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
538 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
539 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
540 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
541 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
542 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
543 const ARMSubtarget *ST) const;
544 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
545 const ARMSubtarget *ST) const;
546 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
547 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
548 SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
549 void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
550 SmallVectorImpl<SDValue> &Results) const;
551 SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
552 SDValue &Chain) const;
553 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
554 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
555 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
556 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
557 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
558 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
560 unsigned getRegisterByName(const char* RegName, EVT VT,
561 SelectionDAG &DAG) const override;
563 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
564 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
565 /// expanded to FMAs when this method returns true, otherwise fmuladd is
566 /// expanded to fmul + fadd.
568 /// ARM supports both fused and unfused multiply-add operations; we already
569 /// lower a pair of fmul and fadd to the latter so it's not clear that there
570 /// would be a gain or that the gain would be worthwhile enough to risk
571 /// correctness bugs.
572 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
574 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
576 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
577 CallingConv::ID CallConv, bool isVarArg,
578 const SmallVectorImpl<ISD::InputArg> &Ins,
579 SDLoc dl, SelectionDAG &DAG,
580 SmallVectorImpl<SDValue> &InVals,
581 bool isThisReturn, SDValue ThisVal) const;
584 LowerFormalArguments(SDValue Chain,
585 CallingConv::ID CallConv, bool isVarArg,
586 const SmallVectorImpl<ISD::InputArg> &Ins,
587 SDLoc dl, SelectionDAG &DAG,
588 SmallVectorImpl<SDValue> &InVals) const override;
590 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
591 SDLoc dl, SDValue &Chain,
592 const Value *OrigArg,
593 unsigned InRegsParamRecordIdx,
595 unsigned ArgSize) const;
597 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
598 SDLoc dl, SDValue &Chain,
600 unsigned TotalArgRegsSaveSize,
601 bool ForceMutable = false) const;
604 LowerCall(TargetLowering::CallLoweringInfo &CLI,
605 SmallVectorImpl<SDValue> &InVals) const override;
607 /// HandleByVal - Target-specific cleanup for ByVal support.
608 void HandleByVal(CCState *, unsigned &, unsigned) const override;
610 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
611 /// for tail call optimization. Targets which want to do tail call
612 /// optimization should implement this function.
613 bool IsEligibleForTailCallOptimization(SDValue Callee,
614 CallingConv::ID CalleeCC,
616 bool isCalleeStructRet,
617 bool isCallerStructRet,
618 const SmallVectorImpl<ISD::OutputArg> &Outs,
619 const SmallVectorImpl<SDValue> &OutVals,
620 const SmallVectorImpl<ISD::InputArg> &Ins,
621 SelectionDAG& DAG) const;
623 bool CanLowerReturn(CallingConv::ID CallConv,
624 MachineFunction &MF, bool isVarArg,
625 const SmallVectorImpl<ISD::OutputArg> &Outs,
626 LLVMContext &Context) const override;
629 LowerReturn(SDValue Chain,
630 CallingConv::ID CallConv, bool isVarArg,
631 const SmallVectorImpl<ISD::OutputArg> &Outs,
632 const SmallVectorImpl<SDValue> &OutVals,
633 SDLoc dl, SelectionDAG &DAG) const override;
635 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
637 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
639 SDValue getCMOV(SDLoc dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
640 SDValue ARMcc, SDValue CCR, SDValue Cmp,
641 SelectionDAG &DAG) const;
642 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
643 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
644 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
645 SelectionDAG &DAG, SDLoc dl) const;
646 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
648 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
650 void SetupEntryBlockForSjLj(MachineInstr *MI,
651 MachineBasicBlock *MBB,
652 MachineBasicBlock *DispatchBB, int FI) const;
654 void EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const;
656 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
658 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
659 MachineBasicBlock *MBB) const;
661 MachineBasicBlock *EmitLowered__chkstk(MachineInstr *MI,
662 MachineBasicBlock *MBB) const;
663 MachineBasicBlock *EmitLowered__dbzchk(MachineInstr *MI,
664 MachineBasicBlock *MBB) const;
667 enum NEONModImmType {
674 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
675 const TargetLibraryInfo *libInfo);
679 #endif // ARMISELLOWERING_H