1 //===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef ARMISELLOWERING_H
16 #define ARMISELLOWERING_H
18 #include "ARMSubtarget.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/CodeGen/FastISel.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
27 class ARMConstantPoolValue;
30 // ARM Specific DAG Nodes
32 // Start the numbering where the builtin ops and target ops leave off.
33 FIRST_NUMBER = ISD::BUILTIN_OP_END,
35 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
36 // TargetExternalSymbol, and TargetGlobalAddress.
37 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
39 CALL, // Function call.
40 CALL_PRED, // Function call that's predicable.
41 CALL_NOLINK, // Function call with branch not branch-and-link.
42 tCALL, // Thumb function call.
43 BRCOND, // Conditional branch.
44 BR_JT, // Jumptable branch.
45 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
46 RET_FLAG, // Return with a flag operand.
48 PIC_ADD, // Add with a PC operand and a PIC label.
50 CMP, // ARM compare instructions.
51 CMPZ, // ARM compare that sets only Z flag.
52 CMPFP, // ARM VFP compare instruction, sets FPSCR.
53 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
54 FMSTAT, // ARM fmstat instruction.
55 CMOV, // ARM conditional move instructions.
56 CNEG, // ARM conditional negate instructions.
60 RBIT, // ARM bitreverse instruction
62 FTOSI, // FP to sint within a FP register.
63 FTOUI, // FP to uint within a FP register.
64 SITOF, // sint to FP within a FP register.
65 UITOF, // uint to FP within a FP register.
67 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
68 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
69 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
71 VMOVRRD, // double to two gprs.
72 VMOVDRR, // Two gprs to double.
74 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
75 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
76 EH_SJLJ_DISPATCHSETUP, // SjLj exception handling dispatch setup.
78 TC_RETURN, // Tail call return pseudo.
82 DYN_ALLOC, // Dynamic allocation on the stack.
84 MEMBARRIER, // Memory barrier (DMB)
85 MEMBARRIER_MCR, // Memory barrier (MCR)
89 VCEQ, // Vector compare equal.
90 VCEQZ, // Vector compare equal to zero.
91 VCGE, // Vector compare greater than or equal.
92 VCGEZ, // Vector compare greater than or equal to zero.
93 VCLEZ, // Vector compare less than or equal to zero.
94 VCGEU, // Vector compare unsigned greater than or equal.
95 VCGT, // Vector compare greater than.
96 VCGTZ, // Vector compare greater than zero.
97 VCLTZ, // Vector compare less than zero.
98 VCGTU, // Vector compare unsigned greater than.
99 VTST, // Vector test bits.
101 // Vector shift by immediate:
103 VSHRs, // ...right (signed)
104 VSHRu, // ...right (unsigned)
105 VSHLLs, // ...left long (signed)
106 VSHLLu, // ...left long (unsigned)
107 VSHLLi, // ...left long (with maximum shift count)
108 VSHRN, // ...right narrow
110 // Vector rounding shift by immediate:
111 VRSHRs, // ...right (signed)
112 VRSHRu, // ...right (unsigned)
113 VRSHRN, // ...right narrow
115 // Vector saturating shift by immediate:
116 VQSHLs, // ...left (signed)
117 VQSHLu, // ...left (unsigned)
118 VQSHLsu, // ...left (signed to unsigned)
119 VQSHRNs, // ...right narrow (signed)
120 VQSHRNu, // ...right narrow (unsigned)
121 VQSHRNsu, // ...right narrow (signed to unsigned)
123 // Vector saturating rounding shift by immediate:
124 VQRSHRNs, // ...right narrow (signed)
125 VQRSHRNu, // ...right narrow (unsigned)
126 VQRSHRNsu, // ...right narrow (signed to unsigned)
128 // Vector shift and insert:
132 // Vector get lane (VMOV scalar to ARM core register)
133 // (These are used for 8- and 16-bit element types only.)
134 VGETLANEu, // zero-extend vector extract element
135 VGETLANEs, // sign-extend vector extract element
137 // Vector move immediate and move negated immediate:
147 VREV64, // reverse elements within 64-bit doublewords
148 VREV32, // reverse elements within 32-bit words
149 VREV16, // reverse elements within 16-bit halfwords
150 VZIP, // zip (interleave)
151 VUZP, // unzip (deinterleave)
154 // Vector multiply long:
156 VMULLu, // ...unsigned
158 // Operands of the standard BUILD_VECTOR node are not legalized, which
159 // is fine if BUILD_VECTORs are always lowered to shuffles or other
160 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
161 // operands need to be legalized. Define an ARM-specific version of
162 // BUILD_VECTOR for this purpose.
165 // Floating-point max and min:
172 // Vector OR with immediate
174 // Vector AND with NOT of immediate
179 /// Define some predicates that are used for node matching.
181 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be
182 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd)
183 /// instruction, returns its 8-bit integer representation. Otherwise,
185 int getVFPf32Imm(const APFloat &FPImm);
186 int getVFPf64Imm(const APFloat &FPImm);
187 bool isBitFieldInvertedMask(unsigned v);
190 //===--------------------------------------------------------------------===//
191 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
193 class ARMTargetLowering : public TargetLowering {
195 explicit ARMTargetLowering(TargetMachine &TM);
197 virtual unsigned getJumpTableEncoding(void) const;
199 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
201 /// ReplaceNodeResults - Replace the results of node with an illegal result
202 /// type with new values built out of custom code.
204 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
205 SelectionDAG &DAG) const;
207 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
209 virtual const char *getTargetNodeName(unsigned Opcode) const;
211 virtual MachineBasicBlock *
212 EmitInstrWithCustomInserter(MachineInstr *MI,
213 MachineBasicBlock *MBB) const;
215 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
216 /// unaligned memory accesses. of the specified type.
217 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON?
218 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
220 /// isLegalAddressingMode - Return true if the addressing mode represented
221 /// by AM is legal for this target, for a load/store of the specified type.
222 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
223 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
225 /// isLegalICmpImmediate - Return true if the specified immediate is legal
226 /// icmp immediate, that is the target has icmp instructions which can
227 /// compare a register against the immediate without having to materialize
228 /// the immediate into a register.
229 virtual bool isLegalICmpImmediate(int64_t Imm) const;
231 /// getPreIndexedAddressParts - returns true by value, base pointer and
232 /// offset pointer and addressing mode by reference if the node's address
233 /// can be legally represented as pre-indexed load / store address.
234 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
236 ISD::MemIndexedMode &AM,
237 SelectionDAG &DAG) const;
239 /// getPostIndexedAddressParts - returns true by value, base pointer and
240 /// offset pointer and addressing mode by reference if this node can be
241 /// combined with a load / store to form a post-indexed load / store.
242 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
243 SDValue &Base, SDValue &Offset,
244 ISD::MemIndexedMode &AM,
245 SelectionDAG &DAG) const;
247 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
251 const SelectionDAG &DAG,
252 unsigned Depth) const;
255 ConstraintType getConstraintType(const std::string &Constraint) const;
257 /// Examine constraint string and operand type and determine a weight value.
258 /// The operand object must already have been set up with the operand type.
259 ConstraintWeight getSingleConstraintMatchWeight(
260 AsmOperandInfo &info, const char *constraint) const;
262 std::pair<unsigned, const TargetRegisterClass*>
263 getRegForInlineAsmConstraint(const std::string &Constraint,
265 std::vector<unsigned>
266 getRegClassForInlineAsmConstraint(const std::string &Constraint,
269 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
270 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
271 /// true it means one of the asm constraint of the inline asm instruction
272 /// being processed is 'm'.
273 virtual void LowerAsmOperandForConstraint(SDValue Op,
274 char ConstraintLetter,
275 std::vector<SDValue> &Ops,
276 SelectionDAG &DAG) const;
278 const ARMSubtarget* getSubtarget() const {
282 /// getRegClassFor - Return the register class that should be used for the
283 /// specified value type.
284 virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
286 /// getFunctionAlignment - Return the Log2 alignment of this function.
287 virtual unsigned getFunctionAlignment(const Function *F) const;
289 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
290 /// be used for loads / stores from the global.
291 virtual unsigned getMaximalGlobalOffset() const;
293 /// createFastISel - This method returns a target specific FastISel object,
294 /// or null if the target does not support "fast" ISel.
295 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
297 Sched::Preference getSchedulingPreference(SDNode *N) const;
299 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
300 MachineFunction &MF) const;
302 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
303 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
305 /// isFPImmLegal - Returns true if the target can instruction select the
306 /// specified FP immediate natively. If false, the legalizer will
307 /// materialize the FP immediate as a load from a constant pool.
308 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
310 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
312 unsigned Intrinsic) const;
314 std::pair<const TargetRegisterClass*, uint8_t>
315 findRepresentativeClass(EVT VT) const;
318 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
319 /// make the right decision when generating code for different targets.
320 const ARMSubtarget *Subtarget;
322 const TargetRegisterInfo *RegInfo;
324 const InstrItineraryData *Itins;
326 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
328 unsigned ARMPCLabelIndex;
330 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
331 void addDRTypeForNEON(EVT VT);
332 void addQRTypeForNEON(EVT VT);
334 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
335 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
336 SDValue Chain, SDValue &Arg,
337 RegsToPassVector &RegsToPass,
338 CCValAssign &VA, CCValAssign &NextVA,
340 SmallVector<SDValue, 8> &MemOpChains,
341 ISD::ArgFlagsTy Flags) const;
342 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
343 SDValue &Root, SelectionDAG &DAG,
346 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
347 bool isVarArg) const;
348 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
349 DebugLoc dl, SelectionDAG &DAG,
350 const CCValAssign &VA,
351 ISD::ArgFlagsTy Flags) const;
352 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
353 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
354 SDValue LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) const;
355 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
356 const ARMSubtarget *Subtarget) const;
357 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
358 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
359 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
360 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
361 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
362 SelectionDAG &DAG) const;
363 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
364 SelectionDAG &DAG) const;
365 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
366 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
367 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
368 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
369 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
370 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
371 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
372 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
373 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
374 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
375 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
377 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
378 CallingConv::ID CallConv, bool isVarArg,
379 const SmallVectorImpl<ISD::InputArg> &Ins,
380 DebugLoc dl, SelectionDAG &DAG,
381 SmallVectorImpl<SDValue> &InVals) const;
384 LowerFormalArguments(SDValue Chain,
385 CallingConv::ID CallConv, bool isVarArg,
386 const SmallVectorImpl<ISD::InputArg> &Ins,
387 DebugLoc dl, SelectionDAG &DAG,
388 SmallVectorImpl<SDValue> &InVals) const;
391 LowerCall(SDValue Chain, SDValue Callee,
392 CallingConv::ID CallConv, bool isVarArg,
394 const SmallVectorImpl<ISD::OutputArg> &Outs,
395 const SmallVectorImpl<SDValue> &OutVals,
396 const SmallVectorImpl<ISD::InputArg> &Ins,
397 DebugLoc dl, SelectionDAG &DAG,
398 SmallVectorImpl<SDValue> &InVals) const;
400 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
401 /// for tail call optimization. Targets which want to do tail call
402 /// optimization should implement this function.
403 bool IsEligibleForTailCallOptimization(SDValue Callee,
404 CallingConv::ID CalleeCC,
406 bool isCalleeStructRet,
407 bool isCallerStructRet,
408 const SmallVectorImpl<ISD::OutputArg> &Outs,
409 const SmallVectorImpl<SDValue> &OutVals,
410 const SmallVectorImpl<ISD::InputArg> &Ins,
411 SelectionDAG& DAG) const;
413 LowerReturn(SDValue Chain,
414 CallingConv::ID CallConv, bool isVarArg,
415 const SmallVectorImpl<ISD::OutputArg> &Outs,
416 const SmallVectorImpl<SDValue> &OutVals,
417 DebugLoc dl, SelectionDAG &DAG) const;
419 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
420 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
421 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
422 SelectionDAG &DAG, DebugLoc dl) const;
424 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
426 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
427 MachineBasicBlock *BB,
428 unsigned Size) const;
429 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
430 MachineBasicBlock *BB,
432 unsigned BinOpcode) const;
436 enum NEONModImmType {
444 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
448 #endif // ARMISELLOWERING_H